Method for forming metal via holes

Abstract

The present invention discloses a method for forming a metal interlayer through-hole, in which a certain thickness of insulating layer material is retained on the side wall of a dielectric groove. When the dielectric groove and the corresponding through-hole are subsequently subjected to integrated etching of the metal interlayer dielectric, the opening size of the dielectric groove remains unchanged and does not become larger because the dielectric groove side wall is protected by the residual insulating layer material. At the same time, due to the effect of the residual insulating layer material on the side wall of the dielectric groove, even if the through-hole is shifted relative to the underlying metal, it will not deviate outside the underlying metal of the corresponding bit line, and the metal spacing on one side will not be smaller due to the displacement of the through-hole, thereby avoiding the risk of metal short circuit between adjacent through-holes, increasing the process window of the through-hole area of the underlying metal, and increasing the window margin of the secondary process, thereby improving the health of the metal interlayer through-hole formation process.

Description

Technical Field

[0001] The present invention relates to semiconductor manufacturing technology, in particular to a method for forming a through hole between metal layers. Background Art

[0002] The existing memory technology is basically only shrunk to 55nm / 40nm nodes. The specific process flow of metal / via technology is generally as follows: Figure 1 As shown, first grow IMD (Inter Metal Dielectric), then metal photo / etch (exposure / etch) part of the IMD, then via photo / etch (via) to open part of the via, and finally perform an all-in-one etch process to completely open and expose the underlying metal, filling it with a bonding layer of Ti / TiN and a copper layer. Figure 2 As shown in the figure, this process has two disadvantages: the metal will expand the top opening size during the subsequent via etching process and the all-in-one etching process, resulting in the risk of metal to metal shorts on adjacent bitlines in the memory array; and the via overlay shift will cause the metal space on one side to be smaller. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a method for forming through-holes between metal layers, which can avoid the risk of metal short circuit between adjacent through-holes, increase the process window of the through-hole area of the bottom metal, and increase the window margin of the secondary process.

[0004] To solve the above technical problems, the present invention provides a method for forming a metal interlayer via hole, which includes the following steps:

[0005] S1. Performing bottom metal 10 process on the wafer;

[0006] S2. growing a metal interlayer dielectric 11;

[0007] S3 performs metal layer exposure / etching to remove a certain thickness of the metal interlayer dielectric 11 directly above the bottom metal 10 to form a dielectric groove 110;

[0008] S4. Growing at least one insulating layer of material 12;

[0009] S5 performs etching of the insulating layer to remove the insulating layer material 12 on the bottom of the dielectric recess 110, retaining a certain thickness of the insulating layer material 12 on the sidewalls of the dielectric recess 110;

[0010] S6 performs through-hole exposure / etching to remove the metal interlayer dielectric 11 between the bottom center of the dielectric groove 110 and the bottom center of the underlying metal 10, forming a through hole 13 from the bottom center of the dielectric groove 110 to the bottom metal 10;

[0011] S7. The dielectric groove 110 and the corresponding through hole 13 are etched integrally with the metal interlayer dielectric 11 to completely open the metal interlayer dielectric 11 to expose the underlying metal 10;

[0012] S8. Removing the residual insulating layer material 12 from the sidewalls of the dielectric recess 110;

[0013] S9. Filler metal 14.

[0014] Preferably, the method for forming a metal interlayer via is a method for forming a metal interlayer via of a memory cell array bit line of a memory.

[0015] Preferably, the insulating layer material 12 is a layer of SiN.

[0016] Preferably, the insulating layer material 12 is a multi-layer structure of Oxide / SiN / Oxide.

[0017] Preferably, the thickness of the insulating layer material 12 grown in step S4 is between 50 angstroms and 150 angstroms.

[0018] Preferably, the thickness of the insulating layer material 12 retained on the sidewall of the dielectric groove 110 in step S5 is between 10 angstroms and 50 angstroms.

[0019] Preferably, in step S9 , the filled metal is a Ti / TiN adhesion layer or a copper material.

[0020] The method for forming a metal interlayer via of the present invention, by optimizing and changing the process scheme, retains a certain thickness of the insulating layer material 12 on the sidewall of the dielectric groove 110. When the dielectric groove 110 and the corresponding via hole are subsequently subjected to an all-in-one etching (All-in-One etching) of the metal interlayer dielectric 11, the opening size of the dielectric groove 110 remains unchanged and does not increase due to the protection of the insulating layer material 12 on the sidewall of the dielectric groove 110. At the same time, the residual insulating layer material 12 on the sidewall of the dielectric groove 110 also plays a role. Figure 11As shown, even if the via is shifted (overlay shift) relative to the underlying metal 10, the via will not be offset outside the underlying metal 10 of the corresponding bit line. The metal space on one side will not be smaller due to the via overlay shift, thereby avoiding the risk of metal to metal short between adjacent vias. The process window of the metal with via area of the underlying metal 10 is increased, and the window margin of the secondary process is increased, thereby improving the health of the via formation process between metal layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for use in the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 It is a schematic diagram of the specific process flow of the existing metal / through-hole process;

[0023] Figure 2 It is a schematic diagram of defects in existing metal / through hole processes;

[0024] Figure 3 2. It is a schematic diagram of growing a metal interlayer dielectric according to an embodiment of a method for forming a metal interlayer via hole of the present invention;

[0025] Figure 4 Schematic diagram of forming a dielectric groove according to an embodiment of a method for forming a metal layer through hole according to the present invention;

[0026] Figure 5 Schematic diagram of growing insulating layer materials according to an embodiment of the method for forming a metal layer through hole of the present invention;

[0027] Figure 6 Schematic diagram of etching the insulating layer in accordance with an embodiment of the method for forming a metal interlayer via hole according to the present invention;

[0028] Figure 7 Schematic diagram of through-hole exposure / etching in accordance with an embodiment of a method for forming a through-hole between metal layers of the present invention;

[0029] Figure 8 2. It is a schematic diagram of integrated etching performed in one embodiment of a method for forming a metal interlayer through hole according to the present invention;

[0030] Figure 92. It is a schematic diagram of removing the residual insulating layer material according to an embodiment of the method for forming a metal layer through hole of the present invention;

[0031] Figure 10 2. It is a schematic diagram of filling metal in an embodiment of a method for forming a metal interlayer via hole according to the present invention;

[0032] Figure 11 It is a schematic diagram of the beneficial technical effects of the method for forming a metal layer through hole of the present invention. DETAILED DESCRIPTION

[0033] The following is a clear and complete description of the technical solutions of the present invention in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0034] Example 1

[0035] like Figures 3 to 10 As shown, the method for forming a metal layer through hole includes the following steps:

[0036] S1. Performing a bottom metal 10 process on the wafer;

[0037] S2. Growth of Inter-Metal Dieletric (IMD) 11, such as Figure 3 As shown;

[0038] S3. Perform metal photo / etching to remove a certain thickness of the intermetallic dielectric (IMD) 11 directly above the bottom metal 10 to form a dielectric groove 110, such as Figure 4 As shown;

[0039] S4. Grow at least one insulating layer material 12, such as Figure 5 As shown;

[0040] S5. Blanket Etch is performed to remove the insulating layer material 12 on the bottom of the dielectric groove 110, and a certain thickness of the insulating layer material 12 is retained on the sidewall of the dielectric groove 110. Figure 6 As shown;

[0041] S6. Perform via photo / etching to remove the intermetallic dielectric (IMD) 11 between the center of the dielectric groove 110 and the bottom metal 10, forming a through hole 13 from the center of the dielectric groove 110 to the bottom metal 10; Figure 7 As shown;

[0042] S7. All-in-One etching is performed on the dielectric groove 110 and the corresponding through hole to completely open the metal interlayer dielectric 11 to expose the bottom metal 10. Figure 8 As shown;

[0043] S8. Removing the residual insulating layer material 12 on the sidewalls of the dielectric recess 110, such as Figure 9 As shown;

[0044] S9. Filler metal 14, such as Figure 10 shown.

[0045] In the method for forming a metal interlayer via in the first embodiment, by optimizing and changing the process scheme, a certain thickness of the insulating layer material 12 is retained on the sidewall of the dielectric groove 110. When the dielectric groove 110 and the corresponding via are subsequently subjected to an all-in-one etching (All-in-One etch) of the metal interlayer dielectric 11, the opening size of the dielectric groove 110 remains unchanged and does not increase due to the protection of the residual insulating layer material 12 on the sidewall of the dielectric groove 110. At the same time, the residual insulating layer material 12 on the sidewall of the dielectric groove 110 also plays a role. Figure 11 As shown, even if the via is shifted (overlay shift) relative to the underlying metal 10, the via will not be offset outside the underlying metal 10 of the corresponding bit line. The metal space on one side will not be smaller due to the via overlay shift, thereby avoiding the risk of metal to metal short between adjacent vias. The process window of the via area of the underlying metal 10 is increased, and the window margin of the secondary process is increased, thereby improving the health of the via formation process between metal layers.

[0046] Example 2

[0047] Based on the first embodiment, the method for forming an inter-metal via is a method for forming an inter-metal via of a memory cell array bit line of a memory.

[0048] Preferably, the insulating layer material 12 can be a layer of SiN or a multi-layer structure of Oxide / SiN / Oxide.

[0049] Preferably, the thickness of the insulating layer material 12 grown in step S4 is between 50 angstroms and 150 angstroms (selected according to specific dimensions).

[0050] Preferably, the thickness of the insulating layer material 12 retained on the sidewall of the dielectric groove 110 in step S5 is between 10 angstroms and 50 angstroms.

[0051] Preferably, in step S9, the filled metal is an adhesive layer such as Ti / TiN or a copper material.

[0052] Preferably, in step S3 , the depth of the dielectric groove 110 formed is 1 / 3 to 2 / 3 of the thickness of the intermetallic dielectric 11 on the bottom metal layer 10 .

[0053] Preferably, the thickness of the intermetallic dielectric 11 grown in step S2 is 200 nm to 500 nm.

[0054] The metal layer via formation method of the second embodiment can improve the memory array bitline short circuit problem at the 55nm / 40nm technology node, increase the process window of the metal through via area of the underlying metal 10 of the bitline, and increase the window margin of the subsequent process, thereby improving the health of the process.

[0055] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for forming a metal interlayer via hole, characterized in that: The following steps are involved: S1. Performing bottom metal (10) process on the wafer; S2. growing a metal interlayer dielectric (11); S3. Expose / etch the metal layer to remove a certain thickness of the intermetallic dielectric (11) directly above the bottom metal (10) to form a dielectric groove (110); S4. growing at least one layer of insulating material (12); S5. performing insulating layer etching to remove the insulating layer material (12) on the bottom of the dielectric groove (110), and retaining a certain thickness of insulating layer material (12) on the sidewall of the dielectric groove (110); S6. Performing through-hole exposure / etching to remove the metal interlayer dielectric (11) between the center of the bottom of the dielectric groove (110) and the bottom metal (10), thereby forming a through-hole (13) from the center of the bottom of the dielectric groove (110) to the bottom metal (10); S7. The dielectric groove (110) and the corresponding through hole (13) are subjected to integrated etching of the metal interlayer dielectric (11), and the metal interlayer dielectric (11) is completely opened to leak the bottom metal (10); S8. removing the residual insulating layer material (12) on the sidewalls of the dielectric groove (110); S9. Filler metal (14).

2. The method for forming a metal layer through hole according to claim 1, wherein: The method for forming a metal interlayer via hole is a method for forming a metal interlayer via hole for a memory cell array bit line of a memory.

3. The method for forming a metal layer through hole according to claim 1, wherein: The insulating layer material (12) is a layer of SiN.

4. The method for forming a metal layer through hole according to claim 1, wherein: The insulating layer material (12) is an Oxide / SiN / Oxide multilayer structure.

5. The method for forming a metal layer through hole according to claim 1, wherein: The thickness of the insulating layer material (12) grown in step S4 is between 50 angstroms and 150 angstroms.

6. The method for forming a metal layer through hole according to claim 1, wherein: In step S5, the thickness of the insulating layer material (12) retained on the sidewall of the dielectric groove (110) is between 10 angstroms and 50 angstroms.

7. The method for forming a metal layer through hole according to claim 1, wherein: In step S9 , the filled metal is a Ti / TiN adhesion layer or a copper material.

8. The method for forming a metal layer through hole according to claim 1, wherein: In step S3, the depth of the formed dielectric groove (110) is 1 / 3 to 2 / 3 of the thickness of the metal interlayer dielectric (11) on the bottom metal (10).

9. The method for forming a metal layer through hole according to claim 1, wherein: The thickness of the metal interlayer dielectric (11) grown in step S2 is 200 nm to 500 nm.

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