Semiconductor package and method of manufacturing semiconductor package

Abstract

A semiconductor package may be provided, comprising: a core substrate; a semiconductor chip located in the core substrate and having a chip pad; a redistribution wiring layer covering the lower surface of the core substrate and comprising redistribution wiring electrically connected to the chip pad and a pair of capacitor pads exposed from the outer surface of the redistribution wiring layer; a conductive paste located on the capacitor pads, respectively; and a capacitor mounted via the conductive paste and having first and second external electrodes located on the capacitor pads, respectively. Each capacitor pad includes a pad pattern exposed from the outer surface of the redistribution wiring layer and includes at least one through-hole pattern, which is at the lower part of the pad pattern and electrically connected to at least one of the redistribution wirings. The through-hole pattern is eccentric from the center line of the pad pattern by a distance.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2020-0140455 filed on October 27, 2020 in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Example embodiments relate to semiconductor packages and / or methods of manufacturing semiconductor packages. More particularly, example embodiments relate to semiconductor packages having passive devices and / or methods of manufacturing the same. Background Art

[0004] A fan-out package with a relatively thin thickness may include a thin film capacitor that can achieve a thinner thickness as a passive device. The thin film capacitor may be a decoupling capacitor for an application processor and may be manufactured in the form of a land side capacitor (LSC). LSC type capacitors may be mounted by solder paste. However, during the reflow process for mounting the capacitor, the flux gas evaporated from the solder paste may be collected to form a relatively large void in the joint, thereby reducing the joint reliability. Summary of the invention

[0005] Some example embodiments provide a semiconductor package capable of improving coupling reliability with a capacitor.

[0006] Some example embodiments provide methods of manufacturing semiconductor packages.

[0007] According to some example embodiments, a semiconductor package may include: a core substrate; at least one semiconductor chip in the core substrate and having a chip pad; a redistribution wiring layer covering the lower surface of the core substrate and including redistribution wiring electrically connected to the chip pad and a pair of capacitor pads, the chip pad and the pair of capacitor pads being exposed from the outer surface of the redistribution wiring layer and being electrically connected to the corresponding redistribution wiring, respectively; a conductive paste being respectively located on the capacitor pads; and a capacitor being located on the pair of capacitor pads via the conductive paste, the capacitor having a first external electrode and a second external electrode, the first external electrode and the second external electrode being respectively located on the capacitor pads. Each capacitor pad may include: a pad pattern exposed from the outer surface of the redistribution wiring layer; and at least one through-hole pattern located at the lower portion of the pad pattern, the at least one through-hole pattern being electrically connected to at least one redistribution wiring. The through-hole pattern may be eccentric from the center line of the pad pattern by a distance.

[0008] According to some example embodiments, a semiconductor package may include: a redistribution wiring layer having a first surface and a second surface opposite to each other, the redistribution wiring layer including at least two layers of redistribution wiring stacked, a pair of capacitor pads exposed from the second surface and electrically connected to the corresponding pair of redistribution wirings, at least one semiconductor chip located on the first surface of the redistribution wiring layer, the at least one semiconductor chip having chip pads electrically connected to the corresponding redistribution wirings, a molded substrate located on the redistribution wiring layer and covering the semiconductor chip, a conductive paste located on the capacitor pads, respectively, and a capacitor located on the pair of capacitor pads via the conductive paste, the capacitor having first and second external electrodes, the first and second external electrodes being located on the capacitor pads, respectively. Each capacitor pad may include: a pad pattern exposed from the second surface of the redistribution wiring layer; and at least one through-hole pattern located at the lower portion of the pad pattern, the at least one through-hole pattern being electrically connected to at least one redistribution wiring. The through-hole pattern may be eccentric from the center line of the pad pattern by a distance. The diameter of the through-hole pattern may be 40% or less of the width of the pad pattern.

[0009] According to some example embodiments, a semiconductor package may include: a core substrate; at least one semiconductor chip in the core substrate and having a chip pad; a redistribution wiring layer covering the lower surface of the core substrate and including a redistribution wiring electrically connected to the chip pad; a solder ball pad exposed from the outer surface of the redistribution wiring layer; a pair of capacitor pads exposed from the outer surface of the redistribution wiring layer and electrically connected to the corresponding redistribution wiring, respectively; a capacitor located on the pair of capacitor pads via a conductive paste, the capacitor having a first and a second external electrode, the first and the second external electrodes being located on the capacitor pads, respectively. Each capacitor pad may include: a pad pattern exposed from the outer surface of the redistribution wiring layer; and at least one through-hole pattern extending downward from the pad pattern and electrically connected to the redistribution wiring layer. The pad pattern may be a rectangular pad having a longer side and a shorter side, and the through-hole pattern is eccentric by a certain distance from a center line passing through the midpoint of the shorter side of the pad pattern. The diameter of the solder ball pad may be greater than the width of each capacitor pad.

[0010] According to some example embodiments, a semiconductor package as a fan-out package may include a core substrate provided as a frame in an area outside a semiconductor chip, a redistribution wiring layer covering a lower surface of the core substrate, and at least one capacitor on an outer surface of the redistribution wiring layer. The redistribution wiring layer may include a pair of capacitor pads exposed from an outer surface thereof, and first and second external electrodes of the capacitor may be located on the pair of capacitor pads via a conductive paste.

[0011] Each capacitor pad may include a pad pattern and at least one via pattern. The via pattern may be off-centered by a desired (or alternatively, predetermined) distance from a centerline of the pad pattern. The diameter of the via pattern may be 40% or less of a width of the pad pattern.

[0012] Therefore, because the via pattern is eccentric from the center of the pad pattern and the via pattern has a relatively small diameter, flux gas generated from a conductive paste such as a solder paste can move to an edge region of the pad pattern and can easily escape from the solder paste, thereby alleviating or preventing a relatively large void from growing on the via pattern. Therefore, the bonding reliability of the capacitor can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 31 Represents non-limiting example embodiments described herein.

[0014] Figure 1 is a cross-sectional view illustrating a semiconductor package according to some example embodiments.

[0015] Figure 2 It is shown Figure 1 Enlarged cross-sectional view of section "A".

[0016] Figure 3 It is shown Figure 2 A plan view of the first and second capacitor pads.

[0017] Figure 4 It is shown installed in Figure 2 A perspective view of a capacitor on first and second capacitor pads in FIG.

[0018] Figures 5 to 18 are diagrams illustrating stages of a method of manufacturing a semiconductor package according to some example embodiments.

[0019] Fig.19 is a cross-sectional view illustrating a portion of a semiconductor package according to some example embodiments.

[0020] Fig. 20 It shows Fig.19 A plan view of the first and second capacitor pads.

[0021] Fig.21 is a cross-sectional view illustrating a semiconductor package according to some example embodiments.

[0022] Fig. 22 It is shown Fig.21 Enlarged cross-sectional view of section "C".

[0023] Fig.23is a cross-sectional view illustrating a semiconductor package according to some example embodiments.

[0024] Figures 24 to 30 are cross-sectional views illustrating stages of a method of manufacturing a semiconductor package according to some example embodiments.

[0025] Fig.31 is a cross-sectional view illustrating a semiconductor package according to some example embodiments. DETAILED DESCRIPTION

[0026] Hereinafter, some example embodiments will be described in detail with reference to the accompanying drawings.

[0027] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, the associated numerical value is intended to include a manufacturing tolerance (e.g., ±10%) around the numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, the intention is not to require the accuracy of the geometric shape, but the tolerance of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified to "about" or "substantially", it should be understood that these values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the numerical value or shape.

[0028] Figure 1 is a cross-sectional view illustrating a semiconductor device according to some example embodiments. Figure 2 It is shown Figure 1 Enlarged cross-sectional view of section "A". Figure 3 It is shown Figure 2 A plan view of the first and second capacitor pads. Figure 4 It is shown installed in Figure 2 A perspective view of a capacitor on first and second capacitor pads in FIG.

[0029] Reference Figures 1 to 4 , the semiconductor package 10 may include a core substrate 100, at least one semiconductor chip 200 arranged in the core substrate 100, a redistribution wiring layer 300 located on the lower surface 104 of the core substrate 100, and at least one capacitor 420 mounted on the outer surface of the redistribution wiring layer 300. In addition, the semiconductor package 10 may further include an upper (back) redistribution wiring layer 350 disposed on the upper surface 102 of the core substrate 100 and an external connection member 400 disposed on the outer surface of the redistribution wiring layer 300.

[0030] In some example embodiments, the semiconductor package 10 may include a core substrate 100 provided as a base substrate, which surrounds the semiconductor chip 200. The core substrate 100 may include a core connection wiring 120, which is provided in a fan-out region outside the region where the semiconductor chip 200 is arranged, to serve as an electrical connection path with the semiconductor chip 200. Therefore, the semiconductor package 10 may be provided as a fan-out package. In addition, the semiconductor package 10 may be provided as a unit package on which a second package is stacked.

[0031] In addition, the semiconductor package 10 may be provided as a system-in-package (SIP). For example, one or more semiconductor chips may be arranged in the core substrate 100. The semiconductor chip may include a logic chip including a logic circuit and / or a memory chip. The logic chip may be a controller that controls the memory chip. The memory chip may include various memory circuits, such as DRAM, SRAM, flash memory, PRAM, ReRAM, FeRAM, MRAM, etc.

[0032] In some example embodiments, the core substrate 100 may have a first surface 102 (e.g., an upper surface) and a second surface 104 (e.g., a lower surface) opposite to each other. The core substrate 100 may have a cavity 106 in a middle region thereof. The cavity 106 may extend from the first surface 102 to the second surface 104 of the core substrate 100.

[0033] The core substrate 100 may include a plurality of stacked insulating layers 110, 112 and core connection wirings 120 provided as conductive connectors in the insulating layers. The plurality of core connection wirings 120 may be provided in a fan-out region outside a region where a semiconductor chip (die) is arranged for electrical connection with the semiconductor chip mounted therein.

[0034] For example, the core substrate 100 may include a first insulating layer 110 and a second insulating layer 112 stacked on the first insulating layer 110. The core connection wiring 120 may include a first metal wiring 122, a first contact 123, a second metal wiring 124, a second contact 125, and a third metal wiring 126. The first metal wiring 122 may be disposed in the second surface 104 of the core substrate 100 (e.g., in the lower surface of the first insulating layer 110), and at least a portion of the first metal wiring 122 may be exposed from the second surface 104. The third metal wiring 126 may be disposed in the first surface 102 of the core substrate 100 (e.g., in the upper surface of the second insulating layer 112), and at least a portion of the third metal wiring 126 may be exposed from the first surface 102. It is understood that the number and arrangement of the insulating layers and the core connection wiring are not limited thereto.

[0035] In some example embodiments, the semiconductor chip 200 may be disposed within the cavity 106 of the core substrate 100. The sidewalls of the semiconductor chip 200 may be spaced apart from the inner sidewalls of the cavity 106. Thus, a gap may be formed between the sidewalls of the semiconductor chip 200 and the inner sidewalls of the cavity 106.

[0036] The semiconductor chip 200 may include a substrate and a chip pad 210 located on an active surface (e.g., a front side 202 of the substrate). The semiconductor chip 200 may be arranged so that the front side on which the chip pad 210 is formed faces downward. Therefore, the chip pad 210 may be exposed from the second surface 104 of the core substrate 100. The front side of the semiconductor chip 200 may be coplanar with the second surface 104 of the core substrate 100. The back side 204 of the semiconductor chip 200 opposite to the front side 202 may be located on a plane higher than the first surface 102 of the core substrate 100.

[0037] In some example embodiments, the sealing layer 130 may be disposed on the first surface 102 of the core substrate 100 to cover the semiconductor chip 200. The sealing layer 130 may be formed to fill a gap between the sidewall of the semiconductor chip 200 and the inner sidewall of the cavity 106. Therefore, the sealing layer 130 may cover the back side of the semiconductor chip 200, the first surface 102 of the core substrate 100, and the inner sidewall of the cavity 106.

[0038] For example, the sealing layer 130 may include a thermosetting insulating material such as epoxy resin, a photoimageable dielectric (PID) material, an insulating film such as Ajinomoto build-up film (ABF), or the like.

[0039] In some example embodiments, the redistribution wiring layer 300 may be arranged on the second surface 104 of the core substrate 100 and the front side 202 of the semiconductor chip 200. The redistribution wiring layer 300 may include a first redistribution wiring 302 electrically connected to the chip pad 210 and the core connection wiring 120 of the semiconductor chip 200, respectively. The first redistribution wiring 302 may be provided on the second surface 104 of the core substrate 100 to serve as a front side redistribution wiring. The redistribution wiring layer 300 may be a front redistribution wiring layer of a fan-out package.

[0040] For example, the redistribution wiring layer 300 may include a first redistribution wiring layer having a first lower redistribution wiring 312 disposed on the first lower insulation layer 310 .

[0041] The first lower insulating layer 310 may be disposed on the second surface 104 of the core substrate 100 and may have a first opening respectively exposing the chip pad 210 of the semiconductor chip 200 and the first metal wiring 122 of the core connection wiring 120. The first lower redistribution wiring 312 may be disposed on the first lower insulating layer 310, and portions of the first lower redistribution wiring 312 may contact the chip pad 210 and the first metal wiring 122, respectively, through the first opening.

[0042] The redistribution wiring layer 300 may include a second redistribution wiring layer having a second lower redistribution wiring 322 disposed on the second lower insulation layer 320 .

[0043] The second lower insulating layer 320 may be disposed on the first lower insulating layer 310 and may have second openings respectively exposing the first lower redistribution wirings 312. The second lower redistribution wirings 322 may be disposed on the second lower insulating layer 320, and portions of the second lower redistribution wirings 322 may respectively contact the first lower redistribution wirings 312 through the first openings.

[0044] The redistribution wiring layer 300 may include a third redistribution wiring layer having third lower redistribution wirings 332 disposed on the third lower insulation layer 330 .

[0045] The third lower insulating layer 330 may be disposed on the second lower insulating layer 320 and may have third openings respectively exposing the second lower redistribution wirings 322. The third lower redistribution wirings 332 may be disposed on the third lower insulating layer 330, and portions of the third lower redistribution wirings 332 may respectively contact the second lower redistribution wirings 322 through the third openings.

[0046] The redistribution wiring layer 300 may include a fourth lower insulation layer 340 disposed on the third lower insulation layer 330 and having fourth openings 341 , 343 exposing portions of the third lower redistribution wirings 332 .

[0047] For example, the first to fourth lower insulating layers may include a polymer layer, a dielectric layer, etc. The first to fourth lower insulating layers may include PID, an insulating film such as ABF, etc. The fourth lower insulating layer may include the same or different material as the first to third lower insulating layers. The first to third lower redistribution wirings may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0048] In some example embodiments, the redistribution wiring layer 300 may include solder ball pads 342 and a pair of capacitor pads 344 exposed from an outer surface thereof. The external connection members 400 may be disposed on the solder ball pads 342 , respectively. The capacitors 420 may be mounted on the pair of capacitor pads 344 .

[0049] like Figures 2 to 4 As shown, a first through hole 341 for electrically connecting to a solder ball pad 342 and a second through hole 343 for electrically connecting to a capacitor pad 344 may be provided in the fourth lower insulating layer 340. The second through hole 343 may include a pair of second through holes 343a, 343b.

[0050] The second through holes 343a, 343b may be arranged in the first direction (X direction) to be spaced apart from each other. The three second through holes 343a may be arranged in the second direction (Y direction) perpendicular to the first direction (X direction) to be spaced apart from each other. The three second through holes 343b may be arranged in the second direction (Y direction) to be spaced apart from each other.

[0051] The diameter D of each second through hole 343a, 343b may be smaller than the diameter (D2) of the first through hole 341. For example, the diameter D1 of each second through hole 343a, 343b may be in the range of 50 μm to 200 μm. The diameter D2 of the first through hole 341 may be in the range of 150 μm to 250 μm. The spacing between the second through holes 343a in the second direction and the spacing between the second through holes 343b in the second direction may be in the range of 250 μm to 450 μm.

[0052] The pair of capacitor pads 344 may include a first capacitor pad 344 a and a second capacitor pad 344 b. Each of the first and second capacitor pads 344 a, 344 b may include a pad pattern 346 and at least one via pattern 348 .

[0053] The pad pattern 346 may be formed to be exposed from the fourth lower insulating layer 340. A via pattern 348 may be formed in each of the second via holes 343a, 343b. The via pattern 348 may extend downward from the pad pattern 346 to contact the third lower redistribution wiring 332. The pad pattern 346 may be electrically connected to the third lower redistribution wiring 332 through the via pattern 348.

[0054] The pad pattern 346 may have a pit 347 at an upper portion of the via pattern 348. The diameter of the pit 347 may be substantially equal to or smaller than the diameter D1 of the via pattern 348. The thickness T1 of the pad pattern 346 may be in the range of 5 μm to 25 μm. The thickness of the via pattern 348 may be the same as or substantially similar to the thickness of the pad pattern 346.

[0055] like Figure 3 As shown, the first capacitor pad 344a may include three through-hole patterns 348 connected to one pad pattern 346. The second capacitor pad 344b may include three through-hole patterns 348 connected to one pad pattern 346. In addition, the pad pattern 346 may have a shape corresponding to the shape of the first and second external electrodes 422a, 422b of the capacitor 420 mounted thereon. For example, the pad pattern 346 may have a rectangular pad shape having a first side (e.g., a relatively long side) and a second side (e.g., a relatively short side).

[0056] The three via patterns 348 may be positioned to be off-center by a desired (or alternatively, predetermined) distance P (eg, P1, P2) from a center line ML of the land pattern 346 . The center line ML may pass through a midpoint of a short side of the land pattern 346 .

[0057] For example, the length of the pad pattern 346 in the extension direction (X direction) of the relatively short side (e.g., the width W of the pad pattern 346) may be in the range of 150 μm to 500 μm. The length of the pad pattern 346 in the extension direction (Y direction) of the relatively long side (e.g., the length L of the pad pattern 346) may be in the range of 600 μm to 1200 μm. The diameter of the through hole pattern 348 may be 40% or less of the width W of the pad pattern 346. The diameter of the through hole pattern 348 may be in the range of 50 μm to 200 μm.

[0058] The pad patterns 346 of the pair of capacitor pads 344 may be spaced apart from each other in the first direction (X direction). A spacing Q between the pad patterns 346 in the first direction (X direction) may be in the range of 130 μm to 300 μm.

[0059] The three through hole patterns 348 may be spaced apart from each other along the extension direction (e.g., the second direction (Y direction)) of the relatively long sides of the pad pattern 346. The spacing between the through hole patterns 348 in the second direction (Y direction) may be in the range of 250 μm to 450 μm. The pad pattern 346 of the first capacitor pad 344a may have two relatively long sides S1a, S2a, and the pad pattern 346 of the second capacitor pad 344b may have two relatively long sides S1b, S2b.

[0060] In some example embodiments, the pad pattern 346 of the first capacitor pad 344a and the pad pattern 346 of the second capacitor pad 344b may have sides S2a and S1b located relatively close to each other. The pad pattern 346 of the first capacitor pad 344a and the pad pattern 346 of the second capacitor pad 344b may have sides S1a and S2b located relatively far from each other.

[0061] The three via patterns 348 of the first capacitor pad 344a may be positioned eccentrically toward the side S2a of the pad pattern 346 positioned relatively close to the pad pattern 346 of the second capacitor pad 344b. That is, the three via patterns 348 of the first capacitor pad 344a may be arranged adjacent to the side S2a.

[0062] The three via patterns 348 of the second capacitor pad 344b may be positioned eccentrically toward the side S1b of the pad pattern 346 positioned relatively close to the pad pattern 346 of the first capacitor pad 344a. That is, the three via patterns 348 of the second capacitor pad 344b may be arranged adjacent to the side S1b.

[0063] In some example embodiments, the pad pattern 346 of the first capacitor pad 344a may have relatively short sides S3a, S4a opposite to each other, and the pad pattern 346 of the second capacitor pad 344b may have relatively short sides S3b, S4b opposite to each other.

[0064] A solder ball pad 342 may be formed in each of the first through holes 341. A diameter of the solder ball pad 342 may be greater than a width W of the pad pattern 346. A diameter of the solder ball pad 342 may be in a range of 160 μm to 260 μm.

[0065] In some example embodiments, external connection members 400 such as solder balls may be respectively disposed on the solder ball pads 342, and a capacitor 420 may be mounted on a pair of capacitor pads 344. First and second external electrodes 422a, 422b of the capacitor 420 may be attached to the first and second capacitor pads 344a, 344b, respectively, through a conductive paste 410.

[0066] The capacitor 420 may be a thin film capacitor as a decoupling capacitor. The capacitor 420 may be a land side capacitor (LSC) type capacitor arranged on an outer surface of the redistribution wiring layer 300 , the outer surface being opposite to the semiconductor chip 200 .

[0067] The conductive paste 410 may include solder paste. The conductive paste 410 may have a void 412 therein. The void 412 may be located above the pit 347. The thickness T2 of the conductive paste 410 may be in the range of 5 μm to 15 μm. The thickness T3 of the capacitor 420 may be in the range of 50 μm to 120 μm.

[0068] In some example embodiments, the upper redistribution wiring layer 350 may be disposed on the first surface 102 of the core substrate 100 and the back side 204 of the semiconductor chip 200, and may include second redistribution wirings 352 respectively electrically connected to the core connection wirings 120. The second redistribution wirings 352 may be disposed on the first surface 102 of the core substrate 100 to serve as back side redistribution wirings. Therefore, the upper redistribution wiring layer may be a back side redistribution wiring layer.

[0069] For example, the upper redistribution wiring layer 350 may include a first upper insulating layer 360 covering a first upper redistribution wiring 362 electrically connected to the core connection wiring 120. The first upper redistribution wiring 362 may be disposed on the sealing layer 130 and may be electrically connected to the core connection wiring 120.

[0070] The upper redistribution wiring layer 350 may include a second upper insulating layer 370 covering the second upper redistribution wiring 372. The second upper redistribution wiring 372 may be disposed on the first upper insulating layer 360 and may be electrically connected to the first upper redistribution wiring 362. The second upper insulating layer 370 may have an opening 371 exposing the second upper redistribution wiring 372.

[0071] For example, the first and second upper insulating layers may include a thermosetting insulating material (e.g., epoxy resin), a photoimageable dielectric (PID) material, an insulating film such as Ajinomoto build-up film (ABF), etc. The first and second lower redistribution wirings may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or alloys thereof.

[0072] In some example embodiments, the external connection member 400 may include a solder ball. The solder ball may have a diameter of 180 μm to 250 μm. The semiconductor package 10 may be mounted on a module substrate (not shown) via the solder ball to form a memory module.

[0073] As described above, the semiconductor package 10 as a fan-out panel level package may include a redistribution wiring layer 300 covering the second surface 104 of the core substrate 100 and at least one capacitor 420 mounted on the outer surface of the redistribution wiring layer 300. The redistribution wiring layer 300 may include a pair of capacitor pads 344 exposed to its outer surface, and the first and second external electrodes 422a, 422b of the capacitor 420 may be mounted on the pair of capacitor pads 344 by a conductive paste 410. Each capacitor pad 344 may include a pad pattern 346 and at least one through-hole pattern 348. The through-hole pattern 348 may be positioned to be eccentric to a desired (or alternatively, predetermined) distance P from the center line ML of the pad pattern 346. The diameter D1 of the through-hole pattern 348 may be 40% or less of the width W of the pad pattern 346.

[0074] Since the via pattern 348 is eccentric from the center of the pad pattern 346 and the diameter of the via pattern 348 is relatively small, the flux gas generated by the solder paste can move to the edge area of ​​the pad pattern 346 and easily escape from the solder paste. Therefore, the bonding reliability of the capacitor 420 can be improved.

[0075] In the following, the manufacturing Figure 1 A method for semiconductor packaging.

[0076] Figures 5 to 18 are diagrams illustrating stages of a method of manufacturing a semiconductor package according to some example embodiments. Figure 5 is a plan view showing a panel in which a plurality of core substrates are formed. Figures 6 to 10 and Fig.17 is along Figure 5 A cross-sectional view taken along line II' in FIG.

[0077] Fig.11 and Figures 13 to 15 It is shown Fig.10 An enlarged cross-sectional view of section "B" in FIG. Fig.18 It is shown Fig.17 Enlarged cross-sectional view of section "B". Fig.12 yes Fig.11 Floor plan, Fig.16 yes Fig.15 Floor plan.

[0078] Reference Figures 5 to 7 , a panel P in which a plurality of core substrates 100 are formed may be prepared, the semiconductor chip 200 may be arranged within the cavity 106 of the core substrate 100 , and then a sealing layer 130 may be formed to cover the semiconductor chip 200 .

[0079] In some example embodiments, the core substrate 100 may be used as a supporting frame for electrical connections for manufacturing a semiconductor package having a fan-out panel level packaging configuration.

[0080] like Figure 5 As shown, the panel P may include a frame region FR on which the core substrate 100 is formed and a scribing region (eg, cutting region CA) surrounding the frame region FR. As described below, the panel P may be sawn along the cutting region CA dividing the frame region FR to form separate core substrates 100.

[0081] The core substrate 100 may have a first surface 102 and a second surface 104 opposite to each other. The core substrate 100 may have a cavity 106 in a middle region of the frame region FR. As described below, the cavity 106 may have a region for accommodating at least one semiconductor chip.

[0082] The core substrate 100 may include a plurality of stacked insulating layers 110, 112 and a core connection wiring 120 that is set as a conductive connector in the insulating layer. A plurality of core connection wirings 120 may be provided to run through the core substrate 100 from the first surface 102 to the second surface 104 of the core substrate 100 to serve as an electrical connection path. That is, the core connection wiring 120 may be arranged in a fan-out region outside the region where the semiconductor chip (die) is arranged for electrical connection with the semiconductor chip mounted therein. For example, the core connection wiring 120 may include a first metal wiring 122, a first contact 123, a second metal wiring 124, a second contact 125, and a third metal wiring 126.

[0083] like Figure 6 As shown, the panel P may be disposed on a barrier tape (or alternatively, a carrier tape) 20 , and at least one semiconductor chip 200 may be disposed within the cavity 106 of the core substrate 100 .

[0084] The second surface 104 of the core substrate 100 may be adhered to the barrier tape 20. For example, about 200 to about 6,000 dies (chips) may be arranged in the cavities 106 of the panel P, respectively. As described below, a cutting or sawing process may be performed to saw the panel P to complete the fan-out panel level package. In some example embodiments, a plurality of semiconductor chips 200 may be arranged in one cavity 106.

[0085] The semiconductor chip 200 may include a substrate and a chip pad 210 located on a front side (e.g., a first surface) of the substrate. The semiconductor chip 200 may be arranged so that the first surface on which the chip pad 210 is formed faces downward. The front side of the semiconductor chip 200 may be coplanar with the second surface 104 of the core substrate 100.

[0086] The semiconductor chip 200 may be disposed in the cavity 106 of the core substrate 100. The sidewalls of the semiconductor chip 200 may be spaced apart from the inner sidewalls of the cavity 106. Therefore, a gap may be formed between the sidewalls of the semiconductor chip 200 and the inner sidewalls of the cavity 106.

[0087] The thickness of the semiconductor chip 200 may be greater than the thickness of the core substrate 100. Therefore, the back side 204 of the semiconductor chip 200 may be positioned higher than the first surface 102 of the core substrate 100. Alternatively, the thickness of the semiconductor chip 200 may be equal to or less than the thickness of the core substrate 100. In this case, the back side 204 of the semiconductor chip 200 may be coplanar with the first surface 102 of the core substrate 100 or positioned lower than the first surface 102 of the core substrate 100.

[0088] like Figure 7As shown, the sealing layer 130 may be formed on the first surface 102 of the core substrate 100 to cover the semiconductor chip 200. The sealing layer 130 may be formed to fill the gap between the sidewall of the semiconductor chip 200 and the inner sidewall of the cavity 106. Therefore, the sealing layer 130 may cover the back side 204 of the semiconductor chip 200, the first surface 102 of the core substrate 100, and the inner sidewall of the cavity 106.

[0089] For example, the sealing layer 130 may include a thermosetting insulating material such as epoxy resin, a photoimageable dielectric (PID) material, an insulating film such as Ajinomoto laminated film (ARF), etc. In the case where the sealing layer 130 includes an insulating film such as ABF, the sealing layer 130 may be formed by a lamination process.

[0090] refer to Figure 8 , a redistribution wiring layer 300 may be formed on the second surface 104 of the core substrate 100 and the front side 202 of the semiconductor chip 200. The redistribution wiring layer 300 may include first redistribution wirings 302 electrically connected to the chip pads 210 and the core connection wirings 120 of the semiconductor chip 200, respectively. The redistribution wiring layer 300 may be a front redistribution wiring layer of a fan-out package.

[0091] For example, after removing the barrier tape 20, Figure 7 The structure in the embodiment is reversed, and the sealing layer 130 may be adhered to the first carrier substrate (not shown). Next, the first lower insulating layer 310 may be formed to cover the second surface 104 of the core substrate 100 and the front surface 202 of the semiconductor chip 200, and then the first lower insulating layer 310 is patterned to form an opening, which exposes the chip pad 210 of the semiconductor chip 200 and the first metal wiring 122 of the core connection wiring 120, respectively.

[0092] For example, the first lower insulating layer 310 may include a polymer layer, a dielectric layer, etc. The first lower insulating layer 310 may include a PID, an insulating film such as ABF, etc. The first lower insulating layer 310 may be formed by a vapor deposition process, a spin coating process, etc.

[0093] Then, first lower redistribution wirings 312 may be formed on the first lower insulating layer 310. The first lower redistribution wirings 312 may make contact with the chip pads 210 through the openings, respectively.

[0094] The first lower redistribution wiring 312 may be formed by forming a seed layer on a portion of the first lower insulating layer 310 and in the first opening, patterning the seed layer, and performing an electroplating process. Thus, at least portions of the first lower redistribution wiring 312 may contact the chip pad 210 and the first metal wiring 122 through the opening.

[0095] For example, the first lower redistribution wiring may include aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt), or an alloy thereof.

[0096] Similarly, a second lower insulating layer 320 may be formed on the first lower insulating layer 310, and then, the second lower insulating layer 320 may be patterned to respectively form openings exposing the first lower redistribution wirings 312. Then, second lower redistribution wirings 322 may be formed on the second lower insulating layer 320 to respectively contact the first lower redistribution wirings 312 through the openings.

[0097] Then, a third lower insulating layer 330 may be formed on the second lower insulating layer 320, and then, the third lower insulating layer 330 may be patterned to respectively form openings exposing the second lower redistribution wirings 322. Then, third lower redistribution wirings 332 may be formed on the third lower insulating layer 330 to respectively contact the second lower redistribution wirings 322 through the openings. Then, a fourth lower insulating layer 340 may be formed on the third lower insulating layer 330 to expose portions of the third lower redistribution wirings 332.

[0098] The fourth lower insulating layer 340 may be used as a passivation layer. As described below, the fourth lower insulating layer 340 may be partially removed by a subsequent via formation process to expose portions of the third lower redistribution wiring 332. In addition, a bump pad (not shown) such as a UBM (under bump metal) may be formed on the portion of the third lower redistribution wiring 332 exposed by the fourth lower insulating layer 340.

[0099] The fourth lower insulating layer 340 may include a photoimageable dielectric (PID) material, an insulating film such as ABF, etc. The fourth lower insulating layer may include the same or different material as the first to third lower insulating layers.

[0100] Reference Fig. 9 , an upper redistribution wiring layer 350 may be formed on the first surface 102 of the core substrate 100 and the sealing layer 130 on the back side 204 of the semiconductor chip 200. The upper redistribution wiring layer 350 may include a second redistribution wiring 352 electrically connected to the core connection wiring 120. The upper redistribution wiring layer 350 may be a back side redistribution wiring layer of a fan-out package.

[0101] For example, after removing the first carrier substrate, the redistribution wiring layer 300 may be adhered to a second carrier substrate (not shown). Then, after the sealing layer 130 on the first surface 102 of the core substrate 100 is partially removed to form an opening exposing the third metal wiring 126 of the core connection wiring 120, a first upper redistribution wiring 362 may be formed on the sealing layer 130. The first upper redistribution wiring 362 may be electrically connected to the core connection wiring 120 through the opening.

[0102] Then, a first upper insulating layer 360 may be formed on the sealing layer 130 to cover the first upper redistribution wiring 362, and then, the first upper insulating layer 360 may be patterned to form openings respectively exposing the first upper redistribution wiring 362. Then, second upper redistribution wirings 372 may be formed on the first upper insulating layer 360 to contact the first upper redistribution wirings 362 through the openings, respectively.

[0103] Then, the second upper insulating layer 370 may be formed on the first upper insulating layer 360 to cover the second upper redistribution wirings 372 , and then, the second upper insulating layer 370 may be patterned to form openings 371 exposing the second upper redistribution wirings 372 , respectively.

[0104] The second upper insulating layer 370 may serve as a passivation layer. Through a subsequent pad formation process, a bump pad (not shown) such as UBM (Under Bump Metal) may be formed on a portion of the second upper redistribution wiring 372 exposed by the second upper insulating layer 370 .

[0105] For example, the first and second upper insulating layers may include a thermosetting insulating material (eg, epoxy resin), a photoimageable dielectric (PID) material, an insulating film (eg, ABF), or the like.

[0106] Reference Figures 10 to 18 , the external connection member 400 and the capacitor 420 may be mounted on the outer surface of the redistribution wiring layer 300 .

[0107] like Fig.10 and Fig.11 As shown, the fourth lower insulating layer 340 may be patterned to form openings 341 , 343 respectively exposing portions of the third lower redistribution wirings 332 .

[0108] The opening may include a first through hole 341 for electrical connection with the solder ball pad and a second through hole 343 for electrical connection with the capacitor pad. The second through hole 343 may include a pair of second through holes 343a, 343b.

[0109] like Fig.12 As shown, the second through holes 343a, 343b may be arranged in the first direction to be spaced apart from each other. The three second through holes 343a may be arranged in the second direction perpendicular to the first direction to be spaced apart from each other. The three second through holes 343b may be arranged in the second direction to be spaced apart from each other.

[0110] The diameter of each second through hole 343a, 343b may be smaller than the diameter of the first through hole 341. For example, the diameter of each second through hole 343a, 343b may be in the range of 50 μm to 200 μm. The diameter of the first through hole 341 may be in the range of 150 μm to 250 μm. The spacing between the second through holes 343a in the second direction and the spacing between the second through holes 343b in the second direction may be in the range of 250 μm to 450 μm.

[0111] The second vias 343a, 343b may be formed in the fourth lower insulation layer 340. In some example embodiments, the second vias 343a, 343b may be formed in the fourth and third lower insulation layers 340, 330 to expose a portion of the second lower redistribution wiring 322. In some other example embodiments, the second vias 343a, 343b may be formed in the fourth to second lower insulation layers 340, 330, 320 to expose a portion of the first lower redistribution wiring 312.

[0112] like Fig.13 As shown, a seed layer 20 may be formed on the fourth lower insulating layer 340 , and a photoresist pattern 30 having openings 31 exposing portions of the seed layer 20 on the third lower redistribution wiring 332 may be formed on the seed layer 20 .

[0113] For example, the seed layer 20 may include an alloy layer including titanium / copper (Ti / Cu), titanium / palladium (Ti / Pd), titanium / nickel (Ti / Ni), chromium / copper (Cr / Cu), or a combination thereof. The seed layer 20 may be formed by a sputtering process.

[0114] A photoresist layer may be formed on the fourth lower insulating layer 340 to cover the seed layer 20. For example, the thickness of the photoresist layer may be in the range of 5 μm to 25 μm. The thickness of the photoresist layer may be determined by considering the thickness of the UBM pad and the like.

[0115] Then, an exposure process may be performed on the photoresist layer to form a photoresist pattern 30 having openings 32 exposing the solder ball pad region and the capacitor pad region.

[0116] like Figures 14 to 16 As shown, an electroplating process may be performed on the seed layer 20 to form a solder ball pad 342 and a pair of capacitor pads 344. Then, the photoresist pattern 30 may be removed and the seed layer 20 under the photoresist pattern 30 may be partially removed to form a seed layer pattern 22.

[0117] The pair of capacitor pads 344 may include a first capacitor pad 344 a and a second capacitor pad 344 b. Each of the first and second capacitor pads 344 a, 344 b may include a pad pattern 346 and at least one via pattern 348 .

[0118] The pad pattern 346 may be exposed from the fourth lower insulating layer 340. A via pattern 348 may be formed in each of the second via holes 343a, 343b. The via pattern 348 may extend downward from the pad pattern 346 to contact the third lower redistribution wiring 332. The pad pattern 346 may be electrically connected to the third lower redistribution wiring 332 through the via pattern 348.

[0119] Because the seed layer 20 is conformally formed on a portion of the fourth lower insulating layer 340 and on the exposed portion of the third lower redistribution wiring 332, the pad pattern 346 may have a pit 347 at an upper portion of the via pattern 348. The diameter of the pit 347 may be substantially equal to or smaller than the diameter of the via pattern 348. The depth of the pit 347 may be equal to or smaller than the thickness of the via pattern 348.

[0120] like Fig.16 As shown, the first capacitor pad 344a may include three through-hole patterns 348 connected to one pad pattern 346. The second capacitor pad 344b may include three through-hole patterns 348 connected to one pad pattern 346. In addition, the pad pattern 346 may have a shape corresponding to the shape of the first and second external electrodes of the capacitor mounted thereon. For example, the pad pattern 346 may have a rectangular pad shape having a first side (relatively long side) and a second side (relatively short side).

[0121] The three via patterns 348 may be positioned to be off-center by a desired (or alternatively, predetermined) distance P from a center line ML of the land pattern 346 . The center line ML may pass through a midpoint of a short side of the land pattern 346 .

[0122] For example, the length of the pad pattern 346 in the extension direction of the short side, that is, the width W of the pad pattern 346 may be in the range of 150 μm to 500 μm. The length of the pad pattern 346 in the extension direction of the long side, that is, the length L of the pad pattern 346 may be in the range of 600 μm to 1200 μm. The diameter of the through hole pattern 348 may be 40% or less of the width W of the pad pattern 346. The diameter of the through hole pattern 348 may be in the range of 50 μm to 200 μm.

[0123] The pad patterns 346 of the pair of capacitor pads 344 may be spaced apart from each other in the first direction. A spacing Q between the pad patterns 346 in the first direction may be in the range of 130 μm to 300 μm.

[0124] The three via patterns 348 may be spaced apart from each other along an extending direction (eg, the second direction) of the relatively long sides of the pad pattern 346. A pitch between the via patterns 348 in the second direction may be in a range of 250 μm to 450 μm.

[0125] The diameter of the solder ball pad 342 may be greater than the width W of the pad pattern 346. The diameter of the solder ball pad 342 may be in the range of 160 μm to 260 μm.

[0126] like Fig.17 and 18 As shown, the external connection members 400 may be respectively disposed on the solder ball pads 342 and the capacitors 420 may be mounted on a pair of capacitor pads 344 .

[0127] For example, a conductive paste 410 such as solder paste may be applied to the first and second capacitor pads 344a, 344b, a flux may be applied to the solder ball pad 342, and then an external connection member such as a solder ball 400 may be provided. Then, the first and second external electrodes 422a, 422b of the capacitor 420 may be attached to the first and second capacitor pads 344a, 344b via the conductive paste 410.

[0128] After attaching the first and second external electrodes 422a, 422b of the capacitor 420 to the first and second capacitor pads 344a, 344b, a reflow process may be performed to attach the first and second external electrodes 422a, 422b to the first and second capacitor pads 344a, 344b. During the reflow process, the solder paste generates flux gas, and a portion of the generated gas forms a void 412 in the conductive paste on the recess 347.

[0129] Since the via pattern 348 is eccentric from the center of the pad pattern 346, the generated flux gas may move to the edge of the pad pattern 346 and may escape easily. In addition, since the via pattern 348 has a relatively small diameter, the void may be reduced or prevented from growing in a large size over the via pattern 348. Therefore, the phenomenon that the flux gas is gathered in the center of the void pad pattern 346 may be reduced or prevented, and the void 412 may be formed in a small size at the edge portion of the pad pattern 346 rather than in the center.

[0130] Then, the core substrate 100 may be subjected to a sawing process to form individual fan-out panel level packages including the core substrate 100 , the redistribution wiring layer 300 formed on the lower surface of the core substrate 100 , and the capacitor 420 mounted on the outer surface of the redistribution wiring layer 300 .

[0131] Fig.19is a cross-sectional view illustrating a portion of a semiconductor package according to some example embodiments. Fig. 20 It shows Fig.19 A plan view of the first and second capacitor pads in FIG. 1 is shown in FIG. 1 . Except for the arrangement of the through hole pattern, the semiconductor package can be similar to the reference Figure 1 The semiconductor packages described are the same or substantially similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated description regarding the above elements will be omitted.

[0132] In some example embodiments, the pad pattern 346 of the first capacitor pad 344a and the pad pattern 346 of the second capacitor pad 344b may be spaced apart from each other in the first direction (X direction). The three through-hole patterns 348 may be positioned to be eccentrically required (or alternatively, predetermined) distance P from the center line ML of the pad pattern 346. The center line ML may pass through the midpoint of the short side of the pad pattern 346. The three through-hole patterns 348 may be spaced apart along the extension direction (e.g., the second direction (Y direction)) of the relatively long side of the pad pattern 346. The pad pattern 346 of the first capacitor pad 344a may have two relatively long sides S1a, S2a, and the pad pattern 346 of the second capacitor pad 344b may have two relatively long sides S1b, S2b.

[0133] In some example embodiments, the pad pattern 346 of the first capacitor pad 344a and the pad pattern 346 of the second capacitor pad 344b may have sides S2a and S1b located relatively close to each other. The pad pattern 344 of the first capacitor pad 344a and the pad pattern 344 of the second capacitor pad 344b may have sides S1a and S2b located relatively far from each other.

[0134] The three via patterns 348 of the first capacitor pad 344a may be positioned eccentrically toward the side S1a of the pad pattern 344, which is positioned relatively far from the pad pattern 344 of the second capacitor pad 344b. That is, the three via patterns 348 of the first capacitor pad 344a may be arranged adjacent to the side S1a.

[0135] The three via patterns 348 of the second capacitor pad 344b may be positioned eccentrically toward the side S2b of the pad pattern 344, which is positioned relatively far from the pad pattern 344 of the first capacitor pad 344a. That is, the three via patterns 348 of the second capacitor pad 344b may be arranged adjacent to the side S2b.

[0136] Fig.21 is a cross-sectional view illustrating a semiconductor package according to some example embodiments. Fig. 22 It is shown Fig.21In addition to the additional second package, the semiconductor package can be the same as the reference Figure 1 The semiconductor packages described are the same or substantially similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated description regarding the above elements will be omitted.

[0137] Reference Fig.21 , the semiconductor package 11 may include a first package and a second package 600 stacked on the first package. The semiconductor package 11 may also include a heat sink 700 disposed on the second package 600. The first package may include a core substrate 100, a semiconductor chip 200, a redistribution wiring layer 300, and an upper redistribution wiring layer 350. The first package may be similar to the reference Figure 1 The unit packages described are the same or substantially similar.

[0138] In some example embodiments, the second package 600 may be stacked on the first package through the conductive connecting member 650 .

[0139] The second package 600 may include a second package substrate 610 , second and third semiconductor chips 620 , 630 mounted on the second package substrate 610 , and a molding member 642 on the second package substrate 610 to cover the second and third semiconductor chips 620 , 630 .

[0140] The second package 600 may be stacked on the first package via a conductive connection member 650. For example, the conductive connection member 650 may include a solder ball, a conductive bump, etc. The conductive connection member 650 may be disposed between the second upper redistribution wiring 386 of the upper redistribution wiring layer 350 and the second bonding pad 614 of the second package substrate 610. Therefore, the first package and the second package 600 may be electrically connected to each other through the conductive connection member 650.

[0141] The second and third semiconductor chips 620, 630 may be stacked on the second package substrate 610 by an adhesive member. The bonding wires 640 may electrically connect the chip pads 622, 632 of the second and third semiconductor chips 620, 630 to the first bonding pads 612 of the second package substrate 610. The second and third semiconductor chips 620, 630 may be electrically connected to the second package substrate 610 by the bonding wires 640.

[0142] Although the second package 600 including two semiconductor chips mounted in a wire bonding manner is shown in the figure, it is understandable that the number and mounting manner of the semiconductor chips of the second package may not be limited thereto.

[0143] In some example embodiments, the heat sink 700 may be disposed on the second package 600 to dissipate heat from the first package and the second package to the outside. The heat sink 700 may be attached to the second package 600 through a thermal interface material (TIM) 710.

[0144] Reference Fig. 22 , the first package may include at least one capacitor 420 mounted on the outer surface of the redistribution wiring layer 300. The capacitor 420 may be mounted on a pair of capacitor pads 344. The first and second external electrodes 422a, 422b of the capacitor 420 may be attached to the first and second capacitor pads 344a, 344b, respectively, by a conductive paste 410. The pair of capacitor pads may be connected to the reference Figures 1 to 4 The capacitor pads described are the same or substantially similar. Therefore, the description of the capacitor pads will be omitted.

[0145] Fig.23 is a cross-sectional view showing a semiconductor package according to some example embodiments. In addition to providing a configuration in which a mold substrate is provided instead of a core substrate, the semiconductor package may be similar to the configuration of the reference Figure 1 The semiconductor packages described are the same or substantially similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated description regarding the above elements will be omitted.

[0146] Reference Fig.23 , the semiconductor package 12 may include a redistribution wiring layer 300, at least one semiconductor chip 200 arranged on the redistribution wiring layer 300, a mold substrate 500 on an upper surface of the redistribution wiring layer 300 to cover at least one surface of the semiconductor chip 200, and at least one capacitor 420 mounted on a lower surface of the redistribution wiring layer 300. In addition, the semiconductor package 12 may further include a backside redistribution wiring layer 350 arranged on an upper surface 502 of the mold substrate 500 and an external connection member 400 arranged on a lower surface of the redistribution wiring layer 300.

[0147] In some example embodiments, the semiconductor chip 200 may include a plurality of chip pads 210 on an active surface (eg, first surface) of the semiconductor chip 200. The semiconductor chip 200 may be accommodated in the mold substrate 500 such that the first surface on which the chip pads 210 are formed faces the redistribution wiring layer 300.

[0148] In some example embodiments, a conductive connection pillar 550 may be provided in a region outside the semiconductor chip 200 to penetrate at least a portion of the mold substrate 500. The conductive connection pillar 550 may be a mold through via (MTV) extending from the upper surface 502 to the lower surface 504 of the mold substrate 500.

[0149] The redistribution wiring layer 300 may be disposed on the lower surface 504 of the mold substrate 500 and may have first redistribution wirings 302 respectively electrically connected to the chip pads 210 of the semiconductor chip 200. The upper redistribution wiring layer 350 may be disposed on the upper surface 502 of the mold substrate 500 and may have second redistribution wirings 352 respectively electrically connected to the conductive connection pillars 550.

[0150] The capacitor 420 may be mounted on a pair of capacitor pads disposed on an outer surface of the redistribution wiring layer 300. The pair of capacitor pads may be connected to the reference Figures 1 to 4 The capacitor pads described are the same or substantially similar. Therefore, the description of the capacitor pads will be omitted.

[0151] In the following, the manufacturing Fig.23 A method for semiconductor packaging.

[0152] Figures 24 to 30 are cross-sectional views illustrating stages of a method of manufacturing a semiconductor package according to some example embodiments.

[0153] Reference Fig.24 , a seed layer 50 and a photoresist pattern 40 having an opening 41 for forming a conductive connector may be formed on the first carrier substrate C1.

[0154] In some example embodiments, the first carrier substrate C1 may include a wafer substrate. The wafer substrate W may be used as a base substrate on which a plurality of semiconductor chips are arranged and a molding member will be formed to cover the semiconductor chips. The wafer substrate may have a shape corresponding to a wafer on which a semiconductor manufacturing process is performed.

[0155] The wafer substrate may include a redistribution wiring region on which a redistribution wiring layer is formed and a scribe region (i.e., a cutting region surrounding the redistribution wiring region). As described below, the redistribution wiring layer and the molding member formed on the wafer substrate may be sawn apart along the cutting region dividing the redistribution wiring region to be singulated.

[0156] For example, the seed layer 50 may be formed by a sputtering process. The seed layer may include an alloy layer including titanium / copper (Ti / Cu), titanium / palladium (Ti / Pd), titanium / nickel (Ti / Ni), chromium / copper (Cr / Cu), or a combination thereof.

[0157] After a photoresist layer is formed on the seed layer 50 , an exposure process may be performed on the photoresist layer to form a photoresist pattern 40 having an opening 41 .

[0158] Reference Fig.25 and Fig.26, an electroplating process may be performed on the seed layer 50 to form a conductive connection column 550 as a conductive connector, the photoresist pattern 40 may be removed, and then, the seed layer 50 under the photoresist pattern 40 may be partially etched.

[0159] Reference Fig. 27 , the semiconductor chip 200 may be arranged on the first carrier substrate C1, and the mold substrate 500 may be formed to cover the semiconductor chip 200. The semiconductor chip 200 may be arranged on the first carrier substrate C1 so that the front side on which the chip pad 210 is formed faces the first carrier substrate C1. For example, the height of the semiconductor chip 200 may be less than the height of the conductive connection pillar 550.

[0160] The mold substrate 500 may be formed on the first carrier substrate C1 to cover the semiconductor chip 200 and the plurality of conductive connection pillars 550. For example, the mold substrate 500 may include epoxy molding compound (EMC). The mold substrate 500 may be formed by a molding process, a screen printing process, a lamination process, etc.

[0161] refer to Fig.28 , can be executed with reference Figure 8 The same or similar process as described above is used to form a redistribution wiring layer 300 on the lower surface 504 of the mold substrate 500 and the front side 202 of the semiconductor chip 200. The redistribution wiring layer 300 may have first redistribution wirings 302 electrically connected to the chip pads 210 and the conductive connection pillars 550 of the semiconductor chip 200, respectively.

[0162] refer to Fig.29 , can be executed with reference Fig. 9 The same or similar processes are described to form the upper redistribution wiring layer 350 on the upper surface 502 of the molded substrate 500 .

[0163] Reference Fig.30 , can be executed and referenced Figures 10 to 18 The same or similar processes are described to arrange the external connection members 400 and the capacitors 420 on the outer surface of the redistribution wiring layer 300 .

[0164] Then, the redistribution wiring layer 300 and the mold substrate 500 may be cut through a sawing process to form individual semiconductor packages.

[0165] Fig.31 is a cross-sectional view showing a semiconductor package according to some example embodiments. In addition to providing a configuration in which a mold substrate is provided instead of a core substrate, the semiconductor package may be similar to the configuration of the reference Fig.21 The semiconductor packages described are the same or substantially similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated description regarding the above elements will be omitted.

[0166] Reference Fig.31 , the semiconductor package 13 may include a first package and a second package 600 stacked on the first package. The first package may be Fig.23 The unit packages described are the same or substantially similar.

[0167] In some example embodiments, a conductive connection pillar 550 may be provided in a region outside the semiconductor chip 200 to penetrate at least a portion of the mold substrate 500. The conductive connection pillar 550 may be a mold through via (MTV) extending from the upper surface 502 to the lower surface 504 of the mold substrate 500.

[0168] The semiconductor package may include a semiconductor device such as a logic device or a memory device. The semiconductor package may include a logic device (e.g., a central processing unit (CPU), a main processing unit (MPU), or an application processor (AP), etc.), and a volatile memory device (e.g., a DRAM device, an HBM device) or a non-volatile memory device (e.g., a flash memory device, a PRAM device, an MRAM device, a ReRAM device, etc.).

[0169] The foregoing is an illustration of some exemplary embodiments and should not be construed as limiting thereof. Although some exemplary embodiments have been described, it will be readily appreciated by those skilled in the art that a variety of modifications may be made in the disclosed exemplary embodiments without substantially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments as defined in the claims.

Claims

1. A semiconductor package, comprising: Core substrate; at least one semiconductor chip located in the core substrate, the at least one semiconductor chip having a chip pad; a redistribution wiring layer covering a lower surface of the core substrate, the redistribution wiring layer comprising redistribution wirings electrically connected to the chip pads and a pair of capacitor pads, the chip pads and the pair of capacitor pads being exposed from an outer surface of the redistribution wiring layer and being electrically connected to corresponding ones of the redistribution wirings, respectively; Conductive paste, respectively located on the capacitor pads; as well as A capacitor is located on a pair of capacitor pads via the conductive paste, the capacitor having a first external electrode and a second external electrode, the first external electrode and the second external electrode are respectively located on the capacitor pads, Wherein, each of the capacitor pads comprises: a pad pattern exposed from an outer surface of the redistribution wiring layer, and at least one through-hole pattern located at a lower portion of the pad pattern, the at least one through-hole pattern being electrically connected to at least one of the redistribution wirings, wherein the through hole pattern is offset from the center line of the pad pattern by a certain distance, and The pad pattern has a concave pit on the upper portion of the through hole pattern.

2. The semiconductor package according to claim 1, wherein A diameter of the via pattern is 40% or less of a width of the land pattern.

3. The semiconductor package according to claim 1, wherein: A width of the land pattern is in a range of 150 μm to 500 μm, and a diameter of the via pattern is in a range of 50 μm to 200 μm.

4. The semiconductor package according to claim 1, wherein: The land pattern is a rectangular land having a first side and a second side, and the center line passes through a midpoint of the second side of the land pattern.

5. The semiconductor package according to claim 4, wherein: At least three through hole patterns are arranged along an extending direction of the first side and are spaced apart from each other.

6. The semiconductor package according to claim 5, wherein: A pitch between the through hole patterns in an extending direction of the first side is in a range of 250 μm to 450 μm.

7. The semiconductor package according to claim 1, wherein: At least one of the conductive pastes has a gap above the recess.

8. The semiconductor package according to claim 1, wherein The redistribution wiring layer further includes solder ball pads exposed from an outer surface of the redistribution wiring layer.

9. The semiconductor package according to claim 8, wherein: A diameter of the solder ball pad is greater than a width of the pad pattern.

10. A semiconductor package, comprising: A redistribution wiring layer having a first surface and a second surface opposite to each other, the redistribution wiring layer comprising at least two layers of stacked redistribution wirings, a pair of capacitor pads exposed from the second surface and electrically connected to a corresponding pair of redistribution wirings in the redistribution wirings, respectively; at least one semiconductor chip located on the first surface of the redistribution wiring layer, the at least one semiconductor chip having chip pads electrically connected to corresponding ones of the redistribution wirings, respectively; a molded substrate, located on the redistribution wiring layer and covering the semiconductor chip; Conductive paste, respectively located on the capacitor pads; as well as A capacitor is located on a pair of capacitor pads via the conductive paste, the capacitor having a first external electrode and a second external electrode, the first external electrode and the second external electrode are respectively located on the capacitor pads, Wherein, each of the capacitor pads comprises: a pad pattern exposed from the second surface of the redistribution wiring layer, and at least one through-hole pattern located at a lower portion of the pad pattern, the at least one through-hole pattern being electrically connected to at least one of the redistribution wirings, The through hole pattern is offset from the center line of the pad pattern by a certain distance. wherein the diameter of the through hole pattern is 40% or less of the width of the pad pattern, and The pad pattern has a concave pit on the upper portion of the through hole pattern.

11. The semiconductor package according to claim 10, wherein: A width of the land pattern is in a range of 150 μm to 500 μm, and a diameter of the via pattern is in a range of 50 μm to 200 μm.

12. The semiconductor package according to claim 10, wherein: The land pattern is a rectangular land having a first side and a second side, and the center line passes through a midpoint of the second side of the land pattern.

13. The semiconductor package according to claim 12, wherein: At least three through hole patterns are arranged along an extending direction of the first side and are spaced apart from each other.

14. The semiconductor package according to claim 13, wherein: A pitch between the through hole patterns in an extending direction of the first side is in a range of 250 μm to 450 μm.

15. The semiconductor package according to claim 10, wherein A pitch between the through hole pattern of one of the capacitor pads and the through hole pattern of another of the capacitor pads is in a range of 130 μm to 300 μm.

16. The semiconductor package according to claim 10, wherein At least one of the conductive pastes has a gap above the recess.

17. The semiconductor package according to claim 10, wherein: The redistribution wiring layer further includes a solder ball pad exposed from the second surface of the redistribution wiring layer, and A diameter of the solder ball pad is greater than a width of the pad pattern.

18. The semiconductor package according to claim 10, further comprising: a conductive connection column penetrating through at least a portion of the mold substrate and electrically connected to a corresponding redistribution wiring among the redistribution wirings; as well as A second package is stacked on the molded substrate and electrically connected to the conductive connection pillar.

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