Passive filter and preparation method thereof

Abstract

The present disclosure provides a passive filter and a preparation method thereof, belonging to the field of radio frequency device technology. The present disclosure provides a passive filter, which includes: a dielectric substrate, at least one capacitor, and at least one inductor. The dielectric substrate includes a slot arranged along the thickness direction of the dielectric substrate, and the inner wall of the slot includes a first part, and the extension direction of the tangent of at least some points on the first part intersects with the extension direction of the plane where the dielectric substrate is located. The capacitor includes a first electrode, a first interlayer dielectric layer, and a second electrode, which are arranged in sequence away from the direction of the dielectric substrate. The first electrode of the capacitor, the second electrode of the capacitor, and the first interlayer dielectric layer have overlapping orthographic projections on the dielectric substrate, covering at least the first part.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of radio frequency devices, and particularly relates to a passive filter and a preparation method thereof. Background Art

[0002] The consumer electronics industry is rapidly evolving, with mobile communication terminals, particularly 5G phones, experiencing rapid growth. Mobile phones are required to process an increasing number of signal frequency bands, and the number of RF chips required is also increasing. Consumers are increasingly favoring mobile phone designs that are miniaturized, lightweight, and have longer battery life. Traditional mobile phones often feature a large number of discrete components on RF PCBs, such as resistors, capacitors, inductors, and filters. These components suffer from large size, high power consumption, numerous solder joints, and significant parasitic parameter variation, making them difficult to meet future demands. The interconnection and matching between RF chips require integrated passive components that are compact, high-performance, and highly consistent. Currently, the integrated passive components on the market are primarily based on Si (silicon) and GaAs (gallium arsenide) substrates. Si-based integrated passive components offer the advantage of low cost, but inherent trace impurities (poor insulation) in Si lead to high microwave loss and mediocre performance. GaAs-based integrated passive components offer excellent performance but are expensive. Summary of the Invention

[0003] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a passive filter and a preparation method thereof.

[0004] In a first aspect, the present disclosure provides a passive filter comprising: a dielectric substrate, at least one capacitor, and at least one inductor; the dielectric substrate comprising a slot arranged along the thickness direction of the dielectric substrate; an inner wall of the slot comprising a first portion, wherein a tangent line of at least some points on the first portion extends in a direction intersecting with an extension direction of a plane on which the dielectric substrate is located; the capacitor comprising a first plate, a first interlayer dielectric layer, and a second plate, arranged in sequence away from the dielectric substrate; the overlapping portion of the orthographic projections of the first plate of the capacitor, the second plate of the capacitor, and the first interlayer dielectric layer on the dielectric substrate at least covering the first portion.

[0005] The dielectric substrate further includes a first connecting via extending through the dielectric substrate along its thickness direction, and a first surface and a second surface disposed opposite each other along the thickness direction; the inductor includes a first substructure disposed on the first surface of the dielectric substrate, a second substructure disposed on the second surface of the dielectric substrate, and a first connecting electrode disposed within the first connecting via, wherein the first connecting electrode connects the first substructure and the second substructure; and the inductor is electrically connected to the capacitor.

[0006] There are multiple inductors, and the multiple inductors include a first inductor and a second inductor; the passive filter includes a first conductive layer; the first conductive layer includes a first substructure of the first inductor, a first substructure of the second inductor, and a first plate of the capacitor; the passive filter includes a second conductive layer; the second conductive layer includes a second substructure of the first inductor and a second substructure of the second inductor; and the first lead end of the first inductor is connected to the first plate of the capacitor, and the second lead end of the second inductor is connected to the first plate of the capacitor.

[0007] The orthographic projection of the first interlayer dielectric layer on the dielectric substrate covers the orthographic projections of the first substructure and the first plate of the capacitor on the dielectric substrate. The passive filter further comprises: a second interlayer dielectric layer disposed on a side of the first interlayer dielectric layer and the second plate of the capacitor facing away from the dielectric substrate; a third interlayer dielectric layer disposed on a side of the second interlayer dielectric layer facing away from the dielectric substrate; and a first connecting pad, a second connecting pad, and a third connecting pad disposed on a side facing away from the second dielectric layer. The first connecting pad is connected to the second lead end of the first inductor via a second connecting via penetrating the first interlayer dielectric layer and the second interlayer dielectric layer; the second connecting pad is connected to the first lead end of the second inductor via a third connecting via penetrating the first interlayer dielectric layer and the second interlayer dielectric layer; and the third connecting pad is connected to the second plate of the capacitor via a fourth connecting via penetrating the second interlayer dielectric layer.

[0008] Wherein, the slot is a blind slot.

[0009] The blind grooves include hemispherical blind grooves, cylindrical blind grooves and cubic blind grooves.

[0010] The overlapping portion of the orthographic projections of the first electrode plate of the capacitor, the second electrode plate of the capacitor, and the first interlayer dielectric layer on the dielectric substrate completely covers the inner wall of the groove.

[0011] Wherein, the dielectric substrate includes a glass base or a silicon base.

[0012] In a second aspect, the present disclosure further provides a method for preparing a passive filter, the method comprising: providing a dielectric substrate, the dielectric substrate comprising a slot arranged along the thickness direction of the dielectric substrate; an inner wall of the slot comprising a first portion, wherein an extension direction of a tangent line of at least some points on the first portion intersects an extension direction of a plane on which the dielectric substrate is located; forming at least one capacitor and at least one inductor; the step of forming the capacitor comprising: sequentially forming a first plate of the capacitor, a first interlayer dielectric layer, and a second plate of the capacitor on a side facing away from the dielectric substrate; wherein the overlapping portion of the orthographic projections of the first plate of the capacitor, the second plate of the capacitor, and the first interlayer dielectric layer on the dielectric substrate covers the first portion.

[0013] The slot includes a blind slot; the dielectric substrate includes a first surface and a second surface oppositely disposed along its thickness direction; and providing a dielectric substrate includes: forming the blind slot on the first surface of the dielectric substrate along its thickness direction.

[0014] Wherein, providing a dielectric substrate further comprises: forming a first connecting via hole in the dielectric substrate along the thickness direction thereof.

[0015] The first connecting via and the groove are formed by an etching process.

[0016] The step of forming the first connecting via and the blind groove includes: performing laser modification on the dielectric substrate; so that the dielectric substrate can be simultaneously isotropically etched and anisotropically etched during a single etching process; and forming the groove and the first connecting via by a single etching process.

[0017] The step of forming at least one of the inductors further includes forming a first inductor and a second inductor; the steps of forming the first inductor and the second inductor include: forming a first connecting electrode in the first connecting via; the dielectric substrate includes a first surface and a second surface disposed opposite to each other; forming a first substructure of the first inductor and a first substructure of the second inductor on the first surface of the dielectric substrate; forming a second substructure of the first inductor and a second substructure of the second inductor on the second surface of the dielectric substrate; the first substructure of the first inductor, the second substructure of the first inductor, and the first connecting electrode forming a coil structure of the first inductor; and the first substructure of the second inductor, the second substructure of the second inductor, and the first connecting electrode forming a coil structure of the second inductor.

[0018] The preparation method further includes: forming a second interlayer dielectric layer on the side of the dielectric substrate away from the first surface, and forming a second connecting via and a third connecting via penetrating the first interlayer dielectric layer and the second interlayer dielectric layer, and a fourth connecting via penetrating the second interlayer dielectric layer; forming a third interlayer dielectric layer on the side of the dielectric substrate away from the second surface;

[0019] The method for preparing the substrate further includes: forming a first connecting pad, a second connecting pad, and a third connecting pad on a side away from the second interlayer dielectric layer;

[0020] The first connecting pad is connected to the first substructure of the first inductor through the second connecting via penetrating the first interlayer dielectric layer and the second interlayer dielectric layer; the second connecting pad is connected to the first substructure of the second inductor through the third connecting via penetrating the first interlayer dielectric layer and the second interlayer dielectric layer; the third connecting pad is connected to the second plate of the capacitor through the fourth connecting via penetrating the second interlayer dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A cross-sectional schematic diagram of a passive filter according to an embodiment of the present disclosure;

[0022] FIG2 is a schematic diagram of a capacitor according to an embodiment of the present disclosure;

[0023] Figure 3 is a schematic diagram of an inductor according to an embodiment of the present disclosure;

[0024] Figure 4 is a circuit diagram of a passive filter according to an embodiment of the present disclosure;

[0025] Figure 5 is a cross-sectional schematic diagram of an integrated filter according to an embodiment of the present disclosure;

[0026] Figure 6 Schematic diagram of the preparation process of the passive filter according to the embodiment of the present disclosure;

[0027] Figure 7 is a schematic diagram of step S10 of an embodiment of the present disclosure;

[0028] Figure 8 Schematic diagram of the preparation process of step S10 of the embodiment of the present disclosure;

[0029] Figure 9 and Figure 10 Schematic diagram of step S102 of an embodiment of the present disclosure;

[0030] Figure 11 is a schematic diagram of step S104 of an embodiment of the present disclosure;

[0031] Figure 12 Schematic diagram of step S11 of an embodiment of the present disclosure;

[0032] Figure 13 is a schematic diagram of step S12 of an embodiment of the present disclosure;

[0033] Figure 14 Schematic diagram of step S13 of an embodiment of the present disclosure;

[0034] Figure 15 Schematic diagram of step S14 of an embodiment of the present disclosure;

[0035] Figure 16 is a schematic diagram of step S15 of an embodiment of the present disclosure;

[0036] Figure 17 Schematic diagram of step S16 of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0038] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0039] The present disclosure provides a passive filter and a method for manufacturing the same. Figure 1 As shown, Figure 1The passive filter in the embodiment of the present disclosure is a schematic cross-sectional view. The passive filter in the embodiment of the present disclosure includes: a dielectric substrate 1, at least one capacitor C, and at least one inductor; the dielectric substrate 1 includes a slot 6 arranged along the thickness direction of the dielectric substrate 1; the inner wall of the slot 6 includes a first portion, and the extension direction of the tangent of at least some points on the first portion intersects the extension direction of the plane of the dielectric substrate 1; the capacitor C includes a first plate 2, a first interlayer dielectric layer 3, and a second plate 4, which are arranged in sequence away from the dielectric substrate 1; the orthographic projections of the first plate 2, the second plate 4, and the first interlayer dielectric layer 3 of the capacitor C on the dielectric substrate 1 overlap, covering at least the first portion.

[0040] Specifically, refer to Figure 1 In the embodiment of the present disclosure, since the slot 6 is provided, and the tangent line of at least some points of the first portion of the inner wall of the slot 6 extends in a direction intersecting with the plane of the dielectric substrate 1, that is, the first portion of the slot 6 has a component perpendicular to the direction along the surface of the dielectric substrate 1. Figure 1 In the passive filter shown, the first portion, i.e., the first plate of the capacitor, covers the portion of the inner wall of the slot. The portion where the orthographic projections of the first plate 2, second plate 4, and first interlayer dielectric layer 3 of capacitor C overlap on the dielectric substrate 1 represents the portion where capacitor C accumulates charge during operation, i.e., the portion that actually forms the capacitor structure. When the portion that actually forms the capacitor structure covers the first portion of the inner wall of the slot 6, since the first portion has a component perpendicular to the surface of the dielectric substrate 1, capacitor C also has a component perpendicular to the surface of the dielectric substrate 1. When the capacitance value of capacitor C is constant, the presence of a component perpendicular to the thickness of the dielectric substrate 1 reduces the area occupied by capacitor C along the surface of the dielectric substrate 1 compared to the conventional method of placing capacitor C directly horizontally on the surface of the dielectric substrate 1. Because the area occupied by capacitor C along the surface of the dielectric substrate 1 is reduced, more capacitors C can be placed on a dielectric substrate 1 of the same size, thereby increasing the density of capacitors C in the passive filter. At the same time, for a capacitor C with a certain capacitance value, the area occupied by the capacitor C on the dielectric substrate 1 along its surface direction can be reduced, thereby reducing the overall size of the passive filter and improving the integration of the passive filter.

[0041] In some embodiments, continue to refer to Figure 1, the overlapping portion of the orthographic projections of the first plate 2 of capacitor C, the second plate 4 of capacitor C, and the first interlayer dielectric layer 3 on the dielectric substrate 1 completely covers the inner wall of the slot 6, and the inner wall of the slot at this time includes at least the first portion. In the embodiment of the present disclosure, the overlapping portion of the orthographic projections of the first plate 2, the second plate 4, and the first interlayer dielectric layer 3 of capacitor C on the dielectric substrate 1 is the portion where the charge of capacitor C accumulates during actual operation, that is, the portion that actually forms the capacitor structure, that is, the capacitor structure completely covers the inner wall of the slot 6. At this time, the structure of the slot 6 can be set, the surface area of ​​the slot 6 can be calculated based on the structure of the slot 6, and the surface area of ​​the first plate 2 and the second plate 4 of capacitor C can be calculated based on the surface area of ​​the slot 6, and finally the capacitance value of capacitor C can be calculated. In this way, the capacitance value of capacitor C in the passive filter can be set more simply. It should be noted that in some embodiments, multiple capacitors C can be set on the inner wall of the slot 6 according to the actual required capacitance value, and each of the multiple capacitors C completely covers the inner wall of the slot 6, which is also within the scope of protection of the embodiment of the present disclosure.

[0042] In some embodiments, as Figure 1 As shown, the slot 6 can be a blind slot. In this way, the possibility of short circuit between the capacitor C and the conductive structure provided on the surface of the dielectric substrate 1 is reduced. In some embodiments, the blind slot can include but is not limited to: a hemispherical blind slot, a cylindrical blind slot and a cubic blind slot. In the embodiment of the present disclosure, when the slot 6 is a hemispherical blind slot, the first part can be any part of the inner wall of the hemispherical blind slot, for example, the first part can be the entire structure of the inner wall of the hemispherical blind slot or a partial structure of the inner wall of the hemispherical blind slot; when the slot 6 is a cylindrical blind slot, the first part can include at least a part of the side wall of the cylindrical blind slot, for example, the first part can be the entire structure of the side wall and the bottom wall of the cylindrical blind slot, the entire structure of the side wall of the cylindrical blind slot and a partial structure of the bottom wall, or only a partial structure of the side wall of the cylindrical blind slot; when the slot 6 is a cubic blind slot, the first part can be at least a part of the side wall of the cubic blind slot. For example, the first portion can be the entire structure of the sidewalls and bottom wall of a cubic blind groove, the entire structure of the sidewalls and a portion of the bottom wall of a cubic blind groove, or only a portion of the sidewall structure of a cubic blind groove. It should be noted that the blind grooves in the disclosed embodiments are not limited to these. For example, they can also be irregularly shaped, indented blind grooves, all of which fall within the scope of protection of the disclosed embodiments. In some embodiments, the blind grooves on the dielectric substrate 1 can be hemispherical, which is a preferred solution. Blind grooves with this structure are simple to prepare. Therefore, the disclosed embodiments will only be described using a hemispherical blind groove on the dielectric substrate 1 as an example.

[0043] Specifically, refer to Figure 2A When the radius of the hemispherical blind groove is R, the surface area of ​​the hemispherical blind groove is S1=2πR 2Therefore, the capacitance value of the capacitor C that completely covers the inner wall of the slot 6 is C0=ε0*ε*2πR 2 / d, where d is the thickness of the dielectric layer, ε is the relative dielectric constant of the dielectric layer, and ε0 is the dielectric constant of vacuum. At this time, the area occupied by the capacitor C along the surface of the dielectric substrate 1 is S2 = πR 2 If there is no blind groove structure, refer to Figure 2B The capacitance value of the capacitor structure set in the region is C1=ε0*ε*πR 2 / d. Thus, in the disclosed embodiment, by completely covering the inner wall of the slot 6, the capacitance of the capacitor C is doubled while occupying the same area along the surface of the dielectric substrate 1. Therefore, for a capacitor C of a certain capacitance value, the area occupied by the capacitor C along the surface of the dielectric substrate 1 can be reduced by reducing the radius of the hemispherical blind slot, thereby reducing the overall size of the passive filter and improving the integration of the passive filter.

[0044] In some embodiments, the dielectric substrate 1 further includes a first connecting via 5 extending through the dielectric substrate 1 along its thickness, and a first surface and a second surface disposed opposite each other along the thickness direction. The inductor includes a first substructure 7 disposed on the first surface of the dielectric substrate 1, a second substructure 8 disposed on the second surface of the dielectric substrate 1, and a first connecting electrode 9 disposed within the first connecting via 5, wherein the first connecting electrode 9 connects the first substructure 7 and the second substructure 8. The inductor is electrically connected to the capacitor C.

[0045] Specifically, in the embodiments of this disclosure, refer to Figure 3 , Figure 3This is a top view of an inductor according to an embodiment of the present disclosure. Each first substructure 7 of the inductor extends along a first direction and is arranged side by side along a second direction; each second substructure 8 of the inductor extends along a third direction and is arranged side by side along the second direction. The first, second, and third directions are all different directions. In this embodiment, the first and second directions are perpendicular to each other, and the first and third directions intersect and are arranged non-perpendicularly. Of course, the extension directions of the first substructures 7 and the second substructures 8 can also be interchanged, and remain within the scope of protection of this embodiment. Furthermore, in this embodiment, an inductor comprising N first substructures 7 and N-1 second substructures 8 is used as an example for illustration, where N ≥ 2 and N is an integer. The first and second ends of each first substructure 7 at least partially overlap with the orthographic projection of a first connecting via 5 on the glass substrate. Furthermore, the first and second ends of each first substructure 7 correspond to different first connecting vias 5, meaning that the orthographic projections of one first substructure 7 and two first connecting vias 5 on the glass substrate at least partially overlap. At this time, the first end of the i-th second substructure 8 of the inductor is connected to the first end of the i-th first substructure 7 and the second end of the i+1-th first substructure 7 to form an inductor coil, where 1≤i≤N-1, and i is an integer.

[0046] It should be noted that the first lead end 10 is connected to the second end of the first first substructure 7 of the inductor, and the second lead end 11 is connected to the first end of the Nth first substructure 7. Furthermore, the first lead end 10 and the second lead end 11 can be arranged on the same layer as the second substructure 8 and made of the same material. In this case, the first lead end 10 can be connected to the second end of the first first substructure 7 through the first connecting via 5, and correspondingly, the second lead end 11 can be connected to the first end of the Nth first substructure 7 through the first connecting via 5.

[0047] In some embodiments, the passive filter includes multiple inductors, including a first inductor L1 and a second inductor L2. The passive filter includes a first conductive layer, which includes a first substructure 7 of the first inductor L1, a first substructure 7 of the second inductor L2, and a first plate 2 of the capacitor C. The passive filter also includes a second conductive layer, which includes a second substructure 8 of the first inductor L1 and a second substructure 8 of the second inductor L2. Furthermore, a first lead terminal 10 of the first inductor L1 is connected to the first plate 2 of the capacitor C, and a second lead terminal 11 of the second inductor L2 is connected to the first plate 2 of the capacitor C.

[0048] In the embodiments of the present disclosure, specific reference is made to Figure 4 , Figure 4 for Figure 1 A circuit diagram of a passive filter is shown in FIG. Figure 4, the passive filter at least includes a first inductor L1, a second inductor L2 and a capacitor C. Among them, the second lead end 11 of the first inductor L1 is connected to the signal input terminal Input, the first lead end 10 of the first inductor L1 is connected to the first plate 2 of the first capacitor C and the second lead end 11 of the second inductor L2. The second lead end 11 of the second inductor L2 is connected to the first lead end 10 of the first inductor L1 and the first plate 2 of the first capacitor C, and the first lead end 10 of the second inductor L2 is connected to the signal output terminal Output. The first plate 2 of the capacitor C is connected to the first lead end 10 of the first inductor L1 and the second lead end 11 of the second inductor L2, and the second plate 4 of the capacitor C is connected to the ground terminal GND. Through this connection method, the basic structure of the passive filter is realized. It should be noted that the passive filter disclosed in the present invention is only described by taking the first inductor L1, the second inductor L2 and the capacitor C as an example. Passive filters including passive components such as multiple inductors or multiple capacitors are also within the scope of protection of the present invention.

[0049] In the embodiment of the present disclosure, in order to explain more clearly Figure 4 The specific structure of the passive filter shown in FIG is described below. Figure 1 The passive filter includes a dielectric substrate 1, on which a capacitor C, a first inductor L1, and a second inductor L2 are integrated. The dielectric substrate 1 includes a blind slot and a first connecting via 5 arranged along its thickness, as well as a first surface and a second surface arranged opposite each other along its thickness. A first connecting electrode 9 is arranged in the first connecting via 5. A first conductive layer is provided on the first surface of the dielectric substrate 1, and a second conductive layer is provided on the second surface of the dielectric substrate 1. The first conductive layer includes a first substructure 7 of the first inductor L1, a first substructure 7 of the second inductor L2, and a first electrode plate 2 of the capacitor C. The second conductive layer includes a second substructure 8 of the second inductor L2 and a second substructure 8 of the first inductor L1. In this manner, the first substructure 7 of the first inductor L1, the first substructure 7 of the second inductor L2, and the first electrode plate 2 of the capacitor C are formed in a single patterning process, and the first substructure 7 of the first inductor L1 and the first substructure 7 of the second inductor L2 are also formed in a single patterning process. The first substructure 7 of the first inductor L1 and the second substructure 8 of the first inductor L1 are connected through the first connecting electrode 9 to form a Figure 3 The first substructure 7 of the second inductor L2 and the second substructure 8 of the second inductor L2 are formed by the first connecting electrode 9 as shown in FIG. Figure 3The inductor structure shown. The first lead end 10 of the first inductor L1 is connected to the first plate 2 of the capacitor C, and the second lead end 11 of the second inductor L2 is connected to the first plate 2 of the capacitor C. The first plate 2 of the capacitor C, the first interlayer dielectric layer 3, and the second plate 4 of the capacitor C are sequentially arranged on the side of the first surface of the dielectric substrate 1 facing away from the dielectric. The overlapping portion of the orthographic projections of the first plate 2, the first interlayer dielectric layer 3, and the second plate 4 of the capacitor C on the dielectric substrate 1 completely covers the inner wall of the blind groove.

[0050] In some embodiments, continue to refer to Figure 1 The orthographic projection of the first interlayer dielectric layer 3 on the dielectric substrate 1 covers the orthographic projections of the first substructure 7 and the first plate 2 of the capacitor C on the dielectric substrate 1. In this manner, the first interlayer dielectric layer 3 of the capacitor C serves as an interlayer insulating layer in the passive filter, protecting the first inductor L1, the second inductor L2, and the capacitor C from corrosion by water and oxygen. The passive filter further includes: a second interlayer dielectric layer 12 disposed on the side of the first interlayer dielectric layer 3 and the second plate 4 of the capacitor C facing away from the dielectric substrate 1; a third interlayer dielectric layer 13 disposed on the side of the second interlayer dielectric layer 12 facing away from the dielectric substrate 1; and a first connection pad 14, a second connection pad 15, and a third connection pad 16 disposed on the side facing away from the second dielectric layer. The second interlayer dielectric layer 12 and the third interlayer dielectric layer 13 serve as a planarization layer located on the first surface side of the dielectric substrate 1 and a planarization layer located on the second surface side of the dielectric substrate 1, respectively, to planarize the film layer located on the first surface side of the dielectric substrate 1 and the film layer located on the second surface side of the dielectric substrate 1, respectively. The first connecting pad 14 is connected to the second substructure 8 through a second connecting via penetrating the first interlayer dielectric layer 3 and the second interlayer dielectric layer 12. The second connecting pad 15 is connected to the second substructure 8 through a third connecting via penetrating the first interlayer dielectric layer 3 and the second interlayer dielectric layer 12. The third connecting pad 16 is connected to the second plate 4 of the capacitor C through a fourth connecting via penetrating the second interlayer dielectric layer 12. Among them, the first connecting pad 14 can be a signal input terminal Input, the second connecting pad 15 can be a signal output terminal Output, and the third connecting pad 16 can be a ground terminal GND. It should be noted that, in some embodiments, the first connecting pad 14 and the second connecting pad 15 are interchangeable, that is, the first connecting pad 14 is the signal output terminal Output and the second connecting pad 15 is the signal input terminal Input, which is also within the scope of protection of the present disclosure.

[0051] In some embodiments, dielectric substrate 1 includes, but is not limited to, any of glass, silicon, flexible substrates, and interlayer dielectric layers including at least an organic insulating layer. Because integrated circuits on glass substrates offer advantages such as small size, light weight, high performance, and low power consumption, dielectric substrate 1 in the disclosed embodiments is glass. The following description uses a glass substrate as an example.

[0052] In some embodiments, as Figure 5 As shown, the passive filter of the embodiment of the present disclosure can be applied to an integrated filter. Figure 5 , Figure 5 The integrated filter shown includes a passive filter, a radio frequency sub-circuit 17 and a package carrier 18. Among them, the first connection pad 14, the second connection pad 15 and the third connection pad 16 in the passive filter are connected to the corresponding signal terminals on the package carrier 18, and the connection signal terminals in the radio frequency sub-circuit 17 are connected to the corresponding signal terminals on the package carrier 18 to form a complete integrated filter. The integrated filter can be an RF front-end device. Its application areas cover almost all RF directions, including 5G communications, vehicle-mounted radar, etc. It should be noted that Figure 5 The integrated filter shown is described by taking only one passive filter and one RF sub-circuit 17 as an example. An integrated filter including multiple passive filters and multiple RF sub-circuits 17 is also within the protection scope of the present disclosure.

[0053] The structural parameters of the various components of the passive filter of the embodiment of the present disclosure are described one by one in the following preparation method, and therefore will not be described in detail here.

[0054] Specifically, an embodiment of the present disclosure provides a method for preparing a passive filter, which may be the above-mentioned substrate. The method comprises the following steps:

[0055] A dielectric substrate 1 is provided, comprising a slot 6 arranged along a thickness direction of the dielectric substrate 1; an inner wall of the slot 6 comprises a first portion, wherein a tangent line of at least some points on the first portion extends in a direction intersecting with an extending direction of a plane on which the dielectric substrate 1 is located;

[0056] At least one capacitor C and at least one inductor are formed; the steps of forming the capacitor C include:

[0057] A first plate 2 of a capacitor C, a first interlayer dielectric layer 3, and a second plate 4 of a capacitor C are sequentially formed on a side facing away from the dielectric substrate 1. The overlapping portion of the orthographic projections of the first plate 2 of the capacitor C, the second plate 4 of the capacitor C, and the first interlayer dielectric layer 3 on the dielectric substrate 1 covers at least the first portion.

[0058] In order to clarify the preparation method in the embodiment of the present disclosure, the preparation method of the passive filter in the embodiment of the present disclosure is described below in conjunction with the accompanying drawings and specific embodiments. Figure 6 shown.

[0059] S10, providing a dielectric substrate 1, and processing the dielectric substrate 1 to form a groove 6 and a first connecting via 5, such as Figure 7 shown.

[0060] In some embodiments, the dielectric substrate 1 selected in step S10 is a glass substrate, and the formed groove 6 may be a blind groove. Figure 8 As shown, step S10 may include the following steps:

[0061] S101 , the dielectric substrate 1 enters a cleaning machine for cleaning.

[0062] In some embodiments, the thickness of the dielectric substrate 1 is about 0.3 mm to 2 mm.

[0063] S102 , applying glue on the first surface of the dielectric substrate 1 , and exposing and developing the surface.

[0064] In some embodiments, the photoresist 19 is evenly coated on the first surface of the dielectric substrate 1, such as Figure 9 As shown. The photoresist 19 at the pre-formed first connecting via hole 5 and the blind groove is exposed to light by exposure. The photosensitive photoresist 19 is removed by chemical means, and the unexposed photoresist 19 is cured. Finally, the first surface at the pre-formed first connecting via hole 5 and the blind groove is exposed to the external environment, as shown. Figure 10 shown.

[0065] S103 , performing laser modification on the first surface of the dielectric substrate 1 .

[0066] In some embodiments, the first surface exposed to the external environment in step S102 is laser-modified at the location corresponding to the pre-formed first connecting via 5, so that the first surface corresponding to the pre-formed first connecting via 5 can be anisotropically etched, and the first surface at the pre-formed blind groove is isotropically etched. In this way, the first connecting via 5 and the blind groove can be formed simultaneously using a single etching process, which simplifies the process.

[0067] In some embodiments, when the precision of the laser is high enough, the order of step S103 and step S102 can be interchanged.

[0068] S104, forming a blind groove and a first connecting via 5 by etching process, Figure 11 shown.

[0069] In some embodiments, an isotropic etching solution is used to etch the dielectric substrate 1 processed in step S103. Since the first surface where the first connecting via 5 is formed can be anisotropically etched after laser treatment, the etching rate of the dielectric substrate 1 along its longitudinal direction is much greater than the etching rate on the horizontal surface, and the first connecting via 5 is finally formed along the thickness direction of the dielectric substrate 1. At the same time, since isotropic etching is performed where the blind groove is formed, the etching rate of the dielectric substrate 1 in all directions is basically the same, and a hemispherical blind groove can finally be formed. In this way, the first connecting via 5 and the blind groove are formed in a single etching process. The formed blind groove is a hemispherical blind groove, which makes it easy to form the capacitor C on the side wall of the blind groove and the capacitance value is easy to calculate, which facilitates the design of the passive filter.

[0070] It should be noted that, in some embodiments, the blind grooves may be partially etched isotropically and partially etched anisotropically, so that blind grooves with different structures can be formed.

[0071] S105 , removing the photoresist 19 on the surface of the dielectric substrate 1 .

[0072] The preparation of step S10 is now completed. The first connecting vias 5 and the blind grooves formed in this way have a simple and mature process and are easy to prepare.

[0073] It should be noted that, in some embodiments, the first connecting via 5 and the slot 6 can be formed using different punching processes and in different steps. For example, in some embodiments, the first connecting via 5 can be prepared by mechanical punching, laser punching, dry etching, and wet etching. In some embodiments, the slot 6 can be prepared by mechanical punching, laser punching, dry etching, and wet etching. In some embodiments, the slot 6 and the first connecting via 5 can be formed by first forming the slot 6 and then forming the first connecting via 5, or by first forming the first connecting via 5 and then forming the slot 6. The above schemes are all within the protection scope of the embodiments of the present disclosure. Similarly, in some embodiments, the slot 6 and the first connecting via 5 can be formed using the same preparation method, or by different preparation methods. The above schemes are all within the protection scope of the embodiments of the present disclosure.

[0074] S11, forming a first connection electrode 9 in the first connection via hole 5, as shown in FIG. Figure 12 shown.

[0075] In some embodiments, step S11 may specifically include the following steps:

[0076] (1) Growing a seed layer: depositing a first metal material on the first surface of the dielectric substrate 1 by magnetron sputtering, flipping the dielectric substrate 1 over, and depositing the first metal material on the second surface by magnetron sputtering. At this time, the first metal material is formed on the sidewall of the first connecting via 5 as a seed layer.

[0077] In some embodiments, the first metal material includes, but is not limited to, at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag). The thickness of the first metal material is approximately 0.2 μm to 10 μm. In the following description, copper is used as the material of the first metal film layer 201 as an example.

[0078] In some embodiments, to enhance adhesion between the first metal material and the first surface of the glass substrate 10, an auxiliary metal film layer may be formed on the first surface of the glass substrate 10 by methods including, but not limited to, magnetron sputtering before forming the first metal material. The material of the auxiliary metal film layer includes, but is not limited to, at least one of nickel (Ni), molybdenum (Mo) alloy, and titanium (Ti) alloy, such as MoNb, and the thickness of the auxiliary metal film layer is approximately 2 nm to 20 nm.

[0079] (2) Electroplating: Place the dielectric substrate 1 on the electroplating machine carrier, press the power pad (pad), and place it in the hole-filling electroplating tank (a special hole-filling electrolyte is used in the tank). Apply current, and the electroplating solution is kept flowing rapidly on the first surface of the dielectric substrate 1. The cations in the electroplating solution on the inner wall of the first connecting via 5 obtain electrons and become atoms and deposit on the inner wall. Through the special hole-filling electrolyte with a special ratio, it is possible to achieve high-speed deposition of metal copper (deposition rate 0.5-3um / min) mainly in the first connecting via. The first and second surfaces of the dielectric substrate 1 are flat areas, and the deposition rate of metal copper on these two surfaces is extremely low (0.005-0.05um / min). As time increases, the metal copper on the inner wall of the first connecting via 5 gradually grows thicker to form a first metal film layer. At this time, the first metal film layer grows more than 5μm compared to the first metal material. At this time, the first metal film layer fills the first connecting via 5.

[0080] In some embodiments, the first metal film layer may not completely fill the first connection via 5. In this step, a filling structure is formed in the first connection via 5 to support the film layer structure on the dielectric substrate 1. The filling structure may be made of an organic insulating material, such as a resin material such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, or silicone. For another example, the organic insulating material may include an elastic material such as urethane or thermoplastic polyurethane (TPU).

[0081] It should be noted that, in the embodiment of the present disclosure, the first metal film layer is used as an example to fully fill the first connection via hole 5 .

[0082] S12, forming the first substructure 7 and the first plate 2 of the capacitor C, as shown in FIG. Figure 13 shown.

[0083] A second metal film layer is deposited on the first surface of the dielectric substrate 1 and within the blind groove. A resist is applied to the second metal film layer, exposed, and developed, followed by etching. After etching, the resist is stripped, and the second metal film layer is patterned. This forms a first conductive layer including the first substructure 7 of the first inductor L1, the first substructure 7 of the second inductor L2, and the first plate 2 of the capacitor C. In the disclosed embodiment, the first plate 2 of the capacitor C completely covers the sidewalls of the blind groove.

[0084] S13, forming a first interlayer dielectric layer 3, and forming a pattern of a second plate 4 of a capacitor C on the side of the first interlayer dielectric layer 3 away from the dielectric substrate 1, as shown in FIG. Figure 14 shown.

[0085] In some embodiments, the material of the first interlayer dielectric layer 3 is an inorganic insulating material. For example, the first interlayer dielectric layer 3 is an inorganic insulating layer formed of silicon nitride (SiNx), an inorganic insulating layer formed of silicon oxide (SiO2), or a stacked combination of SiNx and SiO2 inorganic insulating layers. In some embodiments, the first interlayer dielectric layer 3 covers the first substructure 7 of the first inductor L1, the first substructure 7 of the second inductor L2, and the first plate 2 of the capacitor C. In this way, the first interlayer dielectric layer 3 not only serves as the interlayer dielectric layer of the capacitor C, but also serves as the interlayer insulating layer of the passive filter, protecting the structure between the first interlayer dielectric layer 3 and the dielectric substrate 1 from corrosion by water and oxygen.

[0086] In some embodiments, the second plate 4 of the capacitor C can be formed by magnetron sputtering on the side of the first interlayer dielectric layer 3 facing away from the dielectric substrate 1 to form a third metal film layer, and then coated with glue, exposed, developed, and then wet-etched. After etching, the glue is stripped to form a pattern including the second plate 4 of the capacitor C.

[0087] S14, forming a second interlayer dielectric layer 12 on the side of the second plate 4 of the capacitor C facing away from the dielectric substrate 1, and forming a second connecting via hole penetrating the first dielectric layer and the second interlayer dielectric layer 12, a third connecting via hole penetrating the second interlayer dielectric layer 12, and a fourth connecting via hole penetrating the second interlayer dielectric layer 12, as shown in FIG. Figure 15 shown.

[0088] The material of the second interlayer dielectric layer 12 can be the same as that of the first interlayer dielectric layer 3, and therefore will not be repeated here. The second connecting via at least partially overlaps with the orthographic projection of the second lead terminal 11 of the first inductor L1 on the dielectric substrate 1. The third connecting via at least partially overlaps with the orthographic projection of the first lead terminal 10 of the second inductor L2 on the dielectric substrate 1. The fourth connecting via at least partially overlaps with the orthographic projection of the second plate 4 of the capacitor C on the dielectric substrate 1.

[0089] S15, flip the dielectric substrate 1 over, and form a pattern including the second substructure 8 through a patterning process, such as Figure 16 shown.

[0090] In some embodiments, step S15 may include forming a fourth metal film layer on the second surface of the dielectric substrate 1 by magnetron sputtering, then performing resist coating, exposure, development, and subsequent etching. After etching, stripping the resist to form a second conductive layer including the pattern of the second substructure 8 of the first inductor L1 and the pattern of the second substructure 8 of the second inductor L2.

[0091] The thickness of the fourth metal film layer is greater than 5 μm. The material of the fourth metal film layer can be the same as that of the first metal film layer, so it will not be described in detail here.

[0092] S16, forming a third interlayer dielectric layer 13 on the side of the second substructure 8 facing away from the dielectric substrate 1, as shown in FIG. Figure 17 shown.

[0093] In some embodiments, the material of the third interlayer dielectric layer 13 may be the same as that of the second interlayer dielectric layer 12 , and therefore will not be described again herein.

[0094] S17: Flip the dielectric substrate 1 again, and form the first connecting pad 14, the second connecting pad 15, and the third connecting pad 16 in the second connecting via hole, the third connecting via hole, and the fourth connecting via hole, respectively.

[0095] This completes the preparation of the passive filter.

[0096] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A passive filter, characterized in that: include: A dielectric substrate, at least one capacitor and at least one inductor; the dielectric substrate includes a first connecting via extending through the dielectric substrate along its thickness direction and a first surface and a second surface disposed opposite to each other along its thickness direction; The dielectric substrate further includes: a slot provided along the thickness direction of the dielectric substrate; the slot is a blind slot, and an inner wall of the slot includes a first portion, wherein an extension direction of a tangent line of at least some points on the first portion intersects an extension direction of the plane on which the dielectric substrate is located; The capacitor comprises: a first plate, a first interlayer dielectric layer, and a second plate, which are sequentially arranged in a direction away from the dielectric substrate; the overlapping portion of the orthographic projections of the first plate, the second plate, and the first interlayer dielectric layer on the dielectric substrate at least covers the first portion; The inductor is electrically connected to the capacitor, and includes: a first substructure provided on the first surface of the dielectric substrate, a second substructure provided on the second surface of the dielectric substrate, and a first connecting electrode provided in the first connecting via; the first connecting electrode connects the first substructure and the second substructure; Furthermore, the orthographic projection of the first interlayer dielectric layer of the capacitor on the dielectric substrate covers the orthographic projections of the first substructure and the first electrode plate of the capacitor on the dielectric substrate.

2. The passive filter according to claim 1, wherein There are multiple inductors, and the multiple inductors include a first inductor and a second inductor; The passive filter comprises a first conductive layer; the first conductive layer comprises: a first substructure of the first inductor, a first substructure of the second inductor, and a first plate of the capacitor; The passive filter further includes a second conductive layer; the second conductive layer includes: a second substructure of the first inductor and a second substructure of the second inductor; The first lead end of the first inductor is connected to the first plate of the capacitor, and the second lead end of the second inductor is connected to the first plate of the capacitor.

3. The passive filter according to claim 2, characterized in that The passive filter further comprises: A second interlayer dielectric layer provided on the first interlayer dielectric layer and the second electrode plate of the capacitor on a side facing away from the dielectric substrate; a third interlayer dielectric layer provided on a side of the second interlayer dielectric layer facing away from the dielectric substrate; and, a first connecting pad, a second connecting pad, and a third connecting pad provided on a side away from the second interlayer dielectric layer; The first connecting pad is connected to the second lead end of the first inductor through a second connecting via penetrating the first interlayer dielectric layer and the second interlayer dielectric layer; The second connecting pad is connected to the first lead end of the second inductor through a third connecting via penetrating the first interlayer dielectric layer and the second interlayer dielectric layer; The third connecting pad is connected to the second plate of the capacitor through a fourth connecting via hole penetrating the second interlayer dielectric layer.

4. The passive filter according to claim 1, wherein The blind grooves include hemispherical blind grooves, cylindrical blind grooves and cubic blind grooves.

5. The passive filter according to claim 1, wherein The overlapping portion of the orthographic projections of the first electrode plate of the capacitor, the second electrode plate of the capacitor, and the first interlayer dielectric layer on the dielectric substrate completely covers the inner wall of the groove.

6. The passive filter according to any one of claims 1 to 5, characterized in that: The dielectric substrate includes a glass base or a silicon base.

7. A method for preparing a passive filter, wherein the passive filter is as described in any one of claims 1 to 6; The preparation method comprises: A dielectric substrate is provided, comprising a first connecting via extending through the dielectric substrate along its thickness, and a first surface and a second surface disposed opposite each other along its thickness; and a slot disposed along the thickness of the dielectric substrate; the slot being a blind slot, and an inner wall of the slot including a first portion, wherein a tangent line of at least some points on the first portion extends in a direction intersecting with an extending direction of a plane on which the dielectric substrate is located; forming at least one capacitor and at least one inductor; The steps of forming the capacitor include: A first plate of the capacitor, a first interlayer dielectric layer, and a second plate of the capacitor are sequentially formed on a side away from the dielectric substrate; the overlapping portion of the orthographic projections of the first plate of the capacitor, the second plate of the capacitor, and the first interlayer dielectric layer on the dielectric substrate covers the first portion; The inductor is electrically connected to the capacitor, and includes: a first substructure provided on the first surface of the dielectric substrate, a second substructure provided on the second surface of the dielectric substrate, and a first connecting electrode provided in the first connecting via; the first connecting electrode connects the first substructure and the second substructure; Furthermore, the orthographic projection of the first interlayer dielectric layer of the capacitor on the dielectric substrate covers the orthographic projections of the first substructure and the first electrode plate of the capacitor on the dielectric substrate.

8. The preparation method according to claim 7, characterized in that Providing a dielectric substrate further includes forming the first connecting via hole in the dielectric substrate along a thickness direction thereof.

9. The preparation method according to claim 8, characterized in that The first connecting via hole and the groove are formed by an etching process.

10. The preparation method according to claim 9, characterized in that The step of forming the first connecting via hole and the groove includes: Laser modification is performed on the dielectric substrate so that the dielectric substrate can be simultaneously etched isotropically and anisotropically during a single etching process; and the groove and the first connecting via are formed through a single etching process.

11. The preparation method according to claim 8 or 9, characterized in that: The step of forming at least one of the inductors includes forming a first inductor and a second inductor; The step of forming the first inductor and the second inductor includes: forming a first connecting electrode in the first connecting via hole; forming a first substructure of the first inductor and a first substructure of the second inductor on the first surface of the dielectric substrate; forming a second substructure of the first inductor and a second substructure of the second inductor on the second surface of the dielectric substrate; The first substructure of the first inductor, the second substructure of the first inductor and the first connecting electrode constitute the coil structure of the first inductor; the first substructure of the second inductor, the second substructure of the second inductor and the first connecting electrode constitute the coil structure of the second inductor.

12. The preparation method according to claim 11, characterized in that Also includes: forming a second interlayer dielectric layer on a side of the dielectric substrate facing away from the first surface, and forming a second connecting via hole and a third connecting via hole penetrating the first interlayer dielectric layer and the second interlayer dielectric layer, and a fourth connecting via hole penetrating the second interlayer dielectric layer; forming a third interlayer dielectric layer on a side of the dielectric substrate away from the second surface; The preparation method further comprises: forming a first connecting pad, a second connecting pad and a third connecting pad on a side away from the second interlayer dielectric layer; The first connecting pad is connected to the first substructure of the first inductor through the second connecting via penetrating the first interlayer dielectric layer and the second interlayer dielectric layer; the second connecting pad is connected to the first substructure of the second inductor through the third connecting via penetrating the first interlayer dielectric layer and the second interlayer dielectric layer; the third connecting pad is connected to the second plate of the capacitor through the fourth connecting via penetrating the second interlayer dielectric layer.

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