Semiconductor Structure and Method for Forming the Semiconductor Structure

Abstract

A semiconductor structure and a method for forming the semiconductor structure, the structure comprising: a substrate; a first gate structure and a second gate structure located on the substrate, the width of the first gate structure in the channel length direction being greater than the width of the second gate structure in the channel length direction; a first barrier layer located on the second gate structure; a second barrier layer located on the first gate structure; a dielectric layer located on the substrate, the dielectric layer being located on the sidewalls of the first gate structure, the second gate structure, the first barrier layer, and the second barrier layer. The performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the semiconductor structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. During the evolution of ICs, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometric dimensions (i.e., the smallest components or lines that can be produced using a manufacturing process) have decreased. This scaling process typically provides benefits by increasing production efficiency and reducing associated costs. This scaling also increases the complexity of processing and manufacturing ICs.

[0003] In some IC designs, as the technology node shrinks, one advantage achieved is that, with the reduction of component size, a metal gate is used to replace a typical polysilicon gate to improve device performance. One process for forming a metal gate is called a replacement gate or "post-gate" process, where the metal gate is fabricated "last", which allows for a reduction in the number of subsequent processes, including high-temperature treatments that must be implemented after the formation of the gate.

[0004] However, there are still some problems in the existing process for forming a metal gate using the "post-gate" process. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the semiconductor structure to improve the performance of the semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a first gate structure and a second gate structure located on the substrate, the width of the first gate structure in the channel length direction being greater than the width of the second gate structure in the channel length direction; a first barrier layer located on the second gate structure; a second barrier layer located on the first gate structure; a dielectric layer located on the substrate, the dielectric layer being located on the sidewalls of the first gate structure, the second gate structure, the first barrier layer, and the second barrier layer.

[0007] Optionally, the difference range between the height of the second gate structure and the height of the first gate structure is: -2 nanometers to 2 nanometers.

[0008] Optionally, the width range of the first gate structure is greater than or equal to 240 nanometers; the width range of the second gate structure is 0 nanometers to 96 nanometers.

[0009] Optionally, the etching rate of the material of the first barrier layer is different from that of the dielectric layer; the etching rate of the material of the second barrier layer is different from that of the dielectric layer.

[0010] Optionally, the material of the first barrier layer includes a dielectric material, and the dielectric material includes silicon nitride; the material of the second barrier layer includes a dielectric material, and the dielectric material includes silicon nitride.

[0011] Optionally, the first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer; the second gate structure includes a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

[0012] Optionally, the first gate structure further includes a first work function layer located between the first gate dielectric layer and the first gate layer; the second gate structure further includes a second work function layer located between the second gate dielectric layer and the second gate layer.

[0013] Optionally, it further includes: source-drain doping regions in the substrate on both sides of the first gate structure and both sides of the second gate structure.

[0014] Optionally, the substrate includes: a substrate and a fin structure located on the substrate; the first gate structure and the second gate structure straddle the fin structure; the channel length direction is the extending direction of the fin structure.

[0015] Correspondingly, the technical solution further provides a method for forming a semiconductor structure, including: providing a substrate; forming an initial first gate structure, an initial second gate structure, and a dielectric layer on the substrate, the width of the initial first gate structure in the channel length direction is greater than the width of the initial second gate structure in the channel length direction, the dielectric layer is located on partial sidewalls of the initial first gate structure and sidewalls of the initial second gate structure, and the top surface of the initial first gate structure is higher than the top surface of the initial second gate structure; etching back the initial first gate structure and the initial second gate structure to form a second gate structure and a transitional first gate structure, the top surface of the second gate structure is lower than the top surface of the dielectric layer; forming an initial first barrier layer on the second gate structure and the dielectric layer, the initial first barrier layer exposes the transitional first gate structure; using the initial first barrier layer as a mask to remove part of the transitional first gate structure to form a first gate structure, the top surface of the first gate structure is lower than the top surface of the dielectric layer; forming a second barrier layer on the first gate structure and forming a first barrier layer on the second gate structure.

[0016] Optionally, the difference range between the height of the second gate structure and the height of the first gate structure is: -2 nm to 2 nm.

[0017] Optionally, the width range of the initial first gate structure is greater than or equal to 240 nm; the width range of the initial second gate structure is 0 nm to 96 nm.

[0018] Optionally, the method for forming the initial first barrier layer includes: forming a first barrier material layer on the second gate structure, on the dielectric layer, and on the transitional first gate structure; planarizing the first barrier material layer until the top surface of the transitional first gate structure is exposed, and forming the initial first barrier layer on the second gate structure.

[0019] Optionally, the method for forming the second barrier layer and the first barrier layer includes: forming a second barrier material layer on the first gate structure and on the initial first barrier layer; planarizing the second barrier material layer and the initial first barrier layer until the top surface of the dielectric layer is exposed, forming the second barrier layer on the first gate structure, and forming the first barrier layer on the second gate structure.

[0020] Optionally, the etching rate of the material of the first barrier layer is different from that of the dielectric layer; the etching rate of the material of the second barrier layer is different from that of the dielectric layer.

[0021] Optionally, the material of the first barrier layer includes a dielectric material, and the dielectric material includes silicon nitride; the material of the second barrier layer includes a dielectric material, and the dielectric material includes silicon nitride.

[0022] Optionally, the method for forming the initial first gate structure, the initial second gate structure, and the dielectric layer includes: forming a first dummy gate structure and a second dummy gate structure on the substrate; forming a dielectric layer on the substrate, and the dielectric layer is located on the sidewalls of the first dummy gate structure and the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure, and forming a gate opening in the dielectric layer; forming a gate structure material layer in the gate opening and on the dielectric layer; planarizing the gate structure material layer until the top surface of the dielectric layer is exposed, and forming the initial first gate structure and the initial second gate structure.

[0023] Optionally, after forming the first dummy gate structure and the second dummy gate structure on the substrate and before forming the dielectric layer, it further includes: forming source / drain doping regions in the substrate on both sides of the first dummy gate structure and on both sides of the second dummy gate structure.

[0024] Optionally, the substrate includes: a substrate base and a fin structure located on the substrate base; the initial first gate structure and the initial second gate structure straddle the fin structure; the channel length direction is the extending direction of the fin structure.

[0025] Optionally, the first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer; the second gate structure includes a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

[0026] Optionally, the first gate structure further includes a first work function layer located between the first gate dielectric layer and the first gate layer; the second gate structure further includes a second work function layer located between the second gate dielectric layer and the second gate layer.

[0027] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0028] In the method for forming a semiconductor structure according to the technical solution of the present invention, after forming the initial first gate structure and the initial second gate structure, the initial first gate structure and the initial second gate structure are first etched back to form the second gate structure and the transitional first gate structure, so that the top surface of the second gate structure is lower than the top surface of the dielectric layer. Then, an initial first barrier layer is formed on the second gate structure and the dielectric layer, and the initial first barrier layer exposes the transitional first gate structure. Then, using the initial first barrier layer as a mask, part of the transitional first gate structure is removed to form the first gate structure, and the top surface of the first gate structure is lower than the top surface of the dielectric layer. Finally, a second barrier layer is formed on the first gate structure, and a first barrier layer is formed on the second gate structure. The height difference between the first gate structure and the second gate structure formed by the method is within a preset range, so that the heights of the first gate structure and the second gate structure can be precisely controlled, reducing the situation where the height difference between the formed first gate structure and the second gate structure is large due to the width of the initial first gate structure being greater than the width of the initial second gate structure, thereby making the performance uniformity of the formed semiconductor structure better. Description of the Drawings

[0029] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor structure in an embodiment;

[0030] Figures 2 to 8 is a schematic cross-sectional structure diagram of a semiconductor structure in an embodiment of the present invention. Detailed Embodiments

[0031] As described in the background art, there are still some problems in the process of forming a metal gate by the existing "post-gate" process. The following is an analysis and description in combination with specific embodiments.

[0032] Figure 1 is a schematic cross-sectional structure diagram of a semiconductor structure in an embodiment.

[0033] Please refer to Figure 1, including: a substrate 100, the substrate 100 including a first region I and a second region II; a first gate structure 101 located on the first region I; a second gate structure 102 located on the second region II; a dielectric layer 103 located on the first region I and the second region II, the dielectric layer 103 being located on the sidewalls of the first gate structure 101 and the second gate structure 102.

[0034] In the semiconductor structure, the device density on the first region I is greater than the device density on the second region II. Therefore, in the channel length direction, the width of the first gate structure 101 is greater than the width of the second gate structure 102, so that the surface area of the dielectric layer 103 on the first region I is smaller than the surface area of the dielectric layer 103 on the second region II.

[0035] The first gate structure 101 and the second gate structure 102 are metal gates. In the process of forming the first gate structure 101 and the second gate structure 102 using the back-gate process, a dummy gate structure (not shown) and a dielectric layer 103 (not shown) located on the sidewalls of the dummy gate structure need to be formed on the substrate first, then the dummy gate structure is removed to form a gate opening (not shown) in the dielectric layer 103, a gate structure material layer (not shown) is formed in the gate opening and on the dielectric layer 103, and finally the gate structure material layer is planarized using a chemical mechanical polishing process until the surface of the dielectric layer 103 is exposed to form the first gate structure 101 and the second gate structure 102.

[0036] However, in the process of grinding the gate structure material layer using the chemical mechanical polishing process, since the surface area of the dielectric layer 103 on the first region I is smaller than the surface area of the dielectric layer 103 on the second region II, that is, the surface area of the gate structure material layer on the first region I is larger, so that the contact area between the abrasive of the chemical mechanical polishing process and the gate structure material layer on the first region I is larger, and the contact area between the abrasive of the chemical mechanical polishing process and the dielectric layer 103 on the second region II is larger. The grinding rate of the chemical mechanical polishing process for the dielectric layer 103 is greater than the material grinding rate for the gate structure material layer. Therefore, under the same chemical mechanical polishing process conditions, the grinding degree of the dielectric layer 103 and the gate structure material layer on the second region II is greater than the grinding degree of the gate structure material layer on the first region I, so that the height of the formed first gate structure 101 is higher than the height of the formed second gate structure 102. Thus, when ensuring the height of the second gate structure 102, it is difficult to control the height of each of the first gate structures 101, resulting in uneven height of the formed first gate structures 101, and thus poor performance uniformity of the semiconductor structure.

[0037] To solve the above problems, the technical solution of the present invention provides a semiconductor structure and a method for forming a semiconductor structure. After forming an initial first gate structure and an initial second gate structure, first etch back the initial first gate structure and the initial second gate structure to form a second gate structure and a transitional first gate structure, such that the top surface of the second gate structure is lower than the top surface of the dielectric layer. Then, form a first barrier layer on the second gate structure and the dielectric layer, and the first barrier layer exposes the transitional first gate structure. Next, using the first barrier layer as a mask, remove a part of the transitional first gate structure to form a first gate structure, and the top surface of the first gate structure is lower than the top surface of the dielectric layer. Finally, form a second barrier layer on the first gate structure. The height difference between the first gate structure and the second gate structure formed by the method is within a preset range, so that the heights of the first gate structure and the second gate structure can be precisely controlled, reducing the situation where the height difference between the formed first gate structure and the second gate structure is large due to the width of the initial first gate structure being greater than the width of the initial second gate structure, thereby making the performance uniformity of the formed semiconductor structure better.

[0038] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0039] Figures 2 to 8 It is a schematic cross-sectional structure diagram of the semiconductor structure in the embodiment of the present invention.

[0040] Please refer to Figure 2 , and provide a substrate.

[0041] In this embodiment, the substrate includes: a substrate 200 and a fin structure 201 located on the substrate 200; there is also an isolation layer on the substrate, the isolation layer is located on a part of the sidewalls of the fin structure 201, and the top surface of the isolation layer is lower than the top surface of the fin structure 201.

[0042] In this embodiment, the material of the substrate 200 is silicon; the material of the fin structure 201 includes silicon.

[0043] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP. The material of the fin structure includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0044] Please continue to refer to Figure 2 , an initial first gate structure 202, an initial second gate structure 203, and a dielectric layer 204 are formed on the substrate. The width of the initial first gate structure 202 in the channel length direction is greater than the width of the initial second gate structure 201 in the channel length direction. The dielectric layer is located on the sidewalls of a part of the initial first gate structure 202 and the sidewalls of the initial second gate structure 203, and the top surface of the initial first gate structure 202 is higher than the top surface of the initial second gate structure 203.

[0045] In this embodiment, the initial first gate structure 202 and the initial second gate structure 203 straddle the fin structure 201.

[0046] In this embodiment, the width range of the initial first gate structure 202 is greater than or equal to 240 nanometers; the width range of the initial second gate structure 203 is 0 nanometers to 96 nanometers.

[0047] The forming method of the initial first gate structure 202, the initial second gate structure 203, and the dielectric layer 204 includes: forming a first dummy gate structure (not shown) and a second dummy gate structure (not shown) on the substrate; forming source / drain doping regions 205 in the substrate on both sides of the first dummy gate structure and both sides of the second dummy gate structure; forming a dielectric layer 204 on the substrate, and the dielectric layer is located on the sidewalls of the first dummy gate structure and the sidewalls of the second dummy gate structure; removing the first dummy gate structure and the second dummy gate structure, and forming a gate opening (not shown) in the dielectric layer 204; forming a gate structure material layer (not shown) in the gate opening and on the dielectric layer 204; planarizing the gate structure material layer until the top surface of the dielectric layer 204 is exposed, so as to form the initial first gate structure 202 and the initial second gate structure 203.

[0048] The channel length is the distance between the two sides of the initial first gate structure 202 or between the source-drain doping regions 205 of the initial second gate structure 203. In this embodiment, the channel length direction is the extending direction of the fin structure 201.

[0049] The initial first gate structure 202 includes a first gate dielectric layer (not shown) and a first gate layer (not shown) located on the first gate dielectric layer; the initial second gate structure 203 includes a second gate dielectric layer (not shown) and a second gate layer (not shown) located on the second gate dielectric layer.

[0050] In this embodiment, the initial first gate structure 202 further includes a first work function layer (not shown) located between the first gate dielectric layer and the first gate layer; the initial second gate structure 203 further includes a second work function layer (not shown) located between the second gate dielectric layer and the second gate layer.

[0051] The materials of the first gate dielectric layer and the second gate dielectric layer include high-k materials, the dielectric constant of the high-k materials is greater than 3.9, and the high-k materials include aluminum oxide or hafnium oxide; the materials of the first gate layer and the second gate layer include metals, and the metals include tungsten; the materials of the first work function layer and the second work function layer include N-type work function materials or P-type work function materials, the N-type work function materials include titanium-aluminum, and the P-type work function materials include titanium nitride or tantalum nitride.

[0052] The material of the dielectric layer 204 includes dielectric materials, and the dielectric materials include one or a combination of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the dielectric layer 204 includes silicon oxide.

[0053] Please refer to Figure 3 , etch back the initial first gate structure 202 and the initial second gate structure 203 to form a second gate structure 207 and a transitional first gate structure 206, and the top surface of the second gate structure 207 is lower than the top surface of the dielectric layer 204.

[0054] The process of etching back the initial first gate structure 202 and the initial second gate structure 203 includes a dry etching process or a wet etching process.

[0055] Next, form an initial first barrier layer 209 on the second gate structure 207 and on the dielectric layer 204, and the initial first barrier layer 208 exposes the transitional first gate structure 206. For the formation process of the initial first barrier layer 209, please refer to Figure 4 and Figure 5 .

[0056] Please refer to Figure 4 , a first barrier material layer 208 is formed on the second gate structure 207, on the dielectric layer 204, and on the transitional first gate structure 206.

[0057] The first barrier material layer 208 provides a material layer for forming a first barrier layer on the second gate structure 207 subsequently.

[0058] The material of the first barrier material layer 208 is different from that of the dielectric layer 204. The material of the first barrier material layer 208 has a large etching selectivity ratio with respect to the transitional first gate structure 206 and the second gate structure 207.

[0059] The material of the first barrier material layer 208 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the first barrier material layer 208 includes silicon nitride, and the silicon nitride has a large etching selectivity ratio with respect to the silicon oxide which is the material of the dielectric layer 204.

[0060] The process for forming the first barrier material layer 208 includes a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the process for forming the first barrier material layer 208 includes a chemical vapor deposition process, and the chemical vapor deposition process can rapidly form a first barrier material layer 208 with a relatively thick thickness and a dense structure.

[0061] Please refer to Figure 5 , planarize the first barrier material layer 208 until the top surface of the transitional first gate structure 206 is exposed, and form an initial first barrier layer 209 on the second gate structure 207 and the dielectric layer 204.

[0062] In this embodiment, the process for planarizing the first barrier material layer 208 includes a chemical mechanical polishing process. The etching rates of the initial first barrier layer 209 and the material of the transitional first gate structure 206 are different under the chemical mechanical polishing process. Therefore, during the process of planarizing the first barrier material layer 208, the transitional first gate structure 206 can serve as an etching stop layer for the planarizing process.

[0063] Please refer to Figure 6 , using the initial first barrier layer 209 as a mask, remove a part of the transitional first gate structure 206 to form a first gate structure 210, and the top surface of the first gate structure 210 is lower than the top surface of the dielectric layer 204.

[0064] The process of removing a portion of the transitional first gate structure 206 includes a dry etching process or a wet etching process. The transitional first gate structure 206 has a large etching selectivity with respect to the initial first barrier layer 209, so that the initial first barrier layer 209 can serve as a mask for removing a portion of the transitional first gate structure 206.

[0065] First, the initial first gate structure 202 and the initial second gate structure 203 are etched back to form a second gate structure 207 and a transitional first gate structure 206, such that the top surface of the second gate structure 207 is lower than the top surface of the dielectric layer 204. Then, an initial first barrier layer 209 is formed on the second gate structure 207 and on the dielectric layer 204. The initial first barrier layer 209 exposes the transitional first gate structure 206. Then, using the initial first barrier layer 209 as a mask, a portion of the transitional first gate structure 206 is removed to form a first gate structure 210. For the first gate structure 210 formed by the method, the height of the first gate structure 210 can be adjusted according to the height of the previously formed second gate structure 207, so that the height of the formed first gate structure 210 and the height of the second gate structure 207 can be within a preset range of height difference, thereby making the performance uniformity of the formed semiconductor structure better.

[0066] In this embodiment, the difference range between the height of the second gate structure 207 and the height of the first gate structure 210 is: -2 nm to 2 nm. The difference between the height of the second gate structure 207 and the height of the first gate structure 210 is within a preset range, thereby making the performance uniformity of the formed semiconductor structure better.

[0067] Next, a second barrier layer 212 is formed on the first gate structure 210, and a first barrier layer 213 is formed on the second gate structure 207. For the formation processes of the second barrier layer 212 and the first barrier layer 213, please refer to Figure 7 and Figure 8 .

[0068] Please refer to Figure 7 , a second barrier material layer 211 is formed on the first gate structure 210 and on the initial first barrier layer 209.

[0069] The second barrier material layer 211 provides a material layer for subsequently forming a second barrier layer on the first gate structure 210.

[0070] The material of the second barrier material layer 211 is different from that of the dielectric layer 204. The material of the second barrier material layer 211 includes a dielectric material, and the dielectric material includes one or a combination of more of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the second barrier material layer 211 includes silicon nitride, and the silicon nitride has a large etching selectivity with respect to the silicon oxide which is the material of the dielectric layer 204.

[0071] The process of forming the second barrier material layer 211 includes a chemical vapor deposition process or an atomic layer deposition process. In this embodiment, the process of forming the second barrier material layer 211 includes a chemical vapor deposition process, and the chemical vapor deposition process can rapidly form a second barrier material layer 211 with a relatively thick thickness and a dense structure.

[0072] Please refer to Figure 8 , planarize the second barrier material layer 211 and the initial first barrier layer 209 until the top surface of the dielectric layer 204 is exposed, form the second barrier layer 212 on the first gate structure 210, and form the first barrier layer 213 on the second gate structure 207.

[0073] In this embodiment, the process of planarizing the second barrier material layer 211 includes a chemical mechanical polishing process. The etching rate of the material of the initial first barrier layer 209 is different from that of the dielectric layer 204; the etching rate of the material of the second barrier material layer 211 is different from that of the dielectric layer 204. Therefore, during the process of planarizing the second barrier material layer 211, the dielectric layer 204 can serve as an etching stop layer for the planarization process.

[0074] First, etch back the initial first gate structure 202 and the initial second gate structure 203 to form a second gate structure 207 and a transitional first gate structure 206, such that the top surface of the second gate structure 207 is lower than the top surface of the dielectric layer 204. Then, form an initial first barrier layer 209 on the second gate structure 207 and the dielectric layer 204. The initial first barrier layer 209 exposes the transitional first gate structure 206. Next, using the initial first barrier layer 209 as a mask, remove a part of the transitional first gate structure 206 to form a first gate structure 210, the top surface of the first gate structure 210 being lower than the top surface of the dielectric layer 204. Finally, form a second barrier layer 212 on the first gate structure 210 and a first barrier layer 213 on the second gate structure 207. The height difference between the first gate structure 210 and the second gate structure 207 formed by this method is within a preset range, so that the heights of the first gate structure 210 and the second gate structure 207 can be precisely controlled, reducing the situation where the height difference between the formed first gate structure and the second gate structure is large due to the width of the initial first gate structure 202 being greater than the width of the initial second gate structure 203, thereby making the performance uniformity of the formed semiconductor structure better.

[0075] So far, the height difference range between the formed second gate structure 207 and the first gate structure 210 is small, and the performance uniformity of the formed semiconductor structure is good.

[0076] Correspondingly, an embodiment of the present invention further provides a semiconductor structure. Please continue to refer to Figure 8 , including:

[0077] A substrate;

[0078] A first gate structure 210 and a second gate structure 207 located on the substrate, the width of the first gate structure 210 in the channel length direction being greater than the width of the second gate structure 207 in the channel length direction;

[0079] A first barrier layer 213 located on the second gate structure 207;

[0080] A second barrier layer 212 located on the first gate structure 210;

[0081] A dielectric layer 204 located on the substrate, the dielectric layer 204 being located on the sidewalls of the first gate structure 210, the second gate structure 207, the first barrier layer 213, and the second barrier layer 212.

[0082] In this embodiment, the difference range between the height of the second gate structure 207 and the height of the first gate structure 210 is: -2 nm to 2 nm.

[0083] In this embodiment, the width range of the first gate structure 210 is greater than or equal to 240 nanometers; the width range of the second gate structure 207 is from 0 nanometers to 96 nanometers.

[0084] In this embodiment, the etching rates of the material of the first barrier layer 213 and the material of the dielectric layer 204 are different; the etching rates of the material of the second barrier layer 207 and the material of the dielectric layer 204 are different.

[0085] In this embodiment, the material of the first barrier layer 213 includes a dielectric material, and the dielectric material includes silicon nitride; the material of the second barrier layer includes a dielectric material, and the dielectric material includes silicon nitride.

[0086] In this embodiment, the first gate structure 210 includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer; the second gate structure 207 includes a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

[0087] In this embodiment, the first gate structure 210 further includes a first work function layer located between the first gate dielectric layer and the first gate layer; the second gate structure 207 further includes a second work function layer located between the second gate dielectric layer and the second gate layer.

[0088] In this embodiment, it further includes: source-drain doping regions 205 in the substrate on both sides of the first gate structure 210 and both sides of the second gate structure 207.

[0089] In this embodiment, the substrate includes: a substrate 200 and a fin structure 201 located on the substrate 200; the first gate structure 210 and the second gate structure 207 straddle the fin structure 201; the channel length direction is the extending direction of the fin structure 201.

[0090] For the semiconductor structure, the height difference range between the second gate structure 207 and the first gate structure 210 is relatively small, and the performance uniformity of the semiconductor structure is relatively good.

[0091] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate; Forming an initial first gate structure, an initial second gate structure, and a dielectric layer on the substrate, wherein the width of the initial first gate structure in the channel length direction is greater than the width of the initial second gate structure in the channel length direction, the dielectric layer is located on partial sidewalls of the initial first gate structure and sidewalls of the initial second gate structure, and the top surface of the initial first gate structure is higher than the top surface of the initial second gate structure; Etching back the initial first gate structure and the initial second gate structure to form a second gate structure and a transition first gate structure, wherein the top surface of the second gate structure is lower than the top surface of the dielectric layer; Forming an initial first barrier layer on the second gate structure and on the dielectric layer, the initial first barrier layer exposing the transition first gate structure; Using the initial first barrier layer as a mask to remove part of the transition first gate structure to form a first gate structure, the top surface of the first gate structure being lower than the top surface of the dielectric layer; Forming a second barrier layer on the first gate structure and forming a first barrier layer on the second gate structure.

2. The method for forming a semiconductor structure according to claim 1, wherein The difference range between the height of the second gate structure and the height of the first gate structure is: -2 nanometers to 2 nanometers.

3. The method for forming a semiconductor structure as claimed in claim 1, wherein, The width range of the initial first gate structure is greater than or equal to 240 nanometers; the width range of the initial second gate structure is 0 nanometers to 96 nanometers.

4. The method for forming a semiconductor structure according to claim 1, wherein The forming method of the initial first barrier layer includes: forming a first barrier material layer on the second gate structure, on the dielectric layer, and on the transition first gate structure; planarizing the first barrier material layer until the top surface of the transition first gate structure is exposed, and forming the initial first barrier layer on the second gate structure.

5. The method for forming a semiconductor structure according to claim 1, wherein, The forming methods of the second barrier layer and the first barrier layer include: forming a second barrier material layer on the first gate structure and on the initial first barrier layer; planarizing the second barrier material layer and the initial first barrier layer until the top surface of the dielectric layer is exposed, forming the second barrier layer on the first gate structure, and forming the first barrier layer on the second gate structure.

6. The method for forming a semiconductor structure according to claim 1, wherein The etching rate of the material of the first barrier layer is different from that of the material of the dielectric layer; the etching rate of the material of the second barrier layer is different from that of the material of the dielectric layer.

7. The method for forming a semiconductor structure according to claim 6, wherein, The material of the first barrier layer includes a dielectric material, and the dielectric material includes silicon nitride; the material of the second barrier layer includes a dielectric material, and the dielectric material includes silicon nitride.

8. The method for forming a semiconductor structure according to claim 1, wherein, The forming methods of the initial first gate structure, the initial second gate structure, and the dielectric layer include: forming a first pseudo-gate structure and a second pseudo-gate structure on the substrate; forming a dielectric layer on the substrate, the dielectric layer being located on sidewalls of the first pseudo-gate structure and sidewalls of the second pseudo-gate structure; removing the first pseudo-gate structure and the second pseudo-gate structure to form a gate opening in the dielectric layer; forming a gate structure material layer in the gate opening and on the dielectric layer; planarizing the gate structure material layer until the top surface of the dielectric layer is exposed to form the initial first gate structure and the initial second gate structure.

9. The method for forming a semiconductor structure as claimed in claim 8, wherein, After forming the first pseudo-gate structure and the second pseudo-gate structure on the substrate and before forming the dielectric layer, it further includes: forming source / drain doping regions in the substrate on both sides of the first pseudo-gate structure and on both sides of the second pseudo-gate structure.

10. The method for forming a semiconductor structure according to claim 9, wherein, The substrate includes: a substrate and a fin structure located on the substrate; the initial first gate structure and the initial second gate structure straddle the fin structure; the channel length direction is the extending direction of the fin structure.

11. The method for forming a semiconductor structure according to claim 1, wherein The first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer; the second gate structure includes a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

12. The method for forming a semiconductor structure according to claim 11, wherein, The first gate structure further includes a first work function layer located between the first gate dielectric layer and the first gate layer; the second gate structure further includes a second work function layer located between the second gate dielectric layer and the second gate layer.

13. A semiconductor structure formed by the forming method according to any one of claims 1 to 12, characterized in that, It includes: A substrate; A first gate structure and a second gate structure located on the substrate, the width of the first gate structure in the channel length direction is greater than the width of the second gate structure in the channel length direction; A first spacer located on the sidewall of the first gate structure; A second spacer located on the sidewall of the second gate structure; A first barrier layer located on the second gate structure and on the second spacer; A second barrier layer located on the first gate structure and on the first spacer; A dielectric layer located on the substrate, the dielectric layer is located on the sidewalls of the first gate structure, the sidewalls of the second gate structure, the sidewalls of the first barrier layer, and the sidewalls of the second barrier layer.

14. The semiconductor structure according to claim 13, wherein The difference range between the height of the second gate structure and the height of the first gate structure is: -2 nm to 2 nm.

15. The semiconductor structure according to claim 13, wherein The width range of the first gate structure is greater than or equal to 240 nm; the width range of the second gate structure is 0 nm to 96 nm.

16. The semiconductor structure according to claim 13, wherein, The material of the first barrier layer has a different etching rate from the material of the dielectric layer; the material of the second barrier layer has a different etching rate from the material of the dielectric layer.

17. The semiconductor structure according to claim 16, wherein The material of the first barrier layer includes a dielectric material, and the dielectric material includes silicon nitride; the material of the second barrier layer includes a dielectric material, and the dielectric material includes silicon nitride.

18. The semiconductor structure according to claim 13, wherein, The first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer; the second gate structure includes a second gate dielectric layer and a second gate layer located on the second gate dielectric layer.

19. The semiconductor structure according to claim 18, wherein, The first gate structure further includes a first work function layer located between the first gate dielectric layer and the first gate layer; the second gate structure further includes a second work function layer located between the second gate dielectric layer and the second gate layer.

20. The semiconductor structure according to claim 13, wherein It further includes: Source / drain doping regions in the substrate on both sides of the first gate structure and on both sides of the second gate structure.

21. The semiconductor structure according to claim 13, wherein, The substrate includes: a substrate and a fin structure located on the substrate; the first gate structure and the second gate structure straddle the fin structure; the channel length direction is the extending direction of the fin structure.

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