memory

Abstract

The application provides a memory. A node contact window is defined by a first separation line and a second separation line. A bottom pad layer and a top body layer in the second separation line are sequentially formed on a word line shielding layer. An insulating layer is used to cover the second separation line, so as to improve the isolation performance of the second separation line on adjacent node contacts.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a memory. Background Art

[0002] A memory, such as a dynamic random access memory (DRAM), typically includes a storage capacitor and a storage transistor electrically connected to the storage capacitor. The storage capacitor is used to store charge representing storage information, and the storage transistor can be electrically connected to the storage capacitor through a node contact.

[0003] In existing memory devices, node contact windows for accommodating node contacts are typically defined by intersecting separation lines. Specifically, a sacrificial layer is used in conjunction with backfill to form separation lines that intersect the bit lines. Specifically, the method for forming separation lines that intersect the bit lines generally involves first forming a sacrificial layer, creating a groove in the sacrificial layer, then filling the groove with an isolation material to form the separation line, and finally removing the sacrificial layer to expose the second separation line. However, this manufacturing process is relatively cumbersome, impacting device production efficiency. Summary of the Invention

[0004] An object of the present invention is to provide a memory that can simplify its manufacturing process while ensuring its device performance.

[0005] Specifically, the present invention provides a memory, comprising: a word line, formed in a word line groove located in the substrate, the top of the word line is lower than the top of the word line groove; a word line shielding layer, formed in the space above the word line groove above the word line; a plurality of first separation lines and a plurality of second isolation lines, formed on the substrate, the first separation lines and the second separation lines intersect to define a node contact window; wherein the second separation line includes a bottom pad layer and a top main layer stacked in sequence on the word line shielding layer, the bottom pad layer directly contacts the word line shielding layer; and an insulating layer, at least covering the side walls of the bottom pad layer and the top main layer in the second separation line.

[0006] In the memory provided by the present invention, a node contact window is defined by a first separation line and a second separation line, wherein the bottom pad layer and the top main layer in the second separation line are sequentially formed on the word line shielding layer, and the second separation line is covered with an insulating layer to improve the isolation performance of the second separation line to adjacent node contact portions. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1a A top view illustrating a first dividing line and a second dividing line of a memory in one embodiment of the present invention is shown;

[0008] Figure 1b for Figure 1a A cross-sectional view of a memory in one embodiment of the present invention taken along directions aa' and bb' is shown;

[0009] Figure 2a A top view of an insulating layer is shown schematically for a memory device according to an embodiment of the present invention;

[0010] Figure 2b for Figure 2a A cross-sectional view of a memory in one embodiment of the present invention taken along directions aa' and bb' is shown;

[0011] Figure 3 is a flow chart of a method for forming a memory in one embodiment of the present invention;

[0012] Figure 4a to Figure 4e FIG. 1 is a structural diagram of a method for forming a memory in an embodiment of the present invention during its preparation process.

[0013] The accompanying drawings are numerals as follows:

[0014] 100-substrate;

[0015] 110-trench isolation structure;

[0016] 120-word line;

[0017] 130-word line shielding layer;

[0018] 101-first source / drain region;

[0019] 102-second source / drain region;

[0020] 200-bit line;

[0021] 300-isolation side wall;

[0022] 310-first isolation side wall;

[0023] 320-second isolation side wall;

[0024] 330-third isolation side wall;

[0025] 400-insulation layer;

[0026] 410 - mask layer;

[0027] 420-insulating side wall portion;

[0028] 500a-bit line contact window;

[0029] 500b-node contact window;

[0030] 510b - lateral depression;

[0031] 610- bottom cushion;

[0032] 610a - bottom material layer;

[0033] 620-top main layer;

[0034] 620a - top material layer;

[0035] L1-first dividing line;

[0036] L2 - Second dividing line. DETAILED DESCRIPTION

[0037] The following is a detailed description of the memory device and its formation method proposed by the present invention, with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are highly simplified and not to exact scale, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0038] Figure 1a A top view illustrating a first dividing line and a second dividing line of a memory in one embodiment of the present invention is shown; Figure 1b for Figure 1a A cross-sectional view of a memory in one embodiment of the present invention taken along directions aa' and bb' is shown; Figure 2a A top view of an insulating layer is shown schematically for a memory device according to an embodiment of the present invention;

[0039] Figure 2b for Figure 2a 1 is a cross-sectional view of a memory in one embodiment of the present invention taken along directions aa' and bb'.

[0040] Combine Figure 1a-1b and Figure 2a-2b As shown, the memory includes a substrate 100, a first separation line L1 and a second separation line L2 formed on the substrate 100. The first separation line L1 is formed by a bit line 200 and an isolation spacer 300 covering a sidewall of the bit line 200.

[0041] Specifically, a plurality of active areas AA are formed in the substrate 100. The plurality of active areas AA are arranged in an array, for example, to form an active area array, wherein adjacent active areas AA can be separated from each other by trench isolation structures 110. It is understood that the active areas AA are defined by forming the trench isolation structures 110.

[0042] Furthermore, the active area AA is used to form a memory cell of a memory, such as a memory transistor. Furthermore, the active area AA includes a first source / drain region 101 and a second source / drain region 102. The first source / drain region 101 and the second source / drain region 102 can be used to form the drain and source regions of the memory transistor. The first source / drain region 101 can be electrically connected to a bit line, and the second source / drain region 102 can be electrically connected to a node contact to further electrically connect to a storage capacitor through the node contact.

[0043] In this embodiment, the active area AA extends obliquely relative to the first direction (i.e., the active area AA extends along the Z direction). Furthermore, in each active area AA, the first source / drain region 101 corresponds to the middle region of the active area AA, and the second source / drain region 102 is formed on both ends of the active area AA (i.e., the two second source / drain regions 102 are respectively arranged on both sides of the first source / drain region 101).

[0044] Furthermore, a plurality of word lines 120 are formed in the substrate 100. The word lines 120 extend along the second direction (X direction) and intersect with the corresponding active area AA. The portion of the word line 120 intersecting with the active area AA is located between the first source / drain region 101 and the second source / drain region 102, and is used to constitute the gate structure of the storage transistor.

[0045] Specific reference Figure 1b and Figure 2b As shown, the word line 120 is formed in a word line trench in the substrate 100, and the top of the word line 120 is not higher than the top of the word line trench. In addition, a word line shielding layer 130 is filled in the space above the word line trench above the word line 120, and the word line shielding layer 130 covers the word line 120.

[0046] Continue to refer Figure 1a and Figure 2a As shown, the bit lines 200 in the first separation line L1 are formed on the substrate 100 and extend along the first direction (Y direction), spatially intersecting the corresponding active area AA. The portion of the bit lines 200 that intersects the active area AA constitutes a bit line contact portion, which is electrically connected to the active area AA. In this embodiment, the bit lines 200 cover the first source / drain regions 101 in the active area AA, and at least one second source / drain region 102 is located between adjacent bit lines 200.

[0047] Furthermore, the bit line 200 may include at least two conductive layers stacked from bottom to top, for example, a first conductive layer, a second conductive layer, and a third conductive layer stacked from bottom to top. Furthermore, in the bit line 200, the first conductive layer of the bit line contact portion is used to electrically contact the active area AA, and the second and third conductive layers are sequentially disposed above the first conductive layer to further enable electrical transmission.

[0048] In this embodiment, the bit line 200 further includes a bit line shielding layer, which is formed above the at least two conductive layers to cover the top surfaces of the at least two conductive layers.

[0049] Key References Figure 1a and Figure 1b As shown, a bitline contact window 500a is further formed in the substrate 100, and at least a portion of the active area AA is exposed in the bitline contact window 500a. That is, at least a portion of the active area AA is exposed in the bitline contact window 500a (in this embodiment, the first source / drain region 101 of the active area AA is exposed in the bitline contact window 500a). Furthermore, the bitline contact portion of the bitline 200 further fills the bitline contact window 500a, extending into the substrate and electrically connecting to the active area AA. In this embodiment, the first conductive layer of the bitline contact portion extends downward into the bitline contact window 500a.

[0050] The width of the bit line contact portion of the bit line 200 in the width direction of the bit line is smaller than the opening size of the bit line contact window 500a in the width direction of the bit line. In other words, the width of the bit line contact portion in the second direction (X direction) is smaller than the opening size of the bit line contact window 500a in the second direction (X direction).

[0051] Furthermore, the isolation spacer 300 in the first separation line L1 covers the sidewalls of the bit line 200 and fills the bit line contact window 500a. In this case, the isolation spacer 300 correspondingly covers the sidewalls of the bit line contact portion. As described above, the outer sidewalls of the bit line contact portion are spaced apart from the trench sidewalls of the bit line contact window 500a. Therefore, the isolation spacer 300 correspondingly covers the outer sidewalls of the bit line contact portion and extends into the bit line contact window 500a.

[0052] Specifically, the isolation spacer 300 can be a stacked structure. For example, the isolation spacer 300 includes a first isolation spacer 310 and a second isolation spacer 320. The first isolation spacer 310 is formed at least in the bit line contact window 500a, and the first isolation spacer 310 also has a mesa flush with the top surface of the substrate (i.e., the portion of the first isolation spacer 310 corresponding to the mesa is formed in the bit line contact window 500a), and the bottom of the second isolation spacer 320 is formed on the mesa of the first isolation spacer 310.

[0053] In this embodiment, the portion of the first isolation sidewall 310 formed in the bit line contact window 500a constitutes a first portion, and the first portion of the first isolation sidewall 310 has a table flush with the top surface of the substrate, and the bottom of the second isolation sidewall 320 is formed on the table of the first portion of the first isolation sidewall 310.

[0054] Continue to refer Figure 1b As shown, the first isolation spacer 310 covers the entire sidewall of the bitline 200. That is, the first isolation spacer 310 fills the bitline contact window 500a and extends to cover the entire sidewall of the bitline 200. As described above, the portion of the first isolation spacer 310 formed in the bitline contact window 500a (that is, the portion of the first isolation spacer 310 covering the bitline below the top surface of the substrate) constitutes the first portion, and the portion of the first isolation spacer 310 covering the bitline sidewall above the substrate constitutes the second portion. In this embodiment, the bottom of the second isolation spacer 320 is formed on the first portion and covers the sidewall of the second portion away from the bitline.

[0055] The second isolation spacer 320 may be the outermost layer of the stacked structure of the isolation spacer 300, and the first isolation spacer 310 may be the middle film layer of the stacked structure of the isolation spacer 300. Furthermore, the first isolation spacer 310 and the second isolation spacer 320 may be formed of different materials. For example, the first isolation spacer 310 may be made of silicon oxide, and the second isolation spacer 320 may be made of silicon nitride.

[0056] Of course, the isolation spacer 300 may further include a third isolation spacer 330 , etc. The third isolation spacer 330 is, for example, formed between the first isolation spacer 310 and the second isolation spacer 320 , or formed between the bit line 200 and the first isolation spacer 310 .

[0057] Key References Figure 1aAs shown, in this embodiment, the opening size of the bit line contact window 500a can be further made larger than the width of the first separation line L1 formed by the bit line 200 and the isolation spacer 300. In this case, when the node contact window 500b is defined by the first separation line L1, the node contact window 500b is partially overlapped with the bit line contact window 500a.

[0058] Specifically, there is at least one second source / drain region 102 between adjacent bit lines 200. Accordingly, among the plurality of first separation lines L1 formed by the bit lines 200 and the isolation spacers 300, there is at least one second source / drain region 102 between adjacent first separation lines L1. On this basis, the second separation lines L2 can be further used to separate adjacent second source / drain regions 102 in adjacent first separation lines L1 from each other.

[0059] Specific reference Figure 1a-1b and Figure 2a-2b As shown, a plurality of second separation lines L2 are formed on the substrate 100 and extend along the second direction (X direction) so that the first separation lines L1 and the second separation lines L2 intersect to define a node contact window 500b. In this embodiment, the second source / drain region 102 in the active area AA is exposed in the node contact window 500b.

[0060] Furthermore, the node contact window 500b is recessed downward into the substrate 100, so that a larger area of ​​the active area AA is exposed in the node contact window 500b. That is, the bottom of the node contact window 500b is lower than the top surface of the substrate 100. This facilitates electrical connection between the node contact portion filled in the node contact window 500b and the active area AA.

[0061] In this embodiment, the bottom of the node contact window 500b is recessed downward into the substrate 100, exposing a portion of the trench isolation structure 110. Furthermore, the depth of the node contact window 500b corresponding to the active area AA is greater than the depth of the node contact window 500b corresponding to the trench isolation structure. In other words, the depth of the node contact window 500b recessed downward in the active area AA is greater than the depth of the node contact window 500b recessed downward in the trench isolation structure 110.

[0062] Furthermore, the node contact window 500b and the bitline contact window 500a also have an overlapping region, and the node contact window 500b is further laterally recessed into the portion of the isolation spacer 300 located in the bitline contact window 500a. In this embodiment, the outer sidewall of the first portion of the first isolation spacer 310 formed in the bitline contact window is exposed in the node contact window 500b, that is, the node contact window 500b is laterally recessed into the first portion of the first isolation spacer 310. It will be understood that the lateral recess 510b is formed in the first portion of the first isolation spacer 510.

[0063] It should be noted that in order to recess the node contact window 500b downward into the substrate 100, the exposed substrate is typically etched under the mask of the first dividing line L1 and the second dividing line L2, so that the formed node contact window 500b is further recessed. At this time, the area of ​​the bit line contact window 500a that overlaps with the node contact window 500b is correspondingly attacked by the etching. That is, the portion of the isolation spacer 300 formed in the bit line contact window 500a is corroded, thereby forming the lateral recess 510b.

[0064] As described above, in this embodiment, the isolation sidewall 300 includes an inner first isolation sidewall 310 and an outer second isolation sidewall 320, and the material of the second isolation sidewall 320 is different from the material of the first isolation sidewall 310. Therefore, when etching the substrate 100, the portion of the first isolation sidewall 310 that is higher than the top surface of the substrate can be protected by the second isolation sidewall 320 to avoid erosion, while the portion of the first isolation sidewall 310 that is lower than the top surface of the substrate will form the lateral recess 510b under the erosion of the etchant.

[0065] Continue to refer Figure 1b As shown, the second dividing line L2 can be a laminated structure having multiple film layers. Specifically, the second dividing line L2 includes a bottom pad layer 610 and a top main body layer 620, wherein the top main body layer 620 is formed above the bottom pad layer 610, and the height of the top main body layer 620 is greater than the height of the bottom pad layer 610.

[0066] The bottom pad layer 610 may include a film layer made of a material different from that of the top body layer 620. It should be noted that when performing a patterning process to prepare the top body layer 620, the bottom pad layer 610 may be used as an etch stop layer because the bottom pad layer 610 includes a film layer made of a material different from that of the top body layer 620, thereby effectively improving etching accuracy when patterning the top body layer 620.

[0067] For example, the bottom pad layer 610 may have only one film layer, in which case the material of the film layer is different from the material of the top main body layer 620; or, the bottom pad layer 610 may also include at least two film layers, in which case at least one of the two film layers has a material different from the material of the top main body layer 620.

[0068] In this embodiment, the bottom cushion layer 610 is schematically shown to include three film layers stacked sequentially from bottom to top, and the materials of each of the three film layers can be the same or different. Specifically, the three film layers include a first film layer, a second film layer, and a third film layer stacked sequentially from bottom to top, wherein the first film layer and the third film layer are made of the same material, and the materials of the first film layer and the third film layer are different from the material of the second film layer.

[0069] It should be noted that, in this embodiment, the materials of the first and third film layers in the bottom pad layer 610 can be different from the material of the top body layer 620; the material of the second film layer in the bottom pad layer 610 can also be different from the material of the top body layer 620; or the materials of the first, second, and third film layers in the bottom pad layer 610 can all be different from the material of the top body layer 620. For example, the materials of the first and third film layers in the bottom pad layer 610 include silicon oxide, the material of the second film layer includes silicon nitride, and the top body layer 620 can be a spin-on dielectric (SOD) layer.

[0070] Key References Figure 2a and Figure 2b As shown, in this embodiment, the memory further includes an insulating layer 400 , which covers at least the sidewalls of the first separation line L1 and the second separation line L2 , and further fills the lateral recess 510 b of the isolation spacer 300 .

[0071] That is, the insulating layer 400 fills the lateral recess 510b of the isolation spacer 300, thereby ensuring that the bit line 200 is not exposed from the bottom, preventing the bit line 200 from shorting with the node contact portion (not shown) filled in the node contact window 500b, and improving the isolation performance between the bit line 200 and the node contact portion. In addition, the insulating layer 400 also covers the second separation line L2, which correspondingly improves the isolation performance of the second separation line L2 from the adjacent node contact portion.

[0072] It can be understood that the insulating layer 400 covers the sidewalls of the node contact window 500b to ensure the isolation performance of the various isolation walls of the node contact window 500b. As described above, the node contact window 500b is recessed downward into the substrate 100 and exposes the active area AA and the trench isolation structure 110. The height of the active area AA exposed in the node contact window 500b is different from the height of the trench isolation structure 110 exposed in the node contact window 500b. Based on this, while the insulating layer 400 covers the sidewalls of the node contact window 500b, the bottom of the insulating layer 400 also extends to the area of ​​the node contact window 500b below the top surface of the substrate to overlap the active area AA or the trench isolation structure 110. At this time, the bottom of the insulating layer 400 overlapping the active area AA is also lower than the bottom of the insulating layer 400 overlapping the trench isolation structure 110.

[0073] Furthermore, the dielectric constant of the top body layer 620 is lower than that of silicon nitride (for example, the dielectric constant of the top body layer 620 is lower than 7). It should be noted that the top body layer 620 in the second separation line L2 is greater than the bottom pad layer 610, and therefore the dielectric constant of the top body layer 620 primarily affects the overall dielectric constant of the second separation line L2. In this embodiment, the use of a low-dielectric-constant top body layer 620 correspondingly reduces the overall dielectric constant of the second separation line L2. This effectively reduces the parasitic capacitance between the node contacts filled in adjacent node contact windows, thereby improving the device performance of the resulting memory.

[0074] Furthermore, the hardness of the insulating layer 400 is greater than that of the second dividing line L2, thereby improving the overall mechanical strength. It should be noted that due to the greater height of the top main layer 620 in the second dividing line L2, the hardness of the top main layer 620 directly affects the overall hardness of the second dividing line L2. Therefore, in this embodiment, the hardness of the insulating layer 400 is greater than that of the top main layer 620 to further improve the overall mechanical strength of the second dividing line L2.

[0075] Specifically, the material of the insulating layer 400 may include silicon nitride, and the top body layer 620 in the second dividing line L2 may be a spin-on dielectric layer (SOD).

[0076] Based on the memory described above, the method for forming the memory is described in detail below with reference to the accompanying drawings. Figure 3 FIG. 1 is a flow chart of a method for forming a memory in one embodiment of the present invention. Figure 4a to Figure 4eFIG. 1 is a structural diagram of a method for forming a memory in an embodiment of the present invention during its preparation process.

[0077] In step S100, refer to Figure 4a As shown, a substrate 100 is provided, and a plurality of bit lines 200 are formed on the substrate 100 .

[0078] A plurality of active areas AA are formed in the substrate 100. Specifically, a plurality of trench isolation structures 110 can be formed in the substrate 100 to define the plurality of active areas AA. Furthermore, the first source / drain region 101 and the second source / drain region 102 in the active areas AA can be formed by an ion implantation process.

[0079] Continue to refer Figure 4a As shown, a plurality of word lines 120 are further formed in the substrate 100 , the word lines 120 extend along the second direction and intersect with the corresponding active areas AA, and the first source / drain regions 101 and the second source / drain regions 102 in the active areas AA are respectively arranged on both sides of the word lines 120 .

[0080] In this embodiment, the top surface of the word line 120 is lower than the top of the word line trench in the substrate. That is, the word line 120 does not completely fill the word line trench. Therefore, the word line shielding layer 130 can be further filled in the word line trench above the word line 120. The word line shielding layer 130 covers the word line 120 to prevent the word line 120 from being electrically connected to other devices.

[0081] Furthermore, a plurality of bitline contact windows are formed in the substrate 100, each of which exposes at least a portion of the active area AA. In this embodiment, the bitline contact windows expose the first source / drain regions 101 of the active area AA, and the opening size of the bitline contact windows can be larger than the size of the first source / drain regions 101 (for example, the bitline contact windows can extend laterally from the active area AA to the adjacent trench isolation structure 110). In this way, the first source / drain regions 101 can be exposed to a greater extent, allowing the first source / drain regions 101 to electrically contact the bitlines 200 thereover over a larger area.

[0082] Specifically, the bit line 200 extends along a first direction and fills a corresponding bit line contact window. The portion of the bit line 200 that fills the bit line contact window constitutes a bit line contact portion, which is electrically connected to the first source / drain region 101 in the active area. In this embodiment, the width of the bit line contact portion is smaller than the opening size of the bit line contact window.

[0083] In step S200, continue to refer to Figure 4aAs shown, an isolation spacer 300 is formed, which covers the sidewall of the bit line 200 and fills the bit line contact window, and the bit line 200 and the isolation spacer 300 form a first separation line L1. It should be understood that the first separation line L1 extends in the direction of the extension of the bit line 200.

[0084] As described above, the width dimension of the bit line contact portion is smaller than the opening dimension of the bit line contact window, so that the outer side wall of the bit line contact portion and the groove side wall of the bit line contact window are spaced apart from each other, and the isolation side wall 300 is correspondingly filled in the space between the outer side wall of the bit line contact portion and the groove side wall of the bit line contact window.

[0085] In this embodiment, the isolation spacer 300 is a multi-layer structure. Specifically, the isolation spacer 300 includes a first isolation spacer 310, a second isolation spacer 320, and a third isolation spacer 330. The formation method thereof includes the following steps, for example.

[0086] In the first step, a first isolation spacer 310 is formed. The first isolation spacer 310 covers the sidewall of the bit line BL.

[0087] In this embodiment, the first isolation spacer 310 further fills the bit line contact window, and the portion of the first isolation spacer 310 filling the bit line contact window further has a mesa flush with the top surface of the substrate.

[0088] In the second step, a third isolation spacer 330 and a second isolation spacer 320 are sequentially formed. The bottoms of the third isolation spacer 330 and the second isolation spacer 320 are both formed on the mesa of the first isolation spacer 310 and cover the sidewalls of the first isolation spacer 310. The third isolation spacer 330 and the second isolation spacer 320 can be formed in a self-aligned manner, for example, by a deposition process and an etch-back process.

[0089] Furthermore, the material of the outer second isolation spacer 320 is different from the material of the inner first isolation spacer 310. For example, the material of the second isolation spacer 320 includes silicon nitride, and the material of the first isolation spacer 310 includes silicon oxide.

[0090] It should be noted that in this embodiment, the first isolation spacer 310 fills the bit line contact window and also extends upward to cover the sidewall of the bit line. However, in other embodiments, the first isolation spacer may only fill the bit line contact window, and the remaining isolation spacers may be sequentially formed above the first isolation spacer to cover the sidewall of the bit line.

[0091] Continue to refer Figure 4aAs shown, in this embodiment, the mesa width of the first isolation sidewall 310 is greater than the sum of the thicknesses of the second isolation sidewall and the third isolation sidewall, so that part of the mesa of the first isolation sidewall 310 is exposed.

[0092] In step S300, refer to Figure 4b to Figure 4d As shown, a plurality of second separation lines L2 are formed on the substrate 100. The second separation lines L2 extend along a second direction and intersect with the first separation lines L1 to define node contact windows 500b. In this embodiment, the node contact windows 500b are further recessed downward into the substrate 100, and the node contact windows 500b and the bit line contact windows have an overlapping area. The node contact windows 500b are also laterally recessed into the portion of the isolation spacer 300 located within the bit line contact windows.

[0093] Specifically, the method for forming the second dividing line L2 includes, for example, the following steps.

[0094] Step 1, specific reference Figure 4b As shown, an isolation material layer (in this embodiment, including a bottom material layer 610 a and a top material layer 620 a ) is formed on the substrate 100 .

[0095] The isolation material layer may be a planarized film layer. In this embodiment, the bit lines 200 are used as a grinding stop layer to achieve the planarization process of the isolation material layer. Based on this, the top surface of the isolation material layer is flush with the top surface of the bit lines 200. In this case, it can be considered that the isolation material layer is filled between adjacent bit lines 200.

[0096] Continue to refer Figure 4b As shown, the isolation material layer includes a bottom material layer 610 a and a top material layer 620 a , and the thickness of the top material layer 620 a is greater than that of the bottom material layer 610 a .

[0097] The bottom material layer 610a may be a laminated structure. In this embodiment, the bottom material layer 610a includes a first material layer, a second material layer, and a third material layer stacked sequentially from bottom to top, and at least one of the first material layer, the second material layer, and the third material layer has a film layer made of a material different from that of the top material layer 620a.

[0098] Step 2, specific reference Figure 4c and Figure 4dAs shown, a patterned mask layer 410 is formed, and the isolation material layer is etched using the mask layer 410 as a mask to form the second separation line L2. In this embodiment, the mask layer 410 not only covers the region of the second separation line, but also covers the top surface of the bit line 200 to avoid damage to the bit line 200 when etching the isolation material layer.

[0099] Specifically, the process of etching the isolation material layer using the mask layer 410 as a mask includes a first etching step and a second etching step.

[0100] Specific reference Figure 4c As shown, in the first etching step, the top material layer 620a is etched to form the top main body layer 620 of the second separation line L2, and the etching stops at the bottom material layer 610a. As described above, because the bottom material layer 610a includes a film layer made of a different material than the top material layer 620a, the bottom material layer 610a can be used to control the etching endpoint of the first etching step, facilitating precise control of the first etching step. For example, in the first etching step, the etching selectivity ratio between the top material layer 620a and the bottom material layer 610a is greater than or equal to 4:1.

[0101] In this embodiment, during the first etching step, etching stops at the second material layer disposed in the middle of the bottom material layer 610a. It can be considered that, in the first etching step, the etching selectivity ratio between the top material layer 620a and the second material layer in the bottom material layer 610a is greater than or equal to 4:1.

[0102] Next reference Figure 4d As shown, in the second etching step, the bottom material layer 610a is etched to form a bottom pad layer 610. In this embodiment, in the second etching step, the second material layer and the first material layer are sequentially etched to expose the substrate 100.

[0103] At this point, the second separation line L2 including the top main layer 620 and the bottom pad layer 610 is formed, and the pattern of the node contact window can be defined by the second separation line L2 and the first separation line L1.

[0104] It should be noted that the node contact window 500b to be formed in this embodiment is further recessed downward into the substrate 100. Based on this, after forming the second dividing line L2 to define the pattern of the node contact window, it also includes: further etching the exposed substrate 100 to form a node contact window 500b with a bottom recess.

[0105] In this embodiment, a portion of the active area AA and a portion of the trench isolation structure 110 are exposed at the bottom of the node contact window 500b. Based on this, when etching the exposed substrate 100 to form a node contact window 500b with a bottom recess, the exposed active area AA and the exposed trench isolation structure 110 are correspondingly etched, and the etching depth of the exposed active area AA is greater than the etching depth of the exposed trench isolation structure 110, so that the depth of the formed node contact window 500b recessed downward in the active area AA is greater than the depth of the node contact window 500b recessed downward in the trench isolation junction 110.

[0106] Furthermore, since the node contact window 500 b and the bit line contact window have an overlapping area, a portion of the bit line contact window is exposed in the node contact window 500 b. Therefore, when etching the exposed substrate 100, the portion of the isolation spacer 300 that fills the bit line contact window is also etched and further recessed laterally into the isolation spacer 300.

[0107] Combined with reference Figure 4a and Figure 4d As shown, in this embodiment, the width of the portion of the first isolation sidewall 310 filled in the bit line contact window is greater than the sum of the widths of the second isolation sidewall 320 and the third isolation sidewall 330. At this time, the portion of the first isolation sidewall 310 filled in the bit line contact window will be exposed from the top surface of the substrate 100.

[0108] The outer second isolation material layer 320 is made of a different material than the first isolation material layer 310, and during the etching process of the substrate 100, the second isolation material layer 320 is less etched, thereby allowing the second isolation material layer 320 to protect the inner isolation spacers. However, during the etching process of the substrate 100, the first isolation material layer 310 may be etched at a higher rate, and the exposed portion of the first isolation spacer 310 that fills the bitline contact window will be removed. In particular, as the etching proceeds, the sidewalls of the first isolation spacer 310 are further exposed, causing the etchant to further laterally erode the portion of the first isolation spacer located within the bitline contact window, forming the lateral recess 510b in the portion of the first isolation spacer 310 formed within the bitline contact window.

[0109] In step S400, refer to Figure 4eAs shown, an insulating layer 400 is formed. The insulating layer 400 covers the sidewalls of the first and second separation lines L1 and L2 and also fills the lateral recesses of the isolation spacers. In other words, the insulating layer 400 fills the lateral recesses of the isolation spacers to improve the isolation performance between the bit line 200 and the node contact portion subsequently filled in the node contact window.

[0110] It should be noted that in this embodiment, after the second dividing line L2 is formed using the mask layer 410, the mask layer 410 is retained. Furthermore, when forming the insulating layer 400, a deposition process and an etch-back process can be directly used to self-align the insulating sidewall portions 420 on the sidewalls of the first dividing line L1 and the second dividing line L2. In this case, the mask layer 410 and the insulating sidewall portions 420 can be considered to constitute the insulating layer 400.

[0111] In which, the insulating sidewall portion 420 covers the side walls of the first separation line L1 and the second separation line L2, and the bottom of the insulating sidewall portion 420 also extends to the area of ​​the node contact window 500b below the top surface of the substrate to overlap the active area AA or the trench isolation structure 110, and the bottom of the insulating sidewall portion 420 overlapping the active area AA is lower than the bottom of the insulating sidewall portion 420 overlapping the trench isolation structure 110.

[0112] To sum up, in the memory provided by the present invention, the isolation sidewall used to constitute the first separation line can be allowed to be etched and damaged to have a lateral recess. At this time, the lateral recess of the isolation sidewall can be filled with an insulating layer to prevent the bit line from being exposed and ensure electrical isolation between the bit line and the adjacent node contact portion.

[0113] Furthermore, for node contacts recessed into the substrate, the node contacts are also likely to be laterally recessed into the portion of the isolation sidewall located within the bitline contact. That is, the isolation sidewall is likely to be laterally recessed in the portion of the bitline contact. In this case, the insulating layer will correspondingly fill the lateral recess of the isolation sidewall.

[0114] Furthermore, it should be noted that in conventional processes, the preparation of the second separation line typically involves first forming a sacrificial layer, creating a groove in the sacrificial layer, then filling the groove with an isolation material to form the second separation line, and finally removing the sacrificial layer to expose the second separation line. This prevents etching of the substrate region of the node contact window, prevents erosion of the isolation sidewalls filling the bitline contact window, and ensures the integrity of the isolation sidewalls.

[0115] However, in the memory formation method provided by the present invention, the presence of an insulating layer allows for minor etching damage to the isolation sidewalls forming the first separation line. Based on this, when preparing the second separation line and further forming a downwardly recessed node contact window, the present invention's preparation method can include: first, forming an isolation material layer on the substrate; then, directly patterning the isolation material layer to form the second separation line; and then, further etching the exposed substrate to form a downwardly recessed node contact window. It should be understood that although this process may cause erosion of the isolation sidewalls, resulting in lateral recesses, the isolation performance of the first separation line can still be maintained, compensated by the insulating layer.

[0116] It can be seen that compared with traditional processes, in the memory and its formation method provided by the present invention, since the integrity requirements for the isolation side wall can be relaxed, the isolation material layer can be directly patterned to directly form the second separation line, and its preparation steps are simpler, which is conducive to simplifying the preparation process of the device.

[0117] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0118] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0119] It should also be understood that the terms described herein are intended to describe particular embodiments only and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" as used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. Furthermore, implementation of the methods and / or apparatus in embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A memory, characterized in that: include: substrate; The substrate includes an active area and a trench isolation structure; A word line is formed in a word line trench in the substrate, wherein a top of the word line is lower than a top of the word line trench; A word line shielding layer is formed in a space above the word line trench and above the word line; A plurality of first separation lines and a plurality of second separation lines are formed on the substrate, wherein the first separation lines and the second separation lines intersect to define a node contact window; wherein the second separation lines include a bottom pad layer and a top body layer stacked sequentially on the word line shielding layer, and the bottom pad layer directly contacts the word line shielding layer; and an insulating layer covering at least the sidewalls of the bottom pad layer and the top main body layer in the second dividing line; The node contact window is recessed downward into the substrate and exposes the active area and the trench isolation structure. The bottom surface of the insulating layer is lower than the top surface of the substrate and directly contacts the active area and the trench isolation structure.

2. The memory according to claim 1, wherein The height of the top main body layer is greater than the height of the bottom cushion layer.

3. The memory according to claim 1, wherein The insulating layer has a harderness greater than that of the top body layer.

4. The memory according to claim 1, wherein The top bulk layer has a dielectric constant lower than that of silicon nitride.

5. The memory according to claim 1, wherein The bottom cushion layer includes at least two film layers, and the material of at least one of the at least two film layers is different from the material of the top main body layer.

6. The memory according to claim 1, wherein: The insulating layer includes a mask layer and an insulating sidewall portion, the mask layer covers a top surface of the top body layer, and the insulating sidewall portion covers sidewalls of the bottom pad layer and the top body layer.

7. The memory according to claim 6, wherein: The side surface of the mask layer is aligned with the side surface of the top body layer, and the insulating sidewall portion further covers the side wall of the mask layer.

8. The memory according to claim 1, wherein: The first separation line includes a bit line and an isolation spacer, and the isolation spacer covers a sidewall of the bit line.

9. The memory according to claim 8, wherein The bottom of the node contact window is also laterally recessed into the isolation spacer, and the insulating layer also covers the first separation line and fills the lateral recess of the isolation spacer.

10. The memory according to claim 9, wherein A bit line contact window is formed in the substrate, and the first separation line also fills the bit line contact window on its extension path; the bottom of the node contact window is recessed downward into the substrate, and the recessed portion of the node contact window is also recessed laterally into the portion of the isolation sidewall located in the bit line contact window.

11. The memory according to claim 8, wherein The isolation spacer includes a first isolation spacer and a second isolation spacer; the first isolation spacer covers the sidewall of the bit line, and the bottom of the first isolation spacer further extends laterally to form a mesa; the second isolation spacer covers the sidewall of the first isolation spacer, and the bottom of the second isolation spacer is formed on the mesa of the first isolation spacer; Furthermore, the insulating layer covers the sidewalls of the second isolation spacer, and the bottom of the insulating layer is lower than the bottom of the second isolation spacer.

12. The memory according to claim 11, wherein The bottom of the insulating layer covers the first isolation sidewall.

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