Memory element and method of manufacturing the same
By adding the support column and end thickness of the stacked structure during the manufacturing process of the three-dimensional NAND flash memory, the gate layer erosion and stacked structure collapse problems caused by the contact window opening depth are solved, and the process stability is improved and Pass rate.
Patent Information
- Application Number
- CN202011297319.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Priority Date
- 2020-11-12
- Filing Date
- 2020-11-18
- Publication Date
- 2024-12-31
- Estimated Expiration
- 2040-11-18
AI Technical Summary
During the manufacturing process, the three-dimensional NAND flash memory has a problem that the gate layer is easily etched when the contact window opening depth is deep during the manufacturing process, and the stacked structure is prone to collapse during the etching process, which affects the stability and pass rate of the process.
The supporting column structure is formed on the stacked structure of the memory array region and the step region, and the material thickness is increased at the end, forming a plurality of horizontal openings, increasing the thickness of the end to avoid etching of the gate layer, while simultaneously before etching A support column structure is formed to prevent the laminated structure from collapse.
The gate layer below the shallower contact window opening is effectively avoided to be etched through, increasing process space and pass rate, and the process can be integrated with existing processes, improving manufacturing stability and efficiency.
Smart Images
Figure CN114497050B_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of semiconductor and storage technology, and relates to a memory element and a manufacturing method thereof. Background Art
[0002] Non-volatile memory elements (eg, flash memory) have become a widely used memory element in personal computers and other electronic devices because they have the advantage that stored data will not disappear even after power is turned off.
[0003] The flash memory arrays commonly used in the industry include NOR flash memory and NAND flash memory. Since the structure of NAND flash memory is to connect each storage unit in series, its integration and area utilization are better than NOR flash memory, and it has been widely used in a variety of electronic products. In addition, in order to further improve the integration of memory elements, a three-dimensional NAND flash memory has been developed. However, there are still many challenges associated with three-dimensional NAND flash memory. Summary of the invention
[0004] The present invention provides a memory element, comprising: a substrate, a stacked structure, a dielectric layer and a first contact window. The substrate comprises a memory array region and a step region. The stacked structure is located on the substrate in the memory array region and the step region, wherein the stacked structure comprises a plurality of conductor layers and a plurality of insulating layers stacked alternately with each other. Each of the plurality of conductor layers comprises: a main body portion, located in the memory array region and extending to the step region; and an end portion, connected to the main body portion and located in the step region, wherein the thickness of the end portion is greater than the thickness of the main body portion. The dielectric layer is located on the stacked structure in the memory array region and the step region. The first contact window penetrates the dielectric layer in the step region and the corresponding insulating layer located above the end portion, and lands on the end portion and is connected to the end portion.
[0005] In one embodiment of the present invention, a method for manufacturing a memory element includes: providing a substrate, the substrate including a memory array region and a step region; forming a stacked structure on the substrate in the memory array region and the step region, wherein the stacked structure includes a plurality of first material layers and a plurality of second material layers alternately stacked with each other; patterning the stacked structure to form a step structure in the stacked structure in the step region; removing a portion of the plurality of second material layers at the end of the step structure to form a plurality of first horizontal openings; removing a portion of the plurality of first material layers around the plurality of first horizontal openings to increase the height of the plurality of first horizontal openings; forming an end portion in each of the plurality of first horizontal openings, the material of the end portion being the same as the material of the plurality of second material layers, and the thickness of the end portion being greater than the thickness of the adjacent second material layer; forming a dielectric layer on the stacked structure in the memory array region and the step region; and forming a first contact window in the step region, wherein the first contact window penetrates the dielectric layer in the step region and the corresponding first material layer located above the end portion, and lands on the end portion and is connected to the end portion.
[0006] Based on the above, in multiple embodiments of the present invention, the thickness of the terminal portion of the gate is locally increased to prevent the gate layer below the shallower contact window opening from being etched through during the process of forming the deeper contact window opening. The process of forming the terminal portion can be integrated with the existing process. In addition, before forming the terminal portion, a support column structure can be formed in the stacked structure in the step region to prevent the stacked structure from collapsing during the etching process of forming the terminal portion. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1A to FIG. 1I It is a cross-sectional schematic diagram of a method for manufacturing a three-dimensional memory element according to an embodiment of the present invention.
[0008] FIG. 2A to FIG. 2I It is another cross-sectional schematic diagram of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention.
[0009] FIG. 3A to FIG. 3C It is a cross-sectional schematic diagram of a method for manufacturing a three-dimensional memory element according to another embodiment of the present invention.
[0010] FIG. 4A to FIG. 4C is another cross-sectional schematic diagram of a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.
[0011] FIG. 5A to FIG. 5C FIG. 1 is a top view of an intermediate stage of a three-dimensional memory device according to an embodiment of the present invention.
[0012] Figure 5DIt is shown Figure 5C A partial stereogram of .
[0013]
Explanation of symbols
[0014] 96, 106: Opening
[0015] 98, 98A, 98B, 98C, 98D, 98E: Support structure
[0016] 100: Base
[0017] 101, 101': laminated structure
[0018] 102: First material layer
[0019] 102T: Insulation layer
[0020] 103: Dielectric layer
[0021] 104: Second material layer
[0022] 104E: Filling layer
[0023] 104': Material layer
[0024] 105: Ladder structure
[0025] 107, 107', 121: Horizontal opening
[0026] 108: Charge storage structure
[0027] 110: Channel layer
[0028] 112: Insulation column
[0029] 114: Conductor plug
[0030] 115: Insulation top cover
[0031] 122, 128, 129: Mask layer
[0032] 124: Metal layer
[0033] 126: Gate layer
[0034] 131, 132: Conductor layer
[0035] A1, A2, A3: Area
[0036] C1, C2, C3: Contact window
[0037] CP: Vertical Channel Column
[0038] EP: End
[0039] MP: Main body
[0040] OP1, OP1A, OP1B, OP1C, OP1D: Contact window opening
[0041] R1: Memory array area
[0042] R2: Step Area
[0043] T1, T2, T3, T4: thickness
[0044] I-I', II-II', III-III', IV-IV': tangent DETAILED DESCRIPTION
[0045] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0046] FIG. 1A to FIG. 1I It is a cross-sectional schematic diagram of a method for manufacturing a three-dimensional memory element according to an embodiment of the present invention. FIG. 2A to FIG. 2I It is another cross-sectional schematic diagram of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention. Figure 5A The cross-sectional view of the tangent line I-I' is shown in Figures 1A to 1I shown. Figure 5A The cross-sectional view of the section II-II' is shown in FIG. Figures 2A to 2I shown. Figure 5B The cross-sectional view of the part of the process along the tangent line III-III' is shown in Figures 1A to 1I shown. Figure 5B The cross-sectional view of the part of the process along the tangent line IV-IV' is shown in FIG. Figures 2A to 2I shown.
[0047] Please refer to Figure 1A and 2A , providing a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. In one embodiment, a doped region may be formed in the substrate 100 according to design requirements. The substrate 100 has a memory array region R1 and a step region R2. The step region R2 includes regions A1, A2, and A3 (such as Figure 5A ). A component layer (not shown) and a metal interconnect structure (not shown) may be formed on the substrate 100. The component layer may include active components or passive components. Active components are, for example, transistors, diodes, etc. Passive components are, for example, capacitors, inductors, etc. The metal interconnect structure may include a dielectric layer, a plug, and a wire.
[0048] Please refer to Figure 1A and 2A, a stacked structure 101 is formed above the substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The stacked structure 101 is located on the memory array region R1 and the step region R2. The stacked structure 101 includes a plurality of first material layers 102 and a plurality of second material layers 104 that are alternately stacked. The first material layer 102 may be an insulating layer, such as silicon oxide. The second material layer 104 may be an insulating layer (such as silicon nitride) or a conductive layer (such as doped polysilicon). In one embodiment, the material of the first material layer 102 includes silicon oxide, and the material of the second material layer 104 includes silicon nitride. In another embodiment, the material of the first material layer 102 includes silicon oxide, and the material of the second material layer 104 includes doped polysilicon. In this embodiment, the bottom layer of the stacked structure 101 is the first material layer 102, and the top layer is the second material layer 104, but the present invention is not limited thereto. In addition, in this embodiment, four second material layers 104 and four first material layers 102 are used for illustration, however, the present invention is not limited thereto.
[0049] Next, please refer to Figure 2A , a support structure 98 is formed in the stacked structure 101 of the step region R2. The support structure 98 may also be referred to as a dummy structure. In some embodiments, the method for forming the support structure 98 is as follows. An opening 96 is formed in the stacked structure 101. In one embodiment, the opening 96 may have substantially vertical sidewalls, such as Figure 2A As shown. In another embodiment, the opening 96 may have a slightly inclined sidewall. Afterwards, an insulating layer (not shown) is formed on the stacked structure 101 and in the opening 96. The material of the insulating layer is different from the second material layer 104, for example, silicon oxide. Afterwards, a planarization process, such as a chemical mechanical polishing process or an etch-back process, is performed to remove the insulating layer outside the opening 96 to form a support structure 98 in the opening 96. The support structure 98 can prevent the stacked structure 101 from collapsing in subsequent processes. The support structure 98 can have various shapes, such as a pillar, a fence, or a wall. The support structure 98 can be formed only in the step area R2, or it can be formed in the step area R2 and the memory array area R1 at the same time. The following will refer to FIG. 5A to FIG. 5D , the shape and position of the support structure 98 are explained in detail.
[0050] Please refer to Figure 5A and 5B The opening 96 may be a hole in the stacked structure 101 in the step region R2. The support structure 98 formed in the hole may be a support column. The support structure (support column) 98 is located next to the contact window to be formed later. In some embodiments, please refer to Figure 5AThe supporting structures (supporting columns) 98 may be multiple and may be arranged in a row, and are disposed in the area A2 between the areas A1 and A3, and between the contact windows C1 and C3 of the areas A1 and A3. In other embodiments, please refer to Figure 5B The supporting structures (support pillars) 98 may be multiple and may be arranged in an array, respectively disposed in the areas A1 and A3 , and the contact windows C1 and C3 are respectively located between the supporting structures (support pillars) 98 .
[0051] Please refer to Figure 5C In other embodiments, the opening 96 may be a trench extending from the region A2 of the step region R2 to the memory array region R1. The support structure 98 formed in the trench may be a support wall (slit) extending continuously from the memory array region R1 to the step region R2. Figure 5C and 5D The single support structure (support wall) 98 is shown in the figure, but the present invention is not limited thereto. The support structure (support wall) 98 is disposed in the area A2 and is located between the contact windows C1 and C3.
[0052] Next, please refer to Figure 1B and 2B , an insulating layer 102T is formed on the stacked structure 101 of the memory array region R1 and the step region R2 and the support structure 98. The material of the insulating layer 102T is different from that of the second material layer 104, and the material of the insulating layer 102T is the same as that of the first material layer 102, such as silicon oxide. The insulating layer 102T and the stacked structure 101 can be collectively referred to as a stacked structure 101'.
[0053] Afterwards, please refer to Figure 1C and 2C , the insulating layer 102T, the second material layer 104, the first material layer 102 and the support structure 98 of the stacked structure 101' are patterned so that the ends of the insulating layer 102T, the second material layer 104 and the first material layer 102 form a step structure 105 in the step region R2. In some embodiments, the support structure 98 is patterned into support structures (support pillars) 98A, 98B, 98C and 98D with different heights, such as Figure 2C In other embodiments, the support structure 98 is patterned into support structures (support walls) 98E having different heights, such as Figure 5D shown.
[0054] Please refer to Figure 2CIn the step region R2, the support structures 98A, 98B, 98C and 98D penetrate the first material layer 102 and the second material layer 104 of the step structure 105 and reach the bottom first material layer 102. Except for the top surface of the support column 98D closest to the memory array region R1, which is covered by the insulating layer 102T, the top surfaces of the remaining support structures 98A, 98B and 98C are exposed. In the step region R2, where the support structures 98A, 98B, 98C and 98D are not formed, the second material layer 104 of the step structure 105 is covered by the first material layer 102 and the insulating layer 102T, as shown in FIG. Figure 1C and 2C As shown. That is, the topmost layer of the stepped structure 105 exposes the insulating layer 102T, but does not expose the supporting structure 98D. The remaining layers of the stepped structure 105 expose the top surface of the first material layer 102 and the top surfaces of the supporting structures 98A, 98B, and 98C. The top surface of each first material layer 102 is, for example, coplanar with the supporting structures 98A, 98B, and 98C. In addition, the sidewalls of the stepped structure 105 expose the insulating layer 102T, the first material layer 102, and the second material layer 104.
[0055] Please refer to Figure 5D , the support structure 98 is patterned into a support structure (support wall) 98E. The support structure (support wall) 98E extends continuously from the memory array area R1 to the step area R2. The support structures (support walls) 98E in the memory array area R1 have the same height and are covered by the insulating layer 102T. The support structures (support walls) 98E in the step area R2 have different heights. The topmost step of the step structure 105 exposes the insulating layer 102T, but does not expose the support structure 98E. The remaining steps of the step structure 105 expose the top surface of the first material layer 102 and the top surface of the support structure 98E, and the top surface of each layer of the first material layer 102 is, for example, coplanar with the support structure 98E. In addition, the sidewalls of the step structure 105 expose the insulating layer 102T, the first material layer 102, the second material layer 104 and the support structure 98E. For ease of explanation, the subsequent process is still described below using the support structure 98 , and the support structure 98 may be support structures 98A, 98B, 98C, and 98D or support structure 98E.
[0056] Please refer to Figure 1D and Figure 2D , a pull-back process is performed, such as a selective etching process, to remove the end portion of the second material layer 104 of the stepped structure 105 to form a plurality of horizontal openings 107. In some embodiments, the pull-back process may be performed on all the end portions of the second material layer 104, such as Figure 1D and Figure 2DThe pull-back process can also be performed on the end portion of a single layer or multiple layers of the second material layer 104 (not shown). For example, the mask layer can be used to cover the lower 1 to 2 layers of the second material layer 104 of the stacked structure 101', so that the pull-back process is only performed on the upper 1 to 2 layers of the second material layer 104 of the stacked structure 101', so that the horizontal opening 107 is formed at the end of the upper 1 to 2 layers of the second material layer 104 of the stacked structure 101'.
[0057] The pull-back process is, for example, a selective etching process. The selective etching process may be a dry or wet etching process. In some embodiments, the second material layer 104 is silicon nitride, and the wet etching process uses hot phosphoric acid as an etchant. In some embodiments, the second material layer 104 is doped polysilicon, and the wet etching process uses ammonia as an etchant. The support structure 98 may support the insulating layer 102T and the first material layer 102 to prevent the step structure 105 from collapsing during the selective etching process. The thickness of the first material layer 102 between two adjacent horizontal openings 107 is, for example, 20 nm or greater than 20 nm.
[0058] Please refer to Figure 1E and 2E , an expansion process, such as a selective etching process, is performed to remove the first material layer 102 and the insulating layer 102T exposed by the multiple horizontal openings 107, so that the height of the multiple horizontal openings 107 is increased to form multiple horizontal openings 107'. The selective etching process is, for example, a dry or wet etching process. The selective etching process can use hydrofluoric acid as an etchant, for example. The first material layer 102 between two adjacent horizontal openings 107' has a sufficient thickness to avoid collapse due to being too thin. In order to prevent the first material layer 102 and the insulating layer 102T from collapsing, the ratio of the thickness T4 of the first material layer 102 that has undergone the expansion process of the horizontal opening 107 to the pullback amount (i.e., the width D) of the second material layer 104 is less than or equal to 1:10. For example, if the thickness of the remaining first material layer 102 is 10nm, the pullback amount of the second material layer 104 should be less than or equal to 100nm. If the support structure 98 is formed, the ratio of the thickness T4 of the first material layer 102 that has undergone the horizontal opening 107 expansion process to the pull-back amount (ie, width D) of the second material layer 104 may be greater than or equal to 1:40.
[0059] Please refer to Figure 1F and 2F, a filling layer 104E is formed on the insulating layer 102T and in the plurality of horizontal openings 107'. The filling layer 104E may be made of the same material as the second material layer 104. The filling layer 104E is, for example, a conformal layer, which may conformally cover the insulating layer 102T and fill in the plurality of horizontal openings 107'. The filling layer 104E has good trench filling properties and may fill in the plurality of horizontal openings 107'. In some embodiments, the filling layer 104E may have seams, and these seams may form a plurality of voids in a subsequent thermal process due to the aggregation of the filling layer 104E.
[0060] Please refer to Figure 1F and 2F , the filling layer 104E is, for example, silicon nitride, doped polysilicon or doped amorphous silicon. The amorphous silicon will be crystallized in a subsequent thermal process to form doped polysilicon. In the embodiment where the filling layer 104E and the second material layer 104 are doped polysilicon or doped amorphous silicon, the doping material in the doped polysilicon of the filling layer 104E is of the same type as the doping material in the doped polysilicon of the second material layer 104, or even the same doping material. For example, the filling layer 104E and the second material layer 104 are both polysilicon doped with phosphorus.
[0061] Please refer to Figure 1G and 2G , the filling layer 104E outside the plurality of horizontal openings 107' is removed, so that the top surfaces of the first material layer 102 and the insulating layer 102T are exposed, and the remaining plurality of filling layers 104E are separated from each other. In some embodiments, the filling layer 104E is formed at the end of each second material layer 104. In other embodiments, the filling layer 104E forms the end of the second material layer 104 at the upper layer.
[0062] The side walls of the plurality of filling layers 104E are connected to the side walls of the second material layer 104 to form a continuous material layer 104'. The filling layer 104E is the end portion EP of the material layer 104'; the second material layer 104 is the main body MP of the material layer 104'. The thickness T2 of the end portion EP is greater than the thickness T1 of the main body MP. On the contrary, the thickness T4 of the first material layer 102 covering the end portion EP is less than the thickness T3 of the first material layer 102 covering the main body MP. In addition, in some embodiments, in the longitudinal direction (for example, the Z direction), the end portion EP and another adjacent end portion EP may be staggered (for example, in the Z direction). Figure 1G In some other embodiments, the end portion EP and another adjacent end portion EP may slightly overlap in the longitudinal direction (eg, the Z direction) (not shown).
[0063] Please refer to Figure 1H and2H Then, a dielectric layer 103 is formed on the substrate 100 to cover the stacked structure 101'. Figure 1H As shown, a patterning process is performed to remove a portion of the stacked structure 101' of the memory array region R1 to form one or more openings 106 passing through the stacked structure 101'. In one embodiment, the opening 106 may have a slightly inclined sidewall, such as Figure 1H As shown. In another embodiment, the opening 106 may have substantially vertical sidewalls (not shown). In one embodiment, the opening 106 is also called a vertical channel (VC) hole. A vertical channel column CP is then formed in the opening 106. The vertical channel column CP may be formed by the following method, but is not limited thereto.
[0064] Please refer to Figure 1H , a charge storage structure 108 is formed on the sidewall of the opening 106. The charge storage structure 108 is in contact with the first material layer 102 and the second material layer 104. The material of the charge storage structure 108 is, for example, an oxide / nitride / oxide (ONO) composite layer. In one embodiment, the charge storage structure 108 is formed on the sidewall of the opening 106 in the form of a spacer, and the bottom surface of the opening 106 is exposed.
[0065] Then, please refer to Figure 1H , a channel layer 110 is formed on the charge storage structure 108. The material of the channel layer 110 includes, for example, polysilicon. In one embodiment, the channel layer 110 covers the charge storage structure 108 on the sidewall of the opening 106 and covers the bottom surface of the opening 106. Next, an insulating column 112 is formed at the lower portion of the opening 106. In one embodiment, the material of the insulating column 112 includes, for example, silicon oxide. Thereafter, a conductor plug 114 is formed at the upper portion of the opening 106, and the conductor plug 114 is in contact with the channel layer 110. In one embodiment, the material of the conductor plug 114 includes, for example, doped polysilicon. The channel layer 110 and the conductor plug 114 may be collectively referred to as a vertical channel column CP. The charge storage structure 108 surrounds the vertical outer surface of the vertical channel column CP. Next, an insulating cap layer 115 is formed above the stacked structure 101'. The material of the insulating cap layer 115 includes, for example, silicon oxide.
[0066] Please refer to Fig. 1I and Fig.2IIn the embodiment where the second material layer 104 and the filling layer 104E are doped polysilicon, the material layer 104' formed by the second material layer 104 and the filling layer 104E can be used as a gate layer. The material layer 104' (gate layer) is around the sidewall of the charge storage structure 108. In the embodiment where the second material layer 104 and the filling layer 104E are silicon nitride, a gate replacement process must be further performed to form the gate layer 126, which will be described later. FIG. 3A to FIG. 3C as well as FIG. 4A to FIG. 4C Please explain in more detail.
[0067] Afterwards, please refer to Fig. 1I and Figure 5A In the embodiment where the second material layer 104 and the filling layer 104E are doped polysilicon, or in the embodiment where the second material layer 104 and the filling layer 104E are doped polysilicon and doped amorphous silicon respectively, after forming the insulating cap layer 115, a plurality of contact windows C1 and C3 are respectively formed in the region A1 and the region A3 of the step region R2 (e.g. Fig. 1I and 5A ), and forming a plurality of contact windows C2 (as shown in FIG. Fig. 1I As shown). The contact windows C1 and C3 penetrate the insulating cap layer 115, the dielectric layer 103, the insulating layer 102T and the first material layer 102, and land at the end portion EP of the material layer 104' (gate layer) and are electrically connected thereto, as shown in FIG. Fig. 1I and 5A The contact window C2 passes through the insulating cap layer 115 and the laminated structure 101' and is electrically connected to the conductor plug 114. Fig. 1I shown.
[0068] Please refer to Fig. 1I In one embodiment, each of the contact windows C1 includes a mask layer 128 and a conductor layer 131; each of the contact windows C2 includes a mask layer 129 and a conductor layer 132; each of the contact windows C3 includes a mask layer and a conductor layer (not shown). In one embodiment, the material of the mask layers 128 and 129 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the conductor layers 131 and 132 includes tungsten (W).
[0069] Please refer to Fig. 1I and Figure 5A , 5BOr 5C, the contact windows C1, C2 and C3 can be formed simultaneously or separately. The contact windows C1, C2 and C3 can be formed by the following method. For example, photolithography and etching processes are performed to form a plurality of contact window openings OP1 and OP2. The contact window opening OP1 passes through the insulating cap layer 115, the dielectric layer 103 and the insulating layer 102T (or the first material layer 102) in the area A of the step region R2. The contact window opening OP2 passes through the insulating cap layer 115 in the memory array region R1. Afterwards, a mask layer and a conductor layer are formed in the plurality of contact window openings OP1 and OP2. The contact window C3 in the area A3 of the step region R2 can also be formed simultaneously by the above method.
[0070] Please refer to Fig. 1I , the contact window opening OP1 in the step region R2 includes contact window openings OP1A, OP1B, OP1C and OP1D. The contact window opening OP1A exposes the end portion EP of the bottom layer; the contact window opening OP1D exposes the end portion EP of the top layer. The depth of the contact window opening OP1A farthest from the memory array region R1 is the deepest, and the depth of the contact window opening OP1D closest to the memory array region R1 is the shallowest. During the etching process, the contact window opening OP1D is formed first, exposing the end portion EP of the topmost material layer 104' (gate layer). Etching is then continued to form contact window openings OP1C, OP1B and OP1A in sequence. In the process of continuously etching to form the contact window openings OP1C, OP1B, and OP1A, since the end portion EP of the material layer 104' (gate layer) has a sufficient thickness T2, and there is sufficient etching selectivity between the material layer 104' and the dielectric layer 103, even if the end portion EP is exposed to the contact window opening OP1D, it will not be etched through due to continuous exposure to the etchant. Therefore, the formation of the end portion EP can increase the process yield.
[0071] In the embodiment where the second material layer 104 and the filling layer 104E are silicon nitride, a gate replacement process must be performed before forming the above-mentioned contact windows C1, C2 and C3. FIG. 3A to FIG. 3C as well as FIG. 4A to FIG. 4C , detailed description is as follows.
[0072] FIG. 3A to FIG. 3C It is a cross-sectional schematic diagram of a method for manufacturing a three-dimensional memory element according to another embodiment of the present invention. FIG. 4A to FIG. 4C is another cross-sectional schematic diagram of a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention. Figure 5A The cross-sectional view of the tangent line I-I' is shown in Figures 3A to 3C shown. Figure 5A The cross-sectional view of the section II-II' is shown in FIG. Figures 4A to 4C shown. Figure 5B The cross-sectional view of the section III-III' is shown in FIG. Figures 3A to 3C shown. Figure 5B The cross-sectional view of the part of the process along the tangent line IV-IV' is shown in FIG. Figures 4A to 4C shown.
[0073] Please refer to Figure 1H , 2H , 3A and 4A, according to the above reference Figure 1H and 2H After forming the dielectric layer 103 and the insulating cap layer 115 by a method, a selective etching process is performed to remove the second material layer 104 and the filling layer 104E in the memory array area R1 and the step area R2 to form a plurality of horizontal openings 121. The horizontal openings 121 expose part of the charge storage structure 108, the first material layer 102 and the insulating layer 102T in the memory array area R1. During the etching process, the support structures 98A, 98B, 98C and 98D in the step area R2 can prevent the stacked structure 101' from collapsing. The selective etching process can be an isotropic etching, such as a wet etching process. The etchant used in the wet etching process is, for example, hot phosphoric acid. In some embodiments, after forming the insulating cap layer 115 and before forming the plurality of horizontal openings 121, a dummy pillar can be formed in the step area R2. In some embodiments, a dummy pattern (not shown) can pass through the insulating cap layer 115 and the dielectric layer 103. The dummy pattern may be a dummy pillar or a dummy fence. The dummy pattern may contact the top surface of any or all of the support pillars 98A, 98B, 98C, 98D, or may not contact at all. In other embodiments, the dummy pattern may pass through the insulating cap layer 115, the dielectric layer 103, and the stepped structure 105 to reach the bottom first material layer 102 of the stepped structure 105. The material of the dummy pattern is different from that of the second material layer 104, such as silicon oxide. The dummy pattern may support the stacked structure 101' during the process of forming a plurality of horizontal openings 121 to prevent the stacked structure 101' from collapsing.
[0074] Please refer to Figure 3B and Figure 4B , a conductor layer is formed in the horizontal opening 121. The conductor layer includes, for example, a mask layer 122 and a metal layer 124. In one embodiment, the material of the mask layer 122 includes titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) or a combination thereof, and the material of the metal layer 124 includes tungsten (W). The conductor layer in the horizontal opening 121 serves as a gate layer 126.
[0075] Please refer to Figure 3C , Figure 4C and Figure 5A According to the above method, a plurality of contact windows C1 and C3 are formed in the region A1 and the region A3 of the step region R2, respectively. Figure 3C and 5A As shown, a plurality of contact windows C2 are formed in the memory array region R1, such as Figure 3C shown.
[0076] In the above embodiments, before forming the terminal portion EP, a support column structure 98, 98A, 98B, 98C, 98D and / or 98E may be formed in the stacked structure 101 or 101' of the step region R2 to prevent the stacked structure 101' from collapsing during the etching process of forming the terminal portion EP. In another embodiment, if the stacked structure 101' does not collapse during the etching process of forming the terminal portion EP, it is not necessary to form the support column structure 98, 98A, 98B, 98C, 98D and / or 98E.
[0077] In many embodiments of the present invention, locally increasing the thickness of the end portion of the second material layer (e.g., silicon nitride or doped polysilicon) in the step region can prevent the gate layer below the shallower contact window opening from being etched through during the process of forming contact window openings of different depths. Therefore, the process window can be increased by forming the end portion to increase the pass rate of the process. The end portion can be formed by multiple selective etching and backfilling, and its process can be integrated with the existing process. In addition, before forming the end portion, a support column structure can be formed in the stacked structure in the step region to prevent the stacked structure from collapsing during the etching process of forming the end portion.
[0078] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present disclosure. It should be understood that the above description is only a specific embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the protection scope of the present disclosure.
Claims
1. A method for manufacturing a memory element, characterized in that: include: Providing a substrate, the substrate comprising a memory array region and a step region; forming a stacked structure on the substrate in the memory array region and the step region, wherein the stacked structure comprises a plurality of first material layers and a plurality of second material layers alternately stacked with each other; Patterning the stacked structure to form a stepped structure in the stacked structure in the stepped region; removing portions of the plurality of second material layers at ends of the stepped structure to form a plurality of first horizontal openings; removing portions of the plurality of first material layers around the plurality of first horizontal openings to increase the heights of the plurality of first horizontal openings; forming an end portion in each of the plurality of first horizontal openings, wherein the thickness of the end portion is greater than the thickness of an adjacent second material layer; forming a dielectric layer on the stacked structure of the memory array region and the step region; as well as A first contact window is formed in the step region, wherein the first contact window penetrates the dielectric layer in the step region and the corresponding first material layer above the terminal portion, and lands on and is connected to the terminal portion.
2. The method for manufacturing a memory device according to claim 1, wherein: The method of forming the terminal portion in each of the plurality of first horizontal openings comprises: forming a third material layer on the stacked structure and in the plurality of first horizontal openings; and The third material layer outside the plurality of first horizontal openings is removed to form the end portion in each of the plurality of first horizontal openings.
3. The method for manufacturing a memory element according to claim 2, wherein: Also includes: Before forming the first contact window in the step region, removing the second material layer and the end portion to form a plurality of second horizontal openings; as well as A plurality of conductor layers are formed in the plurality of second horizontal openings.
4. The method for manufacturing a memory device according to claim 1, wherein: Also includes: Before forming the stepped structure, a support structure is formed in the stacked structure in the stepped region.
5. The method for manufacturing a memory device according to claim 4, wherein: The method for forming the support structure comprises: forming an opening in the stacked structure in the stepped region to expose the bottommost first material layer of the stacked structure; and An insulating layer is formed in the opening to form the support structure.
6. The method for manufacturing a memory device according to claim 4, wherein: The method for forming the support structure comprises: forming a channel in the stacked structure of the memory array region and the stepped region to expose the bottommost first material layer of the stacked structure; and An insulating layer is formed in the trench to form the support structure.