Photoelectric conversion apparatus, photoelectric conversion system, and movable body

Abstract

An opto-electric conversion device, an opto-electric conversion system, and a movable body are provided. The opto-electric conversion device includes a plurality of avalanche photodiodes. Each of the plurality of avalanche photodiodes includes an avalanche multiplication unit formed by a first semiconductor region of a first conductivity type disposed at a first depth, and a second semiconductor region of a second conductivity type different from the first conductivity type disposed at a second depth deeper than the first depth. A fourth semiconductor region different in at least one of a conductivity type and an impurity concentration from a third semiconductor region of the second conductivity type is disposed at a position shallower than the third semiconductor region, and a depth of a boundary portion between the third semiconductor region and the fourth semiconductor region is deeper than the avalanche multiplication unit.

Description

Technical Field

[0001] This invention relates to photoelectric conversion devices and photoelectric conversion systems. Background Technology

[0002] A photodetector including an avalanche photodiode (APD) is known, wherein the APD can detect weak signals at the single-photon level by using avalanche (electron avalanche) multiplication. The APD utilizes a first semiconductor region having a first conductivity type with the same polarity as the signal charge and a second semiconductor region having a second conductivity type with a different polarity than the signal charge to form a high electric field region (avalanche multiplication unit).

[0003] In Japanese Patent Application Publication No. 2018-201005, the third semiconductor region of the isolation pixel is set up to the same depth as the avalanche multiplication unit in a cross-sectional view, and is configured to surround the avalanche multiplication unit in a planar view.

[0004] If the pixel size is miniaturized, the distance between the third semiconductor region and the avalanche multiplication unit becomes closer. As a result, a local high electric field region is formed between the third semiconductor region and the first semiconductor region, and the dark count rate (DCR) deteriorates. Summary of the Invention

[0005] According to one aspect of the present invention, a photoelectric conversion device includes: a semiconductor layer; and a plurality of avalanche photodiodes disposed on the semiconductor layer and including a first avalanche photodiode and a second avalanche photodiode; wherein each of the plurality of avalanche photodiodes includes an avalanche multiplication unit, the avalanche multiplication unit being formed by a first semiconductor region of a first conductivity type in which charge carriers of the same conductivity type as the signal charge are considered as majority charge carriers, and a second semiconductor region of a second conductivity type different from the first conductivity type, wherein the first semiconductor region is disposed at a first depth, the second semiconductor region is disposed at a second depth deeper than the first depth, wherein a third semiconductor region of the second conductivity type is disposed between the first avalanche photodiode and the second avalanche photodiode, wherein a fourth semiconductor region is disposed between the first avalanche photodiode and the second avalanche photodiode at a position shallower than the third semiconductor region, the fourth semiconductor region having at least one different conductivity type and impurity concentration from the third semiconductor region, and wherein the depth of the boundary between the third semiconductor region and the fourth semiconductor region is deeper than the avalanche multiplication unit.

[0006] According to another aspect of the present invention, a photoelectric conversion device includes: a semiconductor layer comprising a plurality of photoelectric conversion elements, the semiconductor layer having a first surface and a second surface, the second surface being a light incident surface and opposite to the first surface, wherein each of the plurality of photoelectric conversion elements includes an avalanche photodiode, wherein the avalanche photodiode includes a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, wherein the plurality of photoelectric conversion elements are isolated by an isolation portion including a third semiconductor region of the second conductivity type, wherein the second semiconductor region is configured to contact the third semiconductor region, wherein the plurality of photoelectric conversion elements includes a first photoelectric conversion element and a second photoelectric conversion element disposed in a first direction, the second photoelectric conversion element being disposed adjacent to the first photoelectric conversion element, and wherein the third semiconductor region is disposed between the first photoelectric conversion element and the second photoelectric conversion element such that one end of the third semiconductor region is located closer to the second surface side than to the first surface side, and closer to the first surface side than the second semiconductor region.

[0007] Other features of the invention will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0008] Figure 1 This is a diagram showing the structure of a photoelectric conversion device.

[0009] Figure 2 An example configuration of the sensor substrate is shown.

[0010] Figure 3 An example of the circuit board configuration is shown.

[0011] Figure 4 It is a block diagram of the equivalent circuit including photoelectric conversion elements.

[0012] Figure 5A , 5B Figures 5C and 5C are diagrams illustrating the relationship between the operation and output signal of an avalanche photodiode (APD).

[0013] Figure 6 It is a pixel planar view according to the first exemplary embodiment.

[0014] Figure 7A and 7B It is a pixel cross-sectional view according to the first exemplary embodiment.

[0015] Figure 8 It is a pixel planar view according to the second exemplary embodiment.

[0016] Figure 9A and 9B It is a pixel cross-sectional view according to the second exemplary embodiment.

[0017] Figure 10 It is a pixel planar view according to a third exemplary embodiment.

[0018] Figure 11A and 11B It is a pixel cross-sectional view according to a third exemplary embodiment.

[0019] Figure 12 It is a pixel plan view according to the fourth exemplary embodiment.

[0020] Figure 13A and 13B This is a pixel cross-sectional view according to the fourth exemplary embodiment.

[0021] Figure 14 It is a pixel plan view according to the fifth exemplary embodiment.

[0022] Figure 15A and 15B This is a pixel cross-sectional view according to the fifth exemplary embodiment.

[0023] Figure 16 It is a pixel plan view according to the sixth exemplary embodiment.

[0024] Figure 17A and 17B This is a pixel cross-sectional view according to the sixth exemplary embodiment.

[0025] Figure 18 It is a pixel plan view according to the seventh exemplary embodiment.

[0026] Figure 19A and 19B This is a pixel cross-sectional view according to the seventh exemplary embodiment.

[0027] Figure 20 A photoelectric conversion system according to an eighth exemplary embodiment is shown.

[0028] Figure 21 This is a schematic plan view of a photoelectric conversion device according to the ninth exemplary embodiment.

[0029] Figure 22A and 22B This is a schematic cross-sectional view of a photoelectric conversion device according to a ninth exemplary embodiment.

[0030] Figure 23 It is a potential diagram of the pixels of the photoelectric conversion device according to the ninth exemplary embodiment.

[0031] Figure 24 This is a schematic plan view of a photoelectric conversion device according to the tenth exemplary embodiment.

[0032] Figure 25A and 25B This is a schematic cross-sectional view of a photoelectric conversion device according to the tenth exemplary embodiment.

[0033] Figure 26 This is a schematic cross-sectional view of a photoelectric conversion device according to the tenth exemplary embodiment.

[0034] Figure 27 This is a schematic plan view of a photoelectric conversion device according to the eleventh exemplary embodiment.

[0035] Figure 28A and 28B This is a schematic cross-sectional view of a photoelectric conversion device according to the eleventh exemplary embodiment.

[0036] Figure 29 This is a schematic plan view of a photoelectric conversion device according to the eleventh exemplary embodiment.

[0037] Figure 30A and 30B This is a schematic cross-sectional view of a photoelectric conversion device according to the eleventh exemplary embodiment.

[0038] Figure 31 This is a schematic plan view of a photoelectric conversion device according to the twelfth exemplary embodiment.

[0039] Figure 32A and 32B This is a schematic cross-sectional view of a photoelectric conversion device according to the twelfth exemplary embodiment.

[0040] Figure 33A and 33B This is a schematic cross-sectional view of a photoelectric conversion device according to the thirteenth exemplary embodiment.

[0041] Figures 34A to 34G A method for manufacturing a photoelectric conversion device according to a fourteenth exemplary embodiment is shown.

[0042] Figure 35 This is a block diagram of a photoelectric conversion system according to the fifteenth exemplary embodiment.

[0043] Figure 36A and 36B This is a block diagram of a photoelectric conversion system according to the sixteenth exemplary embodiment.

[0044] Figure 37 This is a block diagram of a photoelectric conversion system according to the seventeenth exemplary embodiment.

[0045] Figure 38This is a block diagram of a photoelectric conversion system according to the eighteenth exemplary embodiment.

[0046] Figure 39A and 39B This is a diagram illustrating a specific example of a photoelectric conversion system according to the nineteenth exemplary embodiment. Detailed Implementation

[0047] The following exemplary embodiments are provided to illustrate the technical concept of the invention and are not intended to limit the invention. The size and positional relationships of the components shown in the figures are sometimes exaggerated for clarity. In the following description, the same components are assigned the same reference numerals, and their descriptions are sometimes omitted. Furthermore, unless there is a technical problem, the structures described in each exemplary embodiment can be replaced by or combined with structures described in other exemplary embodiments.

[0048] Exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In the following description, terms indicating specific directions and positions (e.g., "up," "down," "right," "left," and other terms including these terms) will be used where necessary. These terms are used to facilitate understanding of the invention described with reference to the accompanying drawings. The scope of the invention is not limited by the meaning of these terms.

[0049] In the following description, the anode of the avalanche photodiode (APD) is set to a fixed potential, and the signal is extracted from the cathode side. Therefore, the semiconductor region of the first conductivity type, where charges of the same polarity as the signal charge are considered as majority carriers, is an N-type semiconductor region, and the semiconductor region of the second conductivity type, where charges of the opposite polarity as the signal charge are considered as majority carriers, is a P-type semiconductor region. This invention can also be implemented when the cathode of the APD is set to a fixed potential and the signal is extracted from the anode side. In this case, the semiconductor region of the first conductivity type, where charges of the same polarity as the signal charge are considered as majority carriers, is a P-type semiconductor region, and the semiconductor region of the second conductivity type, where charges of the opposite polarity as the signal charge are considered as majority carriers, is an N-type semiconductor region. The following will describe the case where one node of the APD is set to a fixed potential, but the potentials of the two nodes are variable.

[0050] In this specification, when the term "impurity concentration" is used only, it means the net impurity concentration obtained by subtracting the amount compensated by impurities of the opposite conductivity type. In short, "impurity concentration" refers to net concentration. Regions with higher P-type added impurity concentrations than N-type added impurity concentrations are P-type semiconductor regions. Conversely, regions with higher N-type added impurity concentrations than P-type added impurity concentrations are N-type semiconductor regions.

[0051] In this specification, a "plan view" refers to a view taken from a direction perpendicular to the light incident surface of the semiconductor layer or a surface opposite to the light incident surface, as described later. A section refers to a surface in a direction perpendicular to the light incident surface of the semiconductor layer. When the light incident surface of the semiconductor layer is rough when viewed microscopically, the plan view is defined based on the light incident surface of the semiconductor layer as it is set when viewed macroscopically.

[0052] Semiconductor layer 301 has a first surface and a second surface, wherein the second surface is the surface opposite to the first surface. Light enters the second surface. In this specification, the depth direction is the direction from the first surface of semiconductor layer 301 where the APD is configured toward the second surface. Hereinafter, "first surface" will sometimes be referred to as "front surface," and "second surface" will sometimes be referred to as "back surface." The direction from a predetermined position in semiconductor layer 301 toward the back surface of semiconductor layer 301 will sometimes be indicated as "deep." Conversely, the direction from a predetermined position in semiconductor layer 301 toward the front surface of semiconductor layer 301 will sometimes be indicated as "shallow."

[0053] Reference Figures 1 to 5A 5B and 5C are used to illustrate the common structure of the exemplary embodiments.

[0054] Figure 1 This is a diagram illustrating the structure of a stacked photoelectric conversion device 100. The photoelectric conversion device 100 includes two electrically connected substrates: a sensor substrate 11 and a circuit substrate 21. The sensor substrate 11 includes a first semiconductor layer (semiconductor layer 301) containing the photoelectric conversion element 102 described later, and a first wiring structure. The circuit substrate 21 includes a second semiconductor layer containing circuitry such as the signal processing unit 103 described later, and a second wiring structure. The photoelectric conversion device 100 includes a second semiconductor layer, a second wiring structure, a first wiring structure, and a first semiconductor layer stacked in the order of second semiconductor layer, second wiring structure, first wiring structure, and first semiconductor layer. The photoelectric conversion devices described in the various exemplary embodiments are back-illuminated photoelectric conversion devices where light enters from a second surface, and include a circuit substrate disposed on a first surface.

[0055] Hereinafter, the sensor substrate 11 and circuit substrate 21 will be described as monolithic chips, but the sensor substrate 11 and circuit substrate 21 are not limited to chips. For example, each substrate can be a wafer. Optionally, the substrates can be monolithized after being stacked in a wafer state, or they can be chip-based from a wafer state and then bonded by stacking chips.

[0056] A pixel region 12 is disposed on a sensor substrate 11, and a circuit region 22 for processing the signal detected by the pixel region 12 is disposed on a circuit substrate 21.

[0057] Figure 2This is a diagram showing an example configuration of the sensor substrate 11. Pixels 104, each including a photoelectric conversion element 102 containing an APD, are arranged in a two-dimensional array in a plan view and form pixel regions 12.

[0058] Typically, pixel 104 is the pixel used to form an image. In the case of using pixel 104 in a time-of-flight (TOF) sensor, it is not always necessary to form an image. In other words, pixel 104 can be used to measure the time of light arrival and to measure the amount of light.

[0059] Figure 3 This is a structural diagram of the circuit board 21. The circuit board 21 includes components that process... Figure 2 The photoelectric conversion element 102 shown includes a signal processing unit 103 for the charge converted by photoelectric conversion, a readout circuit 112, a control pulse generation unit 115, a horizontal scanning circuit unit 111, a signal line 113, and a vertical scanning circuit unit 110.

[0060] Figure 2 The photoelectric conversion element 102 shown and Figure 3 The signal processing unit 103 shown is electrically connected via connection wiring provided for each pixel.

[0061] The vertical scanning circuit unit 110 receives control pulses supplied from the control pulse generation unit 115 and supplies the control pulses to each pixel. Logic circuits such as shift registers or address decoders are used as the vertical scanning circuit unit 110.

[0062] The signal output from the photoelectric conversion element 102 of the pixel is processed by the signal processing unit 103. A counter and a memory are set in the signal processing unit 103, and digital values ​​are stored in the memory.

[0063] The horizontal scanning circuit unit 111 inputs control pulses to the signal processing unit 103 for sequentially selecting each column, so as to read the signal from the memory of each pixel storing digital signals.

[0064] The signal processing unit 103 outputs a signal from the pixel selected by the vertical scanning circuit unit 110 on the selected column to the signal line 113.

[0065] The signal output to signal line 113 is output to a recording unit or signal processing unit located outside the photoelectric conversion device 100 via output circuit 114.

[0066] exist Figure 2 In this design, photoelectric conversion elements within a pixel region can be arranged in a one-dimensional manner. There is no need to assign a signal processing unit function to each of all photoelectric conversion elements. For example, multiple photoelectric conversion elements can share a single signal processing unit and perform signal processing sequentially.

[0067] like Figure 2 and 3 As shown, multiple signal processing units 103 are arranged in the region overlapping with pixel region 12 in the plan view. Then, the vertical scanning circuit unit 110, horizontal scanning circuit unit 111, readout circuit 112, output circuit 114, and control pulse generation unit 115 are arranged in a manner that spatially overlaps the ends of the sensor substrate 11 and the ends of the pixel region 12 in the plan view. In other words, the sensor substrate 11 includes pixel region 12 and non-pixel regions arranged around pixel region 12. Then, the vertical scanning circuit unit 110, horizontal scanning circuit unit 111, readout circuit 112, output circuit 114, and control pulse generation unit 115 are arranged in the region overlapping with the non-pixel regions in the plan view.

[0068] Figure 4 Showing includes Figure 2 and 3 An example of a block diagram of the equivalent circuit.

[0069] exist Figure 2 In the sensor substrate 11, a photoelectric conversion element 102 including APD 201 is disposed on the sensor substrate 11, and other components are disposed on the circuit substrate 21.

[0070] The APD 201 generates charge pairs corresponding to the incident light through photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the APD 201. A voltage VH (second voltage), higher than the voltage VL supplied to the anode, is supplied to the cathode of the APD 201. A reverse bias voltage for enabling the APD 201 to perform avalanche multiplication operation is supplied to the anode and cathode. By inducing this voltage state, the charge generated by the incident light causes avalanche multiplication and generates an avalanche current.

[0071] With a reverse bias voltage supplied, the APD 201 operates in either Geiger mode or linear mode. In Geiger mode, the APD 201 operates using a potential difference between the anode and cathode that is greater than the breakdown voltage. In linear mode, the APD 201 operates using a potential difference between the anode and cathode that is close to the breakdown voltage, or a voltage difference equal to or less than the breakdown voltage.

[0072] An APD operating in Geiger mode will be referred to as a single-photon avalanche photodiode (SPAD). For example, the voltage VL (first voltage) is -30V and the voltage VH (second voltage) is 3V. The APD 201 can operate in linear mode or in Geiger mode.

[0073] The quenching element 202 is connected to the APD 201 and the power supply for the voltage VH. The quenching element 202 acts as a load circuit (quenching circuit) when the signal is amplified by avalanche multiplication, and has the function of suppressing avalanche multiplication by reducing the voltage to be supplied to the APD 201 (quenching operation). The quenching element 202 also has the function of returning the voltage to be supplied to the APD 201 to voltage VH by allowing current to flow through an amount corresponding to the voltage drop caused by the quenching operation (recharge operation).

[0074] The signal processing unit 103 includes a waveform shaping unit 210, a counter circuit 211, and a selection circuit 212. In this specification, the signal processing unit 103 only needs to include any one of the waveform shaping unit 210, the counter circuit 211, and the selection circuit 212.

[0075] The waveform shaping unit 210 outputs a pulse signal by shaping the potential change of the cathode of the APD 201 obtained during photon detection. For example, an inverter circuit is used as the waveform shaping unit 210. Figure 4 An example using an inverter as waveform shaping unit 210 is shown, but a circuit with multiple inverters connected in series can be used, or other circuits with waveform shaping effects can be used.

[0076] The counter circuit 211 counts the number of pulse signals output from the waveform shaping unit 210 and stores the count value. When a control pulse pRES is supplied via the drive line 213, the number of pulse signals stored in the counter circuit 211 is reset.

[0077] from Figure 3 The vertical scanning circuit unit 110 shown is via Figure 4 The drive line 214 shown (in) Figure 3 (Not shown) A control pulse pSEL is supplied to the selection circuit 212, and the electrical connection and disconnection between the counter circuit 211 and the signal line 113 are switched. The selection circuit 212 includes, for example, a buffer circuit for the output signal.

[0078] Electrical connections can be switched by configuring switches, such as transistors, between the quenching element 202 and the APD 201, or between the photoelectric conversion element 102 and the signal processing unit 103. Similarly, switches, such as transistors, can be used to electrically switch the supply of voltage VH or voltage VL to the photoelectric conversion element 102.

[0079] In this exemplary embodiment, the structure using counter circuit 211 has been described. However, the photoelectric conversion device 100 can use a time-to-digital converter (TDC) and a memory instead of counter circuit 211 to obtain pulse detection timing. In this case, the generation timing of the pulse signal output from waveform shaping unit 210 is converted into a digital signal by TDC. To measure the timing of the pulse signal, a control pulse pREF (reference signal) is transmitted via a drive line from... Figure 1 The vertical scanning circuit unit 110 shown is supplied to the TDC. Based on the control pulse pREF, the TDC acquires a digital signal indicating the input timing of the signal output from each pixel via the waveform shaping unit 210 as a relative time.

[0080] Figure 5A , 5B Figures 5 and 5C are schematic diagrams illustrating the relationship between the operation and output signals of the APD.

[0081] Figure 5A It is extraction Figure 4 The diagram shows the APD 201, the quenching element 202, and the waveform shaping unit 210. Figure 5A In this context, the input side of the waveform shaping unit 210 is considered as node A, and the output side is considered as node B. Figure 5B Show Figure 5A The waveform change of node A in the diagram, and Figure 5C Show Figure 5A The waveform change of node B in the diagram.

[0082] During the time interval from time t0 to time t1, to Figure 5A A potential difference VH-VL is applied to APD 201. If a photon enters APD 201 at time t1, avalanche multiplication occurs in APD 201, the avalanche multiplication current flows in the quenching element 202, and the voltage at node A drops. If the voltage drop increases further and the potential difference applied to APD 201 becomes smaller, the avalanche multiplication of APD 201 stops at time t2, and the voltage level at node A stops decreasing from a certain fixed value. Thereafter, during the time period from time t2 to time t3, a current compensating for the voltage drop from voltage VL flows to node A, and the potential level at node A statically stabilizes at the original potential level at time t3. At this time, the portion of the output waveform at node A that exceeds a certain threshold undergoes waveform shaping by waveform shaping unit 210 and is output as a signal at node B.

[0083] The configuration of signal line 113 and the configuration of readout circuit 112 and output circuit 114 are not limited to the following. Figure 3The configuration is shown. For example, signal line 113 can be configured to extend in the row direction, and readout circuitry 112 can be configured at the end of the extended signal line 113.

[0084] The photoelectric conversion devices of various exemplary embodiments will be described below.

[0085] The first exemplary embodiment will now be described. Figure 6 This is an enlarged plan view of the pixel portion of the photoelectric conversion device according to a first exemplary embodiment. Figure 6 This is a diagram illustrating APDs arranged on a two-dimensional plane. In this exemplary embodiment, since each pixel includes one APD, therefore... Figure 6 It is a planar view of a pixel portion arranged in a 2×2 pixel grid. Figure 7A Show along Figure 6 The cross-sectional view intercepted by the dashed line A-A' in the figure, and Figure 7B Show along Figure 6 The cross-sectional view is taken by the dashed line B-B' in the figure. Figure 6 The attached figure labels are assigned in the middle and Figure 7A and 7B The corresponding reference numerals in the attached figures are shown. Refer to... Figure 7A and 7B To explain the details of each part.

[0086] In the plan view, the first APD and the third APD are configured in the first direction, and the third APD and the second APD are configured in the second direction orthogonal to the first direction. Figure 6 In this configuration, the first APD and the third APD are arranged on opposite sides, and the first APD and the second APD are arranged diagonally. For example, in... Figure 6 In the diagram, the top-left APD is the first APD, the top-right APD is the third APD, and the bottom-right APD is the second APD. Figure 6 In the middle. The distance between the first semiconductor region 311 of the first APD and the first semiconductor region 311 of the second APD is longer than the distance between the first semiconductor region 311 of the first APD and the first semiconductor region 311 of the third APD.

[0087] exist Figure 7AIn the semiconductor layer 301 shown, a first semiconductor region 311 of a first conductivity type and a second semiconductor region 312 of a second conductivity type are disposed. The first semiconductor region 311 and the second semiconductor region 312 form a PN junction and form an APD for forming an avalanche multiplication unit. A contact plug 341 for supplying voltage VL is formed in the first semiconductor region 311. The semiconductor layer 301 has a surface (first surface) 302 on which the contact plug 341 is formed and a surface (second surface) 303 opposite to the first surface 302. In this exemplary embodiment, the second surface 303 serves as a light incident surface. As described above, the light incident surface is a surface observed macroscopically, and the first surface 302 and the second surface 303 need not be parallel surfaces.

[0088] exist Figure 7A An isolation region 331 is formed between adjacent pixels to prevent avalanche crosstalk. The isolation region 331 includes a trench structure. It is desirable that the interior of the trench structure be formed of a material that increases the reflectivity of photons generated by the avalanche multiplication unit 314 or a material that absorbs the generated photons. The isolation region 331 includes, for example, a deep trench isolation (DTI) and an insulating material disposed within the DTI. The isolation region 331, including the insulating material, prevents photons emitted in the high electric field region of the avalanche multiplication unit 314 from mixing into adjacent pixels. The material of the isolation region 331 is not limited to this. A metallic material such as copper or tungsten can be used to configure the isolation region 331 within the trench structure. This can enhance the light-shielding properties between pixels. An isolation region 331 with a structure having a trench structure and air (e.g., voids) present within the trench structure can also be used.

[0089] The trench transducer (DTI) can penetrate the semiconductor layer 301 from the first surface 302 to the second surface 303. When the DTI is formed from the second surface 303, the DTI can be configured such that its ends are located within the semiconductor layer 301 without reaching the first surface 302. In this case, it is desirable that the ends of the DTI be located at a position at least shallower than the depth of the avalanche multiplication unit 314. In this specification, the depth direction is from the first surface 302 towards the second surface 303. This configuration of the DTI's ends prevents avalanche crosstalk. It is desirable that the DTI be provided to penetrate the semiconductor layer 301. In this exemplary embodiment, an example of providing a trench structure including the DTI as an isolation region 331 has been described; however, the isolation region 331 is an optional component, and the invention includes structures without the isolation region 331.

[0090] A third semiconductor region 321 of the second conductivity type is disposed on the sidewall portion of the isolation region 331. The third semiconductor region 321 has the function of isolating adjacent pixels. When the isolation region 331 is provided, the third semiconductor region 321 also has the function of reducing the dark current generated in the sidewall portion of the isolation region 331.

[0091] In this exemplary embodiment, the third semiconductor region 321 is configured as a boundary on the side of the second surface 303 at depth 402. In this way, the first semiconductor region 311 of the first conductivity type and the third semiconductor region 321 of the second conductivity type are formed at different depths. The third semiconductor region 321 is configured from the second surface 303 to the depth 402 in a manner that contacts the sidewall of the isolation region 331, and is not configured between the depth 402 and the first surface 302.

[0092] When the first semiconductor region 311 of the first conductivity type and the third semiconductor region 321 of the second conductivity type are partially formed at the same depth, the distance between the first semiconductor region 311 and the third semiconductor region 321 narrows as the pixel size is miniaturized. As a result, electric field concentration occurs between the first semiconductor region 311 and the third semiconductor region 321, and the dark count rate (DCR) deteriorates.

[0093] Conversely, in the structure of this exemplary embodiment, the first semiconductor region 311 of the first conductivity type and the third semiconductor region 321 of the second conductivity type are formed at different depths. For example, in Figure 7A In this configuration, the upper surface of the third semiconductor region 321 of the second conductivity type is located below the lower surface of the first semiconductor region 311 of the first conductivity type. Therefore, even with pixel size miniaturization, the distance between the two semiconductor regions can be greater compared to the case where the two semiconductor regions are formed at the same depth. Thus, DCR degradation caused by electric field concentration between the first semiconductor region 311 and the third semiconductor region 321 can be prevented.

[0094] Depth 402 is located at a deeper position than depth 401 corresponding to the PN junction surface of the APD. On the other hand, depth 402 is located at a shallower position than depth 403 where the second semiconductor region 312 is disposed. Depth 403 indicates a position corresponding to half the depth occupied by the second semiconductor region 312.

[0095] In the dark current generated in the sidewall portion of isolation region 331, the dark current charge generated at a location shallower than depth 402 flows into the first semiconductor region 311 via the fifth semiconductor region 313, which has a potential lower than that of the avalanche multiplication unit 314. The dark current component does not pass through the avalanche multiplication unit 314. Therefore, the dark current charge does not undergo avalanche multiplication and is not detected as an APD signal. The dark current charge is therefore not counted as DCR. For this reason, even if the top of the second semiconductor region 312 does not reach the first surface 302, no DCR problem occurs.

[0096] A fifth semiconductor region 313, representing either a first or second conductivity type, is disposed at both ends of the first semiconductor region 311 to mitigate electric field concentration. In this case, the impurity concentration of the fifth semiconductor region 313 is set to be lower than the impurity concentration of the first semiconductor region 311. For example, the impurity concentration of the first semiconductor region 311 is equal to or greater than 6.0 × 10⁻⁶. 18 [atms / cm 3 In the case of […], the impurity concentration of the fifth semiconductor region 313 is equal to or greater than 1.0 × 10⁻⁶. 16 [atms / cm 3 And equal to or less than 1.0 × 10 18 [atms / cm 3 In this specification, impurity concentration refers to the net impurity concentration of a predetermined impurity, and specifically to the net doping concentration.

[0097] The sixth semiconductor region 315 of the second conductivity type is disposed in a region deeper than the second semiconductor region 312, and the seventh semiconductor region 316 of the second conductivity type is disposed in a region deeper than the sixth semiconductor region 315. At this time, the impurity concentration of the second conductivity type in the seventh semiconductor region 316 is set to a higher impurity concentration than that in the sixth semiconductor region 315. Using this structure, the charge photoelectrically converted by the sixth semiconductor region 315 passes through the avalanche multiplier unit 314 disposed on the first surface 302 side, instead of escaping towards the second surface 303 side. This allows for efficient readout of the signal charge and its counting as a signal for the APD.

[0098] Figure 7B Is along with Figure 6 The cross-sectional view is taken by the dashed line B-B' corresponding to the diagonal direction in the image. Figure 7B and Figure 7A The difference lies in that the isolation region 331 is not positioned between adjacent avalanche multiplier units. Since avalanche crosstalk increases as the distance between adjacent avalanche multiplier units decreases, the avalanche crosstalk prevention effect is improved by forming an isolation region between adjacent avalanche multiplier units on opposite sides, rather than between adjacent avalanche multiplier units on the diagonal side. As described above, the isolation region 331 is an isolation region comprising an insulating film such as an oxide film. By employing a structure where the isolation region 331 is not positioned between diagonally arranged avalanche multiplier units, a contact plug 342 for supplying voltage VH to the APD can be formed. Different avalanche multiplier units can then share the contact plug 342.

[0099] When charge carriers undergo avalanche multiplication, avalanche crosstalk sometimes occurs, causing photons emitted in high-electric-field regions to leak into adjacent pixels. Japanese Patent Application Publication No. 2018-201005 discusses preventing avalanche crosstalk by providing a trench structure as an inter-pixel isolation region and arranging an insulator within the trench structure. Japanese Patent Application Publication No. 2018-201005 also discusses forming a third semiconductor region of a second conductivity type in the sidewall portion of the inter-pixel isolation region and supplying a voltage to the third semiconductor region from a contact connected to the anode.

[0100] To reduce the contact resistance with semiconductor layer 301, an eighth semiconductor region 323 of the second conductivity type is disposed below the contact plug 342. In this case, the impurity concentration of the eighth semiconductor region 323 can be at the same level as the impurity concentration of the third semiconductor region 321. Optionally, the impurity concentration of the eighth semiconductor region 323 can be higher than the impurity concentration of the third semiconductor region 321. The distance between the eighth semiconductor region 323 and the first semiconductor region 311 in the diagonal direction is larger than the distance in the opposite side direction. This can suppress the generation of electric field concentration between the first semiconductor region 311 and the eighth semiconductor region 323, and prevent DCR deterioration attributable to electric field concentration. In view of the above, as... Figure 6 As shown, in the plan view, the contact plug 342 and the eighth semiconductor region 323 are not arranged between pixels in the opposite direction, but between pixels in the diagonal direction.

[0101] exist Figure 7B In this configuration, voltage VL is applied to the first semiconductor region 311 via contact plug 341, and voltage VH is applied to the eighth semiconductor region 323 via contact plug 342. The potential applied to the eighth semiconductor region 323 is supplied to the second semiconductor region 312 via the third semiconductor region 321 and the sixth semiconductor region 315. Therefore, by applying a reverse bias voltage to the first semiconductor region 311 of the first conductivity type and the second semiconductor region 312 of the second conductivity type, an avalanche multiplication unit 314 can be formed.

[0102] exist Figure 7B In this configuration, the contact plug 342 is positioned on the first surface 302 side, but potential can be supplied to the third semiconductor region 321 from the second surface 303 side. In this case, since there is no need to configure the eighth semiconductor region 323, the distance between the diagonally opposite avalanche multiplier units 314 can be made closer.

[0103] exist Figure 6In this embodiment, the avalanche multiplication unit is configured as a circle, and the third semiconductor region 321, located below the eighth semiconductor region 323, is configured as a rectangle in plan view; however, this exemplary embodiment is not limited thereto. For example, the first semiconductor region 311 and the third semiconductor region 321 may have the same shape in plan view. In this case, the contact plug 342 is preferably configured on the second surface 303 side.

[0104] A planarization layer, filter layer, and microlens (not shown) can be disposed on the back side of semiconductor layer 301. Various optical filters, such as color filters, infrared cutoff filters, and monochromatic filters, can be used as the filter layer. RGB color filters or RGBW color filters can be used as color filters.

[0105] Using the above structure, according to the first exemplary embodiment, an APD for miniaturizing pixel size can be implemented. Since the isolation region 331 is provided, avalanche crosstalk can also be prevented.

[0106] Reference Figure 8 , 9A 9B and 9B are used to illustrate the photoelectric conversion device according to the second exemplary embodiment. Figure 8 This is a plan view of a photoelectric conversion device according to this exemplary embodiment, and is a diagram showing 2×2 APDs arranged on a two-dimensional plane. Figure 9A Show along Figure 8 The cross-sectional view intercepted by the dashed line A-A' in the figure, and Figure 9B Show along Figure 8 The cross-sectional view is taken by the dashed line B-B' in the figure.

[0107] The photoelectric conversion device according to this exemplary embodiment differs from the photoelectric conversion device of the first exemplary embodiment in that a fourth semiconductor region 322 is disposed between the first surface 302 and the depth 402 in the sidewall portion of the isolation region 331. Since the photoelectric conversion device according to this exemplary embodiment is substantially the same as the photoelectric conversion device of the first exemplary embodiment except for this point and the points to be described below, further description will be omitted.

[0108] A fourth semiconductor region 322 is configured as a boundary on the first surface 302 at depth 402. At least one of the conductivity type and impurity concentration of the fourth semiconductor region 322 differs from that of the third semiconductor region 321. The fourth semiconductor region 322 can be a semiconductor region of a first conductivity type, a semiconductor region of a second conductivity type, or an intrinsic semiconductor region. When the fourth semiconductor region 322 is a semiconductor region of a second conductivity type, the impurity concentration of the second conductivity type of the fourth semiconductor region 322 is set to be lower than the impurity concentration of the third semiconductor region 321. For example, the impurity concentration of the third semiconductor region 321 differs from that of the fourth semiconductor region 322 by more than four times. As an example, the impurity concentration of the third semiconductor region 321 is 1.0 × 10⁻⁶. 17 [atms / cm 3 In the case of […], the impurity concentration of the fourth semiconductor region 322 is 1.0 × 10⁻⁶. 16 [atms / cm 3 When the fourth semiconductor region 322 is a semiconductor region of the first conductivity type, the impurity concentration of the first conductivity type in the fourth semiconductor region 322 is set to be lower than the impurity concentration in the first semiconductor region 311. For example, the impurity concentration in the fourth semiconductor region 322 differs from that in the first semiconductor region 311 by more than ten times. As an example, the impurity concentration in the first semiconductor region 311 is 6.0 × 10⁻⁶. 18 [atms / cm 3 In the case of […], the impurity concentration of the fourth semiconductor region 322 is 1.0 × 10⁻⁶. 16 [atms / cm 3 The impurity concentration of the fourth semiconductor region 322 can be at the same level as the impurity concentration of the semiconductor layer 301, regardless of its polarity.

[0109] It is desirable that the fourth semiconductor region 322 is a semiconductor region of the second conductivity type. When depth 402 is positioned deeper than depth 403, a portion of the dark current generated in the sidewall portion of the isolation region 331, generated at depths where the third semiconductor region 321 is not located, passes through the avalanche multiplication unit 314. This causes DCR degradation.

[0110] However, through such Figure 9A As shown, with depth 402 positioned shallower than depth 403, the dark current charges generated in the sidewall portion of the isolation region 331 recombine in the third semiconductor region 321 of the second conductivity type, which is located at a depth deeper than depth 402. Therefore, DCR deterioration can be prevented.

[0111] According to this exemplary embodiment, an APD for miniaturizing pixel size can be implemented. Avalanche crosstalk can also be prevented due to the isolation region 331.

[0112] Reference Figure 10 , 11A 11B will be used to illustrate the photoelectric conversion device according to the third exemplary embodiment. Figure 10 This is a plan view of a photoelectric conversion device according to this exemplary embodiment, and is a diagram showing 2×2 APDs arranged on a two-dimensional plane. Figure 11A Show along Figure 10 The cross-sectional view intercepted by the dashed line A-A' in the figure, and Figure 11B Show along Figure 10 The cross-sectional view is taken by the dashed line B-B' in the figure.

[0113] The photoelectric conversion device according to this exemplary embodiment differs from the photoelectric conversion device of the second exemplary embodiment in that, in a plan view, the width of the fourth semiconductor region 322 is narrower than the width of the third semiconductor region 321. Since, except for this point and the points to be described below, the photoelectric conversion device according to this exemplary embodiment is substantially the same as the photoelectric conversion device of the second exemplary embodiment, description will be omitted.

[0114] In this specification, "width of the semiconductor region" refers to its length in a direction orthogonal to the depth direction. For example, Figure 11A The width of the fourth semiconductor region 322 refers to the length in a cross section in the depth direction from the interface between the isolation region 331 and the fourth semiconductor region 322 toward the first semiconductor region 311.

[0115] like Figure 10 and 11AAs shown, the width (protrusion amount) of the fourth semiconductor region 322 is offset by C less than the width (protrusion amount) of the third semiconductor region 321 relative to the isolation region 331. More specifically, in the plan view, the distance from the isolation region 331 to the end of the fourth semiconductor region 322 on the first semiconductor region 311 side is less than the distance from the isolation region 331 to the end of the third semiconductor region 321 on the first semiconductor region 311 side. The end of the fourth semiconductor region 322 on the first semiconductor region 311 side refers to the interface between the fourth semiconductor region 322 and the semiconductor region 324 located between the fifth semiconductor region 313 and the fourth semiconductor region 322. Semiconductor region 324 is a semiconductor region that differs from the fourth semiconductor region 322 and the fifth semiconductor region 313 in at least one of conductivity type and impurity concentration. For example, semiconductor region 324 is a semiconductor region of a first conductivity type having an impurity concentration lower than that of the fifth semiconductor region 313. The end of the third semiconductor region 321 on the first semiconductor region 311 side refers to the interface between the third semiconductor region 321 and the sixth semiconductor region 315.

[0116] In this exemplary embodiment, when the fourth semiconductor region 322 is a semiconductor region of a first conductivity type, the fourth semiconductor region 322 may have an impurity concentration equal to that of the first semiconductor region 311. In this exemplary embodiment, when the fourth semiconductor region 322 is a semiconductor region of a second conductivity type, the fourth semiconductor region 322 may have an impurity concentration equal to that of the third semiconductor region 321.

[0117] Even if the fourth semiconductor region 322 has the same impurity concentration as each semiconductor region, if the distance E between the first semiconductor region 311 and the fourth semiconductor region 322 is equal to the distance D between the first semiconductor region 311 and the third semiconductor region 321, the same effect as in the first exemplary embodiment can be obtained.

[0118] The fourth semiconductor region 322 may be an intrinsic semiconductor region, a semiconductor region of the first conductivity type having an impurity concentration lower than that of the first semiconductor region 311, or a semiconductor region of the second conductivity type having an impurity concentration lower than that of the third semiconductor region 321.

[0119] According to this exemplary embodiment, an APD for miniaturizing pixel size can be implemented. Avalanche crosstalk can also be prevented due to the isolation region 331. Furthermore, further miniaturization of pixel size can be achieved compared to the second exemplary embodiment by making the width of the fourth semiconductor region 322 smaller.

[0120] Reference Figure 12 , 13A The photoelectric conversion device according to the fourth exemplary embodiment is described in conjunction with 13B. Figure 12 This is a plan view of a photoelectric conversion device according to a fourth exemplary embodiment, and is a diagram showing 2×2 APDs arranged on a two-dimensional plane. Figure 13A Show along Figure 12 The cross-sectional view intercepted by the dashed line A-A' in the figure, and Figure 13B Show along Figure 12 The cross-sectional view is taken by the dashed line B-B' in the figure. Figure 12 The attached figure labels are assigned in the middle and Figure 13A and 13B The corresponding reference numerals in the attached figures correspond to those in the figure.

[0121] The difference between the photoelectric conversion device according to this exemplary embodiment and the photoelectric conversion device according to the second exemplary embodiment is that, along the... Figure 12 In the cross section intercepted by the dashed line B-B', an isolation region 331 is also disposed between adjacent pixels in the diagonal direction. Since the photoelectric conversion device according to this exemplary embodiment is substantially the same as the photoelectric conversion device of the second exemplary embodiment, except for this point and the points to be described below, the description will be omitted.

[0122] In this exemplary embodiment, in a plan view, isolation regions 331 are configured not only between pixels in the opposite direction but also between pixels in the diagonal direction. In other words, in a cross-section taken along the dashed line B-B', isolation regions 331 are also configured between APDs.

[0123] In the second exemplary embodiment, the contact plugs 342 arranged between diagonally adjacent pixels are shared by four pixels, and the number of contact plugs supplying voltage VH is essentially one contact plug per pixel. On the other hand, in this exemplary embodiment, since the isolation region 331, including the embedded insulating film, is arranged between diagonally adjacent pixels, therefore, as... Figure 12 As shown, in the planar view, the APD should be configured with a certain offset between the centers of adjacent pixels in the diagonal direction. Figure 12 In the example shown, four contact plugs 342 are assigned to one pixel, but the number of contact plugs 342 does not always need to be four. It is sufficient to assign one contact plug with a supply voltage VH to one pixel. Alternatively, one contact plug with a supply voltage VH can be shared by multiple pixels.

[0124] In the second exemplary embodiment, among the photons emitted by the avalanche multiplication unit 314, in relation to... Figure 12Photons traveling diagonally opposite to the dashed line B-B' in the diagram may cause avalanche crosstalk. In this exemplary embodiment, isolation regions 331 are also configured between pixels in the diagonal direction. Therefore, avalanche crosstalk between adjacent pixels in the diagonal direction can be prevented.

[0125] According to this exemplary embodiment, an APD for miniaturizing pixel size can be implemented. Avalanche crosstalk can also be prevented due to the isolation region. Specifically, avalanche crosstalk between adjacent pixels in the diagonal direction can also be prevented.

[0126] Reference Figure 14 , 15A 15B will be used to illustrate the photoelectric conversion device according to the fifth exemplary embodiment. Figure 14 This is a plan view of a photoelectric conversion device according to a fifth exemplary embodiment, and is a diagram showing 2×2 APDs arranged on a two-dimensional plane. Figure 15A Show along Figure 14 The cross-sectional view intercepted by the dashed line A-A' in the figure, and Figure 15B Show along Figure 14 The cross-sectional view is taken by the dashed line B-B' in the figure. Figure 14 The attached figure labels are assigned in the middle and Figure 15A and 15B The corresponding reference numerals in the attached figures correspond to those in the figure.

[0127] The photoelectric conversion device according to this exemplary embodiment differs from the photoelectric conversion device of the second exemplary embodiment in that the isolation region 331 does not reach the second surface 303. Since the photoelectric conversion device according to this exemplary embodiment is substantially the same as the photoelectric conversion device of the second exemplary embodiment, except for this point and the points to be described below, the description will be omitted.

[0128] As an example, in Figure 15A In this configuration, the isolation region 331 is configured up to the boundary between the sixth semiconductor region 315 and the seventh semiconductor region 316. For example, the depth of the seventh semiconductor region 316 from the first surface 302 is 2.5 μm or more.

[0129] The photon source causing avalanche crosstalk is the avalanche multiplier unit 314, and photons generated by the avalanche multiplier unit 314 are unlikely to leak into adjacent pixels via the seventh semiconductor region 316 disposed on the second surface 303 side. Therefore, the isolation region 331 does not need to reach the second surface 303 and can be formed up to... Figure 15A The position is shown as the midpoint in the depth direction. In this case, the difficulty of the process steps in forming the isolation region 331 and the third semiconductor region 321 can be reduced.

[0130] According to this exemplary embodiment, an APD for miniaturizing pixel size can be implemented. Avalanche crosstalk can also be prevented due to the isolation region 331. This reduces the complexity of the manufacturing process.

[0131] Reference Figure 16 , 17A The photoelectric conversion device according to the sixth exemplary embodiment is described in conjunction with 17B. Figure 16 This is a plan view of a photoelectric conversion device according to this exemplary embodiment, and is a diagram showing 2×2 APDs arranged on a two-dimensional plane. Figure 17A Show along Figure 16 The cross-sectional view intercepted by the dashed line A-A' in the figure, and Figure 17B Show along Figure 16 The cross-sectional view is taken by the dashed line B-B' in the figure. Figure 16 The attached figure labels are assigned in the middle and Figure 17A and 17B The corresponding reference numerals in the attached figures correspond to those in the figure.

[0132] The photoelectric conversion device according to this exemplary embodiment differs from the photoelectric conversion device of the fourth exemplary embodiment in that the contact plug supplying voltage VH to the APD is not disposed on the first surface 302 side, and the voltage VH is supplied via the contact plug 343 disposed on the second surface 303 side. Since, except for this point and the points to be described below, the photoelectric conversion device according to this exemplary embodiment is substantially the same as the photoelectric conversion device of the fourth exemplary embodiment, description will be omitted.

[0133] The voltage VH applied from the contact plug 343 is supplied to the second semiconductor region 312 via the seventh semiconductor region 316 and the sixth semiconductor region 315. Therefore, a reverse bias voltage is applied to the first semiconductor region 311 and the second semiconductor region 312, and an avalanche multiplier unit 314 can be formed.

[0134] In this exemplary embodiment, since no contact plug for supplying voltage VH is provided on the first surface 302 side, it is not necessary to form an eighth semiconductor region 323 on the first surface 302 side. Therefore, in Figure 17A and 17B In this configuration, a fourth semiconductor region 322 is used instead of the eighth semiconductor region 323. Without the isolation region 331, the fourth semiconductor region 322 is unnecessary.

[0135] exist Figure 17A and 17B The device is equipped with a contact plug 343, but electrodes such as metal films can be formed to replace the contact plug 343, and potential can be supplied through the electrodes.

[0136] exist Figure 17A and17B In the plan view, the contact plug 343 is positioned at a location overlapping the avalanche multiplier unit 314; however, the contact plug 343 can be positioned at a location not overlapping the avalanche multiplier unit 314. Using this structure, incident light from the second surface 303 side can enter the semiconductor layer without being blocked by the contact plug 343.

[0137] According to this exemplary embodiment, an APD for miniaturizing pixel size can be implemented. Avalanche crosstalk can also be prevented due to the isolation region 331.

[0138] Reference Figure 18 , 19A The photoelectric conversion device according to the seventh exemplary embodiment is described in conjunction with 19B. Figure 18 This is a plan view of a photoelectric conversion device according to a seventh exemplary embodiment, and is a diagram showing 2×2 APDs arranged on a two-dimensional plane. Figure 19A Show along Figure 18 The cross-sectional view intercepted by the dashed line A-A' in the figure, and Figure 19B Show along Figure 18 The cross-sectional view is taken by the dashed line B-B' in the figure. Figure 18 The attached figure labels are assigned in the middle and Figure 19A and 19B The corresponding reference numerals in the attached figures correspond to those in the figure.

[0139] The photoelectric conversion device according to this exemplary embodiment differs from the photoelectric conversion device of the first exemplary embodiment in the structure of the semiconductor region used to form the avalanche multiplication unit 314. Since the photoelectric conversion device according to this exemplary embodiment is substantially the same as the photoelectric conversion device of the first exemplary embodiment, except for this point and the points to be described below, the description will be omitted.

[0140] exist Figure 19A In this configuration, a PN junction is formed between a ninth semiconductor region 351 of the first conductivity type and a tenth semiconductor region 352 of the second conductivity type, and an avalanche multiplication unit 314 is formed. The impurity concentration of the ninth semiconductor region 351 is, for example, at a level similar to that of the tenth semiconductor region 352 of the second conductivity type. Figure 5A The impurity concentration of the tenth semiconductor region 352 is at the same level as that of the first semiconductor region 311, and the impurity concentration of the tenth semiconductor region 352 is, for example, at the same level as that of the first semiconductor region 311. Figure 5A The second semiconductor region 312 is at the same level. Figure 19AIn this configuration, the eleventh semiconductor region 535 is disposed at the same depth as the tenth semiconductor region 352. When the eleventh semiconductor region 535 is a semiconductor region of the second conductivity type, the impurity concentration of the eleventh semiconductor region 535 is lower than the impurity concentration of the tenth semiconductor region 352. When the eleventh semiconductor region 535 is a semiconductor region of the first conductivity type, the impurity concentration of the eleventh semiconductor region 535 is lower than the impurity concentration of the ninth semiconductor region 351. Furthermore, the twelfth semiconductor region 354 is disposed at the same depth as the ninth semiconductor region 351. When the twelfth semiconductor region 354 is a semiconductor region of the first conductivity type, the impurity concentration of the twelfth semiconductor region 354 is lower than the impurity concentration of the ninth semiconductor region 351. When the twelfth semiconductor region 354 is a semiconductor region of the second conductivity type, the impurity concentration of the twelfth semiconductor region 354 is lower than the impurity concentration of the tenth semiconductor region 352.

[0141] The avalanche multiplier unit 314 is formed by an electric field between the ninth semiconductor region 351 and the tenth semiconductor region 352. According to the structure of this exemplary embodiment, the area of ​​the ninth semiconductor region 351 can be kept constant regardless of the pixel size. In the eleventh semiconductor region 535, the potential of the signal charge is set to a lower potential than that in the tenth semiconductor region 352. Using this structure, the charge photoelectrically converted by the sixth semiconductor region 315 is collected by the avalanche multiplier unit 314 via the eleventh semiconductor region 535. By designing the potential in this way, the area of ​​the avalanche multiplier unit 314, which serves as a noise source, can be suppressed to a necessary minimum.

[0142] exist Figure 19A In the plan view, the ninth semiconductor region 351 and the tenth semiconductor region 352 do not overlap each other, but they may partially overlap each other.

[0143] Furthermore, if the potential of the signal charge in the eleventh semiconductor region 535 is set to be lower than that in the tenth semiconductor region 352, then the impurity concentration of the second conductivity type in the tenth semiconductor region 352 and the eleventh semiconductor region 535 can be the same. This point will also be explained in the ninth exemplary embodiment.

[0144] exist Figure 19A In the case where the PN junction depth of the ninth semiconductor region 351 and the tenth semiconductor region 352 is set to depth 401 and the depth of the tenth semiconductor region 352 is configured to be set to depth 403, the relationship between each depth and depth 402 is the same as in the first exemplary embodiment.

[0145] According to this exemplary embodiment, a miniaturized APD for achieving pixel size can be implemented. Since the isolation region 331 is provided, avalanche crosstalk can also be prevented. Furthermore, the signal charge of the avalanche multiplication unit 314 can be collected while reducing the area of ​​the avalanche multiplication unit 314 compared to the first exemplary embodiment. Therefore, light detection efficiency can be improved while reducing noise.

[0146] Reference Figure 20 To illustrate, a photoelectric conversion device according to an eighth exemplary embodiment will be described. In this exemplary embodiment, the isolation region 331b that does not reach the first surface 302 is arranged between adjacent pixels in the diagonal direction. (See reference...) Figure 13A and 13B The isolation region 331 of the fourth exemplary embodiment described is also provided between adjacent pixels in the diagonal direction, but extends to the first surface 302, and differs from this exemplary embodiment in that the isolation region 331 extends to the first surface 302. Since the photoelectric conversion device according to this exemplary embodiment is substantially the same as the photoelectric conversion device of the above exemplary embodiment except for this point and the points to be described below, the description will be omitted.

[0147] The isolation region 331b is expected to be formed to a depth close to the depth 401 where the avalanche multiplication unit 314 is set. This structure can prevent avalanche crosstalk between adjacent pixels in the diagonal direction.

[0148] According to this exemplary embodiment, an APD for miniaturizing pixel size can be implemented. Avalanche crosstalk can also be prevented due to the isolation region. In particular, avalanche crosstalk between adjacent pixels in the diagonal direction can be prevented.

[0149] Reference Figures 21 to 23 To illustrate the photoelectric conversion device according to the ninth exemplary embodiment.

[0150] Figure 21 It is a schematic plan view of 2×2(4) pixels out of the plurality of pixels included in pixel region 12. Figure 21 A plane is shown on the first surface of the semiconductor layer 300.

[0151] Figure 22A It is along Figure 21 The schematic cross-sectional view extending in the first direction is intercepted by the dashed line A-A', and Figure 22B It is along Figure 21 The dashed line B-B' in Figure 22 represents a schematic cross-sectional view extending in a second direction that intersects the first direction. In Figure 22, the first direction corresponds to the opposite side direction, and the second direction corresponds to the diagonal direction. Figure 22A and 22BThe image shows a semiconductor layer 300 included in a sensor substrate and a portion of a contact plug connected to the semiconductor layer 300.

[0152] like Figure 21 As shown, each pixel 104 includes at least one APD. The structure of a pixel 104 including one APD will be described below, but a pixel 104 may include multiple APDs. For convenience, the APD arranged adjacent to the first APD in the opposite direction will be referred to as the second APD, and the APD arranged adjacent to the first APD in the diagonal direction will be referred to as the third APD.

[0153] The details of each semiconductor region will be explained below. Figure 21 A first semiconductor region 1311 of a first conductivity type (e.g., N-type) is shown for forming the avalanche multiplication region of the APD. A third semiconductor region 1313 is disposed around the first semiconductor region 1311.

[0154] exist Figure 21 In this configuration, a sixth semiconductor region 1316 of a second conductivity type (e.g., P-type) is disposed between the first semiconductor region 1311 of the first APD and the first semiconductor region 1311 of the third APD, and is connected to the contact plug.

[0155] An isolation portion (isolation region) including a fourth semiconductor region 1314 of a second conductivity type is disposed between pixels. In the exemplary embodiments described above, an example was given in which the isolation portion (isolation region) includes a trench structure and a semiconductor region. On the other hand, in this exemplary embodiment, an example will be described in which the isolation portion (isolation region) only includes a semiconductor region. The fourth semiconductor region 1314 of the second conductivity type is disposed in a manner that isolates APDs in both the opposite side direction and the diagonal direction. In the plan view, the sixth semiconductor region 1316 is disposed in a manner that overlaps with the fourth semiconductor region 1314.

[0156] like Figure 22A As shown, the semiconductor region included in pixel 104 is disposed in semiconductor layer 300. The APD includes at least a first semiconductor region 1311 of a first conductivity type and a second semiconductor region 1312 of a second conductivity type. The first semiconductor region 1311 and the second semiconductor region 1312 form a PN junction. The impurity concentration of the first semiconductor region 1311 is higher than that of the second semiconductor region 1312. An avalanche multiplication region 1302 is formed by applying a predetermined reverse bias voltage to the first semiconductor region 1311 and the second semiconductor region 1312. The first semiconductor region 1311 is connected to a contact plug 1130 and a voltage is applied via the contact plug 1130. Multiple contact plugs 1130 can be configured.

[0157] A first conductivity type semiconductor region 1301 having an impurity concentration lower than that of the first semiconductor region 1311 can be disposed between the first semiconductor region 1311 and the second semiconductor region 1312. The semiconductor region 1301 can be a first conductivity type semiconductor region or a second conductivity type semiconductor region.

[0158] A third semiconductor region 1313 of a first conductivity type is disposed at the end of the first semiconductor region 1311 to mitigate the electric field. The third semiconductor region 1313 can be a semiconductor region of a second conductivity type, as long as it achieves the purpose of mitigating the electric field. When the third semiconductor region 1313 is a semiconductor region of the first conductivity type, the impurity concentration of the third semiconductor region 1313 is lower than the impurity concentration of the first semiconductor region 1311; and when the third semiconductor region 1313 is a semiconductor region of the second conductivity type, the impurity concentration of the third semiconductor region 1313 is lower than the impurity concentration of the second semiconductor region 1312. The impurity concentration of the third semiconductor region 1313 differs from that of the first semiconductor region 1311 or the second semiconductor region 1312 by more than a factor of two. The third semiconductor region 1313 is an additional semiconductor region and is not required.

[0159] exist Figure 22A and 22B In this configuration, the fourth semiconductor region 1314 of the second conductivity type is configured to isolate pixels in the opposite side direction and the diagonal direction. The second semiconductor region 1312 of the second conductivity type is configured to contact the fourth semiconductor region 1314.

[0160] The fifth semiconductor region 1315 of the second conductivity type is disposed at a deeper location than the second semiconductor region 1312. The fifth semiconductor region 1315 of the second conductivity type is configured to contact the fourth semiconductor region 1314. In a plan view, the fifth semiconductor region 1315 may be disposed over the entire surface of the pixel 104 and partially overlap with the fourth semiconductor region 1314. Figure 22A and 22B In the middle, the fifth semiconductor region 1315 is configured to contact the back side of the semiconductor layer 300, but it can also be configured at a certain distance. Figure 22A and 22B An example is shown of a fifth semiconductor region 1315 formed by ion implantation of a second conductivity type, but the structure is not limited thereto. For example, an example can be adopted in which a pinning film is disposed on the back side of the semiconductor layer 300 and the fifth semiconductor region 1315 is not formed by ion implantation. The pinning film can be made of known materials.

[0161] A planarization layer, filter layer, and microlens (not shown) can be disposed on the back side of semiconductor layer 300. Various optical filters, such as color filters, infrared cutoff filters, and monochromatic filters, can be used as the filter layer. RGB color filters or RGBW color filters can be used as color filters.

[0162] A seventh semiconductor region 1317 of a first conductivity type is disposed between the second semiconductor region 1312 and the fifth semiconductor region 1315. The impurity concentration of the seventh semiconductor region 1317 is higher than the impurity concentration of the semiconductor region 1301 disposed around the seventh semiconductor region 1317. Using this structure, for signal charge, the potential of the seventh semiconductor region 1317 becomes lower than the potential of the semiconductor region 1301, and a larger amount of charge can be collected to the avalanche multiplication region 1302. The seventh semiconductor region 1317 is a semiconductor region disposed as needed, and is not required to be disposed otherwise. Figure 22A and 22B In the cross-sectional view, the seventh semiconductor region 1317 and a portion of the second semiconductor region 1312 are in contact with each other, but the seventh semiconductor region 1317 may be located at a certain distance from the second semiconductor region 1312.

[0163] exist Figure 22A In this configuration, one end (top) of the fourth semiconductor region 1314 of the second conductivity type is positioned shallower than the second semiconductor region 1312 and deeper than the first surface of the semiconductor layer 300. In other words, between the first photoelectric conversion element including the first APD and the second photoelectric conversion element including the second APD, one end of the fourth semiconductor region 1314 is located closer to the second surface than the first surface, and closer to the first surface than the second semiconductor region 1312. Figure 22A As shown, the fourth semiconductor region 1314 is not continuously arranged from the second surface to the first surface in the opposite direction, and one end of the fourth semiconductor region 1314 is arranged at a certain distance from the first surface.

[0164] When a fourth semiconductor region 1314 is continuously disposed between the first APD and the second APD from the second surface to the first surface, a lateral electric field concentration may occur between the fourth semiconductor region 1314 and the first semiconductor region 1311 or the third semiconductor region 1313. On the other hand, if one end of the fourth semiconductor region 1314 is located above and below the second semiconductor region 1312, the depletion layer may extend laterally between the first semiconductor regions 1311 of the first APD and the second APD. Therefore, connections through the depletion layer may occur between pixels.

[0165] Conversely, according to this exemplary embodiment, in the opposite side direction, the upper end of the fourth semiconductor region 1314 is disposed at a position that is deeper than the first surface and shallower than the second semiconductor region 1312. Therefore, punch-through can be suppressed while preventing electric field concentration in the lateral direction.

[0166] like Figure 22B As shown, in the diagonal direction, the fourth semiconductor region 1314 is continuously disposed downwards from the first surface to the same depth as the fifth semiconductor region 1315. Compared to the opposite side direction, it is easier to ensure the distance between the fourth semiconductor region 1314 and the first semiconductor region 1311 or the third semiconductor region 1313 in the diagonal direction. Therefore, the distance between the fourth semiconductor region 1314 and the first semiconductor region 1311 or the third semiconductor region 1313 becomes longer than the distance in the opposite side direction. For this reason, even if the fourth semiconductor region 1314 is disposed up to the first surface in the diagonal direction, electric field concentration in the lateral direction is less likely to occur compared to the opposite side direction. Figure 22B As shown, in the diagonal direction, since voltage will be applied to the second semiconductor region 1312 via the contact plug 131 as described below, the fourth semiconductor region 1314 is continuously arranged diagonally up to the first surface. Since only contact between the fourth semiconductor region 1314 and the sixth semiconductor region 1316 is required, it is not necessary to continuously form the fourth semiconductor region 1314 up to the first surface. It is sufficient that at least the fourth semiconductor region 1314 and the sixth semiconductor region 1316 are in contact with each other.

[0167] A sixth semiconductor region 1316 of the second conductivity type is disposed on the first surface side of the semiconductor layer 300. For example... Figure 21 and 22B As shown, the sixth semiconductor region 1316 is contained within the fourth semiconductor region 1314 of the second conductivity type.

[0168] The impurity concentration of the sixth semiconductor region 1316 is higher than that of the fourth semiconductor region 1314. This structure allows for a lower contact resistance between the metal and the semiconductor compared to the contact resistance generated when the fourth semiconductor region 1314 and the contact plug 131 are connected by connecting the sixth semiconductor region 1316 and the contact plug 131.

[0169] A predetermined reverse bias voltage can be applied to the contact plug 131 connected to the sixth semiconductor region 1316 and the contact plug 1130 connected to the first semiconductor region 1311 to form an avalanche multiplication region 1302.

[0170] (The organization of semiconductor regions at various locations and the relationship between their potentials)

[0171] At a first depth D1, a first semiconductor region 1311 of a first conductivity type, a third semiconductor region 1313 of a first conductivity type or a second conductivity type, a semiconductor region 1301 of a first conductivity type or a second conductivity type, a fourth semiconductor region 1314 of a second conductivity type, and a sixth semiconductor region 1316 of a second conductivity type are configured.

[0172] The first semiconductor region 1311 and the third semiconductor region 1313 are in contact with each other in a plan view. Additionally, the third semiconductor region 1313 and the semiconductor region 1301 are in contact with each other in a plan view.

[0173] The state in which each semiconductor region is configured at a first depth D1 refers, for example, to the state in which the concentration peak of the ion-implanted impurity is configured at the first depth D1. However, the peak need not always be configured at the first depth D1, and it is sufficient to set the region where the diffusion of the impurity can be identified at the first depth D1.

[0174] The second depth D2 is a position deeper than the first depth D1. In other words, the second depth D2 is a position closer to the back surface of the semiconductor layer 300 than the first depth D1. The second semiconductor region 1312 and the fourth semiconductor region 1314 are disposed at the second depth D2.

[0175] The third depth D3 is a position deeper than the second depth D2. In other words, the third depth D3 is a position closer to the back surface of the semiconductor layer 300 than the second depth D2. The seventh semiconductor region 1317, semiconductor region 1301, and fourth semiconductor region 1314 are disposed at the third depth D3.

[0176] The fourth depth D4 is a deeper location than the third depth D3. In other words, the fourth depth D4 is closer to the back surface of the semiconductor layer 300 than the third depth D3. The fifth semiconductor region 1315 and the fourth semiconductor region 1314 are disposed at the fourth depth D4.

[0177] Figure 23 Show Figure 21 , 22A Potential diagram of the APD in 22B.

[0178] exist Figure 23 In the diagram, dashed line 20 indicates the potential distribution of line DD', and solid line 30 indicates the potential distribution of line CC'. Figure 23 The depths D1 to D4 along the horizontal axis correspond to... Figure 22A Depths D1 to D4 in the range.

[0179] like Figure 23As indicated by the dashed line 20, the potential gradually decreases from the fourth depth D4 towards the third depth D3. Furthermore, since the seventh semiconductor region 1317 disposed at the third depth D3 is a first conductivity type semiconductor region, and the second semiconductor region 1312 disposed at the second depth D2 is a second conductivity type semiconductor region, the potential gradually increases from the third depth D3 towards the second depth D2. On the other hand, the third semiconductor region 1313 disposed at the first depth D1 is either a first conductivity type semiconductor region or a second conductivity type semiconductor region with a lower impurity concentration than the second semiconductor region 1312. Therefore, the potential decreases from the second depth D2 towards the first depth D1.

[0180] On the other hand, solid line 30 indicates the same trend as dashed line 20 in that the potential gradually decreases from the fourth depth D4 towards the third depth D3. However, solid line 30 indicates that the potential gradually decreases from the third depth D3 towards the second depth D2. Additionally, the potential decreases sharply from the second depth D2 towards the first depth D1. From the fourth depth D4 to the third depth D3, the potential gradients of dashed line 20 and solid line 30 indicate almost the same trend, and the potential gradient becomes gentler and lower. Therefore, the charge generated in the photodetector moves to the front side (first side) of semiconductor layer 300 using a gentle potential gradient.

[0181] As described above, the first semiconductor region 1311 and the second semiconductor region 1312 form a PN junction, but the impurity concentration of the second semiconductor region 1312 is lower than that of the first semiconductor region 1311. For this reason, if a reverse bias potential is supplied to the first semiconductor region 1311 and the second semiconductor region 1312, a depletion layer region is formed on the side of the second semiconductor region 1312. In this case, although a large electric field is applied to the central portion of the second semiconductor region 1312 surrounding the avalanche multiplication region 1302, a small electric field is applied only to the peripheral portion of the second semiconductor region 1312. Therefore, at the second depth D2, the potential of the solid line 30 drops sharply, and at the second depth D2, the potential of the solid line 30 becomes lower than that of the dashed line 20. On the other hand, since a small electric field is applied only to the peripheral portion of the second semiconductor region 1312, the potential relationship corresponding to the difference in conductivity or impurity concentration between the semiconductor regions is maintained.

[0182] Using this structure, such as Figure 23 As indicated by the dashed line 20 and solid line 30 at the second depth D2, the potential of the electrons, which are signal charges, is lower in the central part of the second semiconductor region 1312 than in the peripheral part. As a result, the photoelectric converted charges become more likely to move towards the central part of the second semiconductor region 1312.

[0183] The charge that has moved to the vicinity of the center of the second semiconductor region 1312 is passed through... Figure 23 The solid line 30 in the middle is accelerated by the steep potential gradient from the second depth D2 toward the first depth D1 and is subject to avalanche multiplication by the avalanche multiplication region 1302.

[0184] Conversely, from the second depth D2 to the first depth D1, Figure 23 The dashed line 20 in the diagram indicates a potential distribution that does not cause avalanche multiplication. Therefore, the generated charge can be counted as signal charge without increasing the area of ​​the avalanche multiplication region 1302 relative to the pixel size.

[0185] The following will provide examples of impurity concentrations in various semiconductor regions. In this example, it is assumed that the first conductivity type is N-type and the second conductivity type is P-type.

[0186] Figure 22B The impurity concentration in the sixth semiconductor region 1316 is approximately 1 × 10⁻⁶. 19 ~10 20 [atoms / cm 3 ].

[0187] The first semiconductor region 1311 of the N-type has a higher impurity concentration than the seventh semiconductor region 1317 of the N-type. For example, the impurity concentration of the first semiconductor region 1311 of the N-type is 1 × 10⁻⁶. 18 [atoms / (cm 3 The above applies, and a potential that is reverse biased relative to the fourth semiconductor region 1314 is supplied to the first semiconductor region 1311 of the N type.

[0188] The impurity concentration of the N-type third semiconductor region 1313 is lower than that of the N-type first semiconductor region 1311. For example, the impurity concentration of the N-type third semiconductor region 1313 is approximately 1 × 10⁻⁶. 16 ~5×10 17 [atoms / cm 3 If the third semiconductor region 1313 is a P-type semiconductor region, an avalanche multiplication electric field is formed between the first semiconductor region 1311 and the third semiconductor region 1313 depending on the impurity concentration of the third semiconductor region 1313, and this leads to noise degradation.

[0189] The impurity concentration of the second semiconductor region 1312 of the P-type is lower than that of the fourth semiconductor region 1314 of the P-type. For example, the impurity concentration of the second semiconductor region 1312 of the P-type is approximately 1 × 10⁻⁶. 16 ~5×10 17 [atoms / cm 3 ].

[0190] exist Figure 22A and 22B In this embodiment, assuming that without the second semiconductor region 1312 of type P, a seventh semiconductor region 1317 of type N, having an impurity concentration lower than that of the first semiconductor region 1311 of type N, is disposed directly below the first semiconductor region 1311 of type N. In this case, charge is generated in the seventh semiconductor region 1317, and the charge can be read from the first semiconductor region 1311 of type N.

[0191] However, avalanche multiplication is difficult to induce under voltage conditions equivalent to this exemplary embodiment. This is because most of the reverse bias potential difference is applied to the depletion layer region of the N-type seventh semiconductor region 1317, thus reducing the potential difference applied to the avalanche multiplication region near the N-type first semiconductor region 1311. On the other hand, in this exemplary embodiment, since the N-type seventh semiconductor region 1317 is surrounded by P-type semiconductor regions in all directions, the potential of the N-type seventh semiconductor region 1317 becomes closer to the level of the surrounding P-type semiconductor regions than that of the N-type first semiconductor region 1311. In other words, by preventing the depletion layer from excessively diffusing into the depth of the semiconductor layer in the P-type second semiconductor region 1312, most of the aforementioned potential difference to be applied can be concentrated on the avalanche multiplication region near the N-type first semiconductor region 1311. As a result, avalanche multiplication of photocarriers can be induced at a lower voltage. At this time, the impurity concentration of the N-type seventh semiconductor region 1317 is lower than that of the N-type first semiconductor region 1311.

[0192] Figure 22A and 22B An example of an N-type seventh semiconductor region 1317 is shown, exhibiting a region with the same impurity concentration. However, the N-type seventh semiconductor region 1317 is desirablely to have a gradient of impurity concentration to obtain a potential structure for charge moving toward the first surface side of the semiconductor layer 300. By employing such an impurity concentration gradient, charge can be easily moved toward the N-type seventh semiconductor region 1317.

[0193] Figure 22A and 22B A p-type second semiconductor region 1312 is shown, consisting of an impurity region with the same impurity concentration. However, any structure can be used, as long as the potential of the central portion of the second semiconductor region 1312 is lower than that of the peripheral portion. For example, a structure can be used in which the impurity concentration of the peripheral portion of the second semiconductor region 1312 is higher than that of the central portion of the p-type second semiconductor region 1312. Furthermore, the central portion of the second semiconductor region 1312 can be an n-type semiconductor region.

[0194] According to this exemplary embodiment, an APD for miniaturizing pixel size can be implemented. Puncture between the first semiconductor region 1311 of the first APD and the first semiconductor region 1311 of the second APD can be prevented, while preventing the generation of an electric field between the fourth semiconductor region 1314 and the first semiconductor region 1311 or the third semiconductor region 1313.

[0195] Reference Figure 24 , 25A 25B will be used to illustrate the photoelectric conversion device according to the tenth exemplary embodiment. Figure 24 This is a schematic plan view of the semiconductor layer 300 of the APD of the photoelectric conversion device according to this exemplary embodiment. Figure 25A It is along Figure 24 The schematic cross-sectional view intercepted by the dashed line A-A' in the figure, and Figure 25B It is along Figure 24 The schematic cross-sectional view is shown by the dashed line B-B'. The photoelectric conversion device according to this exemplary embodiment differs from the photoelectric conversion device of the ninth exemplary embodiment in that the ninth semiconductor region 1319 of the first conductivity type is disposed near the first surface of the semiconductor layer 300. Since the photoelectric conversion device according to this exemplary embodiment is substantially the same as the photoelectric conversion device of the ninth exemplary embodiment, except for this point and the matters to be described below, descriptions will sometimes be omitted by assigning the same reference numerals to the same components as in the ninth exemplary embodiment.

[0196] like Figure 24 As shown in the plan view, the ninth semiconductor region 1319 is arranged around the first semiconductor region 1311 and the third semiconductor region 1313. It is desirable that the impurity concentration of the ninth semiconductor region 1319 is equal to or less than the impurity concentration of the third semiconductor region 1313. For example, when the impurity concentrations of the ninth semiconductor region 1319 and the third semiconductor region 1313 are different, it is desirable that the impurity concentration of the ninth semiconductor region 1319 is more than twice as low as the impurity concentration of the third semiconductor region 1313.

[0197] By configuring the ninth semiconductor region 1319, noise in the signal that may be caused by dark electrons generated by defect energy levels at or near the interface of the first surface of the semiconductor layer 300 can be reduced. If the ninth semiconductor region 1319 is configured, a region with a lower potential relative to dark electrons is formed from the ninth semiconductor region 1319 toward the first semiconductor region 1311. In other words, dark electrons generated near the interface of the first surface of the semiconductor layer 300 become more likely to move toward the first semiconductor region 1311 and become less likely to move toward semiconductor regions 1301 and the seventh semiconductor region 1317. Therefore, dark electrons can be prevented from passing through the avalanche multiplication region 1302, and noise is reduced. Dark electrons that have moved to the first semiconductor region 1311 via the third semiconductor region 1313 are read out without passing through the avalanche multiplication region 1302 and are not identified as a signal. Therefore, even if dark electrons are read out, they are not considered noise.

[0198] The ninth semiconductor region 1319 can be configured such that the impurity concentration decreases with distance from the first semiconductor region 1311, or it can be configured such that the impurity concentration remains the same. The ninth semiconductor region 1319 can have a concentration gradient in the depth direction.

[0199] like Figure 25A As shown, in the opposite direction, the ninth semiconductor region 1319 is preferably configured continuously from the third semiconductor region 1313 of a particular pixel 104 to the third semiconductor region 1313 of the adjacent pixel between adjacent pixels. Figure 24 As shown, in a plan view, the ninth semiconductor region 1319 is preferably configured to surround the first semiconductor region 1311, the third semiconductor region 1313, the sixth semiconductor region 1316, and the fourth semiconductor region 1314. For example, in a plan view, the ninth semiconductor region 1319 is preferably configured in a region other than the first semiconductor region 1311, the third semiconductor region 1313, the sixth semiconductor region 1316, and the fourth semiconductor region 1314. With this structure, it becomes easier to reduce the effects of signal noise degradation caused by dark electrons.

[0200] The ninth semiconductor region 1319 is preferably positioned shallower than the lower end of the first semiconductor region 1311. It is also desirable that the vertical length of the ninth semiconductor region 1319 is shorter than the vertical length of the third semiconductor region 1313. Furthermore, it is desirable that the vertical length of the ninth semiconductor region 1319 is shorter than the vertical length of the first semiconductor region 1311. This structure prevents dark electrons from unintentionally moving into the avalanche multiplication region 1302.

[0201] In the opposite direction, the ninth semiconductor region 1319 and the fourth semiconductor region 1314 can be in contact with each other, or can be as follows: Figure 25A As shown, they are separated from each other. When the ninth semiconductor region 1319 and the fourth semiconductor region 1314 are in contact with each other, it is difficult for charge to move to adjacent pixels. When the ninth semiconductor region 1319 and the fourth semiconductor region 1314 are separated from each other, it is difficult to generate electric field concentration between the fourth semiconductor region 1314 and the first semiconductor region 1311. In the diagonal direction, the ninth semiconductor region 1319 and the fourth semiconductor region 1314 are as follows... Figure 25B The regions shown are in contact with each other, but can be separated from each other. However, as described above, it is desirable that the ninth semiconductor region 1319 be configured to contact the fourth semiconductor region 1314 in order to obtain the noise reduction effect caused by the configuration of the ninth semiconductor region 1319.

[0202] exist Figure 24 In this exemplary embodiment, the ninth semiconductor region 1319 is configured to form part of the first surface of the semiconductor layer 300; however, the ninth semiconductor region 1319 need not always be configured in this manner. For example, the ninth semiconductor region 1319 may be configured at a location away from the first surface.

[0203] like Figure 26 As shown, the third semiconductor region 1313 can be configured to contact the second semiconductor region 1312. Although the third semiconductor region 1313 is... Figure 24 , 25A And in 25B, it is configured in a toroidal shape, but the third semiconductor region 1313 is in Figure 26 The center is configured in a circular shape. For example, as shown... Figure 26 As shown, a third semiconductor region 1313 of a first conductivity type is disposed between the first semiconductor region 1311 and the second semiconductor region 1312. This structure deepens the PN junction surface and prevents localized electric field concentration in the avalanche multiplication region 1302. (Note: The schematic plan view is not directly related to the diagram.) Figure 24 The schematic cross-sectional views in the diagonal direction are the same, except that the third semiconductor region 1313 is disposed between the first semiconductor region 1311 and the second semiconductor region 1312, so the figures are omitted.

[0204] exist Figure 26 In this configuration, the impurity concentration of the third semiconductor region 1313 near the side of the first semiconductor region 1311 and the impurity concentration of the third semiconductor region 1313 near the bottom of the first semiconductor region 1311 can be the same. Optionally, the third semiconductor region 1313 can be configured such that the impurity concentration of the third semiconductor region 1313 decreases as it approaches the second semiconductor region 1312 from the first semiconductor region 1311.

[0205] The impurity concentration in the third semiconductor region 1313 near the first semiconductor region 1311 can be lower than the impurity concentration near the ninth semiconductor region 1319. For example, the impurity concentration in the third semiconductor region 1313 can gradually decrease with distance from the first semiconductor region 1311. This structure can mitigate the concentration of electric field in the lateral direction.

[0206] According to this exemplary embodiment, an APD for miniaturizing pixel size can be implemented. Penetration between pixels can be prevented while preventing the generation of electric fields in the lateral direction. Furthermore, it is easier to form a spatially uniform electric field distribution in the avalanche multiplication region 1302, and noise attributable to electric field concentration can be reduced.

[0207] Reference Figure 27 , 28A 28B will be used to illustrate the photoelectric conversion device according to the eleventh exemplary embodiment. Figure 27 This is a schematic plan view of the semiconductor layer 300 of the APD of the photoelectric conversion device according to this exemplary embodiment. Figure 28A It is along Figure 27 The schematic cross-sectional view intercepted by the dashed line A-A' in the figure, and Figure 28B It is along Figure 27 The schematic cross-sectional view is shown by the dashed line B-B'. The photoelectric conversion device according to this exemplary embodiment differs from the photoelectric conversion device of the tenth exemplary embodiment in that the isolation portion includes a trench structure 1321 in the opposite side direction between pixels. Since, except for this point and the matters to be described below, the photoelectric conversion device according to this exemplary embodiment is substantially the same as the photoelectric conversion device of the tenth exemplary embodiment, descriptions will sometimes be omitted by assigning the same reference numerals to the same components as in the tenth exemplary embodiment.

[0208] Although no trench structure 1321 is configured on the first surface of semiconductor layer 300, the location where the trench structure 1321 is configured is... Figure 27 The trench structure 1321 is represented by a dashed line to facilitate understanding of its planar configuration.

[0209] The trench structure 1321 preferably includes a material different from that of the semiconductor layer 300. The trench structure 1321 preferably includes a reflective material or a light-absorbing material. The reflective or light-absorbing material is, for example, a material that reflects or absorbs more than 20% of light. For example, the trench structure 1321 includes at least one of an insulating member, air, and a metal. In the case that the semiconductor layer 300 is silicon, examples of insulating members include silicon oxide films and silicon nitride films. Using this structure, crosstalk to adjacent APDs can be prevented. More preferably, the trench structure 1321 includes at least one of an insulating member and a metal. In the avalanche multiplication region 1302, a phenomenon called avalanche luminescence sometimes occurs. This is the phenomenon of photons being generated due to the recombination of holes with electrons, which are hot carriers generated by avalanche multiplication. If photons generated by avalanche luminescence leak into adjacent pixels and are photoelectrically converted, electron-hole pairs are generated. In other words, photons generated by avalanche luminescence, rather than incident light, are read out as signals from adjacent pixels, causing aliasing. Because the trench structure 1321 includes metal, it can prevent photons from mixing into adjacent pixels even in the event of avalanche luminescence.

[0210] The trench structure 1321 is preferably configured from the second surface of the semiconductor layer 300 to the same depth as or shallower than the second semiconductor region 1312. This is because this structure can easily prevent crosstalk caused by photons generated by avalanche emission into adjacent pixels. However, the trench structure 1321 can be configured from the second surface to a depth deeper than the second semiconductor region 1312. This is because, again, in this case, it is easier to prevent crosstalk attributable to avalanche emission compared to the case where the trench structure 1321 is not configured.

[0211] exist Figure 28A In this configuration, a trench structure 1321 is formed from the back side of the semiconductor layer 300. The trench structure 1321 is provided by being contained within a fourth semiconductor region 1314. In other words, in the opposite side direction, the pixel is isolated by both the trench structure 1321 and the fourth semiconductor region 1314 of the second conductivity type.

[0212] On the other hand, reference Figure 28B In the diagonal direction, no trench structure 1321 is provided, and the pixels are isolated only by the fourth semiconductor region 1314.

[0213] According to this exemplary embodiment, an APD for miniaturizing pixel size can be implemented. Penetration between pixels can be prevented while preventing the generation of electric fields in the lateral direction. Furthermore, it is easier to form a spatially uniform electric field distribution in the avalanche multiplication region 1302, and noise attributable to electric field concentration can be reduced. Moreover, crosstalk attributable to avalanche luminescence is more easily prevented.

[0214] Since no trench structure 1321 is configured between the pixels in the diagonal direction, the resistance from the contact plug 1131 toward the fifth semiconductor region 1315 can be reduced. This structure makes it easier to form a potential gradient in the direction perpendicular to the semiconductor layer 300 and shortens the time required to collect signal charge into the avalanche multiplication region 1302.

[0215] like Figure 29 , 30A As shown in 30B, the trench structure 1321 can be configured between pixels in the opposite side direction and the diagonal direction. Figure 27 The same, in Figure 29 The location of the trench structure 1321 is indicated by dashed lines to facilitate understanding of its planar configuration. In this case, as... Figure 29 As shown, in a plan view, the trench structure 1321 is configured to surround the entire circumference of the first semiconductor region 1311.

[0216] according to Figure 29 , 30A The structure shown in 30B can prevent crosstalk attributable to avalanche luminescence in the diagonal direction.

[0217] Reference Figure 31 , 32A The photoelectric conversion device according to the twelfth exemplary embodiment is illustrated by 32B. Figure 31 This is a schematic plan view of the semiconductor layer 300 of the APD configured in the photoelectric conversion device according to this exemplary embodiment. Figure 32A It is along Figure 31 The schematic cross-sectional view intercepted by the dashed line A-A' in the figure, and Figure 32B It is along Figure 31 A schematic cross-sectional view taken by the dashed line B-B' in the figure. In the photoelectric conversion device according to this exemplary embodiment, the trench structure 1321 penetrating the semiconductor layer 300 is provided in a manner that isolates pixels in the opposite side direction. Additionally, the trench structure 1321 not penetrating the semiconductor layer 300 is provided in a manner that isolates pixels in the diagonal direction. Since the photoelectric conversion device according to this exemplary embodiment is substantially the same as the photoelectric conversion device of the eleventh exemplary embodiment, except for this point and the matters to be explained below, descriptions will sometimes be omitted by assigning the same reference numerals to the same components as in the eleventh exemplary embodiment.

[0218] In the opposite direction between pixels, the fourth semiconductor region 1314 of the second conductivity type is configured to contact a portion of the trench structure 1321 penetrating the semiconductor layer 300, but the fourth semiconductor region 1314 is not configured in other portions. For example, as Figure 32AAs shown, at a location shallower than the second semiconductor region 1312, a first portion of the trench structure 1321 contacts the fourth semiconductor region 1314. Additionally, a second portion contacts the first conductivity type semiconductor region 1301, and a third portion contacts the ninth semiconductor region 1319. The first, second, and third portions become closer to the first surface of the semiconductor layer 300 in the order of first, second, and third portions. A portion of the trench structure 1321 does not always need to contact the semiconductor region 1301. The trench structure 1321 only needs to partially contact at least the fourth semiconductor region 1314 and the ninth semiconductor region 1319. In this way, the trench structure 1321 includes portions contacting the second conductivity type semiconductor region and portions contacting the first conductivity type semiconductor region. Figure 32A Even when unwanted charges are generated due to the trench structure 1321, the second semiconductor region 1312 and the fourth semiconductor region 1314, which have high potentials, are disposed in the lower part. Additionally, the third semiconductor region 1313 and the ninth semiconductor region 1319, which have lower potentials, are disposed in the upper part. In other words, because the potential makes it difficult for unwanted charges to move to the avalanche multiplication region 1302, even if unwanted charges are generated, they are unlikely to affect the signal to be read.

[0219] As the material for the trench structure 1321, the same material described in the exemplary embodiments above can be used. When the trench structure 1321 includes a portion in contact with a semiconductor region of the first conductivity type, it is desirable to configure a pinning film at least in the region in contact with the semiconductor region of the first conductivity type. Since holes accumulate near the trench structure 1321 due to the pinning film, even if unnecessary charges are generated due to the formation of the trench structure 1321, these unnecessary charges are unlikely to be read as signals. The pinning film can be continuously configured from the lower end of the trench structure 1321 to its upper end.

[0220] Due to the structure and reference in the diagonal direction between pixels Figure 30B The structure described in the eleventh exemplary embodiment is the same, therefore the description will be omitted. In the diagonal direction between pixels, the trench structure 1321 does not need to be as described in the reference. Figure 28B Configured as described.

[0221] According to this exemplary embodiment, an APD for miniaturizing pixel size can be implemented. The generation of electric fields in the lateral direction can be prevented while preventing crosstalk between pixels. Furthermore, it is easier to form a spatially uniform electric field distribution in the avalanche multiplication region 1302, and noise attributable to electric field concentration can be reduced. Moreover, since the trench structure 1321 penetrating the semiconductor layer 300 is configured in the opposite side direction between pixels, crosstalk attributable to avalanche emission is more easily prevented.

[0222] Reference Figure 33A and 33B To illustrate the photoelectric conversion device according to the thirteenth exemplary embodiment. Figure 33A Show Figure 22A The variant example, and Figure 32B Show Figure 25A A variation of the above.

[0223] This exemplary embodiment differs from the exemplary embodiment described above in that the upper surface of the fourth semiconductor region 1314 of the second conductivity type is positioned at the same location as the second semiconductor region 1312. Similarly, with this structure, since the upper surface of the fourth semiconductor region 1314 of the second conductivity type is located below the first semiconductor region 1311 of the first conductivity type, electric field concentration in the lateral direction can be suppressed. Using this structure, an APD for miniaturizing pixel size can be implemented.

[0224] Since other matters are substantially the same as those in the ninth and tenth exemplary embodiments, descriptions will be omitted by assigning the same reference numerals to the same components as in these exemplary embodiments.

[0225] Reference Figures 34A to 34G A method for manufacturing a photoelectric conversion device according to a fourteenth exemplary embodiment will be described. For ease of explanation, a method for manufacturing a photoelectric conversion device according to a second exemplary embodiment will be described; however, photoelectric conversion devices according to other exemplary embodiments can also be manufactured using the same method. Reference will be made to... Figures 34A to 34G The illustration uses a cross-sectional view taken along the opposite sides of adjacent pixels, but a cross-sectional view taken along the diagonal direction can also be created based on a similar approach. Furthermore, known manufacturing methods can be applied to unreferenced methods. Figures 34A to 34G The steps are explained.

[0226] First, such as Figure 34A As shown, semiconductor layer 301 is prepared.

[0227] Next, as Figure 34B As shown, ion implantation of a second conductivity type of impurity is performed on the region becoming the seventh semiconductor region 316 from the normal direction relative to the first surface 302. This forms the seventh semiconductor region 316 at a depth relative to the first surface 302 of the semiconductor layer 301. Similarly, ion implantation of a second conductivity type of impurity is performed on the region becoming the sixth semiconductor region 315. This forms the sixth semiconductor region 315 at a depth in the semiconductor layer 301 shallower than the seventh semiconductor region 316.

[0228] Next, as Figure 34CAs shown, ion implantation of impurities of a second conductivity type is performed on the region that becomes the third semiconductor region 321 from the normal direction relative to the first surface 302. This forms the third semiconductor region 321.

[0229] Next, as Figure 34D As shown, an isolation region 331 is formed between adjacent pixels. The isolation region 331 is formed in the region where the third semiconductor region 321 is disposed. Therefore, the sidewall portion of the isolation region 331 is covered by the third semiconductor region 321.

[0230] Next, as Figure 34E As shown, ion implantation of impurities of a second conductivity type is performed on the region becoming the second semiconductor region 312 from the normal direction relative to the first surface 302. This forms the second semiconductor region 312. Similarly, ion implantation of impurities of a first conductivity type is performed on the region becoming the first semiconductor region 311 from the normal direction relative to the first surface 302, in a manner that contacts the second semiconductor region 312 in the depth direction. This forms the first semiconductor region 311. Therefore, a PN junction is formed between the first semiconductor region 311 and the second semiconductor region 312. If the voltages VL and VH described in the first exemplary embodiment are applied to the PN junction, an avalanche multiplication unit 314 is formed.

[0231] Next, as Figure 34F As shown, impurities are implanted into the region that becomes the fifth semiconductor region 313 from the normal direction relative to the first surface 302. This forms the fifth semiconductor region 313.

[0232] Next, as Figure 34G As shown, a contact plug 341 is formed in the first semiconductor region 311.

[0233] The pixels of this exemplary embodiment can be manufactured using this manufacturing method.

[0234] Reference Figure 35 To illustrate the photoelectric conversion system according to the fifteenth exemplary embodiment. Figure 35 This is a block diagram illustrating the schematic structure of a photoelectric conversion system according to this exemplary embodiment.

[0235] The photoelectric conversion device described in the exemplary embodiments above can be applied to various photoelectric conversion systems. Examples of photoelectric conversion systems to which the photoelectric conversion device can be applied include digital still cameras, digital video cameras, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules that include optical systems such as lenses and imaging devices are also included in photoelectric conversion systems. Figure 35 A block diagram of a digital still camera is shown as an example of these photoelectric conversion systems.

[0236] Figure 35 The illustrated photoelectric conversion system includes an imaging device 1004, used as an example of a photoelectric conversion device, and a lens 1002 that forms an optical image of a subject on the imaging device 1004. The photoelectric conversion system also includes an aperture 1003 for changing the amount of light passing through the lens 1002 and a protective cover 1001 for protecting the lens 1002. The lens 1002 and aperture 1003 serve as an optical system for converging light onto the imaging device 1004. The imaging device 1004 is a photoelectric conversion device according to any of the exemplary embodiments described above, and converts the optical image formed by the lens 1002 into an electrical signal.

[0237] The photoelectric conversion system also includes a signal processing unit 1007, which serves as an image generation unit to generate an image by processing the output signal from the imaging device 1004. The signal processing unit 1007 performs various types of corrections and compressions as needed before outputting image data. The signal processing unit 1007 may be formed in the semiconductor layer on which the imaging device 1004 is disposed, or it may be formed in a different semiconductor layer than the semiconductor layer of the imaging device 1004. The imaging device 1004 and the signal processing unit 1007 may also be formed in the same semiconductor layer.

[0238] The photoelectric conversion system also includes a memory unit 1010 for temporarily storing image data and an external interface unit (external I / F unit) 1013 for communicating with an external computer. The photoelectric conversion system also includes a recording medium 1012, such as a semiconductor memory, for recording or reading captured image data, and a recording medium control interface unit (recording medium control I / F unit) 1011 for recording or reading relative to the recording medium 1012. The recording medium 1012 can be built into the photoelectric conversion system or can be detachably attached to the photoelectric conversion system.

[0239] The photoelectric conversion system also includes a general control / computing unit 1009 for controlling various types of computing and the entire digital still camera, and a timing generation unit 1008 for outputting various timing signals to the imaging device 1004 and the signal processing unit 1007. The timing signals can be input externally. The photoelectric conversion system includes at least the imaging device 1004 and a signal processing unit 1007 for processing the output signals from the imaging device 1004.

[0240] The camera device 1004 outputs a camera signal to the signal processing unit 1007. The signal processing unit 1007 performs predetermined signal processing on the camera signal output from the camera device 1004 and then outputs image data. The signal processing unit 1007 uses the camera signal to generate an image.

[0241] In this way, according to this exemplary embodiment, a photoelectric conversion system applying a photoelectric conversion device (camera device) according to any of the above exemplary embodiments can be realized.

[0242] Reference Figure 36A and 36B To illustrate the photoelectric conversion system and movable body according to the sixteenth exemplary embodiment. Figure 36A and 36B This is a diagram illustrating the structure of the photoelectric conversion system and the movable body according to this exemplary embodiment.

[0243] Figure 36A An example of a photoelectric conversion system associated with a vehicle-mounted camera is shown. The photoelectric conversion system 2300 includes an imaging device 2313. The imaging device 2313 is a photoelectric conversion device according to any of the exemplary embodiments described above. The photoelectric conversion system 2300 includes an image processing unit 2312 for image processing of multiple image data acquired by the imaging device 2313. The photoelectric conversion system 2300 also includes a disparity acquisition unit 2314 for calculating disparity (phase difference between disparity images) from the multiple image data acquired by the photoelectric conversion system 2300. The photoelectric conversion system 2300 also includes a distance acquisition unit 2316 for calculating the distance to a target object based on the calculated disparity, and a collision determination unit 2318 for determining whether a collision is possible based on the calculated distance. In this example, the disparity acquisition unit 2314 and the distance acquisition unit 2316 serve as examples of distance information acquisition units that acquire distance information related to the distance to the target object. More specifically, the distance information is information related to disparity, defocus amount, and distance to the target object. The collision determination unit 2318 can use any information from this distance information to determine the probability of a collision. The distance information acquisition unit can be implemented by specially designed hardware or by a software module. Optionally, the distance information acquisition unit can be implemented by a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC), or a combination thereof.

[0244] The photoelectric conversion system 2300 is connected to the vehicle information acquisition device 2320 and can acquire vehicle information such as vehicle speed, yaw rate, or steering angle. Additionally, a control electronic control unit (ECU) 2330 is connected to the photoelectric conversion system 2300. The ECU 2330 acts as a control device (control unit) that outputs control signals to the vehicle to generate braking force based on the judgment results obtained by the collision judgment unit 2318. The photoelectric conversion system 2300 is also connected to an alarm device 2340, which issues an alarm to the driver based on the judgment results obtained by the collision judgment unit 2318. For example, if the judgment result obtained by the collision judgment unit 2318 indicates a high probability of collision, the control ECU 2330 performs vehicle control to avoid a collision or reduce damage by braking, releasing the accelerator pedal, or suppressing engine output. The alarm device 2340 alerts the user by emitting warning sounds, displaying warning information on the screen of the car navigation system, or vibrating the seat belt or steering wheel.

[0245] In this exemplary embodiment, the photoelectric conversion system 2300 captures images of the vehicle's surroundings (such as the front or rear sides). Figure 36B A photoelectric conversion system 2300 is shown for capturing images of the front side of a vehicle (camera range 2350). A vehicle information acquisition device 2320 sends commands to the photoelectric conversion system 2300 or the camera device 2313. This structure can further improve the accuracy of distance measurement.

[0246] The above illustrates examples of control methods that avoid collisions with other vehicles. Photoelectric conversion systems can also be applied to control autonomous driving by following other vehicles or by maintaining lane departure. Furthermore, in addition to vehicles such as automobiles, photoelectric conversion systems can be applied to mobile bodies (mobile devices) such as ships, aircraft, or industrial robots. Moreover, beyond mobile bodies, photoelectric conversion systems can be applied to devices that widely utilize object recognition, such as Intelligent Transportation Systems (ITS).

[0247] Reference Figure 37 To illustrate the photoelectric conversion system according to the sixteenth exemplary embodiment. Figure 37 This is a block diagram illustrating an example structure of a distance image sensor as a photoelectric conversion system.

[0248] like Figure 37 As shown, the distance image sensor 401 includes an optical system 402, a photoelectric conversion device 403, an image processing circuit 404, a monitor 405, and a memory 406. The distance image sensor 401 can acquire a distance image corresponding to the distance to the subject by receiving light (modulated light or pulsed light) projected from the light source device 411 onto the subject and reflected from the front of the subject.

[0249] The optical system 402 includes one or more lenses and forms an image on the light receiving surface (sensor portion) of the photoelectric conversion device 403 by guiding image light (incident light) from the subject to the photoelectric conversion device 403.

[0250] The photoelectric conversion device described in the above exemplary embodiment is applied to the photoelectric conversion device 403, and a distance signal indicating the distance obtained from the light receiving signal output from the photoelectric conversion device 403 is supplied to the image processing circuit 404.

[0251] The image processing circuit 404 performs image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 403. Then, the distance image (image data) obtained through image processing is supplied to the monitor 405 for display thereon, or supplied to the memory 406 for storage (recording).

[0252] By applying the photoelectric conversion device described above, the distance image sensor 401 with the above structure can acquire a more accurate distance image based on, for example, improvements in pixel characteristics.

[0253] Reference Figure 38 To illustrate the photoelectric conversion system according to the seventeenth exemplary embodiment. Figure 38 This is a diagram illustrating an example of a schematic structure of an endoscopic surgical system that serves as a photoelectric conversion system in this exemplary embodiment.

[0254] Figure 38 This illustrates a surgeon (physician) 1131 using an endoscopic surgical system 1103 to operate on a patient 1132 lying on a patient bed 1133. Figure 38 As shown, the endoscopic surgical system 1103 includes an endoscope 1100, surgical instruments 1110, and a trolley 1134 equipped with various devices for endoscopic surgery.

[0255] Endoscope 1100 includes a tube 1101 and a camera 1102 connected to the proximal end of the tube 1101, wherein the tube 1101 is inserted into the body cavity of the patient 1132 at a predetermined distance from its distal end. Figure 38 The example shown depicts an endoscope 1100 formed as a rigid mirror including a rigid tube 1101, but the endoscope 1100 may be formed as a flexible mirror including a flexible tube.

[0256] An opening for mounting an objective lens is provided at the distal end of the endoscope tube 1101. A light source device 1203 is connected to the endoscope 1100, and the light generated by the light source device 1203 is guided to the distal end of the endoscope tube 1101 through a light guide extending inside the endoscope tube 1101, and then emitted through the objective lens onto the target to be observed in the body cavity of the patient 1132. The endoscope 1100 can be a direct-viewing endoscope, or it can be an oblique-viewing endoscope or a lateral-viewing endoscope.

[0257] An optical system and a photoelectric conversion device are provided inside the camera 1102. Reflected light (observation light) from the observed target is converged to the photoelectric conversion device by the optical system. The photoelectric conversion device performs photoelectric conversion on the observation light and generates an electrical signal corresponding to the observation light (i.e., an image signal corresponding to the observed image). The photoelectric conversion device described in the above exemplary embodiment can be used as a photoelectric conversion device. The image signal is sent as raw data to the camera control unit (CCU) 1135.

[0258] The CCU 1135 includes a central processing unit (CPU) or a graphics processing unit (GPU) and provides overall control over the operation of the endoscope 1100 and the display device 1136. Furthermore, the CCU 1135 receives image signals from the camera 1102 and performs various types of image processing on the image signals for displaying an image based on those signals, such as image enhancement processing (de-mosaic processing).

[0259] Based on the control from CCU 1135, display device 1136 displays an image based on an image signal that has undergone image processing by CCU 1135.

[0260] The light source device 1203 includes a light source such as a light-emitting diode (LED) and supplies illumination light to the endoscope 1100 for taking images of the surgical site.

[0261] Input device 1137 is the input interface of endoscopic surgery system 1103. Users can input various types of information and commands into endoscopic surgery system 1103 via input device 1137.

[0262] The processing tool control device 1138 controls the drive of the energy processing tool 1112 used for cauterizing or cutting tissue or sealing blood vessels.

[0263] The light source device 1203 that supplies illumination light to the endoscope 1100 for capturing images of the surgical site may include, for example, an LED, a laser light source, or a white light source comprising a combination of these. When the white light source includes a combination of RGB laser light sources, the white balance of the captured image can be adjusted within the light source device 1203 because the output intensity and timing of each color (wavelength) can be controlled with high precision. In this case, by emitting lasers from each RGB laser source onto the observation target in a time-division manner and controlling the driving of the image sensor of the camera 1102 in synchronization with the emission timing, images corresponding to each RGB can be captured in a time-division manner. According to this method, a color image can be obtained without setting a color filter in the image sensor.

[0264] The driving of the light source device 1203 can be controlled by changing the intensity of the output light at predetermined intervals. By controlling the driving of the image sensor of the camera 1102 in a time-division manner through timing synchronization with the changes in light intensity to acquire images and combine these images, high dynamic range images without underexposure or overexposure can be generated.

[0265] The light source device 1203 can be configured to supply light in a predetermined wavelength band suitable for special light observation. In special light observation, for example, the wavelength dependence of light absorption in body tissues is utilized. Specifically, by emitting light in a narrower band compared to the illumination light used in normal observation (i.e., white light), images of a predetermined tissue (e.g., blood vessels in the mucosal surface) can be captured with high contrast. Optionally, in special light observation, fluorescence observation can be performed to obtain images by emitting fluorescence generated by emitting excitation light. In fluorescence observation, fluorescence from body tissue can be observed by emitting excitation light onto the body tissue, or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and emitting excitation light of a fluorescence wavelength suitable for the reagent onto the body tissue. The light source device 1203 can be configured to supply narrow-band light and / or excitation light suitable for such special light observation.

[0266] Reference Figure 39A and 39B To illustrate the photoelectric conversion system according to the seventeenth exemplary embodiment. Figure 39AThis diagram illustrates an example of the structure of a pair of glasses 1600 (smart glasses) as a photoelectric conversion system. The glasses 1600 includes a photoelectric conversion device 1602. The photoelectric conversion device 1602 is the photoelectric conversion device described in the first to twelfth exemplary embodiments described above. A display device including a light-emitting device such as an organic light-emitting diode (OLED) or an LED can be provided on the back side of the lens 1601. The number of photoelectric conversion devices 1602 can be one or more. Various types of photoelectric conversion devices can be used in combination. The configuration position of the photoelectric conversion device 1602 is not limited to... Figure 39A The location shown.

[0267] The glasses 1600 also include a control device 1603. The control device 1603 serves as a power source for supplying power to the photoelectric conversion device 1602 and the aforementioned display device. The control device 1603 controls the operation of the photoelectric conversion device 1602 and the display device. In the lens 1601, an optical system is formed for converging light onto the photoelectric conversion device 1602.

[0268] Figure 22B A pair of glasses 1610 (smart glasses) according to an application example is shown. The glasses 1610 includes a control device 1612, which is equipped with a photoelectric conversion device equivalent to the photoelectric conversion device 1602 and a display device. An optical system is formed in the lens 1611 for projecting light emitted from the photoelectric conversion device and display device in the control device 1612 and projecting an image onto the lens 1611. The control device 1612 serves as a power source for supplying power to the photoelectric conversion device and display device and controls the operation of the photoelectric conversion device and display device. The control device may include a gaze detection unit for detecting the wearer's gaze. Infrared light can be used for gaze detection. An infrared emitting unit emits infrared light onto the eyeball of the user viewing the displayed image. A camera unit including a light receiving element detects the reflected light of the emitted infrared light reflected from the eyeball. An image of the eyeball is thus obtained. By including a light reduction unit in the plan view for reducing the light from the infrared emitting unit to the display unit, image quality degradation is suppressed.

[0269] This method detects a user's gaze toward a displayed image from an image of the eye captured using infrared light. Any known method can be applied to gaze detection using an image captured of the eye. As an example, a gaze detection method based on the Purkinje image, obtained through the reflection of light incident on the cornea, can be used.

[0270] More specifically, gaze detection processing is performed based on central pupillary corneal reflection. The user's gaze is detected by calculating an eye vector representing the direction (rotation angle) of the eyeball using the central pupillary corneal reflection based on the pupil image included in the captured image of the eyeball and the Pulcim spot.

[0271] The display device of this exemplary embodiment includes a photoelectric conversion device having a light receiving element, and the display image of the display device can be controlled based on the user's gaze information from the photoelectric conversion device.

[0272] Specifically, in the display device, a first viewing area and a second viewing area other than the first viewing area are determined based on gaze information. The first and second viewing areas can be determined by the control device of the display device, or they can be received from an external control device. Within the display area of ​​the display device, the display resolution of the first viewing area can be controlled to be higher than that of the second viewing area. In other words, the resolution of the second viewing area can be lower than that of the first viewing area.

[0273] The display area includes a first display area and a second display area different from the first display area. A high-priority area can be determined from the first and second display areas based on gaze information. The first and second display areas can be determined by the control device of the display device, or they can be received from an external control device. The resolution of the high-priority area can be controlled to be higher than the resolution of other areas. In other words, the resolution of the relatively low-priority area can be set to a low resolution.

[0274] Artificial intelligence (AI) can be used to determine the primary visual field and areas of high priority. AI can be a model configured to estimate the angle of gaze and the distance to a target present at the end of the gaze from an image of the eye, using teaching data including an image of the eye and the actual direction of the eye's gaze in the image. The AI ​​program can be included in a display device, a photoelectric conversion device, or an external device. In the case where the external device includes the AI ​​program, the AI ​​program is sent to the display device via communication.

[0275] In the case of display control based on gaze detection, the present invention can be expected to be applied to smart mirrors that also include a photoelectric conversion device for capturing images of the outside world. The smart mirror can display external information acquired through image capture in real time.

[0276] The exemplary embodiments described above may be appropriately modified without departing from the technical concept. The exemplary embodiments of the present invention also include examples of adding portions of a particular exemplary embodiment to other exemplary embodiments and examples of replacing portions of a particular exemplary embodiment with portions of other exemplary embodiments.

[0277] According to this exemplary embodiment, the photoelectric conversion device can provide a photoelectric conversion device capable of miniaturizing the pixel size.

[0278] While the invention has been described with reference to exemplary embodiments, it should be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims should be given the broadest understanding to include all such modifications and equivalent structures and functions.

Claims

1. An optical-to-electrical conversion apparatus comprising: a semiconductor layer having a first face and a second face opposite to the first face; and a plurality of avalanche photodiodes configured on the semiconductor layer and including a first avalanche photodiode and a second avalanche photodiode; wherein each of the plurality of avalanche photodiodes includes an avalanche multiplication unit formed by a first semiconductor region of a first conductivity type in which carriers of the same conductivity type as a signal charge are regarded as majority carriers, and a second semiconductor region of a second conductivity type different from the first conductivity type, wherein the first semiconductor region is configured at a first depth, and the second semiconductor region is configured at a second depth deeper than the first depth with respect to the first face, wherein a third semiconductor region of the second conductivity type is configured between the first avalanche photodiode and the second avalanche photodiode, wherein a fourth semiconductor region is a semiconductor region of the second conductivity type and in which an impurity concentration is lower than an impurity concentration of the third semiconductor region of the second conductivity type, or is a semiconductor region of the first conductivity type, and is configured between the first avalanche photodiode and the second avalanche photodiode at a position shallower than the third semiconductor region with respect to the first face, wherein the first semiconductor region includes a top face at a position closer to the first face of the semiconductor layer and a bottom face at a position farther from the first face of the semiconductor layer, wherein the third semiconductor region includes a top face at a position closer to the first face of the semiconductor layer and a bottom face at a position farther from the first face of the semiconductor layer, wherein the top face of the third semiconductor region is deeper than the bottom face of the first semiconductor region with respect to the first face, and wherein the fourth semiconductor region is configured between the top face of the third semiconductor region and the first face.

2. The optical-to-electrical conversion apparatus according to claim 1, further comprising an isolation region having a trench structure configured between the first avalanche photodiode and the second avalanche photodiode, the third semiconductor region and the fourth semiconductor region are configured at a side wall portion of the isolation region. wherein A depth of a boundary portion between the third semiconductor region and the fourth semiconductor region is shallower than a depth of the second semiconductor region with respect to the first face.

3. The photoelectric conversion device according to claim 1, wherein 4. The optical-to-electrical conversion apparatus according to claim 1, the fourth semiconductor region is a semiconductor region of the second conductivity type, and wherein wherein an impurity concentration of the fourth semiconductor region is lower than an impurity concentration of the third semiconductor region of the second conductivity type. the fourth semiconductor region is a semiconductor region of the first conductivity type.

5. The photoelectric conversion device according to claim 1, wherein a width of the fourth semiconductor region is narrower than a width of the third semiconductor region.

6. The photoelectric conversion device according to claim 1, wherein the isolation region penetrates the semiconductor layer from a light incident face of the semiconductor layer to a face opposite to the light incident face.

7. The photoelectric conversion device according to claim 2, wherein 8. The optical-to-electrical conversion apparatus according to claim 2, ​ wherein, the second surface is a light incident surface, and wherein the isolation region is formed from the first surface of the semiconductor layer.

9. The photoelectric conversion apparatus according to claim 2, wherein, the second surface is a light incident surface, and wherein the isolation region is formed from the second surface of the semiconductor layer.

10. The photoelectric conversion apparatus according to claim 2, wherein the plurality of avalanche photodiodes includes a third avalanche photodiode, wherein the first avalanche photodiode and the second avalanche photodiode are adjacently arranged in a first direction, wherein the second avalanche photodiode and the third avalanche photodiode are adjacently arranged in a second direction orthogonal to the first direction, and wherein a distance between a first semiconductor region of the first avalanche photodiode and a first semiconductor region of the third avalanche photodiode is longer than a distance between the first semiconductor region of the first avalanche photodiode and a first semiconductor region of the second avalanche photodiode.

11. The photoelectric conversion device according to claim 10, wherein between the first avalanche photodiode and the third avalanche photodiode in a third direction, a semiconductor region of the second conductivity type is arranged, and the isolation region is not arranged.

12. The photoelectric conversion device according to claim 10, wherein between the first avalanche photodiode and the third avalanche photodiode in a third direction, the isolation region is arranged.

13. The photoelectric conversion device according to claim 12, wherein a length of the isolation region in a depth direction of a cross section of the first avalanche photodiode and the third avalanche photodiode is different from a length of the isolation region in a depth direction of a cross section of the first avalanche photodiode and the second avalanche photodiode.

14. The photoelectric conversion device according to claim 10, wherein in a third direction in which the first avalanche photodiode and the third avalanche photodiode are arranged, a contact plug is arranged between the first avalanche photodiode and the third avalanche photodiode, the contact plug being configured to supply an electric potential to the first avalanche photodiode.

15. The photoelectric conversion device according to claim 8, wherein an electric potential is supplied to each of the plurality of avalanche photodiodes from a light incident surface side of the semiconductor layer.

16. The photoelectric conversion device according to claim 2, wherein at least any one of a metal material, an insulating material, and air is arranged inside the trench structure.

17. The photoelectric conversion apparatus according to claim 1, wherein each of the plurality of avalanche photodiodes includes a fifth semiconductor region of the second conductivity type arranged at the second depth, and wherein a magnitude of an electric potential of a carrier that is the same as the signal charge is lower in the second semiconductor region than in the fifth semiconductor region.

18. The photoelectric conversion device according to claim 1, wherein a depth of a boundary portion between the third semiconductor region and the fourth semiconductor region is shallower than a top surface of the second semiconductor region, or is the same as a depth at which the second semiconductor region is provided.

19. A photoelectric conversion apparatus comprising: a semiconductor layer including a plurality of photoelectric conversion elements, and the semiconductor layer having a first surface and a second surface, the second surface being a surface on which light is incident, and being opposite to the first surface, wherein each of the plurality of photoelectric conversion elements includes an avalanche photodiode, wherein the avalanche photodiode includes a first semiconductor region of a first conductivity type in which a charge of the same polarity as a signal charge is regarded as a majority carrier, and a second semiconductor region of a second conductivity type, wherein the plurality of photoelectric conversion elements are isolated by an isolation portion including a third semiconductor region of the second conductivity type, wherein the second semiconductor region is configured to be in contact with the third semiconductor region, wherein the plurality of photoelectric conversion elements include a first photoelectric conversion element and a second photoelectric conversion element configured in a first direction, the second photoelectric conversion element being configured adjacent to the first photoelectric conversion element, and wherein the third semiconductor region is configured between the first photoelectric conversion element and the second photoelectric conversion element in a manner that an upper end of the third semiconductor region is shallower than an upper surface of the second semiconductor region and deeper than the first surface.

20. The photoelectric conversion apparatus according to claim 19, wherein, the plurality of photoelectric conversion elements include a third photoelectric conversion element configured adjacent to the second photoelectric conversion element, wherein the second photoelectric conversion element and the third photoelectric conversion element are configured in a second direction intersecting the first direction, and wherein the first photoelectric conversion element and the third photoelectric conversion element are configured in a third direction intersecting the first direction and the second direction.

21. The photoelectric conversion device according to claim 20, wherein A bottom end of the third semiconductor region is in contact with the second surface between the first photoelectric conversion element and the third photoelectric conversion element.

22. The photoelectric conversion device according to claim 20, wherein The first direction is a side direction, and the third direction is a diagonal direction.

23. The photoelectric conversion device according to claim 20, wherein A contact plug is connected to the first surface between the first photoelectric conversion element and the third photoelectric conversion element.

24. The photoelectric conversion device according to claim 23, wherein A voltage is applied to the second semiconductor region via the contact plug and the third semiconductor region.

25. The photoelectric conversion apparatus according to claim 19, wherein, a fourth semiconductor region of the first conductivity type is continuously configured between a first semiconductor region of the first photoelectric conversion element and a first semiconductor region of the second photoelectric conversion element, wherein an impurity concentration of the fourth semiconductor region is lower than an impurity concentration of the first semiconductor region, and wherein the fourth semiconductor region constitutes a part of the first surface.

26. The photoelectric conversion device according to claim 25, wherein The fourth semiconductor region includes a first portion having a first impurity concentration, and a second portion farther from the first semiconductor region than the first portion and having a lower impurity concentration than the first portion.

27. The photoelectric conversion device according to claim 20, wherein The isolation portion includes a trench structure.

28. The photoelectric conversion device according to claim 27, wherein The trench structure is configured between the first photoelectric conversion element and the second photoelectric conversion element, and not between the first photoelectric conversion element and the third photoelectric conversion element.

29. The photoelectric conversion device according to claim 27, wherein One end of the trench structure is configured at the same depth as the second semiconductor region.

30. The photoelectric conversion device according to claim 27, wherein The trench structure penetrates the semiconductor layer.

31. The photoelectric conversion device according to claim 27, wherein The trench structure penetrates the semiconductor layer between the first photoelectric conversion element and the second photoelectric conversion element, and does not penetrate the semiconductor layer between the first photoelectric conversion element and the third photoelectric conversion element.

32. The photoelectric conversion apparatus according to claim 30, wherein The trench structure includes a first portion and a second portion located closer to the second face than the first portion, and wherein between the first photoelectric conversion element and the second photoelectric conversion element, the first portion is in contact with the third semiconductor region and the second portion is in contact with the semiconductor region of the first conduction type.

33. The photoelectric conversion device of claim 32, wherein, In the trench structure, a pinning film is arranged in contact with the semiconductor region at least in the second portion.

34. The photoelectric conversion device of claim 27, wherein, An oxide film is arranged in the trench structure.

35. The photoelectric conversion apparatus according to claim 27, wherein, An oxide film, air, and metal are arranged in the trench structure at least one of, wherein at least one of the air and the metal is arranged by being sandwiched by the oxide film.

36. A photoelectric conversion system comprising: The photoelectric conversion apparatus according to any one of claims 1 to 35, and a signal processing unit configured to generate an image using a signal output by the photoelectric conversion apparatus.

37. A movable body including the photoelectric conversion apparatus according to any one of claims 1 to 35, the movable body including: a control unit configured to control movement of the movable body using a signal output by the photoelectric conversion apparatus.

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