Semiconductor element, semiconductor device

Abstract

An object of the present invention is to provide a semiconductor element and a semiconductor device capable of increasing the ratio of Cgc / Cge. It is characterized by having: an emitter electrode formed on a semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and a two-layer dummy active trench, which has an upper-layer dummy portion not connected to the gate electrode in the upper layer and a lower-layer active portion connected to the gate electrode and covered with an insulating film inside the trench of the semiconductor substrate, and the lengthwise length of the lower-layer active portion is larger than the width of the lower-layer active portion.

Description

Technical Field

[0001] The present invention relates to semiconductor elements and semiconductor devices. Background Art

[0002] The following is disclosed in Patent Document 1: Inside a trench, a gate conductive portion connected to a gate potential is provided in an upper layer, and a gate separation portion connected to an emitter potential is provided in a lower layer. Patent Document 1 describes the following: the turn-on di / dt becomes low, and when compared at the same turn-on di / dt, the turn-on loss can be reduced.

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2017-147431

[0004] Sometimes, the emitter of a p-side semiconductor element is connected to the collector of an n-side semiconductor element, the collector of the p-side semiconductor element is connected to the high potential side (p-side) of a power supply, and the emitter of the n-side semiconductor element is connected to the low potential side (n-side) of the power supply. A load is connected to the connection point between the p-side semiconductor element and the n-side semiconductor element. A freewheeling diode is connected to each of the p-side semiconductor element and the n-side semiconductor element. The freewheeling diode connected in anti-parallel with the p-side semiconductor element is called a p-side diode, and the freewheeling diode connected in anti-parallel with the n-side semiconductor element is called an n-side diode.

[0005] In a state where a freewheeling current flows through the n-side diode, if the p-side semiconductor element is turned on, a recovery current flows through the n-side diode. For example, the recovery dV / dt of the n-side diode varies according to the collector current of the p-side semiconductor element. Specifically, the recovery dV / dt of the n-side diode during turn-on loss at low current of the p-side IGBT is larger than the recovery dV / dt at the rated current of the p-side IGBT. Here, the "low current side" means that the collector current of the p-side semiconductor element is small, and the "rated current side" means that the collector current of the p-side semiconductor element is large. The recovery dV / dt of the n-side diode is large when the collector current of the p-side semiconductor element is small, while the recovery dV / dt of the n-side diode is small when the collector current of the p-side semiconductor element is large.

[0006] Thus, if the recovery dV / dt of a diode has a current dependence, the following problem occurs. That is, sometimes the gate resistance of a semiconductor element is set so that a large recovery dV / dt becomes a specified value. Therefore, for example, when the gate resistance is determined so that the recovery dV / dt on the low current side is 20 kV / μs, the dV / dt on the rated current side (for evaluating the turn-on loss) is about 10 kV / μs. As a result, the on-off time of the semiconductor element becomes long, and the turn-on loss (turn-on loss) during turn-on increases. That is, if the recovery dV / dt of a diode has a current dependence, the turn-on loss increases.

[0007] The inventors of the present application have found that in order to suppress the situation where the recovery dV / dt of the freewheeling diode depends on the collector current of the semiconductor element, it is effective to increase the value (Cgc / Cge) obtained by dividing the gate electrode-collector electrode capacitance (Cgc) of the semiconductor element by the gate electrode-emitter electrode capacitance (Cge). More specifically, the increase in the recovery dV / dt at low current can be suppressed by increasing the Cgc of the semiconductor element. In addition, the recovery dV / dt at high current (rated current) can be increased by reducing the Cge of the semiconductor element. The on-off time can be shortened and the conduction loss can be reduced by increasing the value of Cgc / Cge.

[0008] The prior art is a two-layer gate structure in which the trench internal polysilicon is divided into two layers up and down. Specifically, it has a structure composed of a lower active part connected to the gate electrode and an upper dummy part connected to the emitter electrode in the lower layer. Therefore, Cgc is reduced and the ratio of Cgc / Cge is reduced. Therefore, when the gate resistance of the semiconductor element is set so that a large recovery dV / dt becomes a specified value, there is a problem of increased conduction loss. Summary of the Invention

[0009] The present invention is proposed to solve the above-mentioned problems, and its purpose is to provide a semiconductor element and a semiconductor device capable of increasing the ratio of Cgc / Cge, suppressing the situation where the recovery dV / dt of the freewheeling diode depends on the collector current of the semiconductor element, and reducing the conduction loss.

[0010] The semiconductor element according to the present invention is characterized in that it has: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and a two-layer dummy active trench, which has an upper dummy part not connected to the gate electrode in the upper layer and a lower active part connected to the gate electrode and covered with an insulating film in the lower layer inside the trench of the semiconductor substrate, and the length in the length direction of the lower active part is larger than the width of the lower active part.

[0011] Other features of the present invention will be clarified below.

[0012] Effects of the Invention

[0013] According to the present invention, by providing a trench having a dummy part in the upper layer and an active part in the lower layer, the conduction loss can be reduced. Description of the Drawings

[0014] Figure 1 is a cross-sectional view of the semiconductor element related to Embodiment 1.

[0015] Figure 2 is a top view of the semiconductor element.

[0016] Figure 3 is a cross-sectional view of the semiconductor element related to other examples.

[0017] Figure 4 is a top view of the semiconductor element.

[0018] Figure 5 is a cross-sectional view of the semiconductor element related to other examples.

[0019] Figure 6 is a cross-sectional view of the semiconductor element related to other examples.

[0020] Figure 7 is a cross-sectional view of the semiconductor element related to other examples.

[0021] Figure 8 is a cross-sectional view of the semiconductor element related to other examples.

[0022] Figure 9 is a cross-sectional view of the semiconductor element related to other examples.

[0023] Figure 10 is a cross-sectional view of the semiconductor element related to other examples.

[0024] Figure 11 is a cross-sectional view of the semiconductor element related to Embodiment 2.

[0025] Figure 12 is a cross-sectional view of the semiconductor element related to other examples.

[0026] Figure 13 is a cross-sectional view of the semiconductor element related to other examples.

[0027] Figure 14 is a cross-sectional view of the semiconductor element related to Embodiment 3.

[0028] Figure 15 is a cross-sectional view of the semiconductor element related to other examples.

[0029] Figure 16 is a cross-sectional view of the semiconductor element related to other examples.

[0030] Figure 17 is a cross-sectional view of the semiconductor element related to other examples.

[0031] Figure 18It is a cross-sectional view of a semiconductor element involved in other examples.

[0032] Figure 19 It is a cross-sectional view of a semiconductor element involved in other examples.

[0033] Figure 20 It is a cross-sectional view of a semiconductor element involved in other examples.

[0034] Figure 21 It is a cross-sectional view of a semiconductor element involved in other examples.

[0035] Figure 22 It is a cross-sectional view of a semiconductor element involved in other examples.

[0036] Figure 23 It is a cross-sectional view of a semiconductor element involved in other examples.

[0037] Figure 24A It is a cross-sectional view of a semiconductor element involved in Embodiment 4.

[0038] Figure 24B It is a cross-sectional view of a semiconductor element involved in other examples.

[0039] Figure 24C It is a cross-sectional view of a semiconductor element involved in other examples.

[0040] Figure 24D It is a cross-sectional view of a semiconductor element involved in other examples.

[0041] Figure 25 It is a cross-sectional view of a semiconductor element involved in other examples.

[0042] Figure 26 It is a cross-sectional view of a semiconductor element involved in Embodiment 5.

[0043] Figure 27 It is a cross-sectional view of a semiconductor element involved in other examples.

[0044] Figure 28 It is a cross-sectional view of a semiconductor element involved in other examples.

[0045] Figure 29 It is a cross-sectional view of a semiconductor element involved in other examples.

[0046] Figure 30 It is a cross-sectional view of a semiconductor element involved in Embodiment 6.

[0047] Figure 31 It is a cross-sectional view of a semiconductor element involved in other examples.

[0048] Figure 32 It is a cross-sectional view of a semiconductor element involved in other examples.

[0049] Figure 33 It is a circuit diagram showing an application example of a semiconductor element.

[0050] Figure 34 It is a graph showing the relationship between the collector current and the recovery dV / dt.

[0051] Figure 35 It is a cross-sectional view of the semiconductor element according to Embodiment 7.

[0052] Figure 36 It is a cross-sectional view of the semiconductor element according to other examples.

[0053] Figure 37 It is a cross-sectional view of the semiconductor element according to Embodiment 8.

[0054] Figure 38 It is a cross-sectional view of the semiconductor element according to other examples.

[0055] Figure 39 It is a cross-sectional view of the semiconductor element according to other examples.

[0056] Figure 40 It is a graph showing the planar shape of the lower active portion.

[0057] Figure 41 It is a graph showing the planar shape of the lower active portion according to other examples.

[0058] Figure 42 It is a graph showing the planar shape of the lower active portion according to other examples.

[0059] Figure 43 It is a graph showing the planar shape of the lower active portion according to other examples.

[0060] Figure 44 It is a graph showing the planar shape of the lower active portion according to other examples. Detailed Embodiment

[0061] With reference to the accompanying drawings, semiconductor elements and semiconductor devices according to the embodiments will be described. The same or corresponding structural elements are denoted by the same reference numerals, and repeated descriptions may be omitted sometimes. In the following description, n and p represent the conductivity types of semiconductors. In the present invention, the first conductivity type is set to n-type and the second conductivity type is set to p-type for description. The conductivity types can be reversed. In addition, n- represents that the impurity concentration is lower than n, and n+ represents that the impurity concentration is higher than n. Similarly, p- represents that the impurity concentration is lower than p, and p+ represents that the impurity concentration is higher than p.

[0062] Embodiment 1.

[0063] Figure 1This is a cross-sectional view of the semiconductor element 100 according to Embodiment 1. This semiconductor element constitutes an Insulated Gate Bipolar Transistor (hereinafter abbreviated as IGBT). As Figure 1 shown, the semiconductor element 100 has an active trench A. The active trench A has a gate insulating film 8 provided along the trench 7 of the semiconductor substrate, and an active portion 29 provided in contact with the gate insulating film 8 and connected to the gate electrode 15. The gate insulating film 8 is, for example, an oxide film. The term "trench" means a hole provided in the semiconductor substrate or a structure formed in the hole.

[0064] Two layers of dummy active trenches D / A are provided in the semiconductor substrate. Inside the trench 7 of the semiconductor substrate, the two layers of dummy active trenches D / A have an upper dummy portion 13 connected to the gate electrode 15 in the upper layer and a lower active portion 14 connected to the gate electrode 15 in the lower layer. The upper dummy portion 13 and the lower active portion 14 are respectively covered by the gate insulating film 8, thereby being electrically separated. According to an example, the upper dummy portion 13 is connected to the emitter electrode 1.

[0065] Figure 2 is Figure 1 a top view of the semiconductor element 100 at the depth including the p-type base layer 5 shown by the line A-A in Figure 2 illustrates the end region 24 and the outer peripheral region 25 not shown in Figure 1 As Figure 2 shown, in a top view, the active trench A and the two layers of dummy active trenches D / A are provided in a strip shape. When viewed from above, the two layers of dummy active trenches D / A and the active trench A are formed in the cell region 23, which is the region where the base layer 5 is formed. According to other examples, the planar configuration of the two layers of dummy active trenches D / A can be a cross-shaped mesh or a dot-shaped island, rather than a straight line like a strip shape.

[0066] When the semiconductor element 100 is viewed from above, a gate pad can be provided for a part of the cell region 23. The gate pad is a pad connected to the gate electrode formed on the semiconductor substrate.

[0067] As Figure 1 shown, the n+-type source layer 4 is provided in contact with the gate insulating film 8 on both sides in the width direction of the active trench A. The p+-type contact layer 3 is provided between adjacent trenches 7. In addition, the n+-type source layer 4 and the p+-type contact layer 3 can also be configured to be alternately arranged along the extending direction of the active trench A.

[0068] As Figure 1 shown, the semiconductor element has an n-type drift layer 9. The semiconductor substrate is in Figure 1The middle is the range from the n+-type source layer 4 and the p+-type contact layer 3 to the p-type collector layer 11. In Figure 1 the upper end of the n+-type source layer 4 and the p+-type contact layer 3 on the paper surface is referred to as the first main surface of the semiconductor substrate, and the lower end of the p-type collector layer 11 on the paper surface is referred to as the second main surface of the semiconductor substrate. The first main surface of the semiconductor substrate is the main surface on the front side of the semiconductor element 100, and the second main surface of the semiconductor substrate is the main surface on the back side of the semiconductor element 100. The semiconductor element 100 has an n-type drift layer 9 between the first main surface and the second main surface opposite to the first main surface in the unit region, that is, the IGBT region.

[0069] As Figure 1 shown, in the IGBT region, an n-type carrier accumulation layer 6 with a higher concentration of n-type impurities than that of the n-type drift layer 9 is provided on the first main surface side of the n-type drift layer 9. The carrier accumulation layer 6 of the first conductivity type is provided between the base layer 5 and the drift layer 9. The n-type carrier accumulation layer 6 has a lower concentration of impurities of the first conductivity type than the source layer 4 and a higher concentration of impurities of the first conductivity type than the drift layer 9. By providing the n-type carrier accumulation layer 6, the conduction loss when current flows can be reduced. The n-type carrier accumulation layer 6 and the n-type drift layer 9 can also be collectively referred to as the drift layer. In addition, the semiconductor element 100 may not be provided with the n-type carrier accumulation layer 6, and an n-type drift layer 9 may also be provided in the region of the n-type carrier accumulation layer 6 as Figure 1 shown.

[0070] The n-type carrier accumulation layer 6 is formed by ion-implanting n-type impurities into the semiconductor substrate constituting the n-type drift layer 9 and then annealing to diffuse the implanted n-type impurities in the n-type drift layer 9, that is, the semiconductor substrate.

[0071] A p-type base layer 5 is provided on the first main surface side of the n-type carrier accumulation layer 6. The p-type base layer 5 is in contact with the gate insulating film 8 of the active trench A. An n+-type source layer 4 is provided in contact with the gate insulating film 8 of the active trench A on the first main surface side of the p-type base layer 5, and a p+-type contact layer 3 is provided in the remaining regions. The upper ends of the n+-type source layer 4 and the p+-type contact layer 3 constitute the first main surface of the semiconductor substrate. In addition, the p+-type contact layer 3 is a region with a higher concentration of p-type impurities than the p-type base layer 5, and they can be separately named when it is necessary to distinguish the p+-type contact layer 3 from the p-type base layer 5. The p+-type contact layer 3 and the p-type base layer 5 can also be collectively referred to as the p-type base layer.

[0072] In addition, the semiconductor element 100 is provided with an n-type buffer layer 10 having a higher concentration of n-type impurities than the n-type drift layer 9 on the second main surface side of the n-type drift layer 9. The n-type buffer layer 10 is provided to suppress the penetration of the depletion layer extending from the p-type base layer 5 to the second main surface side when the semiconductor element 100 is in the off state. The n-type buffer layer 10 can be formed, for example, by injecting phosphorus (P) or protons (H+), or by injecting both phosphorus (P) and protons (H+). In addition, the semiconductor element 100 can also be provided without the n-type buffer layer 10. Figure 1 The region of the n-type buffer layer 10 is also provided with an n-type drift layer 9. The n-type buffer layer 10 and the n-type drift layer 9 may also be collectively referred to as a drift layer.

[0073] The semiconductor element 100 has a p-type collector layer 11 provided on the second main surface side of the n-type buffer layer 10. That is, the p-type collector layer 11 is provided between the n-type drift layer 9 and the second main surface.

[0074] like Figure 1 As shown, a trench 7 is formed in the semiconductor element 100, which penetrates the p-type base layer 5 from the first main surface of the semiconductor substrate and reaches the n-type drift layer 9. An active portion 29 is provided in the trench 7 via a gate insulating film 8, thereby forming an active trench A. The gate insulating film 8 of the active trench A is in contact with the p-type base layer 5 and the n+ type source layer 4. When a gate driving voltage is applied to the active portion 29, a channel is formed in the p-type base layer 5 in contact with the gate insulating film 8 of the active trench A.

[0075] The other trenches 7 are provided to provide two layers of dummy active trenches D / A. The two layers of dummy active trenches D / A are formed by providing an upper dummy portion 13 and a lower active portion 14 via a gate insulating film 8. The lower active portion 14 is opposite to the n-type drift layer 9 via the gate insulating film 8. The upper dummy portion 13 is opposite to the p-type base layer 5 via the gate insulating film 8. Figure 1 As shown, the interlayer insulating film 2 is provided on the active portion 29 of the active trench A. The emitter electrode 1 is formed on a region of the first main surface of the semiconductor substrate where the interlayer insulating film 2 is not provided and on the interlayer insulating film 2 .

[0076] According to an example, Figure 1As shown, the upper end of the lower active portion 14 is located further below than the lower end of the base layer 5. That is, the upper end of the lower active portion 14 does not reach the base layer 5. When the lower active portion 14 is located within the base layer 5, during conduction, the potential of the base layer 5 changes due to the holes injected into the p-type base layer 5, and a displacement current flows from the base layer 5 into the lower active portion 14, resulting in a deterioration of the dV / dt controllability. Therefore, as shown in the above example, by ensuring that the upper end of the lower active portion 14 does not reach the base layer 5, the inflow of the displacement current into the lower active portion 14 can be suppressed.

[0077] According to another example, as Figure 1 shown, the length of the lower active portion 14 in the longitudinal direction at the carrier accumulation layer 6 is shorter than the length of the lower active portion 14 in the longitudinal direction at the drift layer 9. That is, the length of the lower active portion 14 in the drift layer 9 is longer than the length of the lower active portion 14 in the carrier accumulation layer 6. If the carrier accumulation layer 6 is made too deep, the electric field below the carrier accumulation layer 6 becomes stronger and the breakdown voltage decreases. Therefore, within the carrier accumulation layer 6, there is a limit to increasing the length of the lower active portion 14. Therefore, by making the length of the lower active portion 14 in the drift layer 9 longer, the adverse effect of the breakdown voltage decrease is reduced, and Cgc can be increased.

[0078] As Figure 1 shown, the emitter electrode 1 makes an ohmic contact with the n+-type source layer 4, the p+-type contact layer 3, and the upper dummy portion 13, and is electrically connected to the n+-type source layer 4, the p+-type contact layer 3, and the upper dummy portion 13.

[0079] In Figure 1 , an interlayer insulating film 2 is provided above the upper dummy portion 13, but the interlayer insulating film 2 may not be provided and the emitter electrode 1 may be directly formed above the upper dummy portion 13. As Figure 1 shown, when the interlayer insulating film 2 is formed above the upper dummy portion 13 of the two-layer dummy active trench D / A, it is only necessary to electrically connect the emitter electrode 1 to the upper dummy portion 13 in other cross-sections.

[0080] According to one example, the emitter electrode 1 can be formed of an aluminum alloy such as an aluminum-silicon alloy (Al-Si alloy). According to another example, the emitter electrode 1 can be an electrode composed of a multi-layer metal film in which a coating film is formed by electroless plating or electroplating on an electrode formed of an aluminum alloy. The coating film formed by electroless plating or electroplating can be, for example, a nickel (Ni) coating film. In addition, when there is a minute area such as between adjacent interlayer insulating films 2 that cannot be well filled by the emitter electrode 1, tungsten with better filling properties than the emitter electrode 1 can also be disposed in the minute area, and the emitter electrode 1 can be provided above the tungsten.

[0081] A barrier metal may also be provided between the interlayer insulating film 2 and the emitter electrode 1. The barrier metal may be, for example, a conductor containing titanium (Ti), such as titanium nitride, or TiSi obtained by alloying titanium and silicon (Si). In addition, the barrier metal may be provided only on an n-type semiconductor layer such as the n+-type source layer 4. The barrier metal and the emitter electrode 1 may be collectively referred to as the emitter electrode.

[0082] A collector electrode 12 is provided on the second main surface side of the p-type collector layer 11. The collector electrode 12 is formed under the semiconductor substrate. Similar to the emitter electrode 1, the collector electrode 12 may be made of an aluminum alloy, or an aluminum alloy and a coating film. In addition, the collector electrode 12 may have a structure different from that of the emitter electrode 1. The collector electrode 12 makes an ohmic contact with the p-type collector layer 11 and is electrically connected to the p-type collector layer 11.

[0083] (Manufacturing method)

[0084] Next, an example of a manufacturing method of the semiconductor device according to Embodiment 1 will be described.

[0085] First, a semiconductor substrate constituting the n-type drift layer 9 is prepared. The semiconductor substrate may be, for example, a so-called FZ wafer manufactured by the FZ (Floating Zone) method or a so-called MCZ wafer manufactured by the MCZ (Magnetic applied CZochralki) method, and may be an n-type wafer containing an n-type impurity. The concentration of the n-type impurity contained in the semiconductor substrate is appropriately selected according to the breakdown voltage of the manufactured semiconductor device. For example, for a semiconductor device with a breakdown voltage of 1200V, the concentration of the n-type impurity is adjusted so that the resistivity of the n-type drift layer 9 constituting the semiconductor substrate is about 40 to 120 Ω·cm. In the process of preparing the semiconductor substrate, the entire semiconductor substrate becomes the n-type drift layer 9, but p-type or n-type impurity ions are implanted from the first main surface side or the second main surface side of such a semiconductor substrate, and then the impurity ions are diffused in the semiconductor substrate by heat treatment or the like, thereby forming a p-type or n-type semiconductor layer, and manufacturing the semiconductor device 100.

[0086] In addition, as Figure 2As shown, there is a region that becomes the terminal region 24 around the cell region 23. Hereinafter, a manufacturing method of the structure of the cell region 23 of the semiconductor element 100 will be mainly described, and the terminal region 24 of the semiconductor element 100 can be fabricated by a known manufacturing method. For example, when forming an FLR having a p-type terminal well layer 22 as a breakdown voltage holding structure in the terminal region 24, the p-type impurity ions can be implanted to form the FLR before processing the cell region 23 of the semiconductor element 100, or the p-type impurity ions can be implanted simultaneously when the p-type impurity is ion-implanted into the cell region 23 of the semiconductor element 100 to form the FLR.

[0087] Next, n-type impurities such as phosphorus (P) are implanted from the first main surface side of the semiconductor substrate to form an n-type carrier accumulation layer 6. In addition, p-type impurities such as boron (B) are implanted from the first main surface side of the semiconductor substrate to form a p-type base layer 5. The n-type carrier accumulation layer 6 and the p-type base layer 5 are formed by the following method: after implanting impurity ions into the semiconductor substrate, the impurity ions are diffused by heat treatment. Since the n-type impurities and the p-type impurities are ion-implanted after performing a mask treatment on the first main surface of the semiconductor substrate, they are selectively formed on the first main surface side of the semiconductor substrate. The n-type carrier accumulation layer 6 and the p-type base layer 5 are formed in the cell region 23 and are connected to the p-type terminal well layer 22 in the terminal region 24. In addition, the mask treatment means coating a resist layer on the semiconductor substrate, forming an opening in a specified region of the resist layer using photolithography technology, and forming a mask on the semiconductor substrate in order to perform ion implantation or etching on a specified region of the semiconductor substrate through the opening.

[0088] Next, an n+-type source layer 4 is selectively formed by implanting n-type impurities on the first main surface side of the p-type base layer 5 in the cell region 23 through a mask treatment. The implanted n-type impurities can be, for example, arsenic (As) or phosphorus (P).

[0089] Next, a trench 7 is formed that penetrates the p-type base layer 5 and the carrier accumulation layer 6 from the first main surface side of the semiconductor substrate and reaches the n-type drift layer 9. In the cell region 23, the side wall of the trench 7 that penetrates the n+-type source layer 4 constitutes a part of the n+-type source layer 4. The trench 7 can be formed by the following method: after stacking an oxide film such as SiO2 on the semiconductor substrate, an opening is formed in the oxide film at the portion where the trench 7 is to be formed through a mask treatment, and the semiconductor substrate is etched using the oxide film with the opening as a mask.

[0090] Next, for example, the semiconductor substrate is heated in an oxygen-containing atmosphere, and a gate insulating film 8 is formed on the inner wall of the trench 7 and the first main surface of the semiconductor substrate. The gate insulating film 8 formed on the first main surface of the semiconductor substrate is removed in a subsequent process.

[0091] Next, polysilicon doped with n-type or p-type impurities is stacked in the trench 7 having the gate insulating film 8 formed on its inner wall by CVD (chemical vapor deposition) or the like.

[0092] Next, a mask that opens the two-layer dummy active trench D / A part is formed by mask processing, and the polysilicon in the two-layer dummy active trench D / A is etched to a desired depth to form the lower active part 14.

[0093] Next, for example, after the semiconductor substrate is heated in an oxygen-containing atmosphere and a gate insulating film 8 is formed on the inner wall of the two-layer dummy active trench D / A and the upper part of the lower active part 14, polysilicon doped with n-type or p-type impurities is stacked by CVD or the like to form the upper dummy part 13.

[0094] Next, after the interlayer insulating film 2 is formed on the active trench A and the two-layer dummy active trench D / A in the cell region 23, the gate insulating film formed on the first main surface of the semiconductor substrate is removed. The interlayer insulating film 2 can be, for example, SiO2. And contact holes are formed in the stacked interlayer insulating film 2 by mask processing. The contact holes are formed above the n+-type source layer 4 and above the p+-type contact layer 3.

[0095] Next, for example, an aluminum-silicon alloy (Al-Si-based alloy) can be stacked by PVD such as sputtering or evaporation to form the emitter electrode 1 on the first main surface of the semiconductor substrate and on the interlayer insulating film 2. Alternatively, a nickel alloy (Ni alloy) can be further formed as the emitter electrode 1 by electroless plating or electroplating on the formed aluminum-silicon alloy. If the emitter electrode 1 is formed by plating, a thick metal film can be easily formed as the emitter electrode 1, and thus, the heat capacity of the emitter electrode 1 can be increased to improve heat resistance. In addition, when a nickel alloy is further formed by plating after the emitter electrode 1 made of an aluminum-silicon alloy is formed by PVD, the plating process for forming the nickel alloy can also be performed after the processing on the second main surface side of the semiconductor substrate.

[0096] Next, the second main surface side of the semiconductor substrate is ground to thin the semiconductor substrate to a designed specified thickness. The thickness of the ground semiconductor substrate can be, for example, 80 μm to 200 μm.

[0097] Next, an n-type buffer layer 10 is formed by implanting n-type impurities from the second main surface side of the semiconductor substrate. Then, a p-type collector layer 11 is formed by implanting p-type impurities from the second main surface side of the semiconductor substrate. The n-type buffer layer 10 can be formed, for example, by implanting phosphorus (P) ions. In addition, it can be formed by implanting protons (H+). And it can be formed by implanting both protons and phosphorus. Protons can be implanted from the second main surface of the semiconductor substrate to a deep position with a relatively low acceleration energy. In addition, the implantation depth of protons can be easily changed by changing the acceleration energy. Therefore, when the n-type buffer layer 10 is formed by protons, if multiple implantations are performed while changing the acceleration energy, a wider n-type buffer layer 10 can be formed in the thickness direction of the semiconductor substrate compared to when formed by phosphorus. In addition, phosphorus can increase the activation rate as an n-type impurity compared to protons. Therefore, by forming the n-type buffer layer 10 with phosphorus, even in a thinned semiconductor substrate, depletion layer punch-through can be more reliably suppressed. In order to further thin the semiconductor substrate, it is preferable to form the n-type buffer layer 10 by implanting both protons and phosphorus. At this time, protons are implanted to a deeper position from the second main surface compared to phosphorus.

[0098] The p-type collector layer 11 can be formed, for example, by implanting boron (B). After ion implantation from the second main surface side of the semiconductor substrate, the second main surface is irradiated with a laser for laser annealing to activate the implanted boron and form the p-type collector layer 11. At this time, the phosphorus for the n-type buffer layer 10 implanted from the second main surface of the semiconductor substrate to a shallower position is also simultaneously activated. On the other hand, protons are activated at a relatively low annealing temperature of 380°C to 420°C. Therefore, after implanting protons, attention needs to be paid to the fact that the entire semiconductor substrate does not become a temperature higher than 380°C to 420°C except for the process for activating protons. Laser annealing can make only the vicinity of the second main surface of the semiconductor substrate become high temperature. Therefore, even after implanting protons, it can be used for the activation of n-type or p-type impurities.

[0099] Next, a collector electrode 12 is formed on the second main surface of the semiconductor substrate. The collector electrode 12 can be formed by stacking an aluminum-silicon alloy (Al-Si alloy) or titanium (Ti) etc. by PVD such as sputtering or evaporation, or can be formed by laminating multiple metals such as an aluminum-silicon alloy, titanium, nickel, or gold. And a metal film can also be further formed as the collector electrode 12 by electroless plating or electroplating on the metal film formed by PVD.

[0100] The semiconductor element 100 is fabricated through the above-mentioned processes. Since multiple semiconductor elements 100 are fabricated in a matrix on one n-type wafer, the wafer is cut into individual semiconductor elements 100 by using laser cutting or dicing to complete the semiconductor element 100.

[0101] (Action)

[0102] The inventors of the present application have found that in order to suppress the situation where the recovery dV / dt of the freewheeling diode depends on the collector current of the semiconductor element, it is effective to increase the value (Cgc / Cge) obtained by dividing the gate electrode-collector electrode capacitance (Cgc) of the semiconductor element by the gate electrode-emitter electrode capacitance (Cge). More specifically, by increasing Cgc of the semiconductor element, it is possible to suppress the increase in the recovery dV / dt at low currents. In addition, by reducing Cge of the semiconductor element, it is possible to increase the recovery dV / dt at high currents (rated current). By increasing the value of Cgc / Cge, it is possible to shorten the on-off time and reduce the conduction loss. The semiconductor element according to Embodiment 1 is manufactured based on this finding.

[0103] First, the generation sites of Cgc and Cge in the active trench A will be briefly described. The generation site of Cgc is the region where the active trench A contacts the p-type base layer 5 connected to the emitter electrode 1. The generation site of Cge is the region where the active trench A contacts the n-type drift layer 9 and the n-type carrier accumulation layer 6.

[0104] That is, in order to increase only Cgc without increasing Cge, it is only necessary to increase the region where the active trench A contacts the n-type drift layer 9 without increasing the region where the active trench A contacts the p-type base layer 5 connected to the emitter electrode 1.

[0105] Next, the case of the two-layer dummy active trench D / A will be described. The upper dummy part 13 of the two-layer dummy active trench D / A, which is the region in contact with the p-type base layer 5, is connected to the emitter electrode 1, so Cge is not generated. The lower active part 14 of the two-layer dummy active trench D / A, which is the region in contact with the n-type drift layer 9, is connected to the gate electrode 15, so Cgc is generated. For example, making the length in the length direction of the lower active part 14 longer than the length in the length direction of the upper dummy part 13 helps to increase Cgc.

[0106] In Embodiment 1, the two-layer dummy active trench D / A is adopted. Therefore, compared with a semiconductor element without the two-layer dummy active trench D / A, Cgc can be increased. Therefore, the ratio of Cgc / Cge can be increased. Therefore, the situation where the recovery dV / dt of the freewheeling diode depends on the collector current of the semiconductor element can be suppressed.

[0107] (Modification 1)

[0108] In Embodiment 1, the two-layer dummy active trench D / A is formed in the cell region 23, but the two-layer dummy active trench D / A may also be formed outside the cell region 23. Figure 3It is a cross-sectional view of the semiconductor element according to the modified example. It is also possible to form the two-layer dummy active trench D / A shown in Figure 3 outside the cell region 23. Figure 4 It is a top view showing a layout example of the two-layer dummy active trench D / A. In Figure 4 it is illustrated that the two-layer dummy active trench D / A is formed in the end region 24 and the outer peripheral region 25. The end region 24 is a region that surrounds the cell region 23 when viewed from above. The outer peripheral region 25 is a region that surrounds the end region 24. The two-layer dummy active trench D / A may also be formed in the gate pad region in the cell region 23. Figure 4 The two-layer dummy active trench D / A in

[0109] is square, but it may be formed in a strip shape with a linear pattern, a mesh shape with a cross pattern, or an island shape with a dot pattern.

[0110] (Modified Example 2)

[0111] From the previous description, it is clear that in order to increase Cgc, it is effective to deepen the depth of the trench 7 and increase the regions of the active trench A and the two-layer dummy active trench D / A that are in contact with the n-type drift layer 9.

[0112] Figure 5 It is a cross-sectional view of the semiconductor element according to the modified example 2. The length La of the lower active portion 14 in the trench depth direction is longer than the length Ld of the upper dummy portion 13 in the same direction. That is, La > Ld. And, according to an example, the lengthwise length La of the lower active portion 14 is larger than the lateral width Wa of the lower active portion 14, whereby La > Wa is achieved.

[0113] By making the length La of the lower active portion 14 longer than the length Ld of the upper dummy portion 13, it is possible to particularly increase Cgc generated at the lower active portion 14. In addition, by making the length La of the lower active portion 14 larger than the lateral width Wa of the lower active portion 14, it is possible to efficiently further increase Cgc. This is because the surface of the trench 7 bottom in contact with the drift layer 9 is one, whereas the surfaces of the trench 7 sidewalls in contact with the drift layer 9 are two, and thus an increase in the area of this sidewall causes Cgc to increase efficiently. That is, if the aspect ratio of the lower active portion 14 is increased, it is possible to efficiently increase Cgc.

[0114] By increasing the length of the lower active portion 14, the position of the lower end of the lower active portion 14 can be made far from the n-type carrier accumulation layer 6 where electric field concentration is likely to occur or the p-type base layer 5 where punch-through is likely to occur. Thereby, the effect of the field plate for maintaining breakdown voltage can be improved.

[0115] According to another example, as Figure 6 shown, the length La of the lower active portion 14 can also be made shorter than the length Lb of the upper dummy portion. In this case, La < Ld. By shortening the length La of the lower active portion 14, Cgc generated in the lower active portion 14 is reduced, but the etching time for forming the trench 7 can be shortened, and the process cost can be reduced.

[0116] (Modification Example 3)

[0117] To increase the ratio of Cgc / Cge, it is also effective to reduce Cge. It is clear from the previous description that to reduce Cge, it is effective to reduce the region of the active trench A that contacts the p-type base layer 5.

[0118] Figure 7 is a cross-sectional view of the semiconductor element related to Modification Example 3. The length La in the length direction of the lower active portion of this semiconductor element is larger than the thickness Lp of the p-type base layer 5. That is, La > Lp. By reducing the thickness Lp of the p-type base layer 5, Cge generated at the active trench A can be reduced. And by increasing the length La of the lower active portion 14, Cgc generated in the lower active portion 14 can be made larger. Therefore, the ratio of Cgc / Cge can be further increased.

[0119] (Modification Example 4)

[0120] Figure 8 、 9 is a cross-sectional view of the semiconductor element related to Modification Example 4. The upper end of the lower active portion 14 is located within the base layer 5. In Figure 8 the example, the upper end position of the lower active portion 14 and the lower end position of the base layer 5 are at the same height. In Figure 9 the example, the upper end position of the lower active portion 14 is higher than the lower end position of the base layer 5.

[0121] As Figure 1 shown, when the upper end position of the lower active portion 14 is lower than the lower end position of the p-type base layer 5, a region where the lower active portion 14 does not contact the n-type drift layer 9 or the n-type carrier accumulation layer 6 is generated above the lower active portion 14, and Cgc is not generated in this region. In contrast, as Figure 8 、 9As shown, if a region where the lower active portion 14 is not in contact with the n-type drift layer 9 or the n-type carrier accumulation layer 6 is prevented from being formed above the lower active portion 14, Cgc can be increased.

[0122] (Modification Example 5)

[0123] In Figure 1 the upper end position of the lower active portion 14 is lower than the lower end of the p-type base layer 5, but the upper end position of the lower active portion 14 can also be made lower. For example, the upper end position of the lower active portion 14 can be made lower than the concentration peak position of the n-type carrier accumulation layer 6. According to other examples, as Figure 10 shown, the upper end position of the lower active portion 14 can be made lower than the lower end of the n-type carrier accumulation layer 6.

[0124] When holes injected from the back surface during conduction change the potential of the p-type base layer 5, an oscillation of the gate potential is generated due to the displacement current flowing from the p-type base layer 5 to the lower active portion 14, and the controllability of dV / dt deteriorates. This phenomenon becomes particularly significant when the p-type base layer 5 is floating and when the distance between the lower active portion 14 and the p-type base layer 5 is short. Therefore, as described above, by moving the lower active portion 14 away from the p-type base layer 5, hazards such as gate oscillation can be suppressed.

[0125] Regarding the semiconductor element and semiconductor device according to the following embodiments, the differences from Embodiment 1 will be mainly described.

[0126] Embodiment 2.

[0127] The semiconductor element according to Embodiment 2 is a semiconductor element in which the material of the upper dummy portion of the two-layer dummy active D / A is changed from polysilicon to another material. Figure 11 is a cross-sectional view of the semiconductor element according to Embodiment 2. This semiconductor element has an oxide 16 as the upper dummy portion. According to one example, the oxide 16 can be made of the same material as the interlayer insulating film 2. The trench having the oxide 16 and the lower active portion 14 is called a two-layer oxide active trench O / A.

[0128] Figure 12 is a cross-sectional view of the semiconductor element according to other examples. In Figure 12 the example, a metal 17 is used as the upper dummy portion. This metal 17 can be formed as part of the emitter electrode 1 using the same material as the emitter electrode 1. The trench having the metal 17 and the lower active portion 14 is called a two-layer metal active trench M / A.

[0129] (Manufacturing Method of Two-Layer Oxide Active Trench O / A)

[0130] First, in the same manner as in Embodiment 1, the polysilicon in the two-layer active trench is etched to a desired depth through a mask process to form the lower active portion 14. Next, an interlayer insulating film is stacked over the active trench A and over the lower active portion 14. Thereby, the oxide 16 of the two-layer oxide active trench O / A is formed.

[0131] (Method for manufacturing a two-layer metal active trench M / A)

[0132] Up to the formation of the lower active portion 14, it is the same as the manufacturing method of the two-layer oxide active trench O / A. In order to form the two-layer metal active trench M / A, by reducing the stacking amount of the above-mentioned interlayer insulating film, metal is filled therein to form the metal 17.

[0133] The manufacturing process of the two-layer oxide active trench O / A or the two-layer metal active trench M / A can omit the following processes required in the manufacturing process of the two-layer dummy active trench D / A.

[0134] · The process of forming the gate insulating film 8 on the inner wall of the two-layer dummy active trench D / A and on the upper portion of the lower active portion 14.

[0135] · The process of forming the upper dummy portion 13 by stacking polysilicon doped with n-type or p-type impurities through CVD or the like.

[0136] (Modification 1)

[0137] Figure 13 is a cross-sectional view of the semiconductor element according to Modification 1. The upper dummy portion, i.e., the metal 17, is in contact with the base layer 5. In other words, there is no gate insulating film between the metal 17 and the base layer 5. According to other examples, the Figure 1 gate insulating film between the upper dummy portion 13 and the p-type base layer 5 can also be removed to make them in contact.

[0138] In this way, the p-type base layer 5 can also be electrically connected to the emitter electrode 1 via the upper dummy portion 13 or the metal 17. In addition, the p-type base layer 5 can also be in ohmic contact or Schottky contact with the upper dummy portion 13 or the metal 17. Thereby, when in cutoff, holes are discharged from the p-type base layer 5 to the emitter electrode 1 via the upper dummy portion 13 or the metal 17, so that the amount of holes below the source layer 4 that causes latch-up breakdown can be reduced. Therefore, the latch-up breakdown tolerance is improved.

[0139] Embodiment 3.

[0140] In the present embodiment, the reduction of the coupling capacitance Cge generated between the adjacent active trench A and the upper dummy portion 13 is described. First, the active trench A and the upper dummy portion 13 are briefly described. The inventors found that in Figure 1In the case of a trench configuration where the active trench A as shown is adjacent to the upper dummy part 13 of the two-layer dummy active trench D / A, the upper dummy part 13 at the emitter potential is disposed adjacent to the active trench A at the gate potential. Therefore, Cge is generated as a coupling capacitance between the active trench A and the upper dummy part 13. In addition, this phenomenon has little effect on the region where the upper dummy part 13 faces the p-type base layer 5 electrically connected to the emitter electrode 1. However, particularly when the upper dummy part 13 faces the n-type drift layer 9 and the n-type carrier accumulation layer 6, the effect becomes greater. The semiconductor device according to Embodiment 3 is manufactured based on this finding.

[0141] Figure 14 It is a cross-sectional view of the semiconductor device according to Embodiment 3. In this example, the first structure in which two or more active trenches A are arranged side by side and the second structure in which two or more two-layer dummy active trenches D / A are arranged side by side are alternately provided. By arranging the active trenches A bundled together and arranging the two-layer dummy active trenches D / A bundled together, the density of the adjacent active trenches A and two-layer dummy active trenches D / A is reduced compared to the case where one active trench A and one two-layer dummy active trench D / A are alternately provided.

[0142] Thereby, it is possible to reduce the coupling capacitance Cge between the active trench A and the two-layer dummy active trench D / A while maintaining Cgc. As a more preferable example, the first structure in which three or more active trenches A are arranged side by side and the second structure in which three or more two-layer dummy active trenches D / A are arranged side by side can be alternately provided. Thereby, an active trench A that is not adjacent to the two-layer dummy active trench D / A is formed, so that Cge can be particularly reduced.

[0143] Figure 15 It is a cross-sectional view of the semiconductor device according to another example. In this example, the number of two-layer dummy active trenches D / A is larger than the number of active trenches A. The larger the number of two-layer dummy active trenches D / A, the higher the Cge generation ratio, and the greater the Cge reduction effect achieved by the above continuous configuration.

[0144] (Modification 1)

[0145] Figure 16 It is a cross-sectional view of the semiconductor device according to Modification 1. This semiconductor device has a dummy trench D. The dummy trench D is electrically connected to the emitter electrode 1. The adjustment of the gate capacitance can be achieved by changing the ratio of the dummy trench D in all the trenches. However, Cge is generated as a coupling capacitance between the dummy trench D and the lower active part 14.

[0146] (Modification 2)

[0147] Figure 17This is a cross-sectional view of the semiconductor device according to Modification 2. The semiconductor device has a first structure in which one or more active trenches are arranged side by side, a second structure in which two or more two-layer dummy active trenches D / A are arranged side by side, and a third structure in which one or more dummy trenches are arranged side by side. Further, the second structure is sandwiched by two third structures.

[0148] Thus, by continuously arranging the two-layer dummy active trenches D / A, it is possible to reduce Cge generated between the lower active portion 14 and the dummy trench D. Therefore, the ratio of Cgc / Cge can be increased. However, Cge is generated as a coupling capacitance between the dummy trench D and the lower active portion 14.

[0149] (Modification 3)

[0150] Figure 18 This is a cross-sectional view of the semiconductor device according to Modification 3. The semiconductor device has a first structure in which one or more active trenches A are arranged side by side, a second structure in which one or more two-layer dummy active trenches D / A are arranged side by side, and a third structure in which one or more dummy trenches are arranged side by side. Further, the second structure is sandwiched by the first structure and the third structure.

[0151] By continuously arranging the active trench A and the two-layer dummy active trenches D / A, and continuously arranging the dummy trenches D, it is possible to reduce Cge generated between the lower active portion 14 and the dummy trench D and Cge generated between the active trench A and the dummy trench D. Therefore, the ratio of Cgc / Cge can be further increased.

[0152] (Modification 4)

[0153] Figure 19 This is a cross-sectional view of the semiconductor device according to Modification 4. The upper dummy portion 13f is not connected to the emitter electrode 1 and has a floating potential. The trench having the upper dummy portion 13 and the lower active portion 14 is called a two-layer floating active trench F / A.

[0154] By providing the upper dummy portion 13f having a floating potential, it is possible to reduce Cge generated between the active trench A and the upper dummy portion 13 of the two-layer dummy active trenches D / A. Therefore, the ratio of Cgc / Cge can be further increased.

[0155] (Modification 5)

[0156] Figure 20 This is a cross-sectional view of the semiconductor device according to Modification 5. The semiconductor device has a first trench in which the upper dummy portion 13 is connected to the emitter electrode 1 and a second trench in which the upper dummy portion 13f has a floating potential as the two-layer dummy active trench. Figure 20The two-layer dummy active trench D / A is the first trench, and the two-layer floating active trench F / A is the second trench. The second trench is sandwiched between the first trench and the active trench A.

[0157] Figure 21 It is Figure 20 a semiconductor device in which the two-layer dummy active trench D / A is replaced with a dummy trench D. In this case, the two-layer floating active trench F / A is sandwiched between the dummy trench D and the active trench A.

[0158] According to Figure 20 the structure, Cge generated between the active trench A and the upper dummy part 13 of the two-layer dummy active trench D / A can be reduced. According to Figure 21 the structure, Cge generated between the active trench A and the dummy trench D can be reduced. Therefore, in either structure, the ratio of Cgc / Cge can be further increased.

[0159] (Modification Example 6)

[0160] Figure 22 It is a cross-sectional view of a semiconductor device according to Modification Example 6. For this semiconductor device, the distance between the first structure in which two or more two-layer dummy active trenches D / A are arranged in parallel and the second structure in which two or more active trenches A are arranged in parallel is larger than the distance between the two two-layer dummy active trenches D / A, and is larger than the distance between the two active trenches A. In Figure 22 it is illustrated that the interval Lpad / a between the active trench A and the two-layer dummy active trench D / A is larger than the interval Lpa between the active trench A and another active trench A, and is larger than the interval Lpd / a between the two-layer dummy active trench D / A and another two-layer dummy active trench D / A. That is, Lpad / a > Lpa, Lpd / a.

[0161] In this way, by increasing the distance between the active trench A and the two-layer dummy active trench D / A, the coupling capacitance Cge generated at the upper dummy part 13 of the active trench A and the two-layer dummy active trench D / A becomes smaller. Therefore, the ratio of Cgc / Cge can be further increased.

[0162] (Modification Example 7)

[0163] Figure 23 It is a cross-sectional view of a semiconductor device according to Modification Example 7. This semiconductor device has a first structure in which two or more active trenches A are arranged in parallel, a second structure adjacent to the first structure in which two or more two-layer dummy active trenches D / A are arranged in parallel, and a dummy trench D adjacent to the second structure. And the distance between the second structure and the dummy trench D is larger than the distance between the two active trenches A, the distance between the first structure and the second structure, or the distance between the two two-layer dummy active trenches D / A.

[0164] InFigure 23 The figure shows a case where the interval Lpd / ad between the two-layer dummy active trench D / A and the dummy trench D is larger than the interval Lpa between the active trench A and other active trenches A and the interval Lpd / a between two-layer dummy active trenches D / A and other two-layer dummy active trenches D / A. That is, Lpd / ad > Lpa, Lpd / a.

[0165] In this way, by increasing the distance between the two-layer dummy active trench D / A and the dummy trench D, the coupling capacitance Cge generated between the lower active part 14 of the two-layer dummy active trench D / A and the dummy trench D becomes smaller. Therefore, the ratio of Cgc / Cge can be further increased.

[0166] Embodiment 4.

[0167] Figure 24A It is a cross-sectional view of a semiconductor element according to Embodiment 4. Two or more two-layer dummy active trenches D / A are provided adjacent to each other. The part of the base layer 5 adjacent to the active trench A is connected to the emitter electrode 1. On the other hand, the part of the base layer 5 sandwiched between two two-layer dummy active trenches D / A is not connected to the emitter electrode 1. The part of the base layer 5 sandwiched between two two-layer dummy active trenches D / A can be at a floating potential or be electrically connected to the emitter electrode 1 via a high-resistance resistor in other cross-sections.

[0168] It is possible to Figure 24A replace at least one of the two-layer dummy active trenches D / A with a dummy trench D. In this case, the part of the base layer 5 sandwiched between two dummy trenches D or sandwiched between a dummy trench D and a two-layer dummy active trench D / A can be not connected to the emitter electrode 1 and be at a floating potential, or be electrically connected to the emitter electrode 1 via a high-resistance resistor in other cross-sections.

[0169] Figure 25 It is a cross-sectional view of a semiconductor element according to another example. The part of the base layer 5 adjacent to two active trenches A is connected to the emitter electrode 1. On the other hand, the part of the base layer 5 adjacent to the two-layer dummy active trench D / A is not connected to the emitter electrode 1. Therefore, the part of the base layer 5 sandwiched between the two-layer dummy active trench D / A and the part adjacent to both the active trench A and the two-layer dummy active trench D / A are not connected to the emitter electrode 1. The part of the base layer 5 not connected to the emitter electrode 1 can be at a floating potential or be electrically connected to the emitter electrode 1 via a high-resistance resistor in other cross-sections.

[0170] According to these structures, the ratio of the p-type base layer 5 connected to the emitter electrode 1 for hole discharge can be reduced. If holes are difficult to be discharged to the emitter electrode 1, the amount of hole accumulation in the drift layer 9 increases, and the on-voltage for promoting conductivity modulation can be reduced. Also, the displacement current from the floating p-type base layer 5 flows into the upper dummy portion 13 not connected to the gate electrode 15 and is discharged to the emitter electrode 1. Therefore, it is possible to suppress the phenomenon that the displacement current flows from the floating p-type base layer 5 through the active trench into the gate electrode and the gate potential oscillates, which is a matter of concern usually.

[0171] (Modification Example 1)

[0172] Figure 24B It is a cross-sectional view of the semiconductor element related to Modification Example 1. The portion of the base layer 5 sandwiched by two two-layer dummy active trenches D / A is connected to the emitter electrode 1.

[0173] (Modification Example 2)

[0174] Figure 24C It is a cross-sectional view of the semiconductor element related to Modification Example 2. By providing a plurality of two-layer dummy active trenches D / A, the base layer 5 is divided into a plurality of base portions. And, the plurality of base portions include a base portion 5a connected to the emitter electrode 1 and a base portion 5b not connected to the emitter electrode 1.

[0175] (Modification Example 3)

[0176] Figure 24D It is a cross-sectional view of the semiconductor element related to Modification Example 3. This semiconductor element has at least two dummy trenches D. And, the portion of the base layer 5 sandwiched by two dummy trenches D is not connected to the emitter electrode 1, and the portion of the base layer 5 sandwiched by two two-layer dummy active trenches D / A is connected to the emitter electrode 1.

[0177] In Modifications 1 to 3, at least a part of the base layer 5 sandwiched between two 2-layer dummy active trenches D / A is connected to the emitter electrode 1. When in the cut-off state, an inversion layer is formed around the lower active part 14 of the 2-layer dummy active trench D / A, which acts as a hole discharge path. By connecting the p-type base layer 5 sandwiched between the two 2-layer dummy active trenches D / A to the emitter electrode 1, holes flowing along the lower active part 14 can be discharged, thereby reducing the cut-off loss. By locally floating the p-type base layer 5, carriers can be accumulated to reduce the on-voltage, and the carriers are discharged by the grounded p-type base layer 5 to reduce the cut-off loss. Moreover, at the location where the 2-layer dummy active trench D / A exists, the effect of the hole discharge path is high. Therefore, by floating the p-type base layer 5 between the dummy trenches D to accumulate carriers, the on-voltage can be reduced, and by grounding the p-type base layer 5 between the two 2-layer dummy active trenches D / A, the cut-off loss can be reduced.

[0178] Embodiment 5.

[0179] Figure 26 It is a cross-sectional view of the semiconductor element according to Embodiment 5. This semiconductor element has two active trenches A / A and two dummy trenches D / D. In the two active trenches A / A, the active part is truncated into upper and lower two parts by the intermediate insulating film 30A. In the two dummy trenches D / D, the dummy trench is truncated into upper and lower two parts by the intermediate insulating film 30A. The intermediate insulating film 30A is, for example, an oxide film, similar to the insulating film that separates the upper dummy part 13 and the lower active part 14 of the two-layer dummy active trench D / A.

[0180] Figure 27 It is a cross-sectional view of the semiconductor element according to other examples. The part of the active part of the two active trenches A / A above the intermediate insulating film 30A is covered by the first insulating film 30a, and the part of the active part below the intermediate insulating film 30A is covered by the second insulating film 30b. And the first insulating film 30a is thicker than the second insulating film 30b.

[0181] By making the first insulating film 30a thicker than the second insulating film 30b, Cge generated at the upper active part 18 of the two active trenches A / A becomes smaller, and Cgc is generated at the lower active part 14. Therefore, the ratio of Cgc / Cge can be further increased.

[0182] (Modification 1)

[0183] Figure 28It is a cross-sectional view of the semiconductor element related to Modification Example 1. This semiconductor element has a first insulating film 30a that covers the upper part of the active part above the intermediate insulating film 30A and a second insulating film 30b that covers the lower part of the active part below the intermediate insulating film 30A. The side wall part and the bottom part of the second insulating film 30b are thicker than the first insulating film 30a. Also, this semiconductor element has a third insulating film 31a that covers the upper dummy part 13. The side wall part and the bottom part of the insulating film that covers the lower active part 14 are thicker than the third insulating film 31a.

[0184] In this way, for the two-layer active trench A / A and the two-layer dummy active trench D / A, the thickness of the gate insulating film 8 formed on the side wall and the bottom of the trench 7 of the lower active part 14 is thicker than the gate oxide film that covers the upper active part 18 or the upper dummy part 13.

[0185] According to other examples, it is also possible to make the thickness of the gate insulating film 8 on the side wall of the trench 7 of the lower active part 14 the same as or thinner than the gate insulating film 8 of the upper active part 18, increase Cgc, and make the thickness of the gate insulating film 8 at the bottom and the bottom corners of the trench 7 of the lower active part 14 thinner than the gate insulating film 8 of the upper active part 18, so as to suppress the deterioration of the gate characteristics when the electric field concentrates at the trench bottom.

[0186] By increasing the thickness of the gate insulating film 8 formed on the side wall and the bottom of the trench of the lower active part 14 in the two-layer active trench A / A, it is possible to suppress the deterioration of the gate characteristics caused by the hot carrier injection into the lower active part 14 due to the dynamic avalanche caused by the electric field concentration at the trench bottom during cutoff.

[0187] (Modification Example 2)

[0188] Figure 29 It is a cross-sectional view of the semiconductor element related to Modification Example 2. This semiconductor element has three-layer trenches. Inside the trenches of the semiconductor substrate, the three-layer trenches have a first dummy part 161 connected to the emitter electrode in the upper layer, an active part 14 connected to the gate electrode in the middle layer, and a second dummy part 19 connected to the emitter electrode in the lower layer. The first dummy part 161, the active part 14, and the second dummy part 19 are insulated by, for example, polysilicon inside the trench 7.

[0189] By making the lower part of the three-layer trench the second dummy part 19 at a dummy potential, the hot carriers generated by the dynamic avalanche are injected into the second dummy part 19 that is not electrically connected to the gate electrode 15 instead of the active part 14. Therefore, the deterioration of the gate characteristics can be suppressed. In addition, since it has the active part 14, the same effect as in Embodiment 1 can be achieved.

[0190] Embodiment 6.

[0191] As a method for achieving both a reduction in on-resistance and a reduction in on-off loss, dual-gate drive has been proposed. Dual-gate drive is a technique that reduces the on-off time of an IGBT and the on-off loss by setting the gate drive system to two systems and changing the drive timing of the two gates. Specifically, it is a technique for reducing the carriers in the drift layer before cutoff by turning off one of the gates before cutoff to close the channel. Therefore, both a reduction in on-resistance and a reduction in on-off loss can be achieved simultaneously. In the present embodiment, a semiconductor element related to dual-gate drive is proposed.

[0192] Figure 30 It is a cross-sectional view of the semiconductor element according to Embodiment 6. The gate electrode has a first gate electrode 15 and a second gate electrode 20 of a different system from the first gate electrode 15. The active part 29 is connected to the first gate electrode 15, and the lower active part 142 is connected to the second gate electrode 20.

[0193] Figure 33 It is a diagram showing a structural example of a three-phase inverter circuit. This inverter circuit has p-side semiconductor elements T1, T3, T5 and n-side semiconductor elements T2, T4, T6. According to one example, Figure 30 the semiconductor element can be provided as any one of the p-side semiconductor elements T1, T3, T5 and the n-side semiconductor elements T2, T4, T6.

[0194] According to one example, when the semiconductor element is switched from the on state to the off state, after applying a voltage (turn-off) less than or equal to the threshold voltage to the second gate electrode 20, a voltage less than or equal to the threshold voltage is applied to the first gate electrode 15. As a result, it is possible to reduce Cgc by the amount of Cgc of the lower active part 142 before cutoff. Therefore, Cgc at cutoff when applying a voltage less than or equal to the threshold voltage to the gate electrode 15 only becomes Cgc parasitic in the active trench A. As a result, the on-off time becomes shorter, and thus the cutoff loss can be reduced.

[0195] In addition, by making the timing of applying a voltage (turn-on) greater than or equal to the threshold voltage to the first gate electrode 15 and the second gate electrode 20 during conduction the same, it is possible to perform on-off without reducing Cgc during conduction. Therefore, the same objectives and effects as those described in Embodiment 1 can be achieved.

[0196] (Modification Example 1)

[0197] Figure 31It is a cross-sectional view of the semiconductor element related to Modification Example 1. As the gate electrode, it has a first gate electrode 15 and a second gate electrode 20 of a different system from the first gate electrode 15. The active trench A has a first active trench A1 and a second active trench A2. Moreover, the active part of the first active trench A1 is connected to the first gate electrode 15, and the active part and the lower active part 142 of the second active trench A2 are connected to the second gate electrode 20.

[0198] Figure 32 It is a cross-sectional view of the semiconductor element related to other examples. The part of the active part of the active trench A above the intermediate insulating film is connected to the first gate electrode 15, and the part of the active part below the intermediate insulating film is connected to the second gate electrode 20. Regarding the active part of the active trench A2, both the part above the intermediate insulating film and the part below the intermediate insulating film are connected to the second gate electrode 20. According to Figure 32 this structure, it is possible to separate the channel formation part of the upper active part from the Cgc part of the lower active part 14 and turn on and off at the most appropriate timing respectively.

[0199] By disconnecting the second gate electrode 20 before the semiconductor element is turned off, it is possible to reduce the Cgc of the lower active part 142. And by connecting a part of the active trench A to the second gate electrode 20, it is possible to cut off the active trench A2 or the lower active part 142 connected to the second gate electrode before turning off the channel of the active part connected to the first gate electrode. Thereby, it is possible to reduce the carriers in the drift layer 9 and reduce the turn-off loss.

[0200] (Modification Example 2)

[0201] In Embodiment 6, the operation of the second gate electrode 20 during conduction is not particularly limited, but a voltage greater than or equal to the threshold voltage (turned on) may be applied to the second gate electrode 20 only during low-current conduction. According to an example, the second gate electrode 20 may be turned on only when the current value becomes less than or equal to 20% of the rated current during conduction.

[0202] In Figure 33 it shows the first semiconductor elements T1, T3, T5 whose collectors are connected to the high-potential side of the power supply, and the second semiconductor elements T2, T4, T6 whose emitters are connected to the low-potential side of the power supply and whose collectors are connected to the emitters of the first semiconductor elements T1, T3, T5. As the second semiconductor elements T2, T4, T6, any of the semiconductor elements described in Figures 30 - 32 can be adopted. According to an example, any of the second semiconductor elements T2, T4, T6 is composed of Figure 31 , 32The gate drive circuit 40 shown is controlled. The gate drive circuit 40 applies gate voltages to the first gate electrode 15 and the second gate electrode 20 through different systems. Moreover, when the collector current of the first semiconductor element is greater than a predetermined value, the gate drive circuit applies a voltage greater than or equal to the threshold voltage to the first gate electrode 15 but does not apply a voltage greater than or equal to the threshold voltage to the second gate electrode 20. When the collector current of the first semiconductor element is less than the predetermined value, the gate drive circuit applies a voltage greater than or equal to the threshold voltage to the first gate electrode 15 and the second gate electrode 20. The "predetermined value" of the collector current refers to the value at low current, and at low current, the recovery dV / dt of the diode is larger than the recovery dV / dt at the rated current. This situation is shown, for example, in Figure 34 And, in order to reduce the recovery dV / dt at low current, it is necessary to increase Cgc. Thus, a voltage greater than or equal to the threshold voltage is applied to the first gate electrode 15 and the second gate electrode 20. Since the dV / dt is originally small at the rated current, it is not necessary to increase Cgc. A voltage greater than or equal to the threshold voltage is applied to the first gate electrode 15 but not to the second gate electrode 20.

[0203] By controlling in this way, when conducting at low current, the second gate electrode 20 is turned on. Therefore, Cgc can be increased to reduce the dV / dt at low current. At the rated current, since the second gate electrode 20 is not turned on, Cgc becomes smaller and the on-off time becomes shorter, and the dV / dt can be increased. As a result, the current dependence of the dV / dt can be reduced.

[0204] Embodiment 7.

[0205] Figure 35 is a cross-sectional view of the semiconductor element according to Embodiment 7. This semiconductor element is an RC-IGBT (Reverse Conducting IGBT) having the above technical features. This semiconductor element has an IGBT region with a p-type collector layer 11 on the left side and a diode region with an n-type cathode layer 21 on the right side. According to an example, a plurality of two-layer dummy active trenches D / A are provided, and more two-layer dummy active trenches D / A are provided in the diode region than in the IGBT region.

[0206] By making the ratio of the two-layer dummy active trenches D / A arranged in the IGBT region smaller than the ratio of the two-layer dummy active trenches D / A arranged in the diode region, the active trench A density in the IGBT region can be increased and the channel density can be improved. Thereby, the current-carrying capacity can be improved.

[0207] (Variant 1)

[0208] Figure 36 is a cross-sectional view of the semiconductor element according to Variant 1.Figure 36 The semiconductor device forms an RC-IGBT by having an IGBT region and a diode region. A plurality of two-layer dummy active trenches D / A are provided in the diode region. A plurality of two-layer active dummy trenches A / D are provided in the IGBT region. Inside the trench of the semiconductor substrate, the two-layer active dummy trench A / D has an upper active portion 18 connected to the gate electrode in the upper layer, and a lower dummy portion 39 not connected to the gate electrode and covered by an insulating film, i.e., a gate insulating film 8, in the lower layer.

[0209] Due to the hot carrier injection into the gate oxide film at the bottom of the trench in the IGBT region by dynamic avalanche during cutoff, the gate characteristics deteriorate. By making the trench in the IGBT region a two-layer active dummy trench A / D, the lower layer becomes a dummy portion, so even if hot carriers are injected by dynamic avalanche, the gate characteristics do not deteriorate. Also, Cgc for reducing conduction loss increases due to the two-layer dummy active trench D / A provided in the diode region. Thus, it is possible to achieve both suppression of gate characteristic degradation caused by dynamic avalanche and reduction of conduction loss.

[0210] Embodiment 8.

[0211] Figure 37 is a cross-sectional view of the semiconductor device according to Embodiment 8. Two or more two-layer dummy active trenches D / A are arranged side by side, and the interval between the two two-layer dummy active trenches D / A is smaller than the interval between the active trench and the trench adjacent to the active trench. As the "trench adjacent to the active trench", a two-layer dummy active trench D / A is illustrated in Figure 37 However, the "trench adjacent to the active trench" may also be an active trench or a dummy trench.

[0212] Thus, in the semiconductor device according to Embodiment 8, when observed at the same cell pitch, the density of the two-layer dummy active trenches D / A is high, so the surface area of the lower active portion 14 of the two-layer dummy active trenches D / A facing the drift layer 9 increases. Therefore, Cgc can be increased.

[0213] (Modification 1)

[0214] Figure 38 is a cross-sectional view of the semiconductor device according to Modification 1. The width of the two-layer dummy active trench D / A is smaller than the width of the active trench A. According to other examples, the width of the two-layer dummy active trench D / A is smaller than the width of the dummy trench. According to one example, from Figure 38It can be seen that the distance between two adjacent dummy active trenches D / A is shorter than the distance between the active trench A and the two layers of dummy active trenches D / A. In this way, by reducing the width of the two layers of dummy active trenches D / A, the density of the two layers of dummy active trenches D / A can be increased when observed at the same cell pitch. Therefore, the surface area of the two layers of dummy active trenches D / A increases, and Cgc can be increased.

[0215] (Modification 2)

[0216] Figures 39 - 41 FIG. shows a semiconductor device according to Modification 2. Figure 39 It is a cross-sectional view, Figure 40 along Figure 39 the z-z line of. The two layers of dummy active trenches D / A have a branched shape when viewed from above. In Figure 40 is illustrated a case where the two layers of dummy active trenches D / A are branched into three parts when viewed from above.

[0217] Figure 41 FIG. is a top view of the two layers of dummy active trenches D / A according to other examples. Figure 41 Corresponds to a cross-sectional view at the position along Figure 39 the z-z line of. In the example of Figure 41 , the width of the two layers of dummy active trenches D / A is substantially constant, and there is a portion formed in a ring shape when viewed from above. A drift layer 9 exists at a position surrounded by the ring-shaped portion of the two layers of dummy active trenches D / A. If other expressions are used, the overall width of the two layers of dummy active trenches D / A is substantially constant, but there is a portion that branches by making a part thereof thinner. According to an example, the thinner portion can be provided at the central portion of the two layers of dummy active trenches D / A.

[0218] According to the structure described with reference to Figures 39 - 41 , the surface area of the two layers of dummy active trenches D / A can be increased by branching a part of the two layers of dummy active trenches D / A. Therefore, Cgc can be increased.

[0219] (Modification 3)

[0220] Figure 42 FIG. shows a semiconductor device according to Modification 3. The two layers of dummy active trenches D / A have a main body portion 14A and a protruding portion 14B that protrudes in a direction perpendicular to the length direction of the main body portion 14A when viewed from above. In Figure 42 is illustrated a case where a plurality of protruding portions 14B are provided on the left and right of the main body portion 14A.

[0221] Figure 43It is a top view of a two-layer dummy active trench D / A involved in other examples. The two-layer dummy active trench D / A has a main body portion 14A and a recessed portion 14C that is recessed in a direction perpendicular to the length direction of the main body portion 14A when viewed from above.

[0222] Thus, by providing the protruding portion 14B or the recessed portion 14C, the surface area of the two-layer dummy active trench D / A can be increased compared to the case where neither of them is provided. Therefore, Cgc can be increased.

[0223] According to one example, in order to increase the surface area of the two-layer dummy active trench D / A, the protruding portion 14B or the recessed portion 14C can be miniaturized. For example, as Figure 42 shown, when viewed from above, the width W1 of the protruding portion 14B can be made smaller than the width W2 of the main body portion 14A. In addition, as Figure 43 shown, when viewed from above, the width W1 of the recessed portion 14C can be made smaller than the width W2 of the main body portion 14A. Also, the interval between the plurality of protruding portions 14B formed can be made smaller than the distance between the two-layer dummy active trench D / A and the trench adjacent to the two-layer dummy active trench D / A. Similarly, the interval between the plurality of recessed portions 14C formed can be made smaller than the distance between the two-layer dummy active trench D / A and the trench adjacent to the two-layer dummy active trench D / A.

[0224] (Modification Example 4)

[0225] Figure 44 It is a diagram showing a semiconductor element related to Modification Example 4. The two-layer dummy active trench D / A has a plurality of bent portions 14D when viewed from above. According to one example, the two-layer dummy active trench D / A has a plurality of bent portions 14D when viewed from above and is provided parallel to the active trench A as a whole. Thus, by providing the plurality of bent portions 14D, the surface area of the two-layer dummy active trench D / A is increased. Therefore, Cgc can be increased.

[0226] The features described in the embodiments so far can be combined. In addition, the techniques described in the embodiments so far can be applied to a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). And the semiconductor substrate can be formed of a wide bandgap semiconductor. The wide bandgap semiconductor is, for example, silicon carbide, gallium nitride-based material, or diamond.

[0227] Explanation of reference numerals

[0228] 13 Upper layer dummy portion, 14 Lower layer active portion, A Active trench, D / A Two-layer dummy active trench

Claims

1. A semiconductor device, characterized in that, comprising: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; a two-layer dummy active trench having, inside a trench of the semiconductor substrate, an upper-layer dummy portion not connected to the gate electrode in an upper layer and a lower-layer active portion connected to the gate electrode and covered with an insulating film in a lower layer; and an active trench having a gate insulating film provided along a trench of the semiconductor substrate and an active portion provided in contact with the gate insulating film and connected to the gate electrode, wherein a length of the lower-layer active portion in a trench depth direction is greater than a width of the lower-layer active portion, the active portion is cut into upper and lower two parts with an intermediate insulating film therebetween, the semiconductor element comprising: a first insulating film covering a portion of the active portion located more above the intermediate insulating film; and a second insulating film covering a portion of the active portion located more below the intermediate insulating film, wherein a side wall portion and a bottom portion of the second insulating film are thicker than the first insulating film.

2. The semiconductor element according to claim 1, wherein the two-layer dummy active trench and the active trench are formed in a region where the base layer is formed, i.e., a cell region, when viewed from above.

3. The semiconductor element according to claim 1, wherein the active trench is formed in a region where the base layer is formed, i.e., a cell region, when viewed from above, and the two-layer dummy active trench is formed in a region surrounding the cell region, i.e., an end region, a region surrounding the end region, i.e., an outer peripheral region, or a gate pad region when viewed from above.

4. The semiconductor element according to any one of claims 1 to 3, wherein a length of the lower-layer active portion in a trench depth direction is longer than a length of the upper-layer dummy portion in a trench depth direction.

5. The semiconductor element according to any one of claims 1 to 3, wherein a length of the lower-layer active portion in a trench depth direction is greater than a thickness of the base layer.

6. The semiconductor element according to any one of claims 1 to 3, wherein an upper end of the lower-layer active portion is located in the base layer.

7. The semiconductor element according to any one of claims 1 to 3, wherein a carrier accumulation layer of a first conductivity type having a lower impurity concentration of the first conductivity type than the source layer and a higher impurity concentration of the first conductivity type than the drift layer is provided between the base layer and the drift layer.

8. The semiconductor element according to claim 7, wherein the upper end of the lower-layer active portion is located more below than a lower end of the carrier accumulation layer.

9. The semiconductor element according to any one of claims 1 to 3, wherein the upper-layer dummy portion is connected to the emitter electrode.

10. The semiconductor device according to any one of claims 1 to 3, wherein, the upper dummy part is an oxide or a metal.

11. The semiconductor device according to any one of claims 1 to 3, characterized in that, the upper dummy part is in contact with the base layer.

12. The semiconductor device according to claim 1, characterized in that, a first structure in which two or more of the active trenches are arranged side by side and a second structure in which two or more of the two-layer dummy active trenches are arranged side by side are alternately provided.

13. The semiconductor device according to claim 1, characterized in that, a first structure in which three or more of the active trenches are arranged side by side and a second structure in which three or more of the two-layer dummy active trenches are arranged side by side are alternately provided.

14. The semiconductor device according to claim 12 or 13, characterized in that, the number of the two-layer dummy active trenches is larger than the number of the active trenches.

15. The semiconductor device according to claim 1, characterized in that, it has dummy trenches.

16. A semiconductor device, characterized in that, It has: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; a two-layer dummy active trench which has an upper dummy part not connected to the gate electrode in the upper layer and a lower active part connected to the gate electrode and covered with an insulating film in the lower layer inside the trench of the semiconductor substrate; an active trench which has a gate insulating film provided along the trench of the semiconductor substrate and an active part provided in contact with the gate insulating film and connected to the gate electrode; and dummy trenches, the length of the lower active part in the trench depth direction is larger than the width of the lower active part, the semiconductor device has a first structure in which one or more of the active trenches are arranged side by side, a second structure in which two or more of the two-layer dummy active trenches are arranged side by side, and a third structure in which one or more of the dummy trenches are arranged side by side, the second structure is sandwiched by two of the third structures.

17. The semiconductor device according to claim 15, characterized in that, it has a first structure in which one or more of the active trenches are arranged side by side, a second structure in which one or more of the two-layer dummy active trenches are arranged side by side, and a third structure in which one or more of the dummy trenches are arranged side by side, the second structure is sandwiched by the first structure and the third structure.

18. A semiconductor device, characterized in that, It has: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and A two-layer dummy active trench, which is inside the trench of the semiconductor substrate, has an upper-layer dummy part that is not connected to the gate electrode in the upper layer and a lower-layer active part that is connected to the gate electrode and covered with an insulating film in the lower layer. The length of the lower-layer active part in the trench depth direction is greater than the width of the lower-layer active part. The upper-layer dummy part is set to a floating potential.

19. A semiconductor device, characterized in that, It has: A semiconductor substrate; An emitter electrode formed on the semiconductor substrate; A gate electrode formed on the semiconductor substrate; A drift layer of the first conductivity type formed in the semiconductor substrate; A source layer of the first conductivity type formed on the upper surface side of the semiconductor substrate; A base layer of the second conductivity type formed on the upper surface side of the semiconductor substrate; A collector electrode formed under the semiconductor substrate; and A two-layer dummy active trench, which is inside the trench of the semiconductor substrate, has an upper-layer dummy part that is not connected to the gate electrode in the upper layer and a lower-layer active part that is connected to the gate electrode and covered with an insulating film in the lower layer. The length of the lower-layer active part in the trench depth direction is greater than the width of the lower-layer active part. The semiconductor element has an active trench, which has a gate insulating film provided along the trench of the semiconductor substrate and an active part that is provided in contact with the gate insulating film and connected to the gate electrode. The two-layer dummy active trench has a first trench in which the upper-layer dummy part is connected to the emitter electrode and a second trench in which the upper-layer dummy part becomes a floating potential. The second trench is sandwiched between the first trench and the active trench.

20. A semiconductor device, characterized in that, It has: A semiconductor substrate; An emitter electrode formed on the semiconductor substrate; A gate electrode formed on the semiconductor substrate; A drift layer of the first conductivity type formed in the semiconductor substrate; A source layer of the first conductivity type formed on the upper surface side of the semiconductor substrate; A base layer of the second conductivity type formed on the upper surface side of the semiconductor substrate; A collector electrode formed under the semiconductor substrate; and A two-layer dummy active trench, which is inside the trench of the semiconductor substrate, has an upper-layer dummy part that is not connected to the gate electrode in the upper layer and a lower-layer active part that is connected to the gate electrode and covered with an insulating film in the lower layer. The length of the lower-layer active part in the trench depth direction is greater than the width of the lower-layer active part. The semiconductor element has an active trench, which has a gate insulating film provided along the trench of the semiconductor substrate and an active part that is provided in contact with the gate insulating film and connected to the gate electrode. The semiconductor element has a dummy trench. The upper-layer dummy part is at a floating potential. The two-layer dummy active trench is sandwiched between the dummy trench and the active trench.

21. A semiconductor device, characterized in that, It has: A semiconductor substrate; An emitter electrode formed on the semiconductor substrate; A gate electrode formed on the semiconductor substrate; A drift layer of the first conductivity type formed in the semiconductor substrate; A source layer of the first conductivity type formed on the upper surface side of the semiconductor substrate; A base layer of the second conductivity type, which is formed on the upper surface side of the semiconductor substrate; A collector electrode, which is formed under the semiconductor substrate; and A two-layer dummy active trench, which is inside the trench of the semiconductor substrate, has an upper-layer dummy portion that is not connected to the gate electrode in the upper layer, and a lower-layer active portion that is connected to the gate electrode and covered by an insulating film in the lower layer, The length of the lower-layer active portion in the trench depth direction is greater than the width of the lower-layer active portion, The semiconductor element has an active trench, which has a gate insulating film provided along the trench of the semiconductor substrate and an active portion provided in contact with the gate insulating film and connected to the gate electrode, The distance between a first structure in which two or more of the two-layer dummy active trenches are arranged side by side and a second structure in which two or more of the active trenches are arranged side by side is greater than the distance between two of the two-layer dummy active trenches and greater than the distance between two of the active trenches.

22. A semiconductor device, characterized in that, Having: A semiconductor substrate; An emitter electrode, which is formed on the semiconductor substrate; A gate electrode, which is formed on the semiconductor substrate; A drift layer of the first conductivity type, which is formed in the semiconductor substrate; A source layer of the first conductivity type, which is formed on the upper surface side of the semiconductor substrate; A base layer of the second conductivity type, which is formed on the upper surface side of the semiconductor substrate; A collector electrode, which is formed under the semiconductor substrate; and A two-layer dummy active trench, which is inside the trench of the semiconductor substrate, has an upper-layer dummy portion that is not connected to the gate electrode in the upper layer, and a lower-layer active portion that is connected to the gate electrode and covered by an insulating film in the lower layer, The length of the lower-layer active portion in the trench depth direction is greater than the width of the lower-layer active portion, The semiconductor element has an active trench, which has a gate insulating film provided along the trench of the semiconductor substrate and an active portion provided in contact with the gate insulating film and connected to the gate electrode, The semiconductor element has: A first structure in which two or more of the active trenches are arranged side by side; A second structure adjacent to the first structure, in which two or more of the two-layer dummy active trenches are arranged side by side; And A dummy trench adjacent to the second structure, The distance between the second structure and the dummy trench is greater than the distance between two of the active trenches, the distance between the first structure and the second structure, or the distance between two of the two-layer dummy active trenches.

23. A semiconductor device, characterized in that, Having: A semiconductor substrate; An emitter electrode, which is formed on the semiconductor substrate; A gate electrode, which is formed on the semiconductor substrate; A drift layer of the first conductivity type, which is formed in the semiconductor substrate; A source layer of the first conductivity type, which is formed on the upper surface side of the semiconductor substrate; A base layer of the second conductivity type, which is formed on the upper surface side of the semiconductor substrate; A collector electrode, which is formed under the semiconductor substrate; and A two-layer dummy active trench, which is inside the trench of the semiconductor substrate, has an upper-layer dummy portion that is not connected to the gate electrode in the upper layer, and a lower-layer active portion that is connected to the gate electrode and covered by an insulating film in the lower layer, The length of the lower active part in the trench depth direction is greater than the width of the lower active part. The semiconductor element has an active trench that has a gate insulating film provided along the trench of the semiconductor substrate and an active part provided in contact with the gate insulating film and connected to the gate electrode. The part of the base layer adjacent to the active trench is connected to the emitter electrode. The part of the base layer sandwiched by two of the two-layer dummy active trenches is not connected to the emitter electrode.

24. A semiconductor device, characterized in that, It has: A semiconductor substrate; An emitter electrode formed on the semiconductor substrate; A gate electrode formed on the semiconductor substrate; A drift layer of a first conductivity type formed in the semiconductor substrate; A source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; A base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; A collector electrode formed under the semiconductor substrate; and A two-layer dummy active trench inside the trench of the semiconductor substrate, having an upper dummy part not connected to the gate electrode in the upper layer and a lower active part connected to the gate electrode and covered with an insulating film in the lower layer. The length of the lower active part in the trench depth direction is greater than the width of the lower active part. The semiconductor element has an active trench that has a gate insulating film provided along the trench of the semiconductor substrate and an active part provided in contact with the gate insulating film and connected to the gate electrode. The semiconductor element has at least one dummy trench. The part of the base layer sandwiched by two of the dummy trenches or the part sandwiched by the dummy trench and the two-layer dummy active trench is not connected to the emitter electrode.

25. A semiconductor element, characterized in that, It has: A semiconductor substrate; An emitter electrode formed on the semiconductor substrate; A gate electrode formed on the semiconductor substrate; A drift layer of a first conductivity type formed in the semiconductor substrate; A source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; A base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; A collector electrode formed under the semiconductor substrate; and A two-layer dummy active trench inside the trench of the semiconductor substrate, having an upper dummy part not connected to the gate electrode in the upper layer and a lower active part connected to the gate electrode and covered with an insulating film in the lower layer. The length of the lower active part in the trench depth direction is greater than the width of the lower active part. The semiconductor element has an active trench that has a gate insulating film provided along the trench of the semiconductor substrate and an active part provided in contact with the gate insulating film and connected to the gate electrode. The part of the base layer adjacent to two of the active trenches is connected to the emitter electrode. The part of the base layer adjacent to the two-layer dummy active trench is not connected to the emitter electrode.

26. A semiconductor device, characterized in that, It has: A semiconductor substrate; An emitter electrode formed on the semiconductor substrate; A gate electrode formed on the semiconductor substrate; a first conductivity type drift layer formed in the semiconductor substrate; a first conductive type source layer formed on the upper surface side of the semiconductor substrate; a second conductive type base layer formed on the upper surface side of the semiconductor substrate; a collector electrode formed below the semiconductor substrate; and A two-layer dummy active trench, which has an upper dummy portion not connected to the gate electrode in the upper layer and a lower active portion connected to the gate electrode and covered by an insulating film in the lower layer, inside the trench of the semiconductor substrate, The length of the lower active portion in the trench depth direction is greater than the width of the lower active portion. The semiconductor element has: an active trench having a gate insulating film provided along a trench of the semiconductor substrate, and an active portion provided in contact with the gate insulating film and connected to the gate electrode; and dumb grooves, The dummy trench is divided into two upper and lower parts via an intermediate insulating film.

27. A semiconductor device, characterized in that, have: Semiconductor substrates; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first conductivity type drift layer formed in the semiconductor substrate; a first conductive type source layer formed on the upper surface side of the semiconductor substrate; a second conductive type base layer formed on the upper surface side of the semiconductor substrate; a collector electrode formed below the semiconductor substrate; and A two-layer dummy active trench, which has an upper dummy portion not connected to the gate electrode in the upper layer and a lower active portion connected to the gate electrode and covered by an insulating film in the lower layer, inside the trench of the semiconductor substrate, The length of the lower active portion in the trench depth direction is greater than the width of the lower active portion. The semiconductor element has an active trench including a gate insulating film provided along a trench of the semiconductor substrate, and an active portion provided in contact with the gate insulating film and connected to the gate electrode. The active portion is cut into two upper and lower portions via an intermediate insulating film. The semiconductor element has: a first insulating film covering a portion of the active portion above the intermediate insulating film; and a second insulating film covering a portion of the active portion below the intermediate insulating film, The first insulating film is thicker than the second insulating film.

28. A semiconductor device, characterized in that, have: Semiconductor substrates; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a first conductivity type drift layer formed in the semiconductor substrate; a first conductive type source layer formed on the upper surface side of the semiconductor substrate; a second conductive type base layer formed on the upper surface side of the semiconductor substrate; a collector electrode formed below the semiconductor substrate; and A two-layer dummy active trench, which has an upper dummy portion not connected to the gate electrode in the upper layer and a lower active portion connected to the gate electrode and covered by an insulating film in the lower layer, inside the trench of the semiconductor substrate, The length of the lower active portion in the trench depth direction is greater than the width of the lower active portion. The semiconductor element has a third insulating film covering the upper dummy portion. The side wall portion and the bottom portion of the insulating film covering the lower active portion are thicker than the third insulating film.

29. The semiconductor element according to claim 1, characterized in that the gate electrode has a first gate electrode and a second gate electrode of a different system from the first gate electrode, the active portion is connected to the first gate electrode, and the lower active portion is connected to the second gate electrode.

30. The semiconductor element according to claim 1, characterized in that the gate electrode has a first gate electrode and a second gate electrode of a different system from the first gate electrode, the active trench has a first active trench and a second active trench, the active portion of the first active trench is connected to the first gate electrode, the active portion of the second active trench and the lower active portion are connected to the second gate electrode.

31. A semiconductor device, characterized in that, It has: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and a two-layer dummy active trench inside the trench of the semiconductor substrate, having an upper dummy portion not connected to the gate electrode in the upper layer and a lower active portion connected to the gate electrode and covered by an insulating film in the lower layer, the length of the lower active portion in the trench depth direction is greater than the width of the lower active portion, the semiconductor element has an active trench having a gate insulating film provided along the trench of the semiconductor substrate and an active portion provided in contact with the gate insulating film and connected to the gate electrode, the active portion is cut into two upper and lower parts with an intermediate insulating film therebetween, the gate electrode has a first gate electrode and a second gate electrode of a different system from the first gate electrode, the portion of the active portion above the intermediate insulating film is connected to the first gate electrode, the portion of the active portion below the intermediate insulating film is connected to the second gate electrode.

32. A semiconductor device, characterized in that, It has: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and a two-layer dummy active trench inside the trench of the semiconductor substrate, having an upper dummy portion not connected to the gate electrode in the upper layer and a lower active portion connected to the gate electrode and covered by an insulating film in the lower layer, the length of the lower active portion in the trench depth direction is greater than the width of the lower active portion, An RC-IGBT is formed by having an IGBT region and a diode region. A plurality of the two-layer dummy active trenches are provided. More of the two-layer dummy active trenches are provided in the diode region than in the IGBT region.

33. The semiconductor device according to any one of claims 1, 16, 18 to 28, 31, and 32, wherein a MOSFET is formed.

34. The semiconductor device according to any one of claims 1, 16, 18 to 28, 31, and 32, wherein the semiconductor substrate is formed of a wide bandgap semiconductor.

35. The semiconductor device according to claim 34, wherein the wide bandgap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

36. A semiconductor device, characterized in that, comprises: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and a two-layer dummy active trench inside a trench of the semiconductor substrate, having an upper-layer dummy portion not connected to the gate electrode in the upper layer and a lower-layer active portion connected to the gate electrode and covered with an insulating film in the lower layer, a length of the lower-layer active portion in a trench depth direction is greater than a width of the lower-layer active portion, the length of the lower-layer active portion in the trench depth direction is shorter than a length of the upper-layer dummy portion in the trench depth direction.

37. A semiconductor device, characterized in that, comprises: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and a two-layer dummy active trench inside a trench of the semiconductor substrate, having an upper-layer dummy portion not connected to the gate electrode in the upper layer and a lower-layer active portion connected to the gate electrode and covered with an insulating film in the lower layer, the length of the lower-layer active portion in the trench depth direction is greater than the width of the lower-layer active portion, the semiconductor device has an active trench having a gate insulating film provided along a trench of the semiconductor substrate and an active portion provided in contact with the gate insulating film and connected to the gate electrode, two or more of the two-layer dummy active trenches are arranged side by side, and a distance between the two-layer dummy active trenches is smaller than a distance between the active trench and an adjacent trench.

38. The semiconductor device according to claim 37, wherein a width of the two-layer dummy active trench is smaller than a width of the active trench.

39. The semiconductor device according to claim 37, wherein it has a dummy trench. The width of the two-layer dummy active trench is smaller than the width of the dummy trench.

40. A semiconductor device, characterized in that, comprising: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and a two-layer dummy active trench inside the trench of the semiconductor substrate, having an upper-layer dummy portion not connected to the gate electrode in the upper layer and a lower-layer active portion connected to the gate electrode and covered with an insulating film in the lower layer, the length of the lower-layer active portion in the trench depth direction is larger than the width of the lower-layer active portion, the two-layer dummy active trench has a branched shape in a plan view.

41. A semiconductor device, characterized in that, comprising: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and a two-layer dummy active trench inside the trench of the semiconductor substrate, having an upper-layer dummy portion not connected to the gate electrode in the upper layer and a lower-layer active portion connected to the gate electrode and covered with an insulating film in the lower layer, the length of the lower-layer active portion in the trench depth direction is larger than the width of the lower-layer active portion, the width of the two-layer dummy active trench is substantially constant, and the two-layer dummy active trench has a portion formed in a ring shape in a plan view.

42. A semiconductor device, characterized in that, comprising: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and a two-layer dummy active trench inside the trench of the semiconductor substrate, having an upper-layer dummy portion not connected to the gate electrode in the upper layer and a lower-layer active portion connected to the gate electrode and covered with an insulating film in the lower layer, the length of the lower-layer active portion in the trench depth direction is larger than the width of the lower-layer active portion, the two-layer dummy active trench has: a main body portion; and a protruding portion protruding in a direction perpendicular to the length direction of the main body portion in a plan view or a recessed portion recessed in a direction perpendicular to the length direction of the main body portion in a plan view.

43. The semiconductor element according to claim 42, wherein in a plan view, the width of the protruding portion or the recessed portion is smaller than the width of the main body portion.

44. The semiconductor device according to claim 43, wherein when viewed from above, a plurality of the protruding portions are formed, and the interval between the protruding portions is smaller than the distance between the two-layer dummy active trench and the trench adjacent to the two-layer dummy active trench.

45. The semiconductor device according to claim 43, wherein when viewed from above, a plurality of the recessed portions are formed, and the interval between the recessed portions is smaller than the distance between the two-layer dummy active trench and the trench adjacent to the two-layer dummy active trench.

46. A semiconductor device, characterized in that, comprising: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and a two-layer dummy active trench inside the trench of the semiconductor substrate, having an upper-layer dummy portion not connected to the gate electrode in the upper layer and a lower-layer active portion connected to the gate electrode and covered with an insulating film in the lower layer, the length of the lower-layer active portion in the trench depth direction is larger than the width of the lower-layer active portion, the two-layer dummy active trench has a plurality of bent portions when viewed from above.

47. The semiconductor device according to claim 1, wherein a portion of the base layer sandwiched between two of the two-layer dummy active trenches is connected to the emitter electrode.

48. A semiconductor device, characterized in that, comprising: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and a two-layer dummy active trench inside the trench of the semiconductor substrate, having an upper-layer dummy portion not connected to the gate electrode in the upper layer and a lower-layer active portion connected to the gate electrode and covered with an insulating film in the lower layer, the length of the lower-layer active portion in the trench depth direction is larger than the width of the lower-layer active portion, by providing a plurality of the two-layer dummy active trenches, the base layer is divided into a plurality of base portions, and the plurality of base portions include a portion connected to the emitter electrode and a portion not connected to the emitter electrode.

49. A semiconductor device, characterized in that, comprising: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed on the upper surface side of the semiconductor substrate; a base layer of a second conductivity type formed on the upper surface side of the semiconductor substrate; a collector electrode formed under the semiconductor substrate; and A two-layer dummy active trench, which is inside the trench of the semiconductor substrate, has an upper-layer dummy part that is not connected to the gate electrode in the upper layer and a lower-layer active part that is connected to the gate electrode and covered by an insulating film in the lower layer. The length of the lower-layer active part in the trench depth direction is greater than the width of the lower-layer active part. The semiconductor element has two dummy trenches. The part of the base layer sandwiched by the two dummy trenches is not connected to the emitter electrode. The part of the base layer sandwiched by the two two-layer dummy active trenches is connected to the emitter electrode.

50. A semiconductor device, characterized in that, It has: A semiconductor substrate; An emitter electrode formed on the semiconductor substrate; A gate electrode formed on the semiconductor substrate; A drift layer of the first conductivity type formed in the semiconductor substrate; A source layer of the first conductivity type formed on the upper surface side of the semiconductor substrate; A base layer of the second conductivity type formed on the upper surface side of the semiconductor substrate; A collector electrode formed under the semiconductor substrate; and A two-layer dummy active trench, which is inside the trench of the semiconductor substrate, has an upper-layer dummy part that is not connected to the gate electrode in the upper layer and a lower-layer active part that is connected to the gate electrode and covered by an insulating film in the lower layer. The length of the lower-layer active part in the trench depth direction is greater than the width of the lower-layer active part. An RC-IGBT is formed by having an IGBT region and a diode region. A plurality of the two-layer dummy active trenches are provided in the diode region. A plurality of two-layer active dummy trenches are provided in the IGBT region. Inside the trench of the semiconductor substrate, these two-layer active dummy trenches have an upper-layer active part connected to the gate electrode in the upper layer and a lower-layer dummy part not connected to the gate electrode and covered by an insulating film in the lower layer.

51. The semiconductor element according to any one of claims 1 to 5, characterized in that The upper end of the lower-layer active part is lower than the lower end of the base layer.

52. The semiconductor element according to claim 7, characterized in that The length of the lower-layer active part in the trench depth direction at the carrier accumulation layer is shorter than the length of the lower-layer active part in the trench depth direction at the drift layer.

53. A semiconductor element having: A semiconductor substrate; An emitter electrode formed on the semiconductor substrate; A gate electrode formed on the semiconductor substrate; A drift layer of the first conductivity type formed in the semiconductor substrate; A source layer of the first conductivity type formed on the upper surface side of the semiconductor substrate; A base layer of the second conductivity type formed on the upper surface side of the semiconductor substrate; A collector electrode formed under the semiconductor substrate; And A three-layer trench, which is inside the trench of the semiconductor substrate, has a first dummy part connected to the emitter electrode in the upper layer, an active part connected to the gate electrode in the middle layer, and a second dummy part connected to the emitter electrode in the lower layer.

54. A semiconductor device, characterized in that, It has: A first semiconductor element, whose collector is connected to the high-potential side of the power supply; A second semiconductor element, whose emitter is connected to the low-potential side of the power supply and whose collector is connected to the emitter of the first semiconductor element, and this second semiconductor element has the same structure as the semiconductor element described in any one of claims 29 to 31; A gate drive circuit that applies gate voltages to the first gate electrode and the second gate electrode through different systems, when the collector current of the first semiconductor element is greater than a predetermined value, the gate drive circuit applies a voltage greater than or equal to the threshold voltage to the first gate electrode but does not apply a voltage greater than or equal to the threshold voltage to the second gate electrode, when the collector current of the first semiconductor element is less than a predetermined value, the gate drive circuit applies a voltage greater than or equal to the threshold voltage to the first gate electrode and the second gate electrode.

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