Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, wherein the method comprises: providing a substrate comprising a first region; forming an initial first gate structure on the first region, the initial first gate structure comprising an initial first gate, a top surface of the initial first gate having a first hard mask layer and a protrusion between the first hard mask layer; etching the protrusion and the initial first gate to form at least one first gate opening in the initial first gate structure, to form a first gate structure from the initial first gate structure, and to form a first gate from the initial first gate; and forming a second gate in the first gate opening, the first gate and the second gate being made of different materials, and the second gate material being selected according to different integrated circuit requirements for the performance of the first gate structure, so as to adjust the performance of the first gate structure.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster operation speed, larger data storage capacity and more functions, integrated circuit chips are developing towards higher device density and higher integration. A complete integrated circuit usually includes first zone devices and second zone devices integrated on the same semiconductor substrate, the first zone devices are at least one, the first zone devices are at least one input / output device, the second zone devices are formed in the second zone to realize the main function of the integrated circuit, and the input / output device is used to provide corresponding input signals for the second zone device or output corresponding signals of the second zone device, and the working voltage of the input / output device is higher than that of the second zone device. Due to the difference in working voltage between the first zone device and the second zone device, the structures of the corresponding devices are also different.

[0003] With the continuous development of integrated circuit technology to nanometer level, the design requirements of integrated circuits may not be compatible with existing device processes, such as the existing device performance cannot meet the design requirements of the circuit, so new advanced processes need to be continuously introduced to continuously improve the performance of the device. SUMMARY

[0004] The technical problem solved by the present application is to provide a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.

[0005] To solve the above technical problems, the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a first zone; a first gate structure on the first zone, the first gate structure comprising a first gate, a first hard mask layer on the first gate, and at least one first gate opening in the first gate structure; a second gate in the first gate opening, the material of the second gate being different from that of the first gate.

[0006] Optionally, the resistivity of the material of the second gate is lower than that of the material of the first gate.

[0007] Optionally, the material of the second gate comprises metal; and the material of the first gate comprises polysilicon.

[0008] Optionally, the first gate has first doping ions; and the first doping ions are N-type ions or P-type ions.

[0009] Optionally, further comprising: a first source / drain region in the first region on both sides of the first gate structure; and the first source / drain region having second doping ions.

[0010] Optionally, further comprising: a first contact layer on a surface of the first source / drain region; and the first contact layer being a metal silicide layer.

[0011] Optionally, the substrate further comprises a second region.

[0012] Optionally, further comprising: a second gate structure on the second region.

[0013] Optionally, the second gate structure comprises a third gate; and the third gate being a metal.

[0014] Optionally, the second gate structure further comprises: a second gate dielectric layer between the third gate and the second region.

[0015] Optionally, the second gate dielectric layer being a high-K dielectric material.

[0016] Optionally, the second gate structure further comprises: an oxide layer between the second region and the second gate dielectric layer; and a metal compound layer between the second gate dielectric layer and the third gate.

[0017] Optionally, further comprising: a second source / drain region in the second region on both sides of the second gate structure; and the second source / drain region having second doping ions.

[0018] Optionally, further comprising: a second contact layer on a surface of the second source / drain region; and the second contact layer being a metal silicide.

[0019] Optionally, a dimension of the first gate opening along a gate width direction is less than or equal to 2 microns.

[0020] Optionally, a number of the first gate openings in the first gate structure is greater than one.

[0021] Optionally, a depth of the first gate opening in the first gate is less than a thickness of the first gate.

[0022] Optionally, the first gate structure further comprises: a first gate dielectric layer between the first gate and the first region.

[0023] Optionally, the first gate dielectric layer being a silicon oxide or a high-K dielectric material.

[0024] Optionally, the first hard mask layer being one or more of a silicon oxide, a silicon nitride, a silicon oxynitride, a silicon oxycarbide, a silicon carbonitride, and a silicon oxycarbonitride.

[0025] Accordingly, the technical scheme of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region; forming an initial first gate structure on the first region, the initial first gate structure comprising an initial first gate, a top surface of the initial first gate having a first hard mask layer and a protrusion between the first hard mask layer; etching the protrusion and the initial first gate to form at least one first gate opening in the initial first gate structure, to form a first gate structure from the initial first gate structure, and to form a first gate from the initial first gate; and forming a second gate in the first gate opening, the material of the first gate being different from the material of the second gate.

[0026] Optionally, the material of the first gate comprises polysilicon, and the material of the second gate comprises metal.

[0027] Optionally, the forming method of the protrusion comprises: forming an initial first gate material layer on the substrate; and etching part of the initial first gate material layer to form a first gate material layer and a plurality of protrusions on the first gate material layer.

[0028] Optionally, the first gate material layer also has doped ions, the doped ions being N-type or P-type.

[0029] Optionally, the forming method of the initial first gate structure comprises: forming an initial first hard mask layer on part of the first gate material layer, the initial first hard mask layer being located on the side wall surface and the top surface of the protrusion; etching the first gate material layer with the initial first hard mask layer as a mask to form the initial first gate; and after forming the initial first gate, planarizing the initial first hard mask layer until the top surface of the protrusion is exposed to form the first hard mask layer.

[0030] Optionally, the forming method further comprises: before forming the first gate opening, forming an interlayer dielectric layer on the surface of the substrate, the interlayer dielectric layer also being located on the side wall surface of the initial first gate structure, and the interlayer dielectric layer exposing the first hard mask layer and the top surface of the protrusion.

[0031] Optionally, the forming method of the interlayer dielectric layer comprises: forming an interlayer dielectric material film on the surface of the substrate, the side wall of the initial first gate, and the side wall and the top of the initial first hard mask layer; and planarizing the interlayer dielectric material film until the top surface of the protrusion is exposed to form the interlayer dielectric layer.

[0032] Optionally, the first gate structure further comprises: a first gate dielectric layer between the first gate and the surface of the first region.

[0033] Optionally, the forming method of the second gate includes: filling the second gate material layer in the first gate opening; planarizing the second gate material layer until the surface of the first gate structure is exposed to form the second gate.

[0034] Optionally, the planarization process is a mechanical chemical polishing process.

[0035] Optionally, the second gate material is metal.

[0036] Optionally, before forming the initial first gate structure and after forming the initial first gate, the method further includes: forming a first source / drain region in the first region on both sides of the initial first gate, the first source / drain region having second doping ions.

[0037] Optionally, the method further includes: forming a first contact layer on the surface of the first source / drain region; the material of the first contact layer is metal silicide.

[0038] Optionally, the forming process of the first contact layer includes a self-aligned silicidation process.

[0039] Optionally, the method further includes: the substrate further includes a second region; forming a second gate structure on part of the second region, the second gate structure including a third gate, the material of the third gate being the same as the material of the second gate.

[0040] Optionally, the second gate structure further includes a second gate dielectric layer between the third gate and the substrate.

[0041] Optionally, the material of the second gate dielectric layer includes high-K dielectric material.

[0042] Optionally, the forming method of the second gate structure includes: forming a second gate opening in the interlayer dielectric layer on the second region; forming a third gate in the second gate opening.

[0043] Optionally, the second gate is formed in the first gate opening and the third gate is formed in the second gate opening at the same time; the forming method of the second gate and the third gate includes: forming a second gate material layer on the surface of the interlayer dielectric layer, in the first gate opening and in the second gate opening; planarizing the second gate material layer until the surface of the interlayer dielectric layer is exposed to form the second gate and the third gate.

[0044] Optionally, the planarization process of the gate material layer is a mechanical chemical polishing process.

[0045] Optionally, the forming method of the second gate opening comprises: forming a dummy gate structure on the second region before forming the interlayer dielectric layer, the dummy gate structure comprising a dummy gate; the interlayer dielectric layer is also located on the sidewall of the dummy gate structure and exposes the top surface of the dummy gate; removing the dummy gate to form the second gate opening in the interlayer dielectric layer.

[0046] Optionally, the dummy gate and the initial first gate structure are formed simultaneously, and the forming method of the dummy gate comprises: forming a second hard mask layer on the second region at the same time of forming the initial first hard mask layer on the first region; etching the first gate material layer with the second hard mask layer as a mask to form the dummy gate.

[0047] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0048] In the semiconductor structure provided by the technical scheme, the first gate structure on the first region comprises a first gate and a first hard mask layer on the first gate, and at least one first gate opening is formed in the first gate structure, and a second gate is located in the first gate opening. Since the material of the second gate is different from the material of the first gate, the second gate material with different performance can be selected according to the performance requirement of the first gate structure of different integrated circuits, so as to adjust the performance of the first gate structure, thereby meeting more integrated circuit design requirements.

[0049] Further, the material of the second gate is metal, and the material of the first gate is polysilicon. Since the resistivity value of the metal is lower than that of the polysilicon, the resistivity value of the first gate structure is reduced, thereby obtaining a low-resistance polysilicon gate structure.

[0050] Further, the material of the second gate is metal, and the first gate is connected with the contact plug through the second gate. Since the resistivity value of the metal is lower than that of the polysilicon, the gate structure formed by the first gate and the second gate has a lower contact resistance with the contact plug, and a metal silicide process is not needed to form a low-resistance contact layer on the surface of the first gate, thereby saving the process.

[0051] The forming method of the semiconductor structure provided by the technical scheme can change the performance of the gate electrode composed of the first gate electrode and the second gate electrode by changing the number of openings, the size of the openings, and the performance of the second gate electrode material filled in the openings, so that an optimized gate electrode structure is obtained.

[0052] Further, the size of the first gate electrode opening along the length direction of the gate electrode is less than or equal to 2 microns, so the size of the second gate electrode is small, and the mechanical chemical polishing process is not prone to cause "dishing" defects, so that the second gate electrode is not ground off, the first gate electrode below the second gate electrode is further protected, and the performance of the first gate electrode structure in the first region is improved.

[0053] Further, the material of the second gate electrode is metal, and the material of the first gate electrode is polysilicon. Since the resistivity of the metal is lower than that of the polysilicon, the resistivity of the gate electrode composed of the first gate electrode and the second gate electrode is reduced, so that a polysilicon gate structure with low resistance can be obtained without running a complex metal silicide process.

[0054] Further, the material of the second gate electrode is metal, and the first gate electrode is connected to the contact plug through the second gate electrode. Since the resistivity of the metal is lower than that of the polysilicon, the gate electrode structure formed by the first gate electrode and the second gate electrode has a lower contact resistance with the contact plug, and a low-resistance contact layer does not need to be formed on the surface of the first gate electrode by running a metal silicide process, thereby saving process steps. BRIEF DESCRIPTION OF DRAWINGS

[0055] Figure 1 is a sectional structure schematic diagram of a semiconductor structure;

[0056] Figures 2 to 8 is a sectional structure schematic diagram corresponding to each step of the semiconductor structure forming method in an embodiment of the present application;

[0057] Figures 9 to 15 is a sectional structure schematic diagram corresponding to each step of the semiconductor structure forming method in another embodiment of the present application. DETAILED DESCRIPTION

[0058] As described in the background, the performance of the semiconductor structure formed in the prior art needs to be improved. Now, a semiconductor structure is described and analyzed.

[0059] Figure 1It is a sectional structure schematic diagram of a semiconductor structure.

[0060] Referring to Figure 1 A substrate 100 is provided, and a polysilicon gate structure 101 is formed on a part of the surface of the substrate 100. The polysilicon gate structure 101 comprises a gate dielectric layer 102 on the surface of the substrate 100, and a polysilicon gate 103 on the surface of the gate dielectric layer 101.

[0061] In the above method, the polysilicon gate has a high resistivity, and with the continuous development of semiconductor, it is more and more unable to meet the requirements of existing devices. In another embodiment, a high dose of dopant is doped into the polysilicon gate to reduce the threshold voltage and resistivity of the gate structure, but the resistivity of the polysilicon gate is still high. With the continuous reduction of the feature size of the device to submicron or even nanometer, small size devices (<2 microns) can use metal gate process, and the gate resistivity is low, and the problem of high resistivity of polysilicon gate used in large size devices (>0.7 microns) becomes more and more serious. In order to reduce the resistivity of the polysilicon gate, in another embodiment, a metal silicide process is used to form a layer of metal silicide on the surface of the polysilicon gate to reduce the resistance of the polysilicon gate structure, but several additional processes are required.

[0062] In order to solve the above problems, the present application provides a semiconductor structure and a forming method thereof, wherein a first gate structure is located on a first region, the first gate structure comprises a first gate and a first hard mask layer located on the first gate, the first gate structure has at least one first gate opening, and a second gate is located in the first gate opening. Because the material of the second gate is different from the material of the first gate, different second gate materials with different performance can be selected according to the performance requirements of different integrated circuits for the first gate structure, so as to adjust the performance of the first gate structure, such as selecting a second gate material with low resistivity, which can reduce the resistivity of the first gate structure, without running a metal silicide process, thereby meeting more integrated circuit design requirements.

[0063] In order to make the above-mentioned purposes, characteristics and beneficial effects of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0064] Figures 2 to 8 It is a sectional structure schematic diagram of a semiconductor structure forming method according to an embodiment of the present application.

[0065] Referring to Figure 2 A substrate 200 is provided, and the substrate comprises a first region 201.

[0066] In this embodiment, the substrate 200 further comprises a base 202, an isolation structure 203 on the upper part of the substrate 200 and a deep well 204 in the substrate 200. The isolation structure 203 is used to realize electrical insulation between different semiconductor devices. The deep well 204 is used to isolate noise from the outside to the devices formed on the subsequent substrate.

[0067] The material of the base 202 comprises monocrystalline silicon, and the material of the isolation structure 203 comprises silicon oxide.

[0068] In this embodiment, the deep well 204 is an N-type well, and the forming method thereof comprises: implanting phosphorus ions into the substrate along the direction perpendicular to the substrate 200, with an implantation energy of 10 KeV-3000 KeV and an implantation dose of 10 12 cm -2 ~10 14 cm -2 . In other embodiments, the deep well is formed by implanting boron ions into the substrate to form a P-type well.

[0069] Subsequently, an initial first gate structure is formed on the first region 201, and the initial first gate structure comprises an initial first gate, and the top surface of the initial first gate has a first hard mask layer and a protrusion between the first mask layer. The forming process of the initial first gate structure is shown in Figures 3 to 7 .

[0070] Please refer to Figure 3 , a first gate material layer 205 and a plurality of protrusions 206 on the first gate material layer are formed on the substrate 200.

[0071] The material of the first gate material layer 205 comprises polysilicon. The first gate material layer 205 is used to form a first gate subsequently.

[0072] In this embodiment, the initial first gate material layer 205 further has first doped ions, which are N-type or P-type. The doping method of the doped ions comprises ion implantation. The first doped ions can adjust the threshold voltage of the semiconductor device formed subsequently.

[0073] The forming method of the first gate material layer 205 and the protrusions 206 comprises: forming an initial first gate material layer on the substrate 200; etching part of the initial first gate material layer to form a first gate material layer 205 and a plurality of protrusions 206 on the first gate material layer 205. The protrusions 206 are located on the top surface of the first gate formed subsequently.

[0074] In the embodiment, before forming the initial first gate material layer, a first gate dielectric material layer 207 is formed on the surface of the substrate 200.

[0075] The material of the first gate dielectric material layer 207 includes silicon oxide or high-K dielectric material. In the embodiment, the material of the first gate dielectric material layer 207 is silicon oxide. In other embodiments, the material of the first gate dielectric material layer 207 is high-K dielectric material. The first gate dielectric material layer 207 is used for subsequent formation of a first gate dielectric layer.

[0076] Please refer to Figure 4 The initial first hard mask layer 208 is formed on part of the first gate material layer 205 (for example, as shown in FIG. 2B), and the initial first hard mask layer 208 is located on the sidewall surface and the top surface of the protruding part 206. Figure 3 The first gate material layer 205 is etched with the initial first hard mask layer 208 as a mask to form the initial first gate 209.

[0077] The method for forming the initial first hard mask layer 208 includes: forming a first hard mask material layer on the first gate material layer 205, and etching the first hard mask material layer to expose part of the first gate material layer 205 to form the initial first hard mask layer 208.

[0078] The material of the initial first hard mask layer 208 includes one or more of insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride. The initial first hard mask layer 208 is used as a mask for forming the initial first gate, and is used for subsequent formation of a first hard mask layer.

[0079] The process for etching the first gate material layer 205 includes a dry etching process.

[0080] In the embodiment, the first gate material layer 205 is etched until the surface of the first region 201 is exposed, and the first gate dielectric material layer 207 (for example, as shown in FIG. 2B) is etched to form a first gate dielectric layer 210. In other embodiments, the first gate material layer 205 is etched until the surface of the first gate dielectric material layer 207 is exposed. Figure 3

[0081] Please refer to Figure 5 A first source-drain region 211 is formed in the first region 201 on both sides of the initial first gate 209, and the first source-drain region 211 has second doped ions therein. A first contact layer 212 is formed on the surface of the first source-drain region 211.

[0082] ​In this embodiment, the second doping ions are N-type ions. In other embodiments, the second doping ions are P-type ions. The channel is formed between the first source / drain regions 211 on both sides of the initial first gate 209, and the gate width direction is the length direction of the channel.

[0083] The material of the first contact layer 212 is a metal silicide.

[0084] The first contact layer 212 has a small resistance, which can reduce the contact resistance between the first source / drain regions 211 and the subsequently formed contact plug.

[0085] The forming process of the first contact layer 212 includes a self-aligned silicidation process.

[0086] Please refer to Figure 6 An interlayer dielectric layer 213 is formed on the surface of the substrate 200, and the interlayer dielectric layer 213 is also located on the sidewall surface of the initial first gate 209.

[0087] The forming method of the interlayer dielectric layer 213 includes: forming an interlayer dielectric material film on the surface of the substrate 200, the sidewall of the initial first gate 209, and the sidewall and top of the initial first hard mask layer 208 (as shown in Figure 5 The interlayer dielectric material film is planarized until the top surface of the protruding portion 206 is exposed, and the interlayer dielectric layer 213 is formed. In this embodiment, the interlayer dielectric layer 213 is also located on the surface of the first contact layer 212.

[0088] The interlayer dielectric layer 213 is used to isolate metal interconnection lines and devices in subsequent device manufacturing processes, reduce the parasitic capacitance between metal and substrate, and improve the parasitic field effect transistor formed by metal across different regions.

[0089] In this embodiment, the planarization process also includes planarizing the initial first hard mask layer 208 until the top surface of the protruding portion 206 is exposed, and the first hard mask layer 214 is formed.

[0090] In other embodiments, the planarization process will also thin the protruding portion.

[0091] After the initial first hard mask layer 208 is planarized, an initial first gate structure 215 is formed; the initial first gate structure 215 includes: the initial first gate 209, and the top surface of the initial first gate 209 has the first hard mask layer 214 and the protruding portion 206 located between the first hard mask layer 214. In this embodiment, the initial first gate structure 215 also includes the first gate dielectric layer 210.

[0092] The planarization process is a chemical mechanical polishing process.

[0093] Please refer to Figure 7 , etching the protrusion 206 (as shown in Figure 7 ) and the initial first gate 209 (as shown in Figure 6 ), forming at least one first gate opening 216 in the initial first gate structure 215 (as shown in Figure 6 ), forming a first gate structure 217 with the initial first gate structure 215, and forming a first gate 218 with the initial first gate 209.

[0094] The method for forming the first gate opening 216 further comprises: forming a patterned layer on the surface of the first hard mask layer 214 and the interlayer dielectric layer 213, the patterned layer exposing the protrusion 206, and etching the protrusion 206 and the initial first gate 209 with the patterned layer as a mask to form the first gate opening 216.

[0095] The first gate structure 217 comprises the first gate 218 and the first hard mask layer 214 on the top surface of the first gate 218. In this embodiment, the first gate structure 217 further comprises a first gate dielectric layer 210 between the first gate 218 and the first region 201.

[0096] The size of the first gate opening 216 along the gate width direction is less than or equal to 2 microns.

[0097] The depth of the first gate opening 216 in the first gate 218 is lower than the thickness of the first gate 218. Thus, the formed first gate 218 has a certain thickness, maintaining the performance of the polysilicon gate.

[0098] Please refer to Figure 8 , forming a second gate 219 in the first gate opening 216 (as shown in Figure 7 ), the material of the first gate being different from that of the second gate.

[0099] The method for forming the second gate 219 comprises: filling the first gate opening 216 with a second gate material layer; and planarizing the second gate material layer until the surface of the first gate structure 217 is exposed to form the second gate 219.

[0100] The process of filling the first gate opening 216 with a second gate material layer comprises atomic layer deposition process, physical vapor deposition process, or electroplating process, etc. In this embodiment, the process of filling the first gate opening 216 with a second gate material layer is atomic layer deposition process.

[0101] The material of the second gate 219 includes metals, such as copper, aluminum or tungsten.

[0102] Because the dimension of the first gate opening 216 along the gate width direction is less than or equal to 2 micrometers, the dimension of the second gate 219 along the gate width direction is less than or equal to 2 micrometers.

[0103] The resistivity of the second gate material is lower than that of the first gate material. Therefore, the gate on the first region composed of the first gate 218 and the second gate 219 has a lower resistivity. A gate with a lower resistivity can be obtained without running a metal silicide process to form a metal silicide layer on the surface of the first gate 218.

[0104] The first gate 218 is connected to the subsequently formed contact plug through the second gate 219. Since the resistivity of the second gate material is lower than that of the first gate material, it is not necessary to run the metal silicide process, thereby reducing the contact resistance between the first gate 214 and the contact plug.

[0105] The process for planarizing the second gate material layer includes a mechanical-chemical polishing process. In this embodiment, the first hard mask layer 214 located on the top surface of the first gate 218 has a relatively high hardness compared to the material of the first gate 218, thus protecting the first gate 218 during the polishing process.

[0106] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 8 The system includes: a substrate 200, the substrate including a first region 201; a first gate structure 217 located on the first region 201, the first gate structure 217 including a first gate 218 and a first hard mask layer 214 located on the first gate 218, the first gate structure 217 having at least one first gate opening 216 (e.g., ...). Figure 7 (as shown); a second gate 219 is located within the first gate opening 216, and the material of the second gate 219 is different from the material of the first gate 218.

[0107] The resistivity of the material of the second gate 219 is lower than that of the material of the first gate 218.

[0108] The material of the second gate 219 includes metal; the material of the first gate 218 includes polysilicon.

[0109] The first gate 219 contains a first doped ion, which is an N-type ion or a P-type ion.

[0110] The semiconductor structure further comprises: a first source / drain region 211 in the first region 201 on both sides of the first gate structure 217, the first source / drain region 211 having second doping ions therein.

[0111] The semiconductor structure further comprises: a first contact layer 212 on the surface of the first source / drain region 211; the material of the first contact layer 212 is a metal silicide layer.

[0112] The size of the first gate opening 216 along the gate width direction is less than or equal to 2 microns.

[0113] The number of the first gate opening 216 in each of the first gate structure 217 is greater than one.

[0114] The depth of the first gate opening 216 in the first gate 219 is lower than the thickness of the first gate 219.

[0115] The first gate structure 217 further comprises: a first gate dielectric layer 210 between the first gate 218 and the first region 201.

[0116] The material of the first gate dielectric layer 210 comprises silicon oxide or high-K dielectric material.

[0117] The material of the first hard mask layer 214 comprises one or more of the following insulating materials: silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0118] Figures 9 to 15 The cross-sectional structure of each step in the semiconductor structure forming method of another embodiment of the present application is shown in the following figures.

[0119] Please refer to Figure 9 , a substrate 300 is provided, which comprises a first region 301 and a second region 302.

[0120] In this embodiment, the first region 301 is used to form a first region device; the second region 302 is used to form a second region device.

[0121] The substrate 300 further comprises: a base 303, a deep well 304 in the substrate 300, and an insulating isolation structure 305 on the upper part of the substrate 300. The isolation structure is used to achieve electrical insulation between different semiconductor devices. The deep well 304 is used to isolate the noise generated by the subsequent device formed on the substrate from the outside.

[0122] The material of the base 303 comprises single crystal silicon, and the material of the isolation structure 305 comprises silicon oxide.

[0123] In the embodiment, the deep well 304 is N-type well, and the forming method comprises: implanting phosphorus ions into the substrate along the direction perpendicular to the substrate 200, the implantation energy is 1KeV-3000KeV, and the implantation dose is 10 12 cm -2 -10 14 cm -2 , so as to form the deep well 304. In other embodiments, the deep well is formed by implanting boron ions into the substrate to form P-type well.

[0124] Then, the initial first gate structure is formed on the first region 301, and the initial first gate structure comprises an initial first gate, and the top surface of the initial first gate has a first hard mask layer and a protrusion between the first mask layer; and the pseudo gate structure is formed on the second region 302, and the pseudo gate structure comprises a pseudo gate. The forming process of the initial first gate structure and the pseudo gate structure is shown in Figures 10 to 14 .

[0125] Please refer to Figure 10 , the first gate material layer 306 and the plurality of protrusions 307 on the first gate material layer 306 are formed on the substrate 300.

[0126] The material of the first gate material layer 306 comprises polysilicon. The first gate material layer 306 is used for forming the first gate on the first region 301 and the pseudo gate on the second region 302.

[0127] In the embodiment, the first gate material layer 306 on the first region 301 further has first doped ions, and the first doped ions are N-type or P-type.

[0128] The doping method of the doped ions comprises: forming a mask layer on the surface of the first gate material layer 306 on the second region 302, and the mask layer exposes the first gate material layer on the first region 301; and implanting the first doped ions into the first gate material layer 306 on the first region 301. The first doped ions can adjust the threshold voltage of the subsequently formed first gate.

[0129] The forming method of the first gate material layer 306 and the protrusions 307 comprises: forming an initial first gate material layer on the substrate 300; etching part of the initial first gate material layer to form the first gate material layer 306 and the plurality of protrusions 307 on the first gate material layer 306. The protrusions 307 are located on the top surface of the subsequently formed first gate.

[0130] In this embodiment, the method further includes: forming a second gate dielectric material layer 309 on the substrate 300 before the initial first gate material layer 306 is formed; and forming a first gate oxide material layer 308 on the first region 301 before the second gate dielectric material layer 309 is formed.

[0131] The second gate dielectric material layer 309 is made of a high-k dielectric material. The high-k (i.e., dielectric constant K ≥ 3.9) dielectric layer significantly reduces the quantum tunneling effect of the gate dielectric layer. The high-k dielectric material includes HfO2. The second gate dielectric material layer 309 is used for the subsequent formation of the first gate dielectric layer and the second gate dielectric layer. The second gate dielectric material layer 309 significantly reduces the quantum tunneling effect of the dielectric layer, thereby effectively improving the leakage current of the first gate and the second gate and the resulting power consumption. The first gate oxide material layer 308 is used to improve the interface states between the first gate dielectric layer and the first region 301.

[0132] In other embodiments, a second gate oxide layer is provided between the surface of the second region and the initial second gate dielectric layer. The material of the second gate oxide layer includes silicon oxynitride, which aims to improve the interface states between the high-k dielectric material and the substrate silicon. In other embodiments, a metal compound layer is provided between the second gate dielectric layer and the first gate material layer. The material of the metal compound layer includes titanium nitride, which is used to adjust the threshold voltage of the subsequently formed device.

[0133] Please refer to Figure 11 In part of the first gate material layer 306 (e.g. Figure 10 An initial first hard mask layer 310 is formed on the first region 301, and the initial first hard mask layer 310 is located on the sidewall surface and the top surface of the protrusion 307; while forming the initial first hard mask layer 310 on the first region 301, a second hard mask layer 311 is also formed on the second region 302; the first gate material layer 306 is etched with the initial first hard mask layer 310 as a mask to form the initial first gate 312; the first gate material layer 306 is etched with the second hard mask layer 311 as a mask to form the dummy gate 313.

[0134] The method for forming the initial first hard mask layer 310 and the second hard mask layer 311 includes: forming a first hard mask material layer on the first gate material layer 306, etching the first hard mask material layer to expose a portion of the surface of the first gate material layer 306, and forming the initial first hard mask layer 310 on the first region 301 and the second hard mask layer 311 on the second region 302, respectively.

[0135] The material of the first hard mask material layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride. The initial first hard mask layer 310 is used as a mask for forming an initial first gate, and is used for subsequent formation of a first hard mask layer; and the second hard mask layer 311 is used as a mask for forming a dummy gate.

[0136] The dummy gate structure 316 includes the dummy gate 313 and the second hard mask layer 311 on the dummy gate 313.

[0137] The etching process of the first gate material layer 306 includes a dry etching process.

[0138] In this embodiment, the first gate material layer 306 is etched until the surface of the first region 301 is exposed, and the second gate dielectric material layer 309 (as shown in Figure 10 ) is etched to form a first gate dielectric layer 314, and the first gate oxide material layer 308 is etched to form a first gate oxide layer (not marked in the figure). In other embodiments, the first gate material layer 306 is etched until the surface of the second gate dielectric material layer 309 is exposed.

[0139] In this embodiment, the dummy gate structure 316 further includes a second gate dielectric layer 315; and the method for forming the second gate dielectric layer 315 includes: etching the first gate material layer 306 until the surface of the second region 302 is exposed; and etching the second gate dielectric material layer 309 (as shown in Figure 10 ) to form the second gate dielectric layer 315. In this embodiment, the first hard mask layer 310, the initial first gate 312, the first gate dielectric layer 314, the first gate oxide layer, the second hard mask layer 311, and the dummy gate 313 are formed in the same process, thereby saving process steps and reducing production costs.

[0140] Please refer to Figure 12 , a first source / drain region 317 having second doping ions is formed in the first region 301 on both sides of the initial first gate 312, a second source / drain region 318 having third doping ions is formed in the second region on both sides of the dummy gate 313, a first contact layer 319 is formed on the surface of the first source / drain region 317, and a second contact layer 400 is formed on the surface of the second source / drain region 318.

[0141] In this embodiment, the second doping ions are N-type ions. In other embodiments, the second doping ions are P-type ions. The region between the first source / drain regions 317 and below the initial first gate 312 forms a channel of the first region device, and the direction of the gate width direction indicates the length direction of the channel.

[0142] In this embodiment, the third doping ions are N-type ions. In other embodiments, the third doping ions are P-type ions. The regions between the second source-drain regions 318 and below the dummy gate 313 form the channels of the second region devices, and the direction of the gate width direction indicates the channel length direction.

[0143] The material of the first contact layer 319 is metal silicide. The first contact layer 319 has a small resistance, which can reduce the contact resistance between the first source-drain regions 317 and the subsequently formed conductive plugs.

[0144] The material of the second contact layer 400 is metal silicide. The second contact layer 400 has a small resistance, which can reduce the contact resistance between the second source-drain regions 318 and the subsequently formed conductive plugs, respectively.

[0145] The formation process of the first contact layer 319 includes a self-aligned silicidation process; the formation process of the second contact layer 400 includes a self-aligned silicidation process. In this embodiment, the first contact layer 319 and the second contact layer 400 are formed in the same process, which reduces the process and saves production costs.

[0146] Please refer to Figure 13 , the interlayer dielectric layer 320 is formed on the surface of the substrate 300, and the interlayer dielectric layer 320 is also located on the sidewall surface of the initial first gate 312 and the dummy gate 313.

[0147] The initial first gate structure 321 includes the initial first gate 312, and the top surface of the initial first gate 312 has the first hard mask layer 322 and the protruding part 307 located between the first hard mask layer 322. In this embodiment, the initial first gate structure 321 also includes the first gate dielectric layer 314 and the first gate oxide layer (not labeled in the figure) located between the first gate dielectric layer 314 and the first region 301.

[0148] The formation method of the interlayer dielectric layer 320 and the first hard mask layer 322 includes: forming an interlayer dielectric material film on the surface of the substrate 300, the sidewall of the initial first gate 312, the sidewall and top of the initial first hard mask layer 310 (as shown in Figure 12 ), and the sidewall and top of the dummy gate structure 316 (as shown in Figure 12 ).

[0149] The interlayer dielectric layer 320 is used to isolate the metal interconnection lines and the device in the subsequent device manufacturing process, to reduce the parasitic capacitance between the metal and the substrate, and to improve the formation of parasitic field effect transistors across different regions.

[0150] The planarization process further includes planarizing the initial first hard mask layer 310 and the second hard mask layer 311 (as shown in FIG. 3B) until the top surface of the protrusion 307 (as shown in FIG. 3C) and the top surface of the dummy gate 313 are exposed, thereby forming the first hard mask layer 322. In this embodiment, the planarization process thins the protrusion 307. In other embodiments, the planarization process does not thin the protrusion. Figure 12 Figure 12

[0151] The planarization process is a mechanical chemical polishing process. The protrusion 307 has a dimension along the gate width direction that is less than or equal to 2 microns. In a mechanical chemical polishing process, large size patterns are prone to "dishing" defects in the middle portion. The larger the size of the polished area, the more prone to "dishing" defects in the mechanical chemical polishing process, and the deeper the "dishing" defects, which can even result in the polished area being polished away. In the planarization process, the protrusion 307 has a small size, so it is not prone to "dishing" defects, thereby protecting the initial first gate 312 and the subsequently formed first gate. In the planarization process, the protrusion 307 can be thinned, but as long as part of the protrusion 307 remains, the initial first gate 312 will not be polished away. In addition, in the planarization process, the protrusion 307 is higher than the dummy gate 313, so the initial first gate 312 is also not prone to being polished away.

[0152] Referring to FIG. 3D, the protrusion 307 (as shown in FIG. 3C) and the initial first gate 312 (as shown in FIG. 3D) are etched to form at least one first gate opening 323 in the initial first gate structure 321 (as shown in FIG. 3E), thereby forming a first gate structure 324 from the initial first gate structure 321, and a first gate 325 from the initial first gate 312. The dummy gate 313 (as shown in FIG. 3E) is removed to form a second gate opening 326 in the interlayer dielectric layer. Figure 14 Figure 13 Figure 13 Figure 13 Figure 13

[0153] ​​​​​​​The method for forming the first gate opening 323 further includes: forming a patterned layer on the surface of the first hard mask layer 322 and the interlayer dielectric layer 320, wherein the patterned layer exposes the protrusion 307; and etching the protrusion 307 and the initial first gate 312 using the patterned layer as a mask to form the first gate opening 323.

[0154] The first gate structure 324 includes a first gate 325 and a first hard mask layer 322 located on the top surface of the first gate 325. In this embodiment, the first gate structure 325 further includes a first gate dielectric layer 314 located between the first gate 325 and the first region 301, and a first gate oxide layer (not shown in the figure) located between the first gate dielectric layer 314 and the first region 301.

[0155] The first gate opening 323 has a dimension of less than or equal to 2 micrometers along the gate width direction.

[0156] The depth of the first gate opening 323 within the first gate 312 is less than the thickness of the first gate 312. This allows the formed first gate 312 to have a certain thickness, maintaining its polysilicon gate performance.

[0157] Please refer to Figure 15 In the first gate opening 323 (e.g. Figure 14 While forming the second gate 327 within the second gate opening 326 (as shown), a second gate opening 326 is also formed within the second gate opening 327. Figure 14 A third gate 328 is formed inside (as shown).

[0158] The second gate structure 329 includes a third gate 328 and a second gate dielectric layer 315 located between the third gate 328 and the second region 302.

[0159] The method for forming the second gate 327 and the third gate 328 includes: forming a second gate material layer on the surface of the interlayer dielectric layer 320, inside the first gate opening 323 and inside the second gate opening 326; planarizing the second gate material layer until the surface of the interlayer dielectric layer 320 is exposed, thereby forming the second gate 327 and the third gate 328.

[0160] The process for forming the second gate material layer includes atomic layer deposition, physical vapor deposition, or electroplating. In this embodiment, the process for forming the second gate material layer is atomic layer deposition.

[0161] The materials of the second gate 327 and the third gate 328 include metals, such as copper, aluminum or tungsten.

[0162] Because the size of the first gate opening 323 along the gate width direction is less than or equal to 2 microns, the size of the second gate 327 along the gate width direction is less than or equal to 2 microns. The performance of the gate formed by the first gate and the second gate can be changed by changing the number of the first gate openings 323, the size of the first gate opening 323, and the performance of the second gate material filled in the first gate opening 323, so as to obtain a more optimized gate structure.

[0163] The resistivity of the second gate material is lower than that of the first gate material, so that the gate on the first region formed by the first gate 325 and the second gate 327 has a lower resistivity, and a metal silicide process is not required to form a metal silicide layer on the surface of the first gate 325 to obtain a gate with a lower resistivity.

[0164] The first gate 325 is connected to the contact plug formed subsequently through the second gate 327. Since the resistivity of metal is lower than that of polysilicon, the gate structure formed by the first gate 325 and the second gate 327 has a lower contact resistance with the contact plug, and a metal silicide process is not required to form a low-resistance contact layer on the surface of the first gate 325, thereby saving process steps.

[0165] The process of planarizing the second gate material layer includes a mechanical chemical polishing process. In the embodiment, the first hard mask layer 322 located on the top surface of the first gate 325 protects the first gate 325 during the polishing process because the hardness of the first hard mask layer 322 is relatively large compared to the material of the first gate 312. In other embodiments, the first hard mask layer 322 can be polished away during the polishing process, and the upper part of the first gate 325 is exposed. Since part of the upper part of the first gate 325 is replaced by the second gate material, the size of the gate material exposed on the surface of the upper part of the first gate 325 is relatively small due to the presence of the second gate 327. The smaller the size, the less likely it is to cause "dishing" defects on the surface of the first gate 325, further inhibiting the occurrence of the first gate 325 polysilicon gate material layer being polished away, and thus improving the performance of the device.

[0166] Correspondingly, another embodiment of the present application also provides a semiconductor structure formed by the above forming method, please continue to refer to Figure 15 , comprising: a substrate 300, the substrate comprising a first region 301 and a second region 302; a first gate structure 324 located on the first region 301, the first gate structure 324 comprising a first gate 325 and a first hard mask layer 322 located on the first gate 325, the first gate structure 324 having at least one first gate opening 323 (such as Figure 14the first gate structure 324 includes a first gate 325; the first gate 325 has a first gate opening 323; the first gate 325 is located in the first region 301; the first gate 325 has a first gate material; the first gate material is different from a second gate material of a second gate 327 located in the first gate opening 323; the semiconductor structure further includes a second gate structure 329 located on the second region 302.

[0167] The first gate material has a resistivity lower than a resistivity of the second gate material.

[0168] The first gate material includes a metal; the second gate material includes polysilicon.

[0169] The first gate 325 has a first doping ion; the first doping ion is an N-type ion or a P-type ion.

[0170] The semiconductor structure further includes a first source-drain region 317 located in the first region 301 on both sides of the first gate structure 324; the first source-drain region 317 has a second doping ion.

[0171] The second gate structure 329 includes a third gate 328; the third gate 328 has a third gate material; the third gate material includes a metal.

[0172] The semiconductor structure further includes a first contact layer 319 located on a surface of the first source-drain region 317; the first contact layer 319 has a first contact material; the first contact material is a metal silicide layer.

[0173] The second gate structure 329 further includes a second gate dielectric layer 315 located between the third gate 328 and the second region 302.

[0174] The second gate dielectric layer 315 has a second gate dielectric material; the second gate dielectric material includes a high-K dielectric material.

[0175] The second gate structure 329 further includes an oxide layer located between the second region 302 and the second gate dielectric layer 315; a metal compound layer located between the second gate dielectric layer 315 and the third gate 328.

[0176] A second source-drain region 318 located in the second region on both sides of the second gate structure 329 respectively; the second source-drain region 318 has a second doping ion.

[0177] The semiconductor structure further includes a second contact layer 400 located on a surface of the second source-drain region 318; the second contact layer 400 has a second contact material; the second contact material is a metal silicide layer.

[0178] The first gate opening 323 has a dimension along a gate width direction less than or equal to 2 microns.

[0179] The first gate structure 324 includes a plurality of the first gate openings 323.

[0180] The first gate opening 323 has a depth within the first gate 325 that is less than a thickness of the first gate 325.

[0181] The first gate structure 324 further includes a first gate dielectric layer 314 between the first gate 325 and the first region 301.

[0182] The material of the first gate dielectric layer 314 includes silicon oxide.

[0183] The material of the first hard mask layer 322 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0184] Although the present application has been disclosed with reference to the above embodiments, the application is not limited to the above embodiments. Any modifications and changes can be made without departing from the spirit and scope of the application. The scope of the application should be defined by the appended claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The application comprises: providing a substrate, the substrate comprising a first region; forming an initial first gate structure on the first region, the initial first gate structure comprising an initial first gate, a top surface of the initial first gate having a first hard mask layer and a protrusion between the first hard mask layer, a dimension of the protrusion along a gate width direction being less than or equal to 2 microns; forming an interlayer dielectric layer on the substrate surface, the interlayer dielectric layer being on a sidewall surface of the initial first gate structure; etching the protrusion and the initial first gate to form at least one first gate opening in the initial first gate structure, to form a first gate structure from the initial first gate structure, to form a first gate from the initial first gate, and the first hard mask layer having a hardness greater than a hardness of the first gate; filling the first gate opening with a second gate material layer; planarizing the second gate material layer using a mechanical chemical polishing process until a surface of the first gate structure is exposed, to form a second gate in the first gate opening, the first gate having a material different from a material of the second gate.

2. The method of forming a semiconductor structure of claim 1, wherein, The material of the first gate comprises polysilicon; the material of the second gate comprises metal.

3. The method of forming a semiconductor structure of claim 1, wherein, The method for forming the protrusion comprises: forming an initial first gate material layer on the substrate; etching part of the initial first gate material layer to form a first gate material layer and a plurality of protrusions on the first gate material layer.

4. The method of forming a semiconductor structure of claim 3, wherein, The first gate material layer further has doped ions, the doped ions being N-type or P-type.

5. The method of forming a semiconductor structure of claim 3, wherein, The method for forming the initial first gate structure comprises: forming an initial first hard mask layer on part of the first gate material layer, the initial first hard mask layer being on sidewall surfaces and a top surface of the protrusions; etching the first gate material layer using the initial first hard mask layer as a mask to form the initial first gate; after forming the initial first gate, planarizing the initial first hard mask layer until the top surface of the protrusion is exposed to form the first hard mask layer.

6. The method of forming a semiconductor structure of claim 1, wherein, Further comprising: before forming the first gate opening, forming an interlayer dielectric layer on the substrate surface, the interlayer dielectric layer further being on sidewall surfaces of the initial first gate structure, and the interlayer dielectric layer exposing the first hard mask layer and the top surface of the protrusion.

7. The method of forming a semiconductor structure of claim 6, wherein, The method for forming the interlayer dielectric layer comprises: forming an interlayer dielectric material film on the substrate surface, sidewalls of the initial first gate, and sidewalls and a top of the initial first hard mask layer; planarizing the interlayer dielectric material film until the top surface of the protrusion is exposed to form the interlayer dielectric layer.

8. The method of forming a semiconductor structure of claim 1, wherein, The first gate structure further comprises: a first gate dielectric layer between the first gate and a surface of the first region.

9. The method of forming a semiconductor structure of claim 1, wherein, The second gate material is metal.

10. The method of forming a semiconductor structure of claim 1, wherein, Before forming the initial first gate structure, and after forming the initial first gate, further comprising: forming a first source-drain region in the first region on both sides of the initial first gate, the first source-drain region having second doped ions.

11. The method of forming a semiconductor structure of claim 10, wherein Further comprising: forming a first contact layer on a surface of the first source-drain region; The material of the first contact layer is metal silicide.

12. The method of forming a semiconductor structure of claim 11, wherein, The forming process of the first contact layer includes a self-aligned silicide process.

13. The method of forming a semiconductor structure of claim 6, wherein Further comprising: The substrate further comprises a second region; a second gate structure is formed on part of the second region, the second gate structure comprises a third gate, and the material of the third gate is the same as that of the second gate.

14. The method of forming a semiconductor structure of claim 13, wherein, The second gate structure further comprises a second gate dielectric layer between the third gate and the substrate.

15. The method of forming a semiconductor structure of claim 14, wherein, The material of the second gate dielectric layer comprises a high-K dielectric material.

16. The method of forming a semiconductor structure of claim 13, wherein, The forming method of the second gate structure comprises: forming a second gate opening in the interlayer dielectric layer on the second region; and forming a third gate in the second gate opening.

17. The method of forming a semiconductor structure of claim 16, wherein, The third gate is formed in the second gate opening at the same time when the second gate is formed in the first gate opening; the forming method of the second gate and the third gate comprises: forming a second gate material layer on the surface of the interlayer dielectric layer, in the first gate opening and in the second gate opening; and planarizing the second gate material layer until the surface of the interlayer dielectric layer is exposed, thereby forming the second gate and the third gate.

18. The method of forming a semiconductor structure of claim 17, wherein, The planarization process of the gate material layer is a mechanical chemical polishing process.

19. The method of forming a semiconductor structure of claim 16, wherein, The forming method of the second gate opening comprises: forming a dummy gate structure on the second region before forming the interlayer dielectric layer, the dummy gate structure comprises a dummy gate; the interlayer dielectric layer is further located on the sidewall of the dummy gate structure and exposes the top surface of the dummy gate; and the dummy gate is removed to form the second gate opening in the interlayer dielectric layer.

20. The method of forming a semiconductor structure of claim 19, wherein, The dummy gate and the initial first gate structure are formed at the same time, and the forming method of the dummy gate comprises: forming a second hard mask layer on the second region at the same time when forming an initial first hard mask layer on the first region; and etching the first gate material layer with the second hard mask layer as a mask to form the dummy gate.

21. A semiconductor structure, comprising: Formed by using the forming method of the semiconductor structure according to any one of claims 1 to 20, comprising: A substrate, the substrate comprises a first region; A first gate structure on the first region, the first gate structure comprises a first gate and a first hard mask layer on the first gate, and the first gate structure has at least one first gate opening, the size of the first gate opening along the gate width direction is less than or equal to 2 microns, and the hardness of the first hard mask layer is greater than that of the first gate; An interlayer dielectric layer on the surface of the substrate, the interlayer dielectric layer is further located on the sidewall surface of the first gate; A second gate in the first gate opening, and the material of the second gate is different from that of the first gate.

22. The semiconductor structure of claim 21, wherein, The resistivity of the material of the second gate is lower than that of the material of the first gate.

23. The semiconductor structure of claim 22, wherein, The material of the second gate comprises a metal; and the material of the first gate comprises polysilicon.

24. The semiconductor structure of claim 23, wherein, The first gate has first doping ions; and the first doping ions are N-type ions or P-type ions.

25. The semiconductor structure of claim 21, wherein, Further comprising: First source / drain regions in the first region on both sides of the first gate structure; the first source / drain regions have second doping ions.

26. The semiconductor structure of claim 25, wherein, Further comprising: a first contact layer on a surface of the first source / drain region; a material of the first contact layer is a metal silicide layer.

27. The semiconductor structure of claim 21, wherein, the substrate further includes a second region.

28. The semiconductor structure of claim 27, wherein, further comprising: a second gate structure on the second region.

29. The semiconductor structure of claim 28, wherein, the second gate structure includes a third gate; a material of the third gate includes a metal.

30. The semiconductor structure of claim 29, wherein, the second gate structure further includes a second gate dielectric layer between the third gate and the second region.

31. The semiconductor structure of claim 30, wherein, a material of the second gate dielectric layer includes a high-K dielectric material.

32. The semiconductor structure of claim 31, wherein, the second gate structure further includes an oxidation layer between the second region and the second gate dielectric layer; a metal compound layer between the second gate dielectric layer and the third gate.

33. The semiconductor structure as described in claim 28, characterized in that, further comprising: a second source / drain region in the second region on both sides of the second gate structure; the second source / drain region has second doping ions therein.

34. The semiconductor structure of claim 33, wherein, further comprising: a second contact layer on a surface of the second source / drain region; a material of the second contact layer is a metal silicide.

35. The semiconductor structure of claim 21, wherein, a number of the first gate openings in each of the first gate structures is greater than one.

36. The semiconductor structure of claim 21, wherein, a depth of the first gate opening in the first gate is lower than a thickness of the first gate.

37. The semiconductor structure of claim 21, wherein, the first gate structure further includes a first gate dielectric layer between the first gate and the first region.

38. The semiconductor structure of claim 37, wherein, a material of the first gate dielectric layer includes silicon oxide or a high-K dielectric material.

39. The semiconductor structure of claim 21, wherein, a material of the first hard mask layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

Images