Semiconductor Structure and Method for Forming the Same

Abstract

A semiconductor structure and a method for forming the same, comprising: a substrate, the substrate including an isolation region and a device region, the isolation region including a first region and a second region; a plurality of first fin portions and a plurality of second fin portions located on the device region, the first fin portions further spanning the isolation region, and an isolation opening located on the isolation region being formed within the second fin portions; a plurality of first gate structures formed on the isolation region; a first opening located on the first region; and an isolation structure located within the first opening. The first gate structures provide stress requirements for the second fin portions; the isolation structures provide stress requirements for the first fin portions. By forming the first gate structures and the isolation structures in different steps, different types of stress can be generated in the first fin portions and the second fin portions finally, so as to meet the requirements of different types of transistors, thereby improving the performance of the finally formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the improvement of the integration degree of semiconductor devices, the critical dimensions of transistors are continuously reduced. However, with the sharp reduction of transistor sizes, the thickness of the gate dielectric layer and the operating voltage cannot be changed correspondingly, which increases the difficulty of suppressing the short-channel effect and increases the channel leakage current of the transistor.

[0003] The gate of a fin field-effect transistor (FinFET) forms a fork-shaped 3D structure similar to a fish fin. The channel of the FinFET protrudes from the substrate surface to form fins, and the gate covers the top surface and side walls of the fins, so that an inversion layer is formed on each side of the channel, and the on and off of the circuit can be controlled on both sides of the fins. This design can increase the control of the gate over the channel region, thereby being able to well suppress the short-channel effect of the transistor. However, the fin field-effect transistor still has the short-channel effect.

[0004] In addition, in order to further reduce the influence of the short-channel effect on semiconductor devices and reduce the channel leakage current. The semiconductor technology field has introduced the strained silicon technology, and the methods of the strained silicon technology include: forming grooves in the fins on both sides of the gate structure; forming source / drain doping regions in the grooves through an epitaxial growth process.

[0005] In order to prevent the source / drain doping regions of different transistors from being connected to each other, an isolation layer needs to be formed in the fins. At the same time, in order to reduce the area of the isolation layer and improve the integration degree of the formed semiconductor structure. The prior art has introduced the SDB (Single Diffusion Break) technology.

[0006] However, there are still many problems in the process of forming a semiconductor structure by the existing methods. Summary of the Invention

[0007] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0008] To solve the above problems, the present invention provides a semiconductor structure, including: a substrate, the substrate includes isolation regions and a plurality of device regions arranged along a first direction, the isolation regions are located between adjacent device regions, the isolation regions include a first region and a second region arranged along a second direction, the second direction is perpendicular to the first direction; a plurality of first fin portions and a plurality of second fin portions located on the device regions, the plurality of first fin portions and the plurality of second fin portions are both parallel to the first direction and arranged along the second direction, the first fin portions also span across the isolation regions, there is an isolation opening located on the isolation regions within the second fin portions, the isolation opening penetrates through the second fin portions along the second direction; a plurality of first gate structures formed on the isolation regions, the first gate structures span across the first fin portions and the second fin portions along the second direction; a first opening located on the first region, the first opening is also located between adjacent first gate structures, and the bottom surface of the first opening is lower than the top surface of the first fin portions; an isolation structure located within the first opening.

[0009] Optionally, it further includes: a plurality of second gate structures located on the device regions, the second gate structures span across the first fin portions and the second fin portions along the second direction.

[0010] Optionally, it further includes: a plurality of first source / drain doping layers located within the first fin portions, the first source / drain doping layers are located between adjacent second gate structures, or between adjacent first gate structures and second gate structures, and there are first source / drain ions within the first source / drain doping layers; a plurality of second source / drain doping layers are formed within the second fin portions, the second source / drain doping layers are located between adjacent second gate structures or between adjacent first gate structures and second gate structures, and there are second source / drain ions within the second source / drain doping layers.

[0011] Optionally, the first source / drain ions and the second source / drain ions have different electrical types; the first source / drain ions include N-type ions or P-type ions; the second source / drain ions include P-type ions or N-type ions.

[0012] Optionally, it further includes: a first conductive layer located on the first source / drain doping layer and a first protective layer located on the first conductive layer; a second conductive layer located on the second source / drain doping layer and a second protective layer located on the second conductive layer.

[0013] Optionally, the material of the isolation structure includes silicon nitride.

[0014] Optionally, it further includes: a dielectric layer located on the substrate, the dielectric layer covers the sidewalls of the first gate structures and the second gate structures.

[0015] Optionally, it further includes: an isolation layer located on the substrate, the isolation layer covering partial sidewalls of the first fin and the second fin, and a top surface of the isolation layer being lower than top surfaces of the first fin and the second fin.

[0016] Correspondingly, the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including isolation regions and a plurality of device regions arranged along a first direction, the isolation regions being located between adjacent device regions, the isolation regions including a first region and a second region arranged along a second direction, the second direction being perpendicular to the first direction; forming a plurality of first fins and a plurality of second fins on the device regions, the plurality of first fins and the plurality of second fins being parallel to the first direction and arranged along the second direction, the first fins further spanning across the isolation regions, and an isolation opening located on the isolation regions being formed in the second fins, the isolation opening penetrating through the second fins along the second direction; forming a plurality of first gate structures on the isolation regions, the first gate structures spanning across the first fins and the second fins along the second direction; forming a first opening on the first region, the first opening further being located between adjacent first gate structures, and a bottom surface of the first opening being lower than a top surface of the first fins; and forming an isolation structure in the first opening.

[0017] Optionally, during the process of forming the first gate structures, it further includes: forming a plurality of second gate structures on the device regions, the second gate structures spanning across the first fins and the second fins along the second direction.

[0018] Optionally, before forming the first gate structures and the second gate structures, it further includes: forming a plurality of first source / drain doping layers in the first fins, the first source / drain doping layers being located between adjacent first gate structures, or between adjacent second gate structures, or between adjacent first gate structures and second gate structures, and first source / drain ions being included in the first source / drain doping layers; and forming a plurality of second source / drain doping layers in the second fins, the second source / drain doping layers being located between adjacent second gate structures, or between adjacent first gate structures and second gate structures, and second source / drain ions being included in the second source / drain doping layers.

[0019] Optionally, the first source / drain ions and the second source / drain ions are of different electrical types; the first source / drain ions include N-type ions or P-type ions; and the second source / drain ions include P-type ions or N-type ions.

[0020] Optionally, before forming the first source / drain doping layer and the second source / drain doping layer, the method further includes: forming a plurality of first dummy gate structures on the isolation region, the first dummy gate structures straddling the first fin and the second fin; forming a plurality of second dummy gate structures on the device region, the second dummy gate structures straddling the first fin and the second fin.

[0021] Optionally, the method for forming the first source / drain doping layer and the second source / drain doping layer includes: etching the first fin using the first dummy gate structures and the second dummy gate structures as masks to form a plurality of first source / drain openings in the first fin; etching the second fin using the first dummy gate structures and the second dummy gate structures as masks to form a plurality of second source / drain openings in the second fin; forming the first source / drain doping layer in the first source / drain openings; forming the second source / drain doping layer in the second source / drain openings.

[0022] Optionally, the method for forming the first source / drain doping layer in the first source / drain openings includes: forming a first epitaxial layer in the first source / drain openings using an epitaxial growth process; doping the first source / drain ions into the first epitaxial layer using an in-situ doping process during the formation of the first epitaxial layer to form the first source / drain doping layer.

[0023] Optionally, the method for forming the second source / drain doping layer in the second source / drain openings includes: forming a second epitaxial layer in the second source / drain openings using an epitaxial growth process; doping the second source / drain ions into the second epitaxial layer using an in-situ doping process during the formation of the second epitaxial layer to form the second source / drain doping layer.

[0024] Optionally, after forming the first source / drain doping layer and the second source / drain doping layer, the method further includes: forming a dielectric layer on the substrate, the dielectric layer covering the sidewalls of the first gate structure and the second gate structure.

[0025] Optionally, the method for forming the dielectric layer includes: forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first source / drain doping layer, the second source / drain doping layer, the first dummy gate structures, and the second dummy gate structures; performing a planarization process on the initial dielectric layer until the top surfaces of the first dummy gate structures and the second dummy gate structures are exposed, to form the dielectric layer.

[0026] Optionally, the method for forming the first gate structure and the second gate structure includes: removing the first dummy gate structures to form a first gate opening in the dielectric layer; forming the first gate structure in the first gate opening; removing the second dummy gate structures to form a second gate opening in the dielectric layer; forming the second gate structure in the second gate opening.

[0027] Optionally, before forming the first opening, the method further includes: removing a part of the dielectric layer and a part of the first source / drain doping layer on the first source / drain doping layer to form a first conductive opening; removing a part of the dielectric layer and a part of the second source / drain doping layer on the second source / drain doping layer to form a second conductive opening; forming a first conductive layer in the first conductive opening and a first protective layer on the first conductive layer; forming a second conductive layer in the second conductive opening and a second protective layer on the second conductive layer.

[0028] Optionally, the method for forming the first opening includes: removing the first protective layer, the first conductive layer, and the first fin on the first region, and forming the first opening in the adjacent first gate structure and the first fin.

[0029] Optionally, the method for forming the isolation structure includes: forming an initial isolation structure in the first opening, on the first gate structure, and on the dielectric layer; performing a planarization process on the initial isolation structure until the top surfaces of the first gate structure and the dielectric layer are exposed, and forming the isolation structure in the first opening.

[0030] Optionally, the material of the isolation structure includes silicon nitride.

[0031] Optionally, the method for forming the second fin includes: forming a plurality of initial second fins arranged in parallel along the second direction on the substrate; forming a patterned layer on the substrate to expose a part of the initial second fins; etching the initial second fins using the patterned layer as a mask until the top surface of the substrate is exposed, and forming the second fin.

[0032] Optionally, after forming the first fin and the second fin, the method further includes: forming an isolation layer on the substrate, the isolation layer covering a part of the sidewalls of the first fin and the second fin, and the top surface of the isolation layer being lower than the top surfaces of the first fin and the second fin.

[0033] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0034] In the structure of the technical solution of the present invention, a plurality of first gate structures are located on the isolation region. The first gate structures straddle the second fin portion, and stress requirements are provided for the second fin portion through the first gate structures; a first opening is located on the first region, and the first opening is also located between adjacent first gate structures and within the first fin portion; an isolation structure is located within the first opening, and stress requirements are provided for the first fin portion through the isolation structure. By forming the first gate structures and the isolation structure in different steps, different types of stress can be generated in the first fin portion and the second fin portion finally, so as to meet the requirements of different types of transistors, and further improve the performance of the finally formed semiconductor structure.

[0035] In the forming method of the technical solution of the present invention, a plurality of first gate structures are formed on the isolation region. The first gate structures straddle the second fin portion, and stress requirements are provided for the second fin portion through the first gate structures; a first opening is formed on the first region, the first opening is located between adjacent first gate structures and within the first fin portion, and an isolation structure is formed within the first opening, and stress requirements are provided for the first fin portion through the isolation structure. By forming the first gate structures and the isolation structure in different steps, different types of stress can be generated in the first fin portion and the second fin portion finally, so as to meet the requirements of different types of transistors, and further improve the performance of the finally formed semiconductor structure. Description of the Drawings

[0036] Figures 1 to 3 is a schematic structural diagram of a semiconductor structure;

[0037] Figures 4 to 21 is a schematic structural diagram of each step of an embodiment of the forming method of the semiconductor structure of the present invention. Detailed Embodiment

[0038] As described in the background art, there are still many problems in the process of forming a semiconductor structure. The following will be specifically described with reference to the drawings.

[0039] Please refer to Figures 1 to 3 , Figure 1 is a top view of a semiconductor structure omitting a dielectric layer and an isolation layer, Figure 2 is Figure 1 a cross-sectional schematic view along the A-A direction, Figure 3 is Figure 1Schematic cross-sectional view along the B-B direction; A semiconductor structure includes a substrate 100, the substrate 100 includes isolation regions B1, a first device region A1, and a second device region A2 arranged along a first direction X, the isolation region B1 is located between the first device region A1 and the second device region A2; A plurality of first fin portions 101 and a plurality of second fin portions 102 located on the substrate 100, the first fin portions 101 and the second fin portions 102 are arranged along a second direction Y, the first direction X is perpendicular to the second direction Y, the first fin portions 101 span across the isolation region B1 from the first device region A1 and extend to the second device region A2, the second fin portions 102 have isolation openings 103, the isolation openings 103 penetrate through the second fin portions 102 along the second direction Y, and the isolation openings 103 are located on the isolation region B1; A plurality of gate structures 104 are formed on the first device region A1 and the second device region A2, the gate structures 104 span across the first fin portions 101 and the second fin portions 102; A dielectric layer 105 located on the substrate 100, the dielectric layer 105 covers the sidewalls of the gate structures 104; A first opening (not labeled) located in the dielectric layer 105, the first opening extends along the second direction Y, and the first opening exposes a partial sidewall and a top surface of the first fin portion 101; A second opening (not labeled) located in the dielectric layer 105, the second opening extends along the second direction Y, and the second opening exposes a partial sidewall and a top surface of the second fin portion 102; A first isolation structure 106 located in the first opening; A second isolation structure 107 located in the second opening.

[0040] In this embodiment, by forming the first isolation structure 106 and the second isolation structure 107, it is possible to effectively prevent the short circuit between the first source-drain doping layers formed in the first fin portion 101 and the short circuit between the second source-drain doping layers formed in the second fin portion 102, achieving an isolation effect.

[0041] In this embodiment, the first fin portion 101 is used to form a PMOS transistor structure, and the second fin portion 102 is used to form an NMOS transistor structure. Since the stress requirements for the fin portions of the PMOS transistor structure and the NMOS transistor structure are different, the PMOS transistor structure requires the first fin portion 101 to provide compressive stress, and the compressive stress is generated by the first isolation structure 106 acting on the first fin portion 101, while the NMOS transistor structure requires the second fin portion 102 to provide tensile stress, and the tensile stress is generated by the second isolation structure 107 acting on the second fin portion 102.

[0042] Since tensile stress and compressive stress are two different types of stress, the corresponding structural forms of the first isolation structure 106 and the second isolation structure 107 also need to be different. However, in this embodiment, the first isolation structure and the second isolation structure are formed simultaneously using a global process. Therefore, the structural forms of the first isolation structure and the second isolation structure are the same. As a result, the stress types generated by the first isolation structure and the second isolation structure can only meet the requirements of one type of MOS transistor structure, thereby reducing the performance of the finally formed semiconductor structure.

[0043] On this basis, the present invention provides a semiconductor structure and a method for forming the same. A plurality of first gate structures are formed on the isolation region, and the first gate structures straddle the second fin portion to provide stress requirements for the second fin portion through the first gate structures; a first opening is formed in the first region, the first opening is located between adjacent first gate structures and within the first fin portion, and an isolation structure is formed in the first opening to provide stress requirements for the first fin portion through the isolation structure; a second gate structure is formed on the second region, and the first gate structure straddles the second fin portion to provide stress requirements for the second fin portion through the first gate structure. By forming the first gate structure and the isolation structure in different steps, different types of stress can be generated in the first fin portion and the second fin portion finally, so as to meet the requirements of different types of transistors, thereby improving the performance of the finally formed semiconductor structure.

[0044] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes the embodiments of the present invention in detail with reference to the accompanying drawings.

[0045] Figures 4 to 21 It is a schematic structural diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0046] Please refer to Figure 4 , a substrate 200 is provided. The substrate 200 includes an isolation region B1 and a plurality of device regions A1 arranged along a first direction X. The isolation region B1 is located between adjacent device regions A1. The isolation region B1 includes a first region I and a second region II arranged along a second direction Y. The second direction Y is perpendicular to the first direction X.

[0047] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium.

[0048] Please refer to Figures 5 to 7 , Figure 5 Top view of the semiconductor structure, Figure 6 is Figure 5Cross-sectional schematic view along the C-C direction Figure 7 is Figure 5 Cross-sectional schematic view along the D-D direction. A plurality of first fin portions 201 and a plurality of second fin portions 202 are formed on the device region A1. The plurality of first fin portions 201 and the plurality of second fin portions 202 are all parallel to the first direction X and arranged along the second direction Y. The first fin portion 201 also straddles the isolation region B1. The second fin portion 202 has an isolation opening 203 located on the isolation region B1. The isolation opening 203 penetrates the second fin portion 202 along the second direction Y.

[0049] In this embodiment, the forming method of the second fin portion 202 includes: forming a plurality of initial second fin portions (not shown) parallel to each other along the second direction Y on the substrate 200; forming a patterned layer (not shown) on the substrate 200 to expose part of the initial second fin portions; etching the initial second fin portions using the patterned layer as a mask until the top surface of the substrate 200 is exposed, thereby forming the second fin portion 202.

[0050] In this embodiment, the materials of the first fin portion 201 and the second fin portion 202 are silicon; in other embodiments, the materials of the first fin portion and the second fin portion can also be germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium.

[0051] Please refer to Figure 8 and Figure 9 , Figure 8 and Figure 6 The view directions are the same. Figure 9 and Figure 7 The view directions are the same. After forming the first fin portion 201 and the second fin portion 202, an isolation layer 204 is formed on the substrate 200. The isolation layer 204 covers part of the side walls of the first fin portion 201 and the second fin portion 202, and the top surface of the isolation layer 204 is lower than the top surfaces of the first fin portion 201 and the second fin portion 202.

[0052] In this embodiment, the forming method of the isolation layer 204 includes: forming an initial isolation layer (not shown) on the substrate 200; etching away part of the initial isolation layer to form the isolation layer 204, and the top surface of the isolation layer 204 is lower than the top surfaces of the first fin portion 201 and the second fin portion 202.

[0053] The material of the isolation layer 204 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 204 is silicon oxide.

[0054] After forming the isolation layer 204, the following steps are further included: forming a plurality of first gate structures on the isolation region B1, where the first gate structures span across the first fin 201 and the second fin 202 along the second direction Y; forming a plurality of second gate structures on the device region A1, where the second gate structures span across the first fin 201 and the second fin 202 along the second direction Y; forming a plurality of first source / drain doping layers within the first fin 201, where the first source / drain doping layers are located between adjacent first gate structures, or between adjacent second gate structures, or between adjacent first gate structures and second gate structures, and the first source / drain doping layers contain first source / drain ions; forming a plurality of second source / drain doping layers within the second fin 202, where the second source / drain doping layers are located between adjacent second gate structures, or between adjacent first gate structures and second gate structures, and the second source / drain doping layers contain second source / drain ions. For the specific forming process, please refer to Figures 10 to 17 。

[0055] Please refer to Figure 10 and Figure 11 , Figure 10 and Figure 8 which have the same view direction. Figure 11 and Figure 9 which have the same view direction. Forming a plurality of first dummy gate structures 205 on the isolation region B1, where the first dummy gate structures 205 span across the first fin 201 and the second fin 202; forming a plurality of second dummy gate structures 206 on the device region A1, where the second dummy gate structures 206 span across the first fin 201 and the second fin 202.

[0056] In this embodiment, the method for forming the first dummy gate structure 205 includes: forming a first dummy gate dielectric layer (not labeled) on the isolation layer 204; forming a first dummy gate layer (not labeled) on the first dummy gate dielectric layer; forming a first sidewall (not labeled) on the sidewalls of the first dummy gate layer and the first dummy gate dielectric layer.

[0057] In this embodiment, the material of the first dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer can also be silicon oxynitride.

[0058] In this embodiment, the material of the first dummy gate layer is polysilicon.

[0059] In this embodiment, the method for forming the second dummy gate structure 206 includes: forming a second dummy gate dielectric layer (not labeled) on the isolation layer 204; forming a second dummy gate layer (not labeled) on the second dummy gate dielectric layer; forming a second sidewall (not labeled) on the sidewalls of the second dummy gate layer and the second dummy gate dielectric layer.

[0060] In this embodiment, the material of the second dummy gate dielectric layer is the same as that of the first dummy gate dielectric layer, and the material of the second dummy gate layer is also the same as that of the first dummy gate layer.

[0061] In this embodiment, the first dummy gate structure 205 and the second dummy gate structure 206 are formed simultaneously. By forming the first dummy gate structure 205 and the second dummy gate structure 206 through a global process, the production efficiency can be effectively improved.

[0062] Please refer to Figure 12 and Figure 13 , using the first dummy gate structure 205 and the second dummy gate structure 206 as masks to etch the first fin 201, and forming a plurality of first source / drain openings (not labeled) in the first fin 201; using the first dummy gate structure 205 and the second dummy gate structure 206 as masks to etch the second fin 202, and forming a plurality of second source / drain openings (not labeled) in the second fin 202; forming the first source / drain doping layer 207 in the first source / drain opening; and forming the second source / drain doping layer 208 in the second source / drain opening.

[0063] In this embodiment, the method for forming the first source / drain doping layer 207 in the first source / drain opening includes: forming a first epitaxial layer (not labeled) in the first source / drain opening by using an epitaxial growth process; and performing in-situ doping on the first epitaxial layer during the epitaxial growth process, and doping first source / drain ions into the first epitaxial layer to form the first source / drain doping layer 207.

[0064] In this embodiment, the method for forming the second source / drain doping layer 208 in the second source / drain opening includes: forming a second epitaxial layer (not labeled) in the second source / drain opening by using an epitaxial growth process; and performing in-situ doping on the second epitaxial layer during the epitaxial growth process, and doping second source / drain ions into the second epitaxial layer to form the second source / drain doping layer 208.

[0065] In this embodiment, the electrical types of the first source / drain ions and the second source / drain ions are different; the first source / drain ions are P-type ions, and the second source / drain ions are N-type ions. In other embodiments, the first source / drain ions may also be N-type ions, and the second source / drain ions are P-type ions.

[0066] Please refer to Figure 14 and Figure 15, after forming the first source / drain doping layer 207 and the second source / drain doping layer 208, a dielectric layer 209 is formed on the substrate 200, and the dielectric layer 209 covers the sidewalls of the first dummy gate structure 205 and the second dummy gate structure 206.

[0067] In this embodiment, the method for forming the dielectric layer 209 includes: forming an initial dielectric layer (not shown) on the substrate 200, the initial dielectric layer covering the first source / drain doping layer 207, the second source / drain doping layer 208, the first dummy gate structure 205, and the second dummy gate structure 206; performing a planarization process on the initial dielectric layer until the top surfaces of the first dummy gate structure 205 and the second dummy gate structure 206 are exposed, thereby forming the dielectric layer 209.

[0068] In this embodiment, the material of the dielectric layer 209 is silicon oxide; in other embodiments, the material of the dielectric layer may also be a low-k dielectric material (a low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (an ultra-low-k dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0069] Please refer to Figure 16 and Figure 17 , remove the first dummy gate structure 205 to form a first gate opening (not labeled) in the dielectric layer 209; form the first gate structure 210 in the first gate opening; remove the second dummy gate structure 206 to form a second gate opening (not labeled) in the dielectric layer 209; form the second gate structure 211 in the second gate opening.

[0070] In this embodiment, specifically remove the first dummy gate dielectric layer and the first dummy gate layer of the first dummy gate structure 205; the second dummy gate dielectric layer and the second dummy gate layer of the second dummy gate structure 206.

[0071] In this embodiment, the first gate structure 210 includes: a first gate dielectric layer (not shown), a first gate layer (not shown) located on the first gate dielectric layer, and a first gate protection layer (not shown) located on the first gate layer; the second gate structure 211 includes: a second gate dielectric layer (not shown), a second gate layer (not shown) located on the second gate dielectric layer, and a second gate protection layer (not shown) located on the second gate layer.

[0072] In this embodiment, the materials of the first gate dielectric layer and the second gate dielectric layer include high-k dielectric materials.

[0073] The materials of the first gate layer and the second gate layer include metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the materials of the first gate layer and the second gate layer are tungsten.

[0074] In this embodiment, the materials of the first gate protection layer and the second gate protection layer are silicon nitride.

[0075] Please refer to Figure 18 and Figure 19 , after forming the first gate structure 210 and the second gate structure 211, a part of the dielectric layer 209 on the first source / drain doping layer 207 and a part of the first source / drain doping layer 207 are removed to form a first conductive opening (not labeled); a part of the dielectric layer 209 on the second source / drain doping layer 208 and a part of the second source / drain doping layer 208 are removed to form a second conductive opening (not labeled); a first conductive layer 212 and a first protection layer 213 on the first conductive layer 212 are formed in the first conductive opening; a second conductive layer 214 and a second protection layer 215 on the second conductive layer 214 are formed in the second conductive opening.

[0076] The materials of the first conductive layer 212 and the second conductive layer 214 include metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the materials of the first conductive layer 212 and the second conductive layer 214 are cobalt.

[0077] Please refer to Figure 20 , a first opening 216 is formed on the first region I, the first opening 216 is also located between adjacent first gate structures 210, and the bottom surface of the first opening 216 is lower than the top surface of the first fin 201.

[0078] In this embodiment, the first protection layer 213, the first conductive layer 212 and the first fin 201 on the first region I are removed, and the first opening 216 is formed in the adjacent first gate structures 210 and the first fin 201.

[0079] Please refer to Figure 21 , an isolation structure 217 is formed in the first opening 216.

[0080] In this embodiment, the method for forming the isolation structure 217 includes: forming an initial isolation structure (not shown) within the first opening 216, as well as on the first gate structure 210 and the dielectric layer 209; performing a planarization process on the initial isolation structure until the top surfaces of the first gate structure 210 and the dielectric layer 209 are exposed, and forming the isolation structure 217 within the first opening 216.

[0081] In this embodiment, the material of the isolation structure 217 includes silicon nitride.

[0082] In this embodiment, a plurality of first gate structures 210 are formed on the isolation region B1, and the first gate structures 210 straddle the second fin 202 to provide stress requirements for the second fin 202 through the first gate structures 210; a first opening 216 is formed on the first region I, the first opening 216 is located between adjacent first gate structures 210 and within the first fin 201, and an isolation structure 217 is formed within the first opening 216 to provide stress requirements for the first fin 201 through the isolation structure 217. Different steps are used to form the first gate structure 210 and the isolation structure 217, so that finally different types of stress can be generated in the first fin 201 and the second fin 202 to meet the requirements of different types of transistors, thereby improving the performance of the finally formed semiconductor structure.

[0083] Correspondingly, in an embodiment of the present invention, a semiconductor structure is further provided. Please continue to refer to Figure 21, including: a substrate 200, the substrate 200 including isolation regions B1 and a plurality of device regions A1 arranged along a first direction X, the isolation regions B1 being located between adjacent device regions A1, the isolation regions B1 including a first region I and a second region II arranged along a second direction Y, the second direction Y being perpendicular to the first direction X; a plurality of first fin portions 201 and a plurality of second fin portions 202 located on the device regions A1, the plurality of first fin portions 201 and the plurality of second fin portions 202 being parallel to the first direction X and arranged along the second direction Y, the first fin portions 201 further straddling the isolation regions B1, the second fin portions 202 having isolation openings 203 located on the isolation regions B1, the isolation openings 203 penetrating the second fin portions 202 along the second direction Y; a plurality of first gate structures 210 formed on the isolation regions B1, the first gate structures 210 straddling the first fin portions 201 and the second fin portions 202 along the second direction Y; a first opening 216 located on the first region I, the first opening 216 further being located between adjacent first gate structures 210, and a bottom surface of the first opening 216 being lower than a top surface of the first fin portions 201; an isolation structure 217 located in the first opening 216.

[0084] In this embodiment, a plurality of first gate structures 210 located on the isolation regions B1, the first gate structures 210 straddling the second fin portions 202, provide stress requirements for the second fin portions 202 through the first gate structures 210; a first opening 216 located on the first region I, the first opening 216 further being located between adjacent first gate structures 210 and within the first fin portions 201; an isolation structure 217 located in the first opening 216, provides stress requirements for the first fin portions 201 through the isolation structure 217. The first gate structures 210 and the isolation structure 217 are formed using different steps, such that finally the first fin portions 201 and the second fin portions 202 can generate different types of stress to meet the requirements of different types of transistors, thereby improving the performance of the finally formed semiconductor structure.

[0085] In this embodiment, it further includes: a plurality of second gate structures 211 located on the device regions A1, the second gate structures 211 straddling the first fin portions 201 and the second fin portions 202 along the second direction Y.

[0086] In this embodiment, it further includes: a plurality of first source / drain doping layers 207 located in the first fin portion 201, the first source / drain doping layers 207 being located between adjacent second gate structures 211, or between an adjacent first gate structure 210 and the second gate structure 211, and the first source / drain doping layers 207 having first source / drain ions; a plurality of second source / drain doping layers 208 are formed in the second fin portion 202, the second source / drain doping layers 208 being located between adjacent second gate structures 211 or between an adjacent first gate structure 210 and the second gate structure 211, and the second source / drain doping layers 208 having second source / drain ions.

[0087] In this embodiment, the first source / drain ions and the second source / drain ions are of different electrical types; the first source / drain ions include N-type ions or P-type ions; the second source / drain ions include P-type ions or N-type ions.

[0088] In this embodiment, it further includes: a first conductive layer 212 located on the first source / drain doping layer 207 and a first protective layer 213 located on the first conductive layer 212; a second conductive layer 214 located on the second source / drain doping layer 208 and a second protective layer 215 located on the second conductive layer 214.

[0089] In this embodiment, the material of the isolation structure 217 includes silicon nitride.

[0090] In this embodiment, it further includes: a dielectric layer 209 located on the substrate 200, the dielectric layer 209 covering the sidewalls of the first gate structure 210 and the second gate structure 211.

[0091] In this embodiment, it further includes: an isolation layer 204 located on the substrate 200, the isolation layer 204 covering partial sidewalls of the first fin portion 201 and the second fin portion 202, and the top surface of the isolation layer 204 being lower than the top surfaces of the first fin portion 201 and the second fin portion 202.

[0092] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate comprising isolation regions and a plurality of device regions arranged in a first direction, the isolation regions being located between adjacent device regions, the isolation regions comprising a first region and a second region arranged in a second direction, the second direction being perpendicular to the first direction; A plurality of first fin portions and a plurality of second fin portions located on the device regions, the plurality of first fin portions and the plurality of second fin portions being parallel to the first direction and arranged in the second direction, the first fin portions further spanning across the isolation regions, and the second fin portions having isolation openings located on the isolation regions, the isolation openings penetrating through the second fin portions in the second direction; A plurality of first gate structures formed on the isolation regions, the first gate structures spanning across the first fin portions and the second fin portions in the second direction; A first opening located on the first region, the first opening further being located between adjacent first gate structures, and a bottom surface of the first opening being lower than a top surface of the first fin portions; An isolation structure located within the first opening.

2. The semiconductor structure according to claim 1, wherein, Further comprising: A plurality of second gate structures located on the device regions, the second gate structures spanning across the first fin portions and the second fin portions in the second direction.

3. The semiconductor structure according to claim 2, wherein, Further comprising: A plurality of first source / drain doping layers located within the first fin portions, the first source / drain doping layers being located between adjacent second gate structures, or between adjacent first gate structures and second gate structures, and the first source / drain doping layers having first source / drain ions therein; a plurality of second source / drain doping layers are formed within the second fin portions, the second source / drain doping layers being located between adjacent second gate structures or between adjacent first gate structures and second gate structures, and the second source / drain doping layers having second source / drain ions therein.

4. The semiconductor structure according to claim 3, wherein The first source / drain ions and the second source / drain ions are of different electrical types; the first source / drain ions include N-type ions or P-type ions; the second source / drain ions include P-type ions or N-type ions.

5. The semiconductor structure according to claim 3, wherein, Further comprising: a first conductive layer located on the first source / drain doping layer and a first protective layer located on the first conductive layer; a second conductive layer located on the second source / drain doping layer and a second protective layer located on the second conductive layer.

6. The semiconductor structure according to claim 1, wherein, The material of the isolation structure comprises silicon nitride.

7. The semiconductor structure according to claim 2, wherein, Further comprising: A dielectric layer located on the substrate, the dielectric layer covering sidewalls of the first gate structures and the second gate structures.

8. The semiconductor structure according to claim 1, wherein Further comprising: An isolation layer located on the substrate, the isolation layer covering partial sidewalls of the first fin portions and the second fin portions, and a top surface of the isolation layer being lower than top surfaces of the first fin portions and the second fin portions.

9. A method for forming a semiconductor structure, characterized in that Comprising: Providing a substrate, the substrate comprising isolation regions and a plurality of device regions arranged in a first direction, the isolation regions being located between adjacent device regions, the isolation regions comprising a first region and a second region arranged in a second direction, the second direction being perpendicular to the first direction; A plurality of first fins and a plurality of second fins are formed on the device region. The plurality of first fins and the plurality of second fins are both parallel to the first direction and arranged along the second direction. The first fins also span across the isolation region. The second fins have isolation openings located on the isolation region, and the isolation openings penetrate through the second fins along the second direction. A plurality of first gate structures are formed on the isolation region. The first gate structures span across the first fins and the second fins along the second direction. A first opening is formed on the first region. The first opening is also located between adjacent first gate structures, and the bottom surface of the first opening is lower than the top surface of the first fins. An isolation structure is formed in the first opening.

10. The method for forming a semiconductor structure as described in claim 9, wherein, During the formation of the first gate structures, it further includes: forming a plurality of second gate structures on the device region. The second gate structures span across the first fins and the second fins along the second direction.

11. The method for forming a semiconductor structure according to claim 10, wherein Before the formation of the first gate structures and the second gate structures, it further includes: forming a plurality of first source / drain doping layers in the first fins. The first source / drain doping layers are located between adjacent first gate structures, or between adjacent second gate structures, or between adjacent first gate structures and second gate structures. And the first source / drain doping layers have first source / drain ions. Forming a plurality of second source / drain doping layers in the second fins. The second source / drain doping layers are located between adjacent second gate structures, or between adjacent first gate structures and second gate structures. And the second source / drain doping layers have second source / drain ions.

12. The method for forming a semiconductor structure as described in claim 11, wherein, The first source / drain ions and the second source / drain ions have different electrical types. The first source / drain ions include N-type ions or P-type ions. The second source / drain ions include P-type ions or N-type ions.

13. The method for forming a semiconductor structure as claimed in claim 11, wherein, Before the formation of the first source / drain doping layers and the second source / drain doping layers, it further includes: forming a plurality of first dummy gate structures on the isolation region. The first dummy gate structures span across the first fins and the second fins. Forming a plurality of second dummy gate structures on the device region. The second dummy gate structures span across the first fins and the second fins.

14. The method for forming a semiconductor structure according to claim 13, wherein, The forming method of the first source / drain doping layers and the second source / drain doping layers includes: etching the first fins with the first dummy gate structures and the second dummy gate structures as masks to form a plurality of first source / drain openings in the first fins. Etching the second fins with the first dummy gate structures and the second dummy gate structures as masks to form a plurality of second source / drain openings in the second fins. Forming the first source / drain doping layers in the first source / drain openings. Forming the second source / drain doping layers in the second source / drain openings.

15. The method for forming a semiconductor structure as described in claim 14, wherein, The method of forming the first source / drain doping layers in the first source / drain openings includes: forming a first epitaxial layer in the first source / drain openings by using an epitaxial growth process. During the formation of the first epitaxial layer, doping the first source / drain ions into the first epitaxial layer by using an in-situ doping process to form the first source / drain doping layers.

16. The method for forming a semiconductor structure according to claim 14, wherein The method for forming the second source / drain doping layer in the second source / drain opening includes: forming a second epitaxial layer in the second source / drain opening by using an epitaxial growth process; and doping the second source / drain ions into the second epitaxial layer by using an in-situ doping process during the formation of the second epitaxial layer to form the second source / drain doping layer.

17. The method for forming a semiconductor structure according to claim 13, wherein After forming the first source / drain doping layer and the second source / drain doping layer, it further includes: forming a dielectric layer on the substrate, and the dielectric layer covers the sidewalls of the first gate structure and the second gate structure.

18. The method for forming a semiconductor structure according to claim 17, wherein, The method for forming the dielectric layer includes: forming an initial dielectric layer on the substrate, and the initial dielectric layer covers the first source / drain doping layer, the second source / drain doping layer, the first dummy gate structure, and the second dummy gate structure; performing a planarization process on the initial dielectric layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed, so as to form the dielectric layer.

19. The method for forming the semiconductor structure according to claim 17, wherein, The method for forming the first gate structure and the second gate structure includes: removing the first dummy gate structure, and forming a first gate opening in the dielectric layer; forming the first gate structure in the first gate opening; removing the second dummy gate structure, and forming a second gate opening in the dielectric layer; forming the second gate structure in the second gate opening.

20. The method for forming a semiconductor structure according to claim 17, wherein, Before forming the first opening, it further includes: removing a part of the dielectric layer on the first source / drain doping layer and a part of the first source / drain doping layer to form a first conductive opening; removing a part of the dielectric layer on the second source / drain doping layer and a part of the second source / drain doping layer to form a second conductive opening; forming a first conductive layer in the first conductive opening and a first protective layer on the first conductive layer; forming a second conductive layer in the second conductive opening and a second protective layer on the second conductive layer.

21. The method for forming a semiconductor structure according to claim 20, wherein, The method for forming the first opening includes: removing the first protective layer, the first conductive layer, and the first fin on the first region, and forming the first opening in the adjacent first gate structure and the first fin.

22. The method for forming a semiconductor structure according to claim 17, wherein, The method for forming the isolation structure includes: forming an initial isolation structure in the first opening, on the first gate structure, and on the dielectric layer; performing a planarization process on the initial isolation structure until the top surfaces of the first gate structure and the dielectric layer are exposed, so as to form the isolation structure in the first opening.

23. The method for forming a semiconductor structure according to claim 9, wherein, The material of the isolation structure includes silicon nitride.

24. The method for forming a semiconductor structure according to claim 9, wherein The method for forming the second fin includes: forming a plurality of initial second fins arranged in parallel along the second direction on the substrate; forming a patterned layer on the substrate to expose a part of the initial second fins; etching the initial second fins by using the patterned layer as a mask until the top surface of the substrate is exposed, so as to form the second fin.

25. The method for forming a semiconductor structure according to claim 9, wherein, After forming the first fin and the second fin, it further includes: forming an isolation layer on the substrate, the isolation layer covering partial sidewalls of the first fin and the second fin, and a top surface of the isolation layer being lower than top surfaces of the first fin and the second fin.

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