Semiconductor Structure and Method for Forming the Same

Abstract

A semiconductor structure and a method for forming the same, wherein the method includes: the channel layer includes a first region and a second region arranged along the extending direction of the fin, and the two sides of the first region are respectively adjacent to the second region; forming a plurality of gate layers across the fin, and the plurality of gate layers are located on the second region; forming an interlayer dielectric layer on the substrate, and the interlayer dielectric layer is also located on the sidewalls of the gate layers; forming a trench in the interlayer dielectric layer, and the trench is located on the first region; injecting modified ions into the bottom of the trench to form a doped region in the first region; after forming the doped region, annealing the doped region to form a first isolation region, and the formation of the first isolation region does not need to adopt the method of first etching the fin to form a partition trench and then filling an insulating medium in the partition trench to form the first isolation region, maintaining the stress of the channel layer and improving the performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] With the further development of semiconductor technology, after the feature size of transistors is reduced to the nanoscale, the scaling technology is facing increasingly severe challenges, such as: mobility degradation, source-drain punch-through leakage, hot carrier effect, etc. Among them, mobility degradation is the main difficulty affecting the speed improvement of integrated circuits. By increasing the mobility of carriers in the channel, the mobility degradation caused by factors such as Coulomb interaction due to high channel doping, increased effective electric field strength due to thinning of the gate dielectric, and enhanced interface scattering can be compensated.

[0003] Strained silicon technology is to introduce strain, that is, stress change, into the channel region through the design of device structure and materials, so as to change the lattice structure of the channel region substrate, thereby increasing the mobility of carriers in the channel region and achieving the purpose of improving device performance. Direct epitaxy of strained channel materials in the channel region has become a development trend due to the obvious increase in stress. Germanium-silicon materials have become a research hotspot for new channel materials because of their high carrier mobility, higher device reliability, and compatibility with existing silicon-based processes.

[0004] However, the technology of germanium-silicon channel devices still needs to be continuously improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a semiconductor structure, including: a substrate, the substrate includes a base, a plurality of fin portions on the surface of the base, the fin portion includes a bottom structure layer on the surface of the base, and a channel layer on the bottom structure layer, the channel layer includes a first region and a second region arranged along the extending direction of the fin portion, the two sides of the first region are respectively adjacent to the second region; a gate layer spanning the fin portion, the gate layer is located on the second region; an interlayer dielectric layer on the substrate, the interlayer dielectric layer is also located on the sidewalls of the gate layer; a trench in the interlayer dielectric layer and on the first region; a first isolation region in the first region.

[0007] Optionally, it further includes: source-drain regions in the fin portions on both sides of the gate layer.

[0008] Optionally, the interlayer dielectric layer is located on the second region, the trench is located between adjacent gate layers, and the bottom of the trench does not expose the surface of the fin portion.

[0009] Optionally, it further includes: a blocking layer located on the first region and at the bottom of the trench, and the thickness of the blocking layer is less than 100 angstroms.

[0010] Optionally, the thickness range of the blocking layer is from 5 angstroms to 25 angstroms.

[0011] Optionally, it includes: an opening on the first region between adjacent gate layers, the opening exposing the top surface of the fin; a second isolation layer located within the opening.

[0012] Optionally, the material of the second isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0013] Optionally, the trench is located within the interlayer dielectric layer, and the sidewalls of the trench expose the interlayer dielectric layer, and the bottom of the trench exposes a part of the surface of the first region.

[0014] Optionally, a third isolation layer is located within the trench.

[0015] Optionally, the material of the third isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0016] Optionally, the material of the channel layer includes silicon germanium.

[0017] Optionally, the material of the bottom structure layer includes silicon.

[0018] Optionally, the material of the first isolation region includes silicon oxide.

[0019] Optionally, it further includes: a modified region located on the surface of the substrate and below the first isolation region.

[0020] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including a base, a plurality of fins located on the surface of the base, the fins including a bottom structure layer located on the surface of the base, and a channel layer located on the bottom structure layer, the channel layer including a first region and a second region arranged along the extending direction of the fin, and the first region is adjacent to the second region on both sides; forming a plurality of gate layers across the fins, and the plurality of gate layers are located on the second region; forming an interlayer dielectric layer on the substrate, and the interlayer dielectric layer is also located on the sidewalls of the gate layers; forming a trench within the interlayer dielectric layer, and the trench is located on the first region; injecting modified ions into the bottom of the trench to form a doped region in the first region; after forming the doped region, annealing the doped region to form a first isolation region.

[0021] Optionally, the process parameters of the modified ion implantation include: the ion energy range is from 3 keV to 10 keV, the substrate temperature range is from 80 °C to 150 °C, and the angle range between the ion implantation direction and the substrate normal direction is from 0.1 degree to 10 degrees.

[0022] Optionally, the method of implanting modified ions into the bottom of the trench includes: first implanting a first ion, then implanting a second ion after the first ion implantation is completed, and then implanting a third ion after the second ion implantation is completed. The energy of the second ion implantation is 40% to 70% of the energy of the first ion implantation, and the energy of the third ion implantation is 50% to 20% of the energy of the first ion implantation.

[0023] Optionally, the temperature range of the annealing treatment is from 300 °C to 500 °C.

[0024] Optionally, after forming the gate layer spanning the fin and before forming the interlayer dielectric layer, it further includes: forming source and drain regions in the fins on both sides of the gate layer.

[0025] Optionally, the interlayer dielectric layer is located on the first region and the second region. The method of forming the trench includes: forming a patterned layer on the surfaces of the interlayer dielectric layer and the gate layer, and the patterned layer exposes the interlayer dielectric layer on the first region; using the patterned layer as a mask to etch the interlayer dielectric layer on the first region to form the trench between adjacent gate layers. A part of the interlayer dielectric layer is reserved at the bottom of the trench, and the sidewalls of the trench expose the gate layer.

[0026] Optionally, it includes: the interlayer dielectric layer at the bottom of the trench forms a barrier layer, and the thickness of the barrier layer is less than 100 Å.

[0027] Optionally, the thickness range of the barrier layer is from 5 Å to 25 Å.

[0028] Optionally, after forming the first isolation region, it further includes: removing the barrier layer, forming an opening on the first region between adjacent gate layers; forming a second isolation layer in the opening.

[0029] Optionally, the material of the second isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0030] Optionally, several of the gate layers also span across the first region; the method of forming the trench includes: removing the gate layer on the first region, forming the trench in the interlayer dielectric layer, and the bottom of the trench exposes a part of the surface of the first region.

[0031] Optionally, after forming the first isolation region, the method further includes: forming a third isolation layer in the trench.

[0032] Optionally, the material of the third isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride.

[0033] Optionally, the material of the channel layer includes silicon germanium.

[0034] Optionally, the material of the bottom structure layer includes silicon.

[0035] Optionally, the modified ions include oxygen ions.

[0036] Optionally, the material of the first isolation region includes silicon oxide.

[0037] Optionally, when annealing the doped region, the method further includes: forming a modified region in the bottom structure layer below the first isolation region.

[0038] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0039] In the method for forming a semiconductor structure provided by the technical solution of the present invention, modified ions are implanted into the first region to form a doped region, and the doped region is annealed to form a first isolation region, and a modified region is formed in the bottom structure layer below the first isolation region. The formation of the first isolation region does not require the method of first etching the fins to form a partition trench and then filling an insulating medium in the partition trench to form the first isolation region. Therefore, it is difficult for the channel layer to have a partial stress release due to etching, maintaining the stress of the channel layer, not affecting the improvement of the carrier mobility in the channel region, and improving the performance of the device.

[0040] Furthermore, the material of the channel layer includes silicon germanium; the material of the bottom structure layer includes silicon. Due to the lattice mismatch between germanium and silicon, compressive stress will be generated in the channel layer, and the compressive stress can reduce the conductivity effective mass of holes in the channel direction and improve the speed of PMOS devices.

[0041] Furthermore, before implanting the modified ions into the first region, the method further includes: etching the interlayer dielectric layer on the first region to thin the interlayer dielectric layer on the first region to form a barrier layer. The barrier layer is used as a protective layer during the implantation of modified ions to prevent the surface of the first region from becoming rough due to ion implantation, thereby improving the flatness of the surface of the first isolation region formed subsequently. At the same time, since the barrier layer is an oxide layer, during the process of implanting modified ions and the annealing process, it can block the diffusion of germanium ions in the fin material towards the top of the fin and cause the germanium ions to diffuse towards the bottom of the fin. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figures 1 to 3 is a cross-sectional schematic view of a semiconductor structure formation process;

[0043] Figures 4 to 12 is a schematic structural view of each step of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0045] As described in the background art, the performance of a semiconductor structure formed by using the existing germanium-silicon channel device technology needs to be improved urgently. A semiconductor structure is now combined for description and analysis.

[0046] Figures 1 to 3 is a cross-sectional schematic view of a semiconductor structure formation process.

[0047] Please refer to Figure 1 , a substrate 100 is provided, and the substrate 100 includes: a base 101 and fin portions 102 located on the surface of the base. The fin portions 102 include a bottom structure layer 103 located on the surface of the base 101 and a channel layer 104 located on the bottom structure layer 103; a gate layer 105 is formed across the fin portions 102; source-drain regions 106 are formed in the fin portions 102 on both sides of the gate layer 105; an interlayer dielectric layer 107 is formed on the surface of the substrate 100, and the interlayer dielectric layer 107 also covers the sidewalls of the gate layer 105.

[0048] Please refer to Figure 2 , a patterned hard mask layer 108 is formed on the surface of the interlayer dielectric layer 107 and the gate layer 105, and the hard mask layer 108 exposes a part of the gate layer 105; the gate layer 105 and the fin portions 102 are etched using the hard mask layer 108 as a mask, and isolation trenches 109 are formed in the interlayer dielectric layer 107 and the fin portions 102.

[0049] Please refer to Figure 3 , the isolation trenches 109 are filled with insulating dielectrics such as silicon oxide and silicon nitride to form an isolation structure 110.

[0050] In the above method, the channel layer 104 is used to form the channel of the germanium-silicon channel device. The channel layer 104 is located on the bottom structure layer 103. The material of the channel layer 104 is germanium-silicon material, and the material of the bottom structure layer 103 is silicon. Due to the lattice mismatch between germanium and silicon, compressive stress will be generated on the channel layer 104. The compressive stress can reduce the conductivity effective mass of holes in the channel direction and improve the speed of PMOS devices. However, during the formation of the isolation structure 110, part of the stress of the channel layer 104 will be released due to the cut caused by the isolation trench 109. In addition, the stress generated by the device region adjacent to the isolation trench 109 (such as the interlayer dielectric layer 107) on the channel layer 104 will also change due to the isolation channel 109, greatly reducing the stress obtained by the finally formed channel region, thereby limiting the improvement of the carrier mobility in the channel region and affecting the performance of the device.

[0051] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure. Modifying ions are implanted into the first region to form a doped region, and the doped region is annealed to form a first isolation region, and the bottom structure layer located below the first isolation region is formed into a modified region. The formation of the first isolation region does not require the method of first etching the fin to form an isolation trench and then filling the isolation trench with an insulating medium. Therefore, the situation of partial stress release of the channel layer caused by etching will not occur, the stress of the channel layer is maintained, the improvement of the carrier mobility of the channel is not affected, and the performance of the device is improved.

[0052] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the accompanying drawings.

[0053] Figures 4 to 12 It is a schematic structural diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0054] Please refer to Figure 4 and Figure 5 , Figure 5 which is a top view, Figure 4 and Figure 5 is a schematic cross-sectional view along the tangent direction of AB. A substrate 200 is provided. The substrate 200 includes a substrate 201 and a plurality of fins 202 located on the surface of the substrate 201. The fins 202 include a bottom structure layer 203 located on the surface of the substrate 201 and a channel layer 204 located on the bottom structure layer 203. The channel layer 204 includes a first region Ⅰ and a second region Ⅱ arranged along the extending direction of the fins. The two sides of the first region Ⅰ are adjacent to the second region Ⅱ respectively.

[0055] The material of the substrate 201 can be single-crystalline silicon, polycrystalline silicon or amorphous silicon, or can also be semiconductor materials such as silicon, germanium, silicon germanide, gallium arsenide, etc., and can also be a semiconductor-on-insulator structure. In this embodiment, the material of the substrate 201 is single-crystalline silicon.

[0056] The material of the bottom structure 203 includes silicon. In this embodiment, the material of the bottom structure 203 is single-crystalline silicon.

[0057] The material of the channel layer 204 includes silicon germanium. The channel layer 204 is used to form the channel of the device subsequently. Due to the lattice mismatch between germanium and silicon, compressive stress will be generated in the channel layer 204, and the compressive stress can reduce the conductivity effective mass of holes in the channel direction and improve the speed of the PMOS device.

[0058] The first region Ⅰ is used to form the first isolation region subsequently; the second region Ⅱ is used to form MOS devices subsequently.

[0059] In this embodiment, the substrate 200 further includes an isolation structure (not marked in the figure) located on the surface of the substrate 201 and covering part of the sidewalls of the fin 202, and the top surface of the isolation structure is lower than the top surface of the fin 202. Subsequently, a plurality of gate layers spanning the fin 202 are formed, and the gate layers are located on the isolation structure. The isolation structure is used to achieve electrical insulation between different semiconductor devices.

[0060] The material of the isolation structure includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxide silicon, carbon nitride silicon, and carbon oxynitride silicon. In this embodiment, the material of the isolation structure is silicon oxide.

[0061] Please refer to Figure 6 and Figure 7 , Figure 6 and Figure 4 which have the same view direction, Figure 7 and Figure 5 which have the same view direction, to form a plurality of gate layers 205 spanning the fin 202, and a plurality of the gate layers 205 are located on the second region Ⅱ; an interlayer dielectric layer 206 is formed on the substrate 200, and the interlayer dielectric layer 206 is also located on the sidewalls of the gate layers 205.

[0062] The material of the gate layer 205 includes silicon. In this embodiment, the material of the gate layer 205 is polycrystalline silicon. In other embodiments, the material of the gate layer 205 can also be single-crystalline silicon, amorphous silicon, silicon carbide, etc.

[0063] The material of the interlayer dielectric layer 206 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbonitride, and silicon carbon oxynitride. In this embodiment, the material of the interlayer dielectric layer 206 is silicon oxide. The interlayer dielectric layer 206 is used to isolate metal interconnects from devices in subsequent device manufacturing processes, reduce the parasitic capacitance between the metal and the substrate, and improve the parasitic field-effect transistors formed when the metal spans different regions.

[0064] The formation process of the interlayer dielectric layer 206 includes a chemical vapor deposition process. In this embodiment, the formation process of the interlayer dielectric layer 206 is a fluid vapor chemical deposition process. The formation process of the interlayer dielectric layer 206 is an HDP CVD (high density plasma chemical vapor deposition) process. The HDP CVD process has good step coverage, which is beneficial to reducing defects such as voids in the formed interlayer dielectric layer 206.

[0065] In this embodiment, after forming the gate layer 205 across the fin 202 and before forming the interlayer dielectric layer 206, source / drain regions 207 are also formed in the fins 202 on both sides of the gate layer 205. Specifically, source / drain regions 207 are formed in the fins 202 on the second region II on both sides of the gate layer 205.

[0066] In this embodiment, the interlayer dielectric layer 206 is located on the first region I and the second region II. In other embodiments, several gate layers 205 also span across the first region I.

[0067] For simplicity, the view directions of the subsequent reference figures are the same as those of Figure 4 the view.

[0068] Subsequently, trenches are formed in the interlayer dielectric layer 206, and the trenches are located on the first region I. For the method of forming the trenches, please refer to Figures 8 to 9 .

[0069] Please refer to Figure 8 , a patterned layer 208 is formed on the surfaces of the interlayer dielectric layer 206 and the gate layer 205, and the patterned layer 208 exposes the interlayer dielectric layer 206 on the first region I.

[0070] In this embodiment, the patterning layer 208 includes a first photolithography layer (not marked in the figure) on the surfaces of the interlayer dielectric layer 206 and the gate layer 205, a second photolithography layer (not marked in the figure) on the surface of the first photolithography layer, and a third photolithography layer (not marked in the figure) on the surface of the second photolithography layer. The material of the first photolithography layer is photoresist; the material of the second photolithography layer is a silicon-based anti-reflection material; the material of the third photolithography layer is a carbon-containing polymer. The patterning layer 208 includes three layers of photolithography materials, which is beneficial to improving the resolution of the pattern and the fidelity during the process.

[0071] Please refer to Figure 9 , using the patterning layer 208 as a mask, etch the interlayer dielectric layer 206 on the first region I to form the trench 209 between adjacent gate layers 205. A part of the interlayer dielectric layer 206 is reserved at the bottom of the trench 209, and the sidewalls of the trench 209 expose the gate layer 205.

[0072] In this embodiment, a barrier layer 210 is further formed on the interlayer dielectric layer 206 at the bottom of the trench 209, and the thickness of the barrier layer 210 is less than 100 angstroms.

[0073] In this embodiment, the thickness range of the barrier layer 210 is 5 angstroms to 25 angstroms. Subsequently, modified ions are implanted into the bottom of the trench 209 to form a doped region in the first region I. After the doped region is formed, the doped region is annealed to form a first isolation region. The barrier layer 210 is used as a protective layer during the implantation of modified ions, avoiding the roughness of the surface of the first region I due to ion implantation, thereby improving the flatness of the surface of the subsequently formed first isolation region. At the same time, since the barrier layer 210 is an oxide layer, during the subsequent processes of implanting modified ions and annealing, it can block the diffusion of germanium ions in the material of the fin 202 towards the top of the fin 202, and make the germanium ions diffuse towards the bottom of the fin 202.

[0074] In other embodiments, several of the gate layers 205 also span across the first region I. The method for forming the trench 209 includes: removing the gate layer 205 on the first region I, and forming the trench 209 in the interlayer dielectric layer 206, and the bottom of the trench 209 exposes a part of the surface of the first region I.

[0075] Please refer to Figure 10 , and inject modified ions 211 into the bottom of the trench 209 to form a doped region 212 in the first region I.

[0076] The process parameters of the modified ion 211 implantation include: the ion energy range is from 3 keV to 10 keV, the substrate temperature range is from 80 °C to 150 °C, and the angle range between the ion implantation direction and the substrate normal direction is from 0.1 degree to 10 degrees. Since the angle range between the ion implantation direction and the substrate normal direction is small, the probability of injecting ions into the sidewall of the trench 209 is reduced, avoiding damage to the gate layer 205 or the interlayer dielectric layer 206 exposed on the sidewall of the trench 209.

[0077] The method of injecting the modified ion 211 into the bottom of the trench 209 includes: first injecting a first ion, injecting a second ion after the first ion injection is completed, and injecting a third ion after the second ion injection is completed. The second ion injection energy is 40% to 70% of the first ion injection energy, and the third ion injection energy is 50% to 20% of the first ion injection energy. The injection of the modified ion 211 is completed in three times, and the energy of the injected ions decreases continuously, which is beneficial to realizing the injection of ions at different depths in the first region I and achieving a uniform distribution of the injected ions in the first region I.

[0078] The modified ion 211 includes oxygen ions. The material of the first region I is germanium silicon. Since the bonding ability of the Si - O bond is stronger than that of the Ge - O bond, the injection of the modified ion 211 modifies the first region I into a region with high oxygen and low germanium content, that is, the germanium content range in the first region I decreases from 20% to 30% to less than 10%, forming the doped region 212.

[0079] Please refer to Figure 11 , after forming the doped region 212 (as Figure 10 shown), the doped region 212 is annealed to form the first isolation region 213.

[0080] Before annealing the doped region 212, the patterned layer 208 is also removed.

[0081] The process of removing the patterned layer 208 includes one or both of a dry process and a wet process. In this embodiment, the process of removing the patterned layer 208 is a dry process. Specifically, the process of removing the patterned layer 208 is an ashing process. The ashing process can improve the removal rate of the patterned layer 208 and reduce the damage to the gate layer 205 and the interlayer dielectric layer 206 during the process of removing the patterned layer 208, and has high reliability.

[0082] Annealing the doped region 212 also causes the bottom structure layer 203 located below the first isolation region 213 to form a modified region 214.

[0083] The temperature range of the annealing treatment is from 300 degrees Celsius to 500 degrees Celsius.

[0084] The material of the first isolation region 213 includes silicon oxide.

[0085] Under the process conditions of the annealing treatment, germanium is prone to diffusion. Coupled with the fact that the bonding ability of the Si-O bond is stronger than that of the Ge-O bond, the material of the doped region 212 reacts to form silicon oxide, forming the first isolation region 213. Due to the function of the barrier layer 210, germanium in the doped region 212 diffuses downward in the direction perpendicular to the substrate or in the direction parallel to the substrate. Due to the anisotropic characteristics of the diffusion of germanium in the silicon crystal, the probability of germanium diffusing in the direction perpendicular to the substrate is much greater than that in the direction parallel to the substrate, causing the bottom structure layer 203 located below the first isolation region 213 to form a material layer with a high germanium content, that is, the modified region 214.

[0086] The formation of the first isolation region 213 does not require the method of first etching the fin to form a partition trench and then filling the insulating medium in the partition trench to form the first isolation region. Therefore, it is difficult for the channel layer to have partial stress release due to etching, maintaining the stress of the channel layer, not affecting the improvement of the carrier mobility in the channel region, and improving the performance of the device.

[0087] Please refer to Figure 12 , after forming the first isolation region 213, remove the barrier layer 210 (as Figure 11 shown), and form an opening (not marked in the figure) on the first region I between adjacent gate layers 205; form a second isolation layer 215 in the opening.

[0088] The formation process of the second isolation layer 215 includes a chemical vapor deposition process. In this embodiment, the formation process of the second isolation layer 215 is a fluid vapor chemical deposition process. The formation process of the second isolation layer 215 is an HDP CVD (high density plasma chemical vapor deposition) process. The HDP CVD process has a good step coverage rate, which is beneficial to reducing defects such as voids in the formed second isolation layer 215.

[0089] The material of the second isolation layer 215 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, and silicon carbon oxynitride. The second isolation layer 215 and the first isolation region 213 together form a single diffusion isolation structure for realizing electrical insulation between different devices.

[0090] In other embodiments, part of the surface of the first region Ⅰ is exposed at the bottom of the trench 209. After forming the first isolation region 213, a third isolation layer is further formed in the trench 209.

[0091] The formation process of the third isolation layer is the same as that of the second isolation layer 215; the material of the third isolation layer is the same as that of the second isolation layer 215, which will not be elaborated here. The third isolation layer and the first isolation region 213 together form a double-diffusion isolation structure for achieving electrical insulation between different devices.

[0092] Correspondingly, the technical solution of the present invention also provides an embodiment of a semiconductor structure formed by the above formation method. Please continue to refer to Figure 12 , including: a substrate 200, the substrate 200 includes a base 201 and a plurality of fin portions 202 located on the surface of the base 201. The fin portions 202 include a bottom structure layer 203 located on the surface of the base 201 and a channel layer 204 located on the bottom structure layer 203. The channel layer 204 includes a first region Ⅰ and a second region Ⅱ arranged along the extending direction of the fin portion 202. The two sides of the first region Ⅰ are adjacent to the second region Ⅱ respectively; a gate layer 205 spanning the fin portion 202, the gate layer 205 is located on the second region Ⅱ; an interlayer dielectric layer 206 located on the substrate 200, the interlayer dielectric layer 206 is also located on the sidewalls of the gate layer 205; a trench 209 (as Figure 11 shown) located in the interlayer dielectric layer 206 and on the first region Ⅰ; a first isolation region 213 located in the first region Ⅰ.

[0093] The semiconductor structure further includes source-drain regions located in the fin portions 202 on both sides of the gate layer 205.

[0094] The interlayer dielectric layer 206 is located on the second region Ⅱ. The trench 209 is located between adjacent gate layers 205, and the surface of the fin portion 209 is not exposed at the bottom of the trench 209.

[0095] The semiconductor structure further includes a barrier layer 210 (as Figure 11 shown) located on the first region Ⅰ and at the bottom of the trench 209. The thickness of the barrier layer 210 is less than 100 angstroms.

[0096] The thickness range of the barrier layer 210 is from 5 angstroms to 25 angstroms. The barrier layer 210 is used as a protective layer during modified ion implantation to prevent the surface of the first region I from becoming rough due to ion implantation, thereby improving the flatness of the surface of the subsequently formed first isolation region. At the same time, since the barrier layer 210 is an oxide layer, during the processes of modified ion implantation and annealing treatment, it can prevent germanium ions in the material of the fin 202 from diffusing towards the top of the fin 202, but cause germanium ions to diffuse towards the bottom of the fin 202.

[0097] The semiconductor structure includes: an opening (not marked in the figure) on the first region I between adjacent gate layers 205, the opening exposing the top surface of the fin 202; a second isolation layer 215 located within the opening.

[0098] The material of the second isolation layer 215 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0099] The trench (not marked in the figure) is located within the interlayer dielectric layer 206, and the sidewalls of the trench expose the interlayer dielectric layer 206, and the bottom of the trench 209 exposes a part of the surface of the first region I.

[0100] A third isolation layer (not marked in the figure) located within the trench.

[0101] The material of the third isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

[0102] The material of the channel layer 204 includes germanium silicon.

[0103] The material of the bottom structural layer 203 includes silicon.

[0104] The material of the first isolation region 213 includes silicon oxide.

[0105] The semiconductor structure further includes: a modified region 214 located on the surface of the substrate 201 and below the first isolation 213 region.

[0106] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate, the substrate including a base, a plurality of fin portions located on the surface of the base, the fin portions including a bottom structure layer located on the surface of the base, and a channel layer located on the bottom structure layer, the channel layer including a first region and a second region arranged along the extending direction of the fin portion, and the two sides of the first region are respectively adjacent to the second region; A gate layer spanning the fin portion, the gate layer being located on the second region; An interlayer dielectric layer located on the substrate, and the interlayer dielectric layer is also located on the sidewalls of the gate layer; A trench located in the interlayer dielectric layer and on the first region; A first isolation region located in the first region, the forming method of the first isolation region including injecting modified ions into the bottom of the trench to form a doped region in the first region, and after forming the doped region, annealing the doped region to form the first isolation region.

2. The semiconductor structure according to claim 1, characterized in that, Further comprising: Source-drain regions located in the fin portions on both sides of the gate layer.

3. The semiconductor structure according to claim 1, wherein, The interlayer dielectric layer is located on the second region, the trench is located between adjacent gate layers, and the bottom of the trench does not expose the surface of the fin portion.

4. The semiconductor structure according to claim 3, wherein Further comprising: A barrier layer located on the first region and at the bottom of the trench, and the thickness of the barrier layer is less than 100 angstroms.

5. The semiconductor structure according to claim 4, wherein, The thickness range of the barrier layer is from 5 angstroms to 25 angstroms.

6. The semiconductor structure according to claim 1, wherein, Comprising: An opening located on the first region between adjacent gate layers, and the opening exposes the top surface of the fin portion; A second isolation layer located in the opening.

7. The semiconductor structure according to claim 6, wherein The material of the second isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

8. The semiconductor structure according to claim 1, wherein The trench is located in the interlayer dielectric layer, and the sidewalls of the trench expose the interlayer dielectric layer, and the bottom of the trench exposes a part of the surface of the first region.

9. The semiconductor structure according to claim 8, wherein, A third isolation layer located in the trench.

10. The semiconductor structure according to claim 9, wherein, The material of the third isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

11. The semiconductor structure according to claim 1, wherein, The material of the channel layer includes germanium silicon.

12. The semiconductor structure according to claim 1, wherein, The material of the bottom structure layer includes silicon.

13. The semiconductor structure according to claim 1, wherein The material of the first isolation region includes silicon oxide.

14. The semiconductor structure according to claim 1, wherein, Further comprising: A modified region located on the surface of the base and below the first isolation region.

15. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including a base, a plurality of fin portions located on the surface of the base, the fin portions including a bottom structure layer located on the surface of the base, and a channel layer located on the bottom structure layer, the channel layer including a first region and a second region arranged along the extending direction of the fin portion, and the two sides of the first region are respectively adjacent to the second region; Forming a plurality of gate layers spanning the fin portion, and the plurality of gate layers are located on the second region; Forming an interlayer dielectric layer on the substrate, and the interlayer dielectric layer is also located on the sidewalls of the gate layer; Forming a trench in the interlayer dielectric layer, and the trench is located on the first region; Injecting modified ions into the bottom of the trench to form a doped region in the first region; After forming the doped region, annealing the doped region to form the first isolation region.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The process parameters of the modified ion implantation include: the ion energy range is from 3 keV to 10 keV, the substrate temperature range is from 80 °C to 150 °C, and the included angle range between the ion implantation direction and the substrate normal direction is from 0.1 degree to 10 degrees.

17. The method for forming a semiconductor structure according to claim 15, wherein The method for implanting modified ions into the bottom of the trench includes: first implanting a first ion, then implanting a second ion after the first ion implantation is completed, and then implanting a third ion after the second ion implantation is completed. The implantation energy of the second ion is 40% to 70% of the implantation energy of the first ion, and the implantation energy of the third ion is 50% to 20% of the implantation energy of the first ion.

18. The method for forming a semiconductor structure according to claim 15, wherein The temperature range of the annealing treatment is from 300 °C to 500 °C.

19. The method for forming a semiconductor structure according to claim 15, wherein, After forming the gate layer across the fin, before forming the interlayer dielectric layer, it further includes: forming source and drain regions in the fins on both sides of the gate layer.

20. The method for forming a semiconductor structure as claimed in claim 15, wherein The interlayer dielectric layer is located on the first region and the second region. The method for forming the trench includes: forming a patterned layer on the surface of the interlayer dielectric layer and the gate layer, and the patterned layer exposes the interlayer dielectric layer on the first region; using the patterned layer as a mask to etch the interlayer dielectric layer on the first region to form the trench between adjacent gate layers. A part of the interlayer dielectric layer is reserved at the bottom of the trench, and the sidewall of the trench exposes the gate layer.

21. The method for forming a semiconductor structure as claimed in claim 20, wherein, It includes: The interlayer dielectric layer at the bottom of the trench forms a blocking layer, and the thickness of the blocking layer is less than 100 Å.

22. The method for forming a semiconductor structure according to claim 21, wherein, The thickness range of the blocking layer is from 5 Å to 25 Å.

23. The method for forming a semiconductor structure according to claim 21, wherein, After forming the first isolation region, it further includes: removing the blocking layer, forming an opening on the first region between adjacent gate layers; forming a second isolation layer in the opening.

24. The method for forming a semiconductor structure according to claim 23, wherein, The material of the second isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

25. The method for forming a semiconductor structure as described in claim 15, characterized in that, Several of the gate layers also span across the first region; the method for forming the trench includes: removing the gate layer on the first region, forming the trench in the interlayer dielectric layer, and the bottom of the trench exposes a part of the surface of the first region.

26. The method for forming a semiconductor structure according to claim 25, wherein After forming the first isolation region, it further includes: forming a third isolation layer in the trench.

27. The method for forming a semiconductor structure as described in claim 26, wherein, The material of the third isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride, and silicon carbon oxynitride.

28. The method for forming a semiconductor structure according to claim 15, wherein, The material of the channel layer includes germanium silicon.

29. The method for forming a semiconductor structure according to claim 15, wherein, The material of the bottom structure layer includes silicon.

30. The method for forming a semiconductor structure according to claim 15, wherein, The modified ion includes oxygen ion.

31. The method for forming a semiconductor structure according to claim 15, wherein The material of the first isolation region includes silicon oxide.

32. The method for forming a semiconductor structure according to claim 15, wherein, For the annealing treatment of the doped region, it further includes: making the bottom structure layer located below the first isolation region form a modified region.

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