Flyback switching power supply and control circuit and method therefor

Abstract

A flyback switching power supply, a control circuit and a method thereof are provided. The control circuit for the flyback switching power supply comprises: an input voltage detection module configured to detect an input DC voltage of the flyback switching power supply by detecting a voltage on a first auxiliary winding when a primary power tube is in a conduction state and a ZVS power tube is in an off state; a voltage difference detection module configured to detect a difference between the input DC voltage of the flyback switching power supply and a drain-source voltage of the primary power tube by detecting the voltage on the first auxiliary winding in a dead time before the primary power tube changes from the off state to the conduction state after the ZVS power tube changes from the conduction state to the off state; and a ZVS power tube control module configured to control conduction and off of the ZVS power tube based on the input DC voltage of the flyback switching power supply and the difference between the input DC voltage of the flyback switching power supply and the drain-source voltage of the primary power tube.

Description

Technical Field

[0001] The present invention relates to an integrated circuit, and more particularly to a flyback switching power supply and a control circuit and method thereof. Background Art

[0002] A switching power supply, also known as an alternating current power supply or switching converter, is a type of power supply. Its function is to convert a voltage level to the voltage or current required by the user through various topologies (e.g., flyback, buck, or boost). Summary of the Invention

[0003] According to an embodiment of the present invention, a control circuit for a flyback switching power supply includes a main inductor, a first auxiliary winding, a second auxiliary winding, a primary power tube connected between the main inductor and ground, and a zero voltage switching (ZVS) power tube connected between the second auxiliary winding and ground. The control circuit includes: an input voltage detection module configured to detect the input DC voltage of the flyback switching power supply by detecting the voltage on the first auxiliary winding when the primary power tube is in an on state and the ZVS power tube is in an off state; a voltage difference The detection module is configured to detect the difference between the input DC voltage of the flyback switching power supply and the drain-source voltage of the primary power tube by detecting the voltage on the first auxiliary winding during a dead time after the ZVS power tube changes from the on state to the off state and before the primary power tube changes from the off state to the on state; and the ZVS power tube control module is configured to control the conduction and shutdown of the ZVS power tube based on the input DC voltage of the flyback switching power supply and the difference between the input DC voltage of the flyback switching power supply and the drain-source voltage of the primary power tube.

[0004] A flyback switching power supply according to an embodiment of the present invention includes the above-mentioned control circuit for a flyback switching power supply.

[0005] According to an embodiment of the present invention, a control method for a flyback switching power supply includes a main inductor, a first auxiliary winding, a second auxiliary winding, a primary power transistor connected between the main inductor and ground, and a zero voltage switching (ZVS) power transistor connected between the second auxiliary winding and ground. The control method includes: when the primary power transistor is in an on state and the ZVS power transistor is in an off state, detecting the input DC voltage of the flyback switching power supply by detecting the voltage on the first auxiliary winding; during a dead time after the ZVS power transistor changes from an on state to an off state and before the primary power transistor changes from an off state to an on state, detecting the difference between the input DC voltage of the flyback switching power supply and the drain-source voltage of the primary power transistor by detecting the voltage on the first auxiliary winding; and controlling the on and off of the ZVS power transistor based on the input DC voltage of the flyback switching power supply and the difference between the input DC voltage of the flyback switching power supply and the drain-source voltage of the primary power transistor.

[0006] According to embodiments of the present invention, a flyback switching power supply and its control circuit and method can adaptively adjust the on-time of a ZVS power transistor by accurately detecting the drain-source voltage of the primary power transistor, thereby minimizing the switching losses of the primary power transistor. Furthermore, by minimizing the switching losses of the primary power transistor, the power consumption and conducted and radiated electromagnetic interference (EMI) performance of the flyback switching power supply can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present invention can be better understood from the following description of specific embodiments of the present invention in conjunction with the accompanying drawings, in which:

[0008] Figure 1 The circuit diagram of a traditional quasi-resonant flyback switching power supply is shown.

[0009] Figure 2 Shown Figure 1 Schematic diagram of waveforms of the drain-source voltage Vds of the primary power tube S1, the gate drive signal Gate, and the current Ip flowing through the primary power tube S1.

[0010] Figure 3 FIG. 4 shows a circuit schematic diagram of a traditional ZVS flyback switching power supply.

[0011] Figure 4 Shown Figure 3 Schematic diagram of waveforms of the drain-source voltage Vds of the primary power tube S1, the gate drive signal Gate1, and the current Ip flowing through the primary power tube S1, as well as the gate drive signal Gate0 of the ZVS power tube S0 and the current Iz flowing through the ZVS power tube S0.

[0012] Figure 5A circuit schematic diagram of a flyback switching power supply according to an embodiment of the present invention is shown.

[0013] Figure 6 Shown Figure 5 Schematic diagram of waveforms of the drain-source voltage Vds and gate drive signal Gate1 of the primary power tube S1, the gate drive signal Gate0 of the ZVS power tube S0, the voltage VDEM at the circuit node DEM between the auxiliary winding Ns2 and ground, and the two sampling signals Samp1 and Samp2.

[0014] Figure 7 A circuit diagram of an example implementation of the input voltage detection module 502 is shown.

[0015] Figure 8 A circuit diagram of an example implementation of the voltage difference detection module 504 is shown.

[0016] Figure 9 Shows the Figure 7 and Figure 8 Simplified example circuit after synthesis.

[0017] Figure 10 A schematic diagram of an example implementation of the ZVS power tube control module 506 is shown.

[0018] Figure 11 A circuit diagram of an example implementation of the operation and comparison unit 5062 is shown.

[0019] Figure 12 FIG. 5 is a circuit diagram showing another example implementation of the operation and comparison unit 5062 .

[0020] Figure 13 A circuit diagram of an example implementation of the control signal generation unit 5064 is shown.

[0021] Figure 14 Shown Figure 13 Schematic diagram of waveforms of the first enable pulse signal INC_pulse, the second enable pulse signal DEC_pulse, the on-control signal Vref_on, the on-characterization signal Vramp_ton, and the pulse width modulation signal PWM_ZVS.

[0022] Figure 15 A circuit diagram of another example implementation of the control signal generation unit 5064 is shown.

[0023] Figure 16 A control principle flow chart for a flyback switching power supply according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0024] The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present invention by illustrating examples of the present invention. The present invention is by no means limited to any specific configuration and algorithm proposed below, but covers any modification, replacement, and improvement of elements, components, and algorithms without departing from the spirit of the present invention. In the accompanying drawings and the following description, known structures and techniques are not shown to avoid causing unnecessary ambiguity to the present invention.

[0025] With the increasing demand for small-sized, high-frequency, and high-power-density switching power supplies, low-voltage or zero-voltage switching (ZVS) flyback switching power supplies are becoming more and more widely used.

[0026] Figure 1 The circuit diagram of the traditional quasi-resonant flyback switching power supply is shown in FIG. Figure 1 As shown, the main inductor Lp and the parasitic capacitance Cp of the primary power tube S1 (for example, a metal oxide semiconductor field effect transistor (MOSFET), a bipolar junction NPN transistor (BJT-NPN), an insulated gate bipolar transistor (IGBT), and a gallium nitride (GaN) transistor, etc.) form an LC resonant cavity; when the primary power tube S1 changes from the on state to the off state, the main inductor Lp begins to demagnetize; when the main inductor Lp is demagnetized, the main inductor Lp and the parasitic capacitance Cp of the primary power tube S1 enter a free resonance state; the quasi-resonant controller detects the voltage V on the auxiliary winding Ns. DEM When the set low voltage threshold is reached (ie, when the drain-source voltage of the primary power tube S1 resonates to near the valley voltage), the primary power tube S1 is controlled to change from the off state to the on state.

[0027] Figure 2 Shown Figure 1 Schematic diagram of the waveform of the drain-source voltage Vds of the primary power tube S1, the gate drive signal Gate, and the current Ip flowing through the primary power tube S1. Figure 2As shown, during the period from time t0 to time t1, the gate drive signal Gate is at a high level, the primary power tube S1 is in the on state, the drain-source voltage Vds of the primary power tube S1 is zero voltage, and the current Ip flowing through the power tube S1 gradually increases from zero current to Ipk; during the period from time t1 to time t3, the gate drive signal Gate is at a low level, the primary power tube S1 is in the off state, the drain-source voltage Vds of the primary power tube S1 increases to a stable value during the period from time t1 to time t2 and gradually decreases during the period from time t2 to time t3, and the current Ip flowing through the primary power tube S1 is zero current; at time t3, the drain-source voltage Vds of the primary power tube S1 decreases to the set low voltage threshold, the gate drive signal Gate changes from a low level to a high level, and the primary power tube S1 changes from the off state to the on state.

[0028] Compared to traditional flyback switching power supplies that use a hard-switching conduction method, the turn-on loss of a quasi-resonant flyback switching power supply is reduced. However, due to the limitations of the detection method for the valley voltage of the drain-source voltage Vds of the primary power tube S1, the drain-source voltage Vds of the primary power tube S1 does not drop to a truly low voltage when it changes from the off state to the on state. Therefore, the primary power tube S1 still has a certain amount of switching loss, which is more obvious when operating at high input voltage. Here, the switching loss of the primary power tube S1 can be calculated using equation (1).

[0029]

[0030] In order to further reduce the turn-on loss of the flyback switching power supply, a zero voltage switching (ZVS) flyback switching power supply is proposed. Figure 3 FIG. 4 shows a circuit schematic diagram of a traditional ZVS flyback switching power supply. Figure 4 Shown Figure 3 Schematic diagram of waveforms of the drain-source voltage Vds of the primary power tube S1, the gate drive signal Gate1, and the current Ip flowing through the primary power tube S1, as well as the gate drive signal Gate0 of the ZVS power tube S0 and the current Iz flowing through the ZVS power tube S0.

[0031] Combine Figure 3 and Figure 4It can be seen that at time t1, the primary power tube S1 changes from the on state to the off state, the main inductor Lp begins to demagnetize, the secondary freewheeling diode Do changes from the off state to the on state, the body diode of the ZVS power tube S0 changes from the off state to the on state, and the ZVS capacitor Cz begins to charge; at time t2, the charging voltage on the ZVS capacitor Cz increases to Vout*Ns3 / Ns1, and the body diode of the ZVS power tube S0 changes from the on state to the off state; at time t3, the demagnetization of the main inductor Lp is completed, and the parasitic capacitance Cp of the main inductor Lp and the primary power tube S1 enters the free resonance state; at time t4, the ZVS power tube S0 changes from the off state to the on state, and the ZVS capacitor Cz has a negative impact on the ZVS auxiliary The auxiliary winding Ns3 discharges, and the winding current Iz flowing through the ZVS auxiliary winding Ns3 reverses and gradually increases. At this time, the drain-source voltage Vds of the primary power tube S1 is clamped at Vbulk+Ns1 / Np*Vout; at time t5, the ZVS power tube S0 changes from the on state to the off state, and the winding current Iz flowing through the ZVS auxiliary winding Ns3 is transmitted to the primary side to participate in LC resonance, so that the voltage on the parasitic capacitance Cp of the primary power tube S1 (that is, the drain-source voltage Vds of the primary power tube S1) quickly resonates to the minimum voltage within the dead time; at time t6, the primary power tube S1 changes from the off state to the on state (at this time, the drain-source voltage Vds of the primary power tube S1 is approximately zero voltage).

[0032] exist Figure 3 In the ZVS flyback switching power supply shown in FIG, the time the ZVS power tube S0 is in the on state and the charging voltage on the ZVS capacitor Cz determine the negative demagnetization energy of the ZVS auxiliary winding Ns3. The higher the negative demagnetization energy of the ZVS auxiliary winding Ns3, the lower the resonance of the drain-source voltage Vds of the primary power tube S1, which can further reduce the switching loss of the primary power tube S1. However, when a high-voltage power tube is used as the primary power tube S1, when the drain-source voltage Vds of the primary power tube S1 is very low, the parasitic capacitance Cp of the primary power tube S1 will increase nonlinearly. According to equation (1), even when the drain-source voltage Vds of the primary power tube S1 is minimum (very close to zero voltage), the switching loss of the primary power tube S1 is not minimum. In addition, the nonlinear characteristics of the parasitic capacitance Cp of the primary power tube S1 will produce very large du / dt and di / dt, which will deteriorate the conducted and radiated EMI performance of the ZVS flyback switching power supply.

[0033] exist Figure 3 In the ZVS flyback switching power supply shown in FIG, the drain-source voltage Vds of the primary power tube S1 cannot be accurately detected, and the conduction time of the ZVS power tube S0 is determined by Figure 3The ZVS conduction ratio setting circuit shown is fixedly set or set according to a certain ratio based on the input DC voltage VBulk. It cannot adaptively determine whether the product of the parasitic capacitance Cp of the primary power tube S1 and the drain-source voltage Vds of the primary power tube S1 is minimized, and thus cannot control the primary power tube S1 to change from the off state to the on state with minimum power consumption.

[0034] In order to make Figure 3 The primary power tube S1 in the ZVS flyback switching power supply shown in the figure changes from the off state to the on state with the lowest power consumption. Figure 3 Based on the ZVS flyback switching power supply shown, a flyback switching power supply and a control circuit and method thereof according to an embodiment of the present invention are proposed.

[0035] Figure 5 FIG1 shows a circuit diagram of a flyback switching power supply according to an embodiment of the present invention. Figure 3 and Figure 5 It can be seen that Figure 5 The flyback switching power supply shown is Figure 3 The system architecture of the ZVS flyback switching power supply shown is basically the same, including a main inductor Lp, a first auxiliary winding Ns2, a second auxiliary winding Ns3, a primary power transistor S1 connected between the main inductor Lp and ground, a ZVS power transistor S0 connected between the second auxiliary winding Ns3 and ground, and a ZVS pulse width modulation (PWM) controller 500 for controlling the on and off of the primary power transistor S1 and the ZVS power transistor S0; Figure 5 The flyback switching power supply shown is Figure 3 The difference of the ZVS flyback switching power supply shown is mainly that the ZVS PWM controller 500 includes an input voltage detection module 502 , a voltage difference detection module 504 , and a ZVS power tube control module 506 .

[0036] In the ZVS PWM controller 500, the input voltage detection module 502 is configured to detect the input DC voltage VBulk of the flyback switching power supply by detecting the voltage on the first auxiliary winding Ns2 when the primary power transistor S1 is in the on state and the ZVS power transistor S0 is in the off state. The voltage difference detection module 504 is configured to detect the difference between the input DC voltage VBulk of the flyback switching power supply and the drain-source voltage Vds of the primary power transistor S1 by detecting the voltage on the first auxiliary winding Ns2 during the dead time after the ZVS power transistor S0 changes from the on state to the off state and before the primary power transistor S1 changes from the off state to the on state. The ZVS power transistor control module 506 is configured to control the conduction and shutdown of the ZVS power transistor S0 based on the input DC voltage VBulk of the flyback switching power supply and the difference between the input DC voltage VBulk of the flyback switching power supply and the drain-source voltage Vds of the primary power transistor S1.

[0037] According to an embodiment of the present invention, a ZVS PWM controller 500 for a flyback switching power supply can adaptively adjust the on-time of the ZVS power tube S0 by accurately detecting the drain-source voltage Vds when the primary power tube S1 changes from the off state to the on state, thereby controlling the primary power tube S1 to be turned on with minimum power consumption.

[0038] Figure 6 Shown Figure 5 The waveform diagram of the drain-source voltage Vds and gate drive signal Gate1 of the primary power tube S1, the gate drive signal Gate0 of the ZVS power tube S0, the voltage VDEM at the circuit node DEM between the auxiliary winding Ns2 and the ground, and the two sampling signals Samp1 and Samp2. Figure 5 and Figure 6 , the input voltage detection module 502, the voltage difference detection module 504, and the ZVS power tube control module 506 are described.

[0039] like Figure 5 and Figure 6 As shown, in some embodiments, the input voltage detection module 502 may be in a period when the primary power tube S1 is in the on state and the ZVS power tube S0 is in the off state, for example Figure 6 At the time t0 shown, the input DC voltage VBulk is detected by detecting the voltage VDEM on the first auxiliary winding Ns2 using the falling edge of the sampling signal Samp1. At the time t0, the voltage Vaux_t0 on the first auxiliary winding Ns2 is as shown in equation (2):

[0040]

[0041] like Figure 5 and Figure 6 As shown, in some embodiments, the voltage difference detection module 504 may be within the dead time after the ZVS power tube S0 changes from the on state to the off state and before the primary power tube S1 changes from the off state to the on state, for example, Figure 6 At time t6, the voltage VDEM on the first auxiliary winding Ns2 is detected by using the falling edge of the sampling signal Samp2 to detect the difference between the input DC voltage VBulk and the drain-source voltage Vds of the primary power transistor S1. At time t6, the voltage Vaux_t6 on the first auxiliary winding Ns2 is as shown in equation (3):

[0042]

[0043] Equation (4) can be derived from equations (2) and (3), so that the drain-source voltage Vds of the primary power tube S1 when it changes from the off state to the on state can be accurately calculated.

[0044]

[0045] like Figure 5 and Figure 6 As shown, in some embodiments, the ZVS power tube control module 506 can obtain the drain-source voltage Vds when the primary power tube S1 changes from the off state to the on state by directly or indirectly performing a differential operation on the detection results obtained by the input voltage detection module 502 and the voltage difference detection module 504, and adaptively adjust the on time of the ZVS power tube S0 based on the drain-source voltage Vds when the primary power tube S1 changes from the off state to the on state.

[0046] Figure 7 FIG. 5 shows a circuit diagram of an example implementation of the input voltage detection module 502. Figure 5 and Figure 7 As shown, in some embodiments, the input voltage detection module 502 can be further configured to: fix the voltage at the first circuit node (e.g., circuit node DEM) between the first auxiliary winding Ns2 and the ground at a predetermined voltage by clamping the voltage at the first circuit node; obtain a first mirror current (e.g., I1 or I2) by mirroring the first input current (e.g., Idem1) from the first auxiliary winding Ns2; and obtain a first sampling signal (e.g., Isp1 or Vsp1) representing the input DC voltage VBulk of the flyback switching power supply by sampling the first mirror current.

[0047] For example, Figure 7As shown, during a sampling pulse Samp1, the voltage at the circuit node DEM between the first auxiliary winding Ns2 and ground is clamped to a potential close to "zero", for example, 0.1V, through the operational amplifier OPA1, the compensation capacitor C1, and the output-stage buffer NMOS transistor NM1. The power transistors PM0, PM1, and PM2 form a mirror current source. The power transistor PM1 mirrors the first input current Idem1 flowing through the power transistor PM0 to generate a mirror current I1, and the power transistor PM2 mirrors the first input current Idem1 flowing through the power transistor PM0 to generate a mirror current I2. At the falling edge of the sampling pulse Samp1, the voltage V1 generated by the mirror current I1 flowing through the resistor Rsp1 is sampled by the voltage sampling and holding circuit to generate a first sampling voltage Vsp1 proportional to the input DC voltage VBulk. At the falling edge of the sampling pulse Samp1, the mirror current I2 is sampled by the current sampling and holding circuit to generate a first sampling current Isp1 proportional to the input DC voltage VBulk.

[0048] If combined Figure 5 and Figure 7 As described above, by detecting the first input current Idem1 from the first auxiliary winding Ns2, the voltage Vaux on the first auxiliary winding Ns2 can be detected, thereby detecting the input DC voltage VBulk of the flyback switching power supply. Specifically, the first input current Idem1 from the first auxiliary winding Ns2 can be expressed as:

[0049]

[0050] Because Ns2 / Np*VBulk is much larger than 0.1V, the first input current Idem1 can be approximately expressed as:

[0051]

[0052] That is, the first input current Idem1 from the first auxiliary winding Ns2 is approximately proportional to the input DC voltage VBulk.

[0053] Figure 8 FIG. 5 shows a circuit diagram of an example implementation of the voltage difference detection module 504. Figure 5 and Figure 8As shown, in some embodiments, the voltage difference detection module 504 can be further configured to: fix the voltage at a second circuit node (e.g., circuit node DEM) between the first auxiliary winding Ns2 and the ground at a predetermined voltage by clamping the voltage at the second circuit node, wherein the second circuit node and the first circuit node are the same circuit node or different circuit nodes; obtain a second mirror current (I3 or I4) by mirroring the second input current (e.g., Idem2) from the first auxiliary winding Ns2; and obtain a second sampling signal (e.g., Isp2 or Vsp2) representing the voltage difference Vbulk-Vds between the input DC voltage VBulk of the flyback switching power supply and the drain-source voltage Vds of the primary power tube S1 by sampling the second mirror current.

[0054] For example, Figure 8 As shown, during the sampling pulse Samp2, the voltage at the circuit node DEM between the first auxiliary winding Ns2 and the ground is clamped to a potential close to "zero", for example, 0.1V, by the operational amplifier OPA2, the compensation capacitor C2, and the output-stage buffer NMOS transistor NM2. The power transistors PM3, PM4, and PM5 form a mirror current source. The power transistor PM4 mirrors the second input current Idem2 flowing through the power transistor PM3 to generate a mirror current I3, and the power transistor PM5 mirrors the second input current Idem2 flowing through the power transistor PM3 to generate a mirror current I4. At the falling edge of the sampling pulse Samp2, the voltage V2 generated by the mirror current I3 flowing through the resistor Rsp2 is sampled by the voltage sampling and holding circuit to generate a second sampled voltage Vsp2 proportional to the input DC voltage VBulk. At the falling edge of the sampling pulse Samp2, the mirrored current I4 is sampled by the current sampling and holding circuit to generate a second sampled current Isp2 proportional to the input DC voltage VBulk.

[0055] If combined Figure 5 and Figure 8 As described above, by detecting the second input current Idem2 from the first auxiliary winding Ns2, the voltage Vaux on the first auxiliary winding Ns2 can be detected, and thus the difference VBulk-Vds between the input DC voltage VBulk and the drain-source voltage Vds of the primary power transistor S1 can be detected. Specifically, the second input current Idem2 from the first auxiliary winding Ns2 can be expressed as:

[0056]

[0057] Because Ns2 / Np*(VBulk-Vds) is much larger than 0.1V, the second input current Idem2 can be approximately expressed as:

[0058]

[0059] That is, the second input current Idem2 from the first auxiliary winding Ns2 is approximately proportional to the difference VBulk-Vds between the input DC voltage VBulk and the drain-source voltage Vds of the primary power transistor S1 .

[0060] By setting Figure 7 and Figure 8 The circuit parameters in the circuit shown can set the conversion gain between Vsp1 and VBulk to be equal to the conversion gain between Vsp2 and VBulk-Vds. Figure 9 Shows the Figure 7 and Figure 8 Simplified example circuit after synthesis. Figure 9 The circuit shown is similar in principle to Figure 7 and Figure 8 The circuit shown is the same and will not be repeated here.

[0061] Figure 10 FIG. 5 is a schematic diagram showing an example implementation of the ZVS power tube control module 506. Figure 10 As shown, the ZVS power tube control module 506 can be further configured to: obtain a sampled differential signal representing the drain-source voltage Vds of the primary power tube S1 by performing a differential operation on the first sampling signal and the second sampling signal; generate a first on-time control signal (for example, INC) for controlling the on-time of the ZVS power tube S0 to increase by comparing the sampled differential signal with a predetermined upper threshold; generate a second on-time control signal DEC for controlling the on-time of the ZVS power tube to decrease by comparing the sampled differential signal with a predetermined lower threshold; and generate a pulse width modulation signal (for example, PWM_ZVS) for controlling the on and off of the ZVS power tube based on the first on-time control signal and the second on-time control signal.

[0062] like Figure 10As shown, the ZVS power tube control module 506 includes an operation and comparison unit 5062 and a control signal generation unit 5064, wherein: the operation and comparison unit 5062 is configured to obtain a sampled differential signal representing the drain-source voltage Vds of the primary power tube S1 by directly or indirectly performing a differential operation on the first sampling signal and the second sampling signal, and generate a first on-time control signal INC and a second on-time control signal DEC by comparing the sampled differential signal with a predetermined upper threshold and a predetermined lower threshold respectively; the control signal generation unit 5064 is configured to generate a pulse width modulation signal PWM_ZVS for controlling the conduction and shutdown of the ZVS power tube S0 based on the clock signal Clk_zvs (for controlling the frequency of the pulse width modulation signal PWM_ZVS), the first on-time control signal INC, and the second on-time control signal DEC.

[0063] Figure 11 FIG. 5 shows a circuit diagram of an example implementation of the operation and comparison unit 5062. Figure 11 As shown, the operation and comparison unit 5062 includes a subtractor, a voltage comparator VCOMP1, and a voltage comparator VCOMP2, wherein: the subtractor performs a differential operation on the first sampling voltage Vsp1 and the second sampling voltage Vsp2 to obtain a differential sampling voltage VDS_in; when the differential sampling voltage VDS_in exceeds a predetermined upper threshold voltage Vref_max, the first on-time control signal INC output by the voltage comparator VCOMP1 is low, and the second on-time control signal DEC output by the voltage comparator VCOMP2 is high, and the on-time of the ZVS power tube S0 will increase; when the differential sampling voltage VDS_in is lower than a predetermined lower threshold voltage Vref_min, the second on-time control signal DEC output by the voltage comparator VCOMP2 is low, and the first on-time control signal INC output by the voltage comparator VCOMP1 is high, and the on-time of the ZVS power tube S0 will decrease; when Vref_min is lower than the predetermined lower threshold voltage Vref_min, the second on-time control signal DEC output by the voltage comparator VCOMP2 is low, and the first on-time control signal INC output by the voltage comparator VCOMP1 is high, and the on-time of the ZVS power tube S0 will decrease. <VDS_in<Vref_max时,电压比较器VCOMP1输出的第一导通时间控制信号INC为高电平,电压比较器VCOMP2输出的第二导通时间控制信号DEC也为高电平,ZVS功率管S0的导通时间将保持不变。

[0064] Figure 12 FIG. 5 shows a circuit diagram of another example implementation of the operation and comparison unit 5062. Figure 12As shown, the operation and comparison unit 5062 includes a subtractor, a current comparator ICOMPB1, and a current comparator ICOMPB2, wherein: the subtractor performs a differential operation on the first sampling current Isp1 and the second sampling current Isp2 to obtain a differential sampling current IDS_in; when the differential sampling current IDS_in exceeds a predetermined upper threshold current Iref_max, the first on-time control signal INC output by the current comparator ICOMPB1 is low, and the second on-time control signal DEC output by the current comparator ICOMPB2 is high, and the on-time of the ZVS power tube S0 will increase; when the differential sampling current IDS_in is lower than a predetermined lower threshold current Iref_min, the second on-time control signal DEC output by the current comparator ICOMPB2 is low, and the first on-time control signal INC output by the current comparator ICOMPB1 is high, and the on-time of the ZVS power tube S0 will decrease; when Iref_min is <IDS_in<Iref_max时,电流比较器ICOMP1输出的第一导通时长控制信号INC为高电平,电流比较器ICOMP2输出的第二导通时长控制信号DEC也为高电平,ZVS功率管S0的导通时间将保持不变。

[0065] Figure 13 FIG. 5 shows a circuit diagram of an example implementation of the control signal generating unit 5064. Figure 13 As shown, the control signal generating unit 5064 can be further configured to: generate a first enable pulse signal INC_pulse based on the first on-time control signal INC; generate a second enable pulse signal DEC_pulse having a pulse width equal to the first enable pulse signal INC_pulse based on the second on-time control signal DEC; generate an on-control signal Vref_ton for controlling the on-time of the ZVS power tube S0 by controlling the charging and discharging of the capacitor C3 using the first enable pulse signal INC_pulse and the second enable pulse signal DEC_pulse; generate an on-characterization signal Vramp_ton for characterizing the on-time of the ZVS power tube S0 by controlling the charging and discharging of the capacitor C4 using the pulse width modulation signal PWM_ZVS; generate an off-control signal off for controlling the ZVS power tube S0 to change from the on state to the off state based on the on-control signal Vref_ton and the on-characterization signal Vramp_ton; and generate a pulse width modulation signal PWM_ZVS based on the off-control signal off and the clock signal Clk_zvs.

[0066] Specifically, if Figure 13As shown, the first enable pulse signal generator generates a first enable pulse signal INC_pulse with a fixed pulse width Tsp based on the first conduction time control signal INC, and the second enable pulse signal generator generates a second enable pulse signal DEC_pulse with a fixed pulse width Tsp based on the second conduction time control signal DEC; the first enable pulse signal INC_pulse controls the closing and opening of the switch S3, and the second enable pulse signal DEC_pulse controls the closing and opening of the switch S4; when the switch S3 is closed and the switch S4 is opened, the capacitor C1 is charged; when the switch S3 is opened and the switch S4 is closed, the capacitor C2 is discharged; the charging voltage Vr on the capacitor C2 ef_ton is the on-control signal used to control the on-time of the ZVS power tube S0. At the rising edge of the pulse-width modulation signal PWM_ZVS, the current source I2 charges the capacitor C4. The charging voltage Vramp_ton on the capacitor C4 is the on-characterizing signal used to characterize the on-time of the ZVS power tube S0. The voltage comparator VCOMP3 compares Vref_ton with Vramp_ton to generate the off-control signal off for controlling the shutdown of the ZVS power tube S0. The SR trigger and the logic control unit generate the pulse-width modulation signal PWM_ZVS based on the off-control signal off and the clock signal Clk_ZVS.

[0067] Figure 14 Shown Figure 13 Schematic diagram of the waveforms of the first enable pulse signal INC_pulse, the second enable pulse signal DEC_pulse, the on-control signal Vref_on, the on-characterization signal Vramp_ton, and the pulse width modulation signal PWM_ZVS. Figure 13 and Figure 14 It can be seen that at time t1, the first enable pulse signal INC_pulse changes from a low level to a high level (i.e., the first on-time control signal INC changes from a low level to a high level), the second enable pulse signal DEC_pulse remains at a low level (i.e., the second on-time control signal DEC remains at a low level), the switch S3 changes from open to closed, the switch S4 remains open, the current source I1 begins to charge the capacitor C3, and the charging voltage Vref_ton on the capacitor C3 begins to increase linearly from the initial value V0. The increase ΔV of the charging voltage Vref_ton on the capacitor C3 at time t2 can be expressed as:

[0068]

[0069] After time t2, the duration that the pulse width modulation signal PWM_ZVS is at a high level will increase as the charging voltage Vref_ton on the capacitor C3 increases. The increased time ΔT can be expressed as:

[0070]

[0071] From equations (9) and (10), we can get ΔT as:

[0072]

[0073] At time t3, the first enable pulse signal INC_pulse remains at a low level (i.e., the first on-time control signal INC remains at a low level), the second enable pulse signal DEC_pulse changes from a low level to a high level (i.e., the second on-time control signal DEC changes from a low level to a high level), the switch S3 remains open, the switch S4 changes from open to closed, the current source I1 begins to discharge the capacitor C3, and the charge voltage Vref_ton on the capacitor C3 begins to decrease linearly from V0+2ΔV. Because the discharge current of the capacitor C3 is equal to the charging current, and the discharge time is equal to the charging time, at time t4, the charge voltage Vref_ton on the capacitor C3 decreases by ΔV. Similarly, after time t4, the duration that the pulse width modulation signal PWM_ZVS is at a high level decreases by ΔT.

[0074] When the first and second on-time control signals INC and DEC are both low, the switches S3 and S4 are turned off, the charging voltage Vref_ton of the capacitor C3 remains unchanged, and the duration for which the pulse width modulation signal PWM_ZVS is at a high level also remains unchanged.

[0075] As can be seen from equation (11), by properly setting the circuit parameters C3, I1, C4, I2, and Tsp, the amount of time ΔT by which the conduction time of the ZVS power tube S0 increases or decreases can be adjusted, thereby adjusting the drain-source voltage Vds of the primary power tube S1 when it changes from the off state to the on state.

[0076] Figure 15 FIG. 5 shows a circuit diagram of another example implementation of the control signal generating unit 5064. Figure 15As shown, the control signal generating unit 5064 can be further configured to: generate a first enable pulse signal INC_pulse based on the first on-time control signal INC; generate a second enable pulse signal DEC_pulse having a pulse width equal to the first enable pulse signal INC_pulse based on the second on-time control signal DEC; generate a pulse counting encoding signal Q[(m-1):0] for controlling the on-time of the ZVS power tube S0 using a bidirectional counting encoder based on the first enable pulse signal INC_pulse and the second enable pulse signal DEC_pulse; generate an off control signal off for controlling the ZVS power tube S0 from the on state to the off state using the on-time generation and selector based on the pulse counting encoding signal Q[(m-1):0]; and generate a pulse width modulation signal PWM_ZVS based on the off control signal off and the clock signal Clk_ZVS.

[0077] Specifically, if Figure 15 As shown, the first enable pulse signal generator generates a first enable pulse signal INC_pulse with a fixed pulse width Tsp based on the first conduction time control signal INC, and the second enable pulse signal generator generates a second enable pulse signal DEC_pulse with a fixed pulse width Tsp based on the second conduction time control signal DEC; the bidirectional counting encoder monitors the first and second enable pulse signals INC_pulse and DEC_pulse to achieve bidirectional counting of the increase and decrease of the conduction time of the ZVS power tube S0, thereby generating a pulse counting code signal Q[(m-1):0]; here, assuming m=6, the conduction time generation and selector generates a 6-bit binary code 000000~1111 based on the pulse counting code signal Q[(m-1):0]. 11, a total of 64 coded latch states; the on-time generation and selector divides the minimum duration Ton_min to the maximum duration Ton_max of the ZVS power tube S0 in the on-state into 64 equal parts according to the 64 codes, each equal part is ΔT; each binary coded latch state corresponds to a duration, for example, as shown in the figure, the binary code 000000 corresponds to Ton_min, the binary code 000001 corresponds to Ton_min+ΔT, the binary code 000010 corresponds to Ton_min+2ΔT, the binary code 000011 corresponds to Ton_min+3ΔT, the binary code 000100 corresponds to Ton_min+4ΔT······, the binary code 111110 corresponds to Ton_min+(2 6-2)ΔT, with the binary code 111111 corresponding to Ton_max. Thus, the on-time generator and selector generates and selects the corresponding Ton duration based on the 6-bit binary code output by the bidirectional counting encoder. This generates the off-control signal "off" through the OR logic circuit, which then generates the pulse-width modulation signal PWM_ZVS through the SR flip-flop and logic control unit.

[0078] Figure 16 FIG. 1 shows a flow chart of the control principle for a flyback switching power supply according to an embodiment of the present invention. Figure 16 As shown, the control process for the flyback switching power supply includes: S1602, when the primary power tube S1 is in the on state and the ZVS power tube S0 is in the off state, detecting the input DC voltage VBulk; S1604, during the dead time after the ZVS power tube S0 changes from the on state to the off state and before the primary power tube S1 changes from the off state to the on state, detecting the difference VBulk-Vds between the input DC voltage VBulk and the drain-source voltage Vds of the primary power tube S1; S1606, based on the input DC voltage VBulk and the difference VBulk between the input DC voltage VBulk and the drain-source voltage Vds of the primary power tube S1 ulk-Vds, calculate the source-drain voltage Vds of the primary power tube S1; S1608, when the drain-source voltage Vds of the primary power tube S1 is higher than the predetermined upper limit threshold, reduce the drain-source voltage Vds of the primary power tube S1 by extending the conduction time of the ZVS power tube S0; S1610, when the drain-source voltage Vds of the primary power tube S1 is lower than the predetermined lower limit threshold, increase the drain-source voltage Vds of the primary power tube S1 by shortening the conduction time of the ZVS power tube S0; S1612, when the drain-source voltage Vds of the primary power tube S1 is between the predetermined upper limit threshold and the predetermined lower limit threshold, the conduction time of the ZVS power tube S0 remains unchanged. In this way, the drain-source voltage Vds of the primary power tube S1 when it changes from the off state to the on state can be controlled to be near the predetermined upper threshold and the predetermined lower threshold, so that the switching loss of the primary power tube S1 is minimized, thereby improving the power consumption and EMI conduction and radiation performance of the flyback switching power supply.

[0079] The present invention may be implemented in other specific forms without departing from its spirit and essential characteristics. For example, the algorithms described in the specific embodiments may be modified without departing from the basic spirit of the present invention. Therefore, the present embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the invention is defined by the appended claims rather than the foregoing description, and all modifications coming within the meaning and scope of equivalents of the claims are intended to be included within the scope of the present invention.

Claims

1. A control circuit for a flyback switching power supply, the flyback switching power supply comprising a main inductor, a first auxiliary winding, a second auxiliary winding, a primary power transistor connected between the main inductor and ground, and a zero voltage switching (ZVS) power transistor connected between the second auxiliary winding and ground, the control circuit comprising: an input voltage detection module, configured to detect the input DC voltage of the flyback switching power supply by detecting the voltage on the first auxiliary winding when the primary power tube is in the on state and the ZVS power tube is in the off state, and to generate a first sampling signal representing the input DC voltage of the flyback switching power supply; a voltage difference detection module configured to detect a difference between an input DC voltage of the flyback switching power supply and a drain-source voltage of the primary power tube by detecting a voltage on the first auxiliary winding during a dead time after the ZVS power tube changes from an on state to an off state and before the primary power tube changes from an off state to an on state, and to generate a second sampling signal representing the difference between the input DC voltage of the flyback switching power supply and the drain-source voltage of the primary power tube; as well as The ZVS power tube control module is configured as follows: Obtaining a sampling differential signal representing the drain-source voltage of the primary power tube by performing a differential operation on the first sampling signal and the second sampling signal; By comparing the sampled differential signal with a predetermined upper threshold, a first on-time control signal is generated for controlling the on-time of the ZVS power tube to increase; By comparing the sampled differential signal with a predetermined lower threshold, a second on-time control signal is generated for controlling the on-time of the ZVS power tube to decrease; generating a first enable pulse signal based on the first on-time control signal; generating, based on the second on-time control signal, a second enable pulse signal having a pulse width equal to that of the first enable pulse signal; By controlling the charging and discharging of the first capacitor using the first enable pulse signal and the second enable pulse signal, a conduction control signal for controlling the conduction time of the ZVS power tube is generated; By controlling the charging and discharging of the second capacitor using a pulse width modulation signal for controlling the on and off of the ZVS power tube, a conduction characterization signal for characterizing the on time of the ZVS power tube is generated; Based on the conduction control signal and the conduction characterization signal, generating a shutdown control signal for controlling the ZVS power tube to change from a conduction state to a shutdown state; as well as The pulse width modulation signal is generated based on the shutdown control signal and a clock signal.

2. The control circuit according to claim 1, wherein: The input voltage detection module is further configured to: clamping the voltage at a first circuit node between the first auxiliary winding and ground to fix the voltage at the first circuit node at a predetermined voltage; Obtaining a first mirror current by mirroring the first input current from the first auxiliary winding; as well as A first sampling signal representing an input DC voltage of the flyback switching power supply is obtained by sampling the first mirror current.

3. The control circuit according to claim 2, wherein: The voltage difference detection module is further configured to: clamping the voltage at a second circuit node between the first auxiliary winding and ground to the predetermined voltage, wherein the second circuit node and the first circuit node are the same circuit node or different circuit nodes; Obtaining a second mirror current by mirroring the second input current from the first auxiliary winding; and By sampling the second mirror current, a second sampling signal representing the difference between the input DC voltage of the flyback switching power supply and the drain-source voltage of the primary power tube is obtained.

4. The control circuit according to claim 1, wherein: The first on-time control signal is at a low level when the sampled differential signal is greater than the predetermined upper threshold value, and is at a high level when the sampled differential signal is less than the predetermined upper threshold value, and the second on-time control signal is at a low level when the sampled differential signal is less than the predetermined lower threshold value, and is at a high level when the sampled differential signal is greater than the predetermined lower threshold value.

5. A flyback switching power supply, comprising the control circuit according to any one of claims 1 to 4.

6. A control method for a flyback switching power supply, the flyback switching power supply comprising a main inductor, a first auxiliary winding, a second auxiliary winding, a primary power transistor connected between the main inductor and ground, and a zero voltage switching (ZVS) power transistor connected between the second auxiliary winding and ground, the control method comprising: When the primary power tube is in the on state and the ZVS power tube is in the off state, detecting the input DC voltage of the flyback switching power supply by detecting the voltage on the first auxiliary winding, and generating a first sampling signal representing the input DC voltage of the flyback switching power supply; During a dead time after the ZVS power tube changes from the on state to the off state and before the primary power tube changes from the off state to the on state, detecting a difference between an input DC voltage of the flyback switching power supply and a drain-source voltage of the primary power tube by detecting a voltage on the first auxiliary winding, and generating a second sampling signal representing the difference between the input DC voltage of the flyback switching power supply and the drain-source voltage of the primary power tube; Obtaining a sampling differential signal representing the drain-source voltage of the primary power tube by performing a differential operation on the first sampling signal and the second sampling signal; By comparing the sampled differential signal with a predetermined upper threshold, a first on-time control signal is generated for controlling the on-time of the ZVS power tube to increase; By comparing the sampled differential signal with a predetermined lower threshold, a second on-time control signal is generated for controlling the on-time of the ZVS power tube to decrease; generating a first enable pulse signal based on the first on-time control signal; generating, based on the second on-time control signal, a second enable pulse signal having a pulse width equal to that of the first enable pulse signal; By controlling the charging and discharging of the first capacitor using the first enable pulse signal and the second enable pulse signal, a conduction control signal for controlling the conduction time of the ZVS power tube is generated; By controlling the charging and discharging of the second capacitor using a pulse width modulation signal for controlling the on and off of the ZVS power tube, a conduction characterization signal for characterizing the on time of the ZVS power tube is generated; Based on the conduction control signal and the conduction characterization signal, generating a shutdown control signal for controlling the ZVS power tube to change from a conduction state to a shutdown state; as well as The pulse width modulation signal is generated based on the shutdown control signal and a clock signal.

7. The control method according to claim 6, wherein: Detecting the input DC voltage of the flyback switching power supply by detecting the voltage on the first auxiliary winding includes: clamping the voltage at a first circuit node between the first auxiliary winding and ground to fix the voltage at the first circuit node at a predetermined voltage; Obtaining a first mirror current by mirroring the first input current from the first auxiliary winding; and A first sampling signal representing an input DC voltage of the flyback switching power supply is obtained by sampling the first mirror current.

8. The control method according to claim 7, wherein: Detecting the difference between the input DC voltage of the flyback switching power supply and the drain-source voltage of the primary power tube by detecting the voltage on the first auxiliary winding includes: clamping the voltage at a second circuit node between the first auxiliary winding and ground to the predetermined voltage, wherein the second circuit node and the first circuit node are the same circuit node or different circuit nodes; Obtaining a second mirror current by mirroring the second input current from the first auxiliary winding; and By sampling the second mirror current, a second sampling signal representing the difference between the input DC voltage of the flyback switching power supply and the drain-source voltage of the primary power tube is obtained.

9. The control method according to claim 6, wherein: The first on-time control signal is at a low level when the sampled differential signal is greater than the predetermined upper threshold value, and is at a high level when the sampled differential signal is not greater than the predetermined upper threshold value, and the second on-time control signal is at a low level when the sampled differential signal is less than the predetermined lower threshold value, and is at a high level when the sampled differential signal is not less than the predetermined lower threshold value.

Images