Multiplexed integrating amplifier for detecting signal loss

Abstract

A signal loss circuit has a multiplexer and a photodiode coupled to a first input of the multiplexer. A reference signal generator is coupled to a second input of the multiplexer. An amplifier is coupled to an output of the multiplexer. A splitter includes an input of the multiplexer coupled to an output of the amplifier. A first capacitor is coupled to a first output of the splitter. A second capacitor is coupled to a second output of the splitter. A comparator has a first input coupled to the first output of the splitter and a second input coupled to the second output of the splitter.

Description

[0001] This application is a divisional application of application No. 201910729351.9, with the title of "Multiplexed Integrating Amplifier for Detecting Signal Loss", filed on August 7, 2019. TECHNICAL FIELD

[0002] The present invention relates generally to semiconductor devices, and more specifically to detecting signal loss using a multiplexed integrating amplifier. BACKGROUND

[0003] Semiconductor devices are common in modern electronics. The number and density of electronic elements of a semiconductor device vary. Discrete semiconductor devices typically contain one type of electronic element, such as a light emitting diode (LED), a photodiode, a small signal transistor, a resistor, a capacitor, an inductor, or a power metal-oxide-semiconductor field-effect transistor (MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electronic elements. Examples of integrated semiconductor devices include microcontrollers, microprocessors, charge-coupled devices (CCDs), solar cells, and digital micromirror devices (DMDs).

[0004] Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, sending and receiving electromagnetic signals, controlling electronic devices, converting sunlight to electricity, and creating visual projections for television displays. Semiconductor devices exist in the entertainment, communication, power conversion, networking, computer, and consumer product domains. Semiconductor devices can also be used in military applications, aviation, automotive, industrial controllers, and office equipment.

[0005] Optical fibers are commonly used to transmit signals between semiconductor devices that are far apart from each other. Light waves into an optical fiber are produced using a light emitting diode (LED), a laser diode, or other electronically controllable light source. The optical fiber directs the light waves from the light source device to the target device. The target device includes a photodiode that converts the optical signal to an electrical signal for processing. An avalanche photodiode (APD) is often used, along with a transimpedance amplifier (TIA) to amplify the electrical signal for use by the semiconductor device.

[0006] Figure 1a illustrates a simplified optical receiver circuit. An optical signal is received from an optical fiber and directed to a photodiode 20. In some embodiments, the photodiode 20 is an avalanche photodiode. The photodiode 20 regulates a current source 24 that draws current from a voltage source 26 to a ground node 28, thereby controlling the input signal delivered to a transimpedance amplifier (TIA) 30. The transimpedance amplifier 30 outputs a differential pair signal as a transimpedance amplifier output 40, which is coupled to a transceiver for further processing.

[0007] Figure Ib shows a portion of the transceiver circuitry for an optical system. The transimpedance amplifier output 40 is coupled to the input of a receiver limiting amplifier (RLA) 50. The receiver limiting amplifier 50 outputs a constant power output signal 60 to other transceiver logic that converts the signal to digital data. To determine when the input signal is lost, the transceiver includes a signal loss (LOS) circuit.

[0008] In the past, the signal loss circuit consisted of a reference signal generator 70 that outputs a reference signal 72 to a signal loss amplifier 74. The reference signal 72 is similar to the signal at the transimpedance amplifier output 40, which is approximately the minimum amplitude level suitable for input to the receiver limiting amplifier 50. The reference signal 72 operates as a threshold, typically 5 millivolts (mV) peak-to-peak. The signal loss amplifier 74 is as identical as possible to the receiver limiting amplifier 50. A comparator 78 is used to compare the outputs of the receiver limiting amplifier 50 and the signal loss amplifier 74. If the amplitude of the data output signal 60 is lower than the output amplitude of the signal loss amplifier 74, then the comparator 78 asserts a signal loss signal 80 to notify the system of a signal loss.

[0009] The receiver limiting amplifier 50 in the main data path of an optical receiver typically includes a large amplifier stage and can draw a large current. Since the receiver limiting amplifier 50 is in the main data path, the data stream cannot be interrupted to check for signal loss. Therefore, a second identical amplifier 74 is provided to make the signal loss comparison. The two identical amplifiers allow the reference signal to be compared to the received data without interrupting the main data path, but require a large amount of space on the optical receiver chip and significantly increase the total current consumption. Also, the comparator 78 represents a significant load to the receiver limiting amplifier 50, thus degrading the performance of the receiver limiting amplifier. Therefore, a signal loss circuit with reduced circuit area requirements and current requirements is needed. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figures la and lb show a fiber optic receiver with a prior art signal loss detection circuit;

[0011] Figures 2a-2e show a signal loss circuit with a multiplexed integrator amplifier;

[0012] Figure 3 A multi-stage amplifier for a multiplexed signal loss circuit is shown;

[0013] Figure 4 A multi-stage amplifier is shown with switches built into the rectifier that are used to demultiplex and switch the signal output; and

[0014] Figure 5A timing diagram showing various signals within the multiplexed integrating amplifier is shown. DETAILED DESCRIPTION

[0015] The application is described in one or more embodiments in the following description with reference to the drawings, in which like numbers represent the same or similar elements. Although the application is described in accordance with the best of present knowledge, those skilled in the art will appreciate that the specification is intended to cover alternatives, modifications and equivalents of the application that can be included within the spirit and scope of the application as defined by the appended claims and supported by the following disclosure and drawings.

[0016] Figure 2a shows an optical receiver circuit with a signal loss (LOS) circuit 100. The input of the signal loss circuit 100 is coupled to the differential signal of the transimpedance amplifier output 40 and in parallel with the receiver limiting amplifier 50. The signal loss circuit 100 does not have the same amplifier as the receiver limiting amplifier 50 that receives a reference signal and does not compare its output to the receiver limiting amplifier output signal 60, but generates a LOS signal 80 independently of the receiver limiting amplifier 50. The signal loss circuit 100 has much smaller footprint than the receiver limiting amplifier 50 and also consumes much less current. Therefore, replacing the signal loss amplifier 74 in the prior art that is the same as the receiver limiting amplifier 50 with the signal loss circuit 100 can reduce the overall circuit size and current consumption of the fiber transceiver.

[0017] Figure 2b is a schematic diagram of the signal loss circuit 100. The transimpedance amplifier output 40 is routed to one input of a multiplexer (MUX) 110. The second input of the multiplexer 110 is coupled to a reference signal generator 120. The reference signal generator 120 outputs a reference signal 122 that is approximately the minimum magnitude of the transimpedance amplifier output 40 that the receiver limiting amplifier 50 can accept. Therefore, if the magnitude of the transimpedance amplifier output 40 drops below the magnitude of the reference signal 122, then the signal loss signal 80 is valid. Further details of the reference signal generator 120 are shown in Figure 2c.

[0018] The multiplexer 110 alternates between the output transimpedance amplifier output 40 and the reference signal 122, generating a multiplexer output 126 to the signal loss amplifier block 130. When the multiplexer 110 switches which signal is output, the multiplexer 110 optionally shorts the multiplexer output 126 to 0 mV for a brief period to allow the signal loss amplifier block 130 to zero out. The signal loss amplifier block 130 has an amplifier that increases the size of the multiplexer output 126 to a more useful size for comparison. Because there is no comparison to the output of the receiver limiting amplifier 50, the amplifier in the signal loss amplifier block 130 has a smaller footprint requirement and current requirement than the signal loss amplifier 74 in the prior art. The signal loss amplifier block 130 rectifies the amplified signal and outputs a combined direct current (DC) signal 136 that has a voltage potential proportional to the size of the signal received from the multiplexer output 126. The combined direct current signal 136 is called combined because depending on the state of the multiplexer 110, the same electrical conductor will have a signal from either the data path or the reference path. The signal loss amplifier block 130 is shown in more detail in FIG. 2d, with other features shown in Figure 3 and 4

[0019] The combined direct current signal 136 is routed to a demux 140. Depending on whether the multiplexer 110 is coupling the transimpedance amplifier output 40 or the reference signal 122 to the signal loss amplifier block 130, the multiplexer 140 splits the combined direct current signal 136 into either a data direct current signal 142 or a reference direct current signal 144 output. If the input to the signal loss amplifier block 130 is coupled through the multiplexer 110 to the transimpedance amplifier output 40, the demux 140 couples the combined direct current signal 136 to the data direct current signal 142 and presents a high impedance to the reference direct current signal 144. If the input to the signal loss amplifier block 130 is coupled through the multiplexer 110 to the reference signal 122, the demux 140 couples the combined direct current signal 136 to the reference direct current signal 144 and presents a high impedance to the data direct current signal 142. There is also a brief period of time when the multiplexer 110 switches which input is coupled to the multiplexer output 126 for the automatic zeroing of the signal loss amplifier block 130. During the automatic zeroing period, both outputs of the demux 140 are at high impedance.

[0020] ​The comparator block 150 receives the data DC signal 142 and the reference DC signal 144 and compares to determine if a signal loss has occurred. The comparator block 150 includes a pair of integration capacitors coupled to the data DC signal 142 and the reference DC signal 144, respectively. When the separator 140 couples the combined DC signal 136 to the data DC signal 142, the data integration capacitor in the comparator block 150 charges to the voltage potential of the combined DC signal 136. When the separator 140 has a high impedance output of the data DC signal 142, the data integration capacitor in the comparator block 150 holds the voltage level. Similarly, when the separator 140 couples the combined DC signal to the reference DC signal 144, the reference integration capacitor in the comparator block 150 charges to the voltage of the combined DC signal 136, otherwise the reference integration capacitor holds the voltage level during high impedance.

[0021] The comparator in the comparator block 150 determines if the voltage potential difference between the two conductors of the data DC signal 142 is higher or lower than the voltage potential between the two conductors of the reference DC signal 144 by comparing the voltage potentials of the two capacitors. If the voltage potential received on the data DC signal 142 is less than the voltage potential received on the reference DC signal 144, the magnitude of the transimpedance amplifier output 40 has fallen below the magnitude of the reference signal 122. The signal loss signal 80 is asserted by the comparator block 150 and the incoming optical signal should be considered lost by the device. Other details of the comparator block 150 are shown in FIG. 2e, where other features are shown in Figure 4

[0022] The signal loss circuit 100 is able to determine signal loss using only a single signal loss amplifier that is significantly smaller than the same amplifier required in the prior art as the receiver limiting amplifier 50. The signal loss circuit 100 time multiplexes the signal loss amplifier block 130 between the data signal and the reference signal 122 for the transimpedance amplifier output 40. Because the signal loss circuit 100 is coupled in parallel to the main data path of the receiver limiting amplifier 50, rather than using the output of the receiver limiting amplifier 50 in the signal loss comparison, the data signal to the signal loss amplifier block 130 can be interrupted. Because the data received during the interruption will be lost, the data to the receiver limiting amplifier 50 is not interruptable. However, the data signal to the signal loss circuit 100 is only used for the signal loss comparison and does not need to receive optical data correctly.

[0023] ​The data signal and the reference signal 122 at the output of the transimpedance amplifier 40 are time multiplexed in the signal loss amplifier block 130, then de-multiplexed at the output of the signal loss amplifier block for comparison. The multiplexed integrating amplifier for the signal loss detection (MIALOS) system provides a significantly reduced size and power for the optical transceiver. By removing the comparator 78 as a load for the receiver limiting amplifier, the performance of the main data receiver limiting amplifier 50 can be improved. Having a single amplifier path for signal loss detection allows for the use of a smaller amplifier stage as jitter is a smaller issue. The single amplifier path also means that the data and reference signals receive the same amount of amplification over temperature, process, and supply voltage variations, improving the accuracy of the signal loss comparison. Additionally, any DC offset from the signal loss amplifier block 130 is the same for the data and reference paths, so it can be cancelled out when comparing the DC difference in the comparator block 150. Any noise picked up by the signal loss amplifier block 130 can also be common to the data and reference signals, then cancelled out in the DC comparison.

[0024] One aspect of optical transceivers that makes the multiplexed signal loss amplifier topology difficult to implement in the prior art is that the transmission gates typically used in optical transceivers are not fast enough to multiplex the received signals quickly. Typically, Bi-CMOS technology is used to fabricate the transceiver with BJTs for RF amplification and CMOS for control logic. Since the RF signals are not switched through the CMOS control logic, the slower CMOS technology is used to save money. The CMOS portion of the Bi-CMOS process used in the prior art is too slow to properly implement the signal loss circuit 100. The signal loss circuit 100 uses CMOS transmission gates that are accurate at the full switching frequency of the data signal, such as 5 GHz for a 10 gigabit data connection.

[0025] One advantage of the multiplexed topology with the signal loss circuit 100 independent of the receiver limiting amplifier 50 is that the receiver limiting amplifier can be turned off to save power while the control logic can still monitor the signal for a valid or invalid signal loss signal 80. In the prior art, if the receiver limiting amplifier 50 is turned off, there is nothing to compare to the reference signal. The signal loss circuit 100 can also be turned off while still receiving data through the receiver limiting amplifier 50.

[0026] Figure 2c shows further details of the reference signal generator 120. The signal generator 120 has a signal loss reference voltage generator 151 and a signal loss reference modulator 152. The voltage generator 151 is controlled by a signal loss level input 154, a signal loss hysteresis input 155, and a signal loss state input 156. The voltage generator 151 includes a digital-to-analog converter (DAC) and a buffer driver to output a direct current voltage 158 to the modulator 152 based on the signals received at the inputs 154-156. The direct current voltage 158 is a voltage configured by the inputs 154-156 to be approximately equal to the minimum acceptable peak-to-peak voltage swing across the transimpedance amplifier output 40. The direct current voltage 158 includes two conductors with two different voltage levels that are referenced to a common mode voltage.

[0027] The value of the direct current voltage 158 is controlled by the inputs 154-156. In one embodiment, the inputs 154-156 are connected to hardware registers within the transceiver that are controlled by a processor internal or external to the transceiver. The signal loss level input 154 sets a default direct current voltage value for the direct current voltage 158. In one embodiment, the signal loss level input 154 is an 8-bit input to the voltage generator 151 that sets the direct current voltage 158 to a value between 0 mV and 127 mV, with the binary value of the input 154 setting the direct current voltage value to 0.5 mV increments. Not all values of the signal loss level input 154 are recommended, for example, in some embodiments, signal loss accuracy can only be guaranteed in a range between 10 mV and 100 mV.

[0028] The signal loss hysteresis input 155 controls the amount of hysteresis applied when the signal loss occurs. In one embodiment, the signal loss hysteresis input 155 is a three-bit value that sets the value of the hysteresis in decibels (dB). In one embodiment, each binary digit increment of the signal loss hysteresis input 155 increases the hysteresis of the voltage generator 151 by 0.5 dB, for example, 0b000 disables the hysteresis, 0b001 provides a hysteresis of 0.5 dB, and 0b111 provides a hysteresis of 3.5 dB. In other embodiments, the conversion between the binary value of the signal loss hysteresis input 155 and the actual hysteresis value can use any suitable encoding.

[0029] When the signal loss circuit 100 causes the signal loss signal 80 to be active, the signal loss state input 156 is active. The signal loss state input 156 can be directly coupled to the signal loss signal 80, or there can be intervening logic. When a signal loss is detected, the signal loss state input 156 informs the voltage generator 151, and thus an application of hysteresis. When the signal loss state input 156 is active, the DC voltage 158 is increased by a gain factor set by the signal loss hysteresis input 155, for example, a 1.0 dB hysteresis setting of the hysteresis input would increase the DC voltage 158 from 50 mV to approximately 56.1 mV. A 1.0 dB hysteresis setting for a 50 mV threshold level means that if the transimpedance amplifier output 40 falls below 50 mV, i.e., below the signal loss threshold, the loss of optical signal will be deemed to have occurred until the transimpedance amplifier output 40 rises to at least 56.1 mV. The hysteresis reduces the likelihood of the signal loss signal 80 rapidly switching between active and inactive.

[0030] In addition to the inputs 154-156, there can also be an input to the voltage generator 151 or a programmable register within the voltage generator 151 to set a temperature slope of the DC voltage 158. The voltage generator 151 is programmable to match the falling gain of the transimpedance amplifier 30 as the temperature rises. In one embodiment, there are eight separate slopes between 0 dB / °C and 0.028 dB / °C, which correspond to codes 0x00 through 0x07 in the register. A programmable temperature slope correction block in the voltage generator 151 applies a bias current to the voltage generator such that the DC voltage 158 tracks the changes in the transimpedance amplifier output 40 to give an accurate optical signal level threshold. The temperature can be detected by a temperature detection circuit in the voltage generator 151 or on the transimpedance amplifier 30. The temperature detection circuit can be a thermistor with a resistance that varies with temperature, a capacitor with a capacitance that depends on the temperature value, or any other suitable device.

[0031] The signal loss modulator 152 receives the DC voltage signal 158 from the voltage generator 151 and chops the voltage at a suitable frequency to produce the reference signal 122. The signal loss modulator 152 includes a switch that alternates between outputting the voltage potential of the DC voltage 158 to the reference signal 122 or outputting 0 V to the reference signal output. Thus, the reference signal 122 becomes an alternating current signal with a peak-to-peak amplitude approximately equal to the voltage potential of the DC voltage 158. In one embodiment, the signal loss modulator 152 chops the DC voltage 158 at 10 megahertz (MHz) to produce the reference signal 122.

[0032] The reference signal 122 is coupled to the multiplexer 110 along with the transimpedance amplifier output 40, and the multiplexer 110 couples one of the two signals to the signal loss amplifier block 130 via a multiplexer output 126. Figure 2d shows details of the signal loss amplifier block 130. The multiplexer output 126 is coupled as an input to a signal loss amplifier 160. In one embodiment, the signal loss amplifier 160 is a high speed linear amplifier. The signal loss amplifier 160 outputs an amplified version of the multiplexer output 126 as a signal loss amplifier output 162.

[0033] The signal loss amplifier output 162 is an alternating current (AC) signal that is substantially the same as the transimpedance amplifier output 40 or the reference signal 122, depending on the signal output by the multiplexer 110. The AC signal of the signal loss amplifier output 162 is coupled to a radio frequency (RF) rectifier 164. The rectifier 164 includes diodes configured in a full wave bridge rectifier to produce a combined direct current signal 136. Other rectifier topologies are used in other embodiments. The combined direct current signal 136 includes a voltage potential on two conductors that is approximately equal to the amplitude of the signal loss amplifier output 162. A capacitor in the comparator block 150 holds the voltage potential of the combined direct current signal 136 near the peak voltage of the AC signal. With no significant load on the combined direct current signal 136, the ripple remains at a relatively low level.

[0034] The signal loss amplifier output 162 is also coupled to an auto-zero amplifier block 166. The auto-zero amplifier block 166 includes a differential operational transconductance amplifier (OTA). The differential operational transconductance amplifier in the auto-zero amplifier block 166 amplifies the direct current offset from the signal loss amplifier 160 and outputs a bias direct current 168 to the signal loss amplifier. The bias current 168 is fed to a sampling and hold circuit to correct for the direct current offset of the signal loss amplifier 160. The zeroed offset value is stored as charge on a capacitor in the auto-zero amplifier block 166. The capacitor is significantly smaller than the capacitor required in direct current restoration circuits in prior art topologies.

[0035] In some embodiments, automatic zeroing occurs when the multiplexer 110 switches the signal being amplified. When the signal is switched, there is a brief period of time where the multiplexer 110 shorts the input of the amplifier 160 to zero millivolts. The automatic zeroing amplifier 166 changes the bias current 168 during automatic zeroing to zero the output of the amplifier 160. The bias current 168 remains constant when the amplifier 160 is amplifying either the transimpedance amplifier output 40 or the reference signal 122, and automatic zeroing occurs again when the multiplexer 110 switches the input signal to the amplifier block 130. In other embodiments, the automatic zeroing amplifier block 166 can update the automatic zeroing bias current 168 less frequently, or can constantly update the bias current even when the amplifier 160 is in an active state. In other embodiments, the input to the automatic zeroing amplifier 166 is provided by the combined DC signal 136 instead of the AC signal from the signal loss amplifier output 162.

[0036] The combined DC signal 136 is a voltage potential that represents the amplitude of whichever signal is currently input to the signal loss amplifier block 130 (either the reference signal 122 or the transimpedance amplifier output 40). The combined DC signal 136 is passed to the splitter 140 and split into two different inputs to the comparator block 150 depending on which signal is input to the amplifier block 130. If the block 130 is amplifying the transimpedance amplifier output 40, then the splitter 140 couples the combined DC signal 136 to the data DC signal 142, and the reference DC signal 144 is a high impedance output from the splitter. If the block 130 is amplifying the reference signal 122, then the splitter 140 couples the combined DC signal 136 to the reference DC signal 144, and the data DC signal 142 is a high impedance output from the splitter. High impedance means that the splitter 140, similar to an open connection to a particular output, does not draw a large current from or output a large current to the high impedance output. In the high impedance state, the individual capacitors in the comparator block 150 can hold a charge and maintain a relatively constant voltage potential when the other splitter 140 output is selected.

[0037] Figure 2e shows details of the comparator block 150 receiving the data DC signal 142 and the reference DC signal 144 from the splitter 140. The comparator block 150 has two integrating capacitors. The data integrating capacitor 172 receives a voltage potential from the data DC signal 142 and charges to a voltage potential proportional to the peak-to-peak amplitude of the transimpedance amplifier output 40. The data integrating capacitor 172 then maintains approximately the same voltage potential while the amplifier block 130 switches to amplify the reference signal 122. When the reference signal 122 is amplified, the splitter 140 couples the combined DC signal 136 to the reference DC signal 144 and charges the reference integrating capacitor 174 to a voltage potential proportional to the reference signal 122.

[0038] The decoupler 140 alternately updates the capacitors 172 and 174 while the other capacitor maintains its voltage potential. The comparator 176 receives the voltage potentials of the data DC signal 142 and the reference DC signal 144 and outputs a signal indicating which of the two inputs is higher. In one embodiment, the comparator 176 is implemented using an operational amplifier capable of comparing two differential inputs. When the data DC signal 142 is lower than the reference DC signal 144, the comparator 176 outputs a logic signal to indicate a signal loss. The output of the comparator 176 can be active low or active high. In some embodiments, the comparator block 150 includes a resistive-capacitive filter between the input of the integrator capacitors 172-174 and the comparator 176 to reduce the effect of noise on the DC signals 142 and 144 on the comparator 176.

[0039] The output of the comparator 176 is optionally routed through a glitch filter 180 to produce the signal loss signal 80. The glitch filter 180 is a delay filter that requires the output of the comparator 176 to be active for a threshold time before the active signal loss signal 80. In one embodiment, the glitch filter includes a 2.5 microsecond (μβ) delay. The delay can be configured by a resistive-capacitive (RC) filter that slows the rise time of the signal from the comparator 176 to a buffer in the glitch filter 180. The glitch filter 180 reduces the likelihood of the active signal loss signal 80 being activated by very short glitches in the optical signal that are normal and do not necessarily result in data loss.

[0040] Figure 3 An embodiment of the signal loss amplifier block 130 is shown as signal loss amplifier block 130b having two amplifier stages 160a and 160b. The first amplifier 160a receives the multiplexer output 126 and applies amplification to produce a first stage amplified signal 162a. The output of the amplifier 160a is rectified by a rectifier 164a and provided as a first stage DC signal 136a to the switch 140b. The first stage amplified signal 162a is also coupled as an input to the second stage amplifier 160b. The second stage amplifier 160b applies a second amplification factor on top of the amplification already done by the first stage amplifier 160a. The output of the second stage amplifier 160b is rectified by a rectifier 164b and coupled as a second stage amplified signal 162b to the switch 140b.

[0041] The operation of switch 140b is similar to that of separator 140 in the previous embodiment. However, in addition to demultiplexing the input to data DC signal 142 or reference DC signal 144, switch 140b also includes a switch for selecting the output of first-stage amplifier 160a or the output of second-stage amplifier 160b. The two-stage amplifier-enabled signal loss circuit 100 applies different amounts of amplification depending on the amplitude of the input signal.

[0042] Smaller input signals typically require greater amplification to ensure accurate comparison with a reference. In one embodiment, if the amplitude of the reference signal 122 is less than or equal to 20mV, two amplification stages are used. Otherwise, only the first amplification stage is used. To use two amplification stages, switch 140 connects the second-stage DC signal 136b to the appropriate DC signal 142 or 144. To use only the first amplification stage, switch 140 connects the first-stage DC signal 136a to the appropriate output. To save power, the signal loss circuit 100 can be configured to de-energize the second-stage amplifier 160b when only the first stage is used.

[0043] The auto-zero amplifier 166b has a first-stage amplified signal 162a and a second-stage amplified signal 162b as inputs. Based on the correct input, the auto-zero amplifier 166b returns to zero, depending on which output the switch 140b is using. Therefore, the output being used is the same as the output being zeroed.

[0044] Figure 4 It shows that it can be used with Figure 3 A switching RF rectifier used together by two amplifier stages. Each rectifier block 200 includes a switch 202, which switches and demultiplexes the outputs of amplifiers 160a and 160b to capacitors 172 and 174. Switch 202 can be implemented using CMOS logic gates, bipolar junction transistors, or any other electronic device that can be used to control current. Switch 202 Implementation Figure 3 The function of switch 140b is the same as that of switch 202, but switch 202 is contained in rectifier block 200 with rectifier 164.

[0045] Switch 202a is coupled between the first-stage rectifier 164a and the data integrating capacitor 172. During periods when only the first amplifier stage 160a is activated, the second amplifier stage 160b is not used, and the multiplexer 110 connects the transimpedance amplifier output 40 to the amplifier block 130, switch 202a is closed by a controller or other logic to connect the data integrating capacitor 172 to the rectifier 164a and charge the data integrating capacitor to the potential voltage of the first-stage DC signal 136a. Switch 202b is opened to prevent modification of the value stored in the reference integrating capacitor 174.

[0046] Switch 202b is coupled between the first stage rectifier 164a and the reference integration capacitor 174. During time periods when only the first amplifier stage 160a is active, the second amplifier stage 160b is not used, and the multiplexer 110 connects the reference signal 122 to the amplifier block 130, the switch 202b is closed by the controller or other logic to connect the reference integration capacitor 174 to the rectifier 164a and charge the reference integration capacitor to the voltage potential of the first stage DC signal 136a. Switch 202a is open to prevent modification of the value stored on the data integration capacitor 172.

[0047] Switch 202c is coupled between the second stage rectifier 164b and the data integration capacitor 172. During time periods when both the first amplifier stage 160a and the second amplifier stage 160b are used in series, and the multiplexer 110 connects the transimpedance amplifier output 40 to the amplifier block 130, the switch 202c is closed by the controller to charge the data integration capacitor 172 to the voltage potential of the second stage DC signal 136b from the rectifier 164b. Switch 202d is open to prevent modification of the voltage potential stored in the reference integration capacitor 174.

[0048] Switch 202d is coupled between the second stage rectifier 164b and the reference integration capacitor 174. During time periods when both the first amplifier stage 160a and the second amplifier stage 160b are used in series, and the multiplexer 110 connects the reference signal 122 to the amplifier block 130, the switch 202d is closed by the controller or other logic to charge the reference integration capacitor 174 to the voltage potential of the second stage DC signal 136b from the rectifier 164b. Switch 202c is open to maintain the voltage potential on the data integration capacitor 172.

[0049] Figure 5 A timing diagram showing the operation of the signal loss circuit 100 is shown. The first graph shows the reference signal 122 as a function of time, labeled REF 122. The threshold is set to 40 mV peak-to-peak, so the AC signal of the reference signal 122 extends from -20 mV to +20 mV at time t0. The second graph shows the transimpedance amplifier output 40, labeled TIA OUT 40. At time t0, the amplitude of the transimpedance amplifier output 40 is greater than the 40 mV peak-to-peak threshold.

[0050] Figure 5The third graph in FIG. 12 shows the multiplexer output 126. The multiplexer output 126 alternates between outputting the reference signal 122 and the transimpedance amplifier output 40. The shading of the various graph sections of the multiplexer output 126 indicates the source. If the multiplexer 110 is outputting the reference signal 122 at a given time on the graph (e.g., from time tl to time t4), that section has a square or diamond shading similar to the graph of the reference signal 122. If the multiplexer output 126 is outputting the transimpedance amplifier output 40 (e.g., from time t5 to time t8), that section of the graph of the multiplexer output 126 will be shaded with diagonal lines (as in the graph of the transimpedance amplifier output 40).

[0051] The multiplexer 110 repeatedly alternates between outputting the reference signal 122 and the transimpedance amplifier output 40. In Figure 5 In FIG. 12, the multiplexer 110 first outputs the reference signal 122 from time tl to t4, and then outputs the transimpedance amplifier output 40 from time t5 to t8. As the signal loss circuit 100 operates, the multiplexer 110 continues to alternate between outputting the reference signal 122 and the transimpedance amplifier output 40. The time axis is labeled in convenient time units for the purpose of explaining the function of the signal loss circuit 100, and need not necessarily use normal time units, e.g., μs. In one embodiment, each signal is output by the multiplexer 110 for 6-10 μs. The time for outputting each signal should be long enough to properly integrate the signal on the capacitors 172 and 174. The time units also need not necessarily be constant, i.e., the zeroing period between each signal output to the multiplexer output 126 need not necessarily be one quarter of the signal output time.

[0052] Each time the multiplexer 110 switches which signal is being output, the output is shorted to 0 mV for a period of time. The auto-zeroing amplifier block 166 adjusts the signal loss amplifier 160 so that the amplifier outputs approximately 0 mV when the multiplexer output 126 is at 0 mV. Each time the multiplexer output 126 is switched, the signal loss circuit 100 zeroes the amplifier block 160 so that the new signal is properly zeroed with the amplifier. Figure 5 The graph in FIG. 12 begins at time to, where the multiplexer output 126 is at 0 mV for one unit of time. Between to and tl, the input to the amplifier block 130 from the multiplexer 110 is at 0 mV, and the auto-zeroing amplifier 166 adjusts the signal loss amplifier 160 to output approximately 0 mV.

[0053] Figure 5The fourth plot in FIG. 2 shows the voltage potential of the data DC signal 142 and the reference DC signal 144. At time tl, when the multiplexer 110 begins outputting the reference signal 122, the voltage potential of the reference DC signal 144 rises as the reference integration capacitor 174 charges. The reference DC signal 144 rises to approximately 40 mV DC voltage, which is the peak-to-peak voltage potential of the reference signal 122. Since the reference signal 122 is first output by the multiplexer 110, the voltage on the reference integration capacitor 174 is momentarily higher than the data integration capacitor 172, and the signal loss signal 80 is asserted. The signal loss signal 80 is asserted for a short period of time, from time tl to time t2, and the signal loss circuit 100 is configured to ignore the false assertion of the signal loss signal 80 during the startup period. Figure 5 The fifth and final plot in FIG. 2 shows the voltage potential of the data DC signal 142 and the reference DC signal 144. At time tl, when the multiplexer 110 begins outputting the reference signal 122, the voltage potential of the reference DC signal 144 rises as the reference integration capacitor 174 charges. The reference DC signal 144 rises to approximately 40 mV DC voltage, which is the peak-to-peak voltage potential of the reference signal 122. Since the reference signal 122 is first output by the multiplexer 110, the voltage on the reference integration capacitor 174 is momentarily higher than the data integration capacitor 172, and the signal loss signal 80 is asserted. The signal loss signal 80 is asserted for a short period of time, from time tl to time t2, and the signal loss circuit 100 is configured to ignore the false assertion of the signal loss signal 80 during the startup period.

[0054] The multiplexer 110 completes outputting the reference signal 122 at time t4, and again outputs a time unit of 0 mV to the auto-zero signal loss amplifier 160 before switching to output the transimpedance amplifier output 40 between time t5 and time t8. When the multiplexer 110 outputs the transimpedance amplifier output 40 between t5 and t8, the data DC signal 142 rises in voltage potential as the data integration capacitor 172 charges, which is approximately equal to the peak-to-peak amplitude of the transimpedance amplifier output 40. Shortly after time t6, the data DC signal 142 increases above the reference DC signal 144, resulting in the signal loss signal 80 being de-asserted. At the same time, the isolator 140 output to the reference DC signal 144 is in high impedance to allow the reference integration capacitor 174 to maintain the reference DC voltage steady as the data DC signal 142 charges.

[0055] After another auto-zero period from time t8 to t9, the reference signal 122 is again output to the reference DC signal 144 from time t9 to time tl2. The reference signal 122 does not change, so the reference DC signal 144 remains at the existing voltage potential of approximately 40 mV. At the same time, the isolator 140 output to the data DC signal 142 is in high impedance to allow the data integration capacitor 172 to maintain the data DC signal voltage potential steady.

[0056] From time t13 to time t16, multiplexer 110 again outputs transimpedance amplifier output 40. At time t14, the amplitude of transimpedance amplifier output 40 begins to decrease due to the decrease in the amplitude of the optical signal received by photodiode 20. Accordingly, the amplitude of multiplexer output 126 begins to decrease at time t14. As multiplexer 110 no longer outputs transimpedance amplifier output 40, the decreasing peak-to-peak amplitude of transimpedance amplifier output 40 and multiplexer output 126 decreases the voltage potential of data DC signal 142 from time t14 to time t16. From time t16 to t21, the amplitude of transimpedance amplifier output 40 continues to decrease as signal loss circuit 100 automatically zeros and updates reference DC signal 144. However, multiplexer 110 does not pass transimpedance amplifier output 40, and thus data DC signal 142 is not updated until time t21. The output of splitter 140 to data DC signal 142 is high impedance, and the voltage potential is maintained by data integration capacitor 172.

[0057] By time t21, the amplitude of transimpedance amplifier output 40 has decreased below the amplitude of reference signal 122 when multiplexer 110 again outputs transimpedance amplifier output 40. As the voltage of data DC signal 142 is low, data integration capacitor 172 begins to discharge at time t21. Shortly after time t21, the voltage potential of data DC signal 142 decreases below the voltage potential of reference DC signal 144, causing comparator 176 to assert signal loss signal 80. Data DC signal 142 continues to decrease until time t24, at which time the output from splitter 140 becomes high impedance.

[0058] Shortly after time t21, when signal loss signal 80 is asserted, the hysteresis feature of reference signal generator 120 begins and increases the peak-to-peak voltage potential of reference signal 122. At time t25, the next time multiplexer 110 outputs reference signal 122, the increased voltage potential is reflected to reference DC signal 144. Data DC signal 142 will need to increase to a voltage potential slightly higher than the initial value of reference signal 122 to de-assert signal loss signal 80.

[0059] While one or more embodiments of the application have been illustrated and described, it will be clear to those skilled in the art that modifications and adaptations can be made to those embodiments without departing from the scope of the present application as set forth in the following claims.

Claims

1. A semiconductor device comprising: a multiplexer; a photodiode coupled to a first input of the multiplexer; a reference signal generator coupled to a second input of the multiplexer, wherein the multiplexer is configured to switch between outputting a first signal received from the first input and a second signal received from the second input; a first amplifier coupled to an output of the multiplexer; a splitter comprising an input of the splitter coupled to an output of the first amplifier, wherein the splitter is configured to switch with the multiplexer such that the first signal is output on a first output of the splitter and the second signal is output on a second output of the splitter; and a comparator comprising a first input of the comparator coupled to the first output of the splitter and a second input of the comparator coupled to the second output of the splitter.

2. The semiconductor device of claim 1, further comprising: a first capacitor coupled to the first output of the splitter; and a second capacitor coupled to the second output of the splitter. the multiplexer is configured to temporarily output 0 mV when switching between outputting the first signal and the second signal.

3. The semiconductor device according to claim 1, wherein 4. The semiconductor device of claim 3, further comprising an output of the comparator coupled to an input of the reference signal generator.

5. The semiconductor device of claim 1, further comprising a limiting amplifier coupled to the photodiode in parallel with the multiplexer.

6. The semiconductor device of claim 1, further comprising a transconductance amplifier coupled from an output of the first amplifier to an input of the first amplifier.

7. A semiconductor device comprising: a multiplexer; a data input coupled to a first input of the multiplexer; a reference signal generator coupled to a second input of the multiplexer; an amplifier coupled to an output of the multiplexer; a splitter comprising an input of the splitter coupled to an output of the amplifier; and a comparator comprising a first input of the comparator coupled to a first output of the splitter and a second input of the comparator coupled to a second output of the splitter.

8. The semiconductor device of claim 7, further comprising a rectifier coupled to an output of the amplifier.

9. The semiconductor device of claim 7, further comprising: a first capacitor coupled to the first output of the splitter; and a second capacitor coupled to the second output of the splitter.

10. A method of detecting signal loss comprising: receiving a data signal at a first input of a multiplexer; receiving a reference signal at a second input of the multiplexer; configuring the multiplexer to switch between outputting the data signal to an amplifier and outputting the reference signal to the amplifier; coupling an input of a splitter to an output of the amplifier, wherein the splitter is configured to switch with the multiplexer such that the data signal is output on a first output of the splitter and the reference signal is output on a second output of the splitter; ​ ​ ​ coupling a first output of the splitter to a first input of the comparator; and coupling a second output of the splitter to a second input of the comparator.

11. The method of claim 10, further comprising temporarily outputting 0 mV from the multiplexer when switching between the output data signal and the output reference signal.

12. The method of claim 10, further comprising rectifying the output of the amplifier to generate a direct current (DC) signal.

13. The method of claim 10, further comprising: coupling a first output of the splitter to a first capacitor; and coupling a second output of the splitter to a second capacitor.

14. The method of claim 13, wherein, the comparator compares the first input to the second input to determine whether a loss of signal has occurred.

Images