Correction method, analog-to-digital converter and circuit structure

Abstract

The application discloses a correction method, an analog-to-digital converter and a circuit structure. The correction method comprises the following steps: converting an analog input signal by using a first analog-to-digital converter to obtain a first M-bit code value; adding a disturbance to the first M-bit code value to obtain a second M-bit code value; loading the first M-bit code value and the second M-bit code value into a second analog-to-digital converter respectively and converting the analog input signal to obtain a first N-bit code value and a second N-bit code value; processing the first N-bit code value and the second N-bit code value according to a capacitor weight relationship to obtain a first output code value and a second output code value; and correcting the capacitor weight relationship to obtain an updated weight when an output difference between the first output code value and the second output code value is greater than a preset error. The application adds the disturbance to the first M-bit code value, so that the second analog-to-digital converter generates two groups of output code values for the same analog input signal, the capacitor weight relationship can be corrected according to the two groups of output code values, thereby reducing system error and ensuring the linearity of the system.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and more specifically, to a calibration method, an analog-to-digital converter, and a circuit structure. Background Technology

[0002] In related technologies, since the digital output code value of a successive approximation register (SAR) analog-to-digital converter (ADC) corresponds one-to-one with the analog input signal, the result of each comparison must be accurate to ensure the linearity of the SAR ADC. This requires the capacitor weighting relationship to be accurate. In high-precision ADC applications, problems such as capacitor mismatch can no longer be ignored, directly affecting the linearity of medium- and high-precision SAR ADCs. Therefore, ensuring the linearity of the system in the design of high-precision SAR ADCs is a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0003] Implementations of this application relate to a correction method, an analog-to-digital converter, and a circuit structure.

[0004] The correction method of this application is used for a successive approximation analog-to-digital converter (ADC). The ADC includes an M-bit first ADC and an N-bit second ADC, where N is greater than M. The first M bits of the first ADC's capacitor correspond to the first M high-order bits of the second ADC's capacitor. The correction method includes: acquiring an analog input signal; converting the analog input signal using the first ADC to obtain a first M-bit code value; loading the first M-bit code value onto the first M bits of the second ADC's code value and converting the analog input signal using the second ADC to obtain a first N-bit code value; adding a perturbation to the first M-bit code value to obtain a second M-bit code value; loading the second M-bit code value onto the first M bits of the second ADC's code value and converting the analog input signal using the second ADC to obtain a second N-bit code value; processing the first N-bit code value and the second N-bit code value according to a capacitor weighting relationship to obtain a first output code value and a second output code value; determining whether the output difference between the first output code value and the second output code value is greater than a preset error; and correcting the capacitor weighting relationship to obtain updated weights when the output difference is greater than the preset error.

[0005] In some embodiments, the first analog-to-digital converter includes a first digital-to-analog converter, a first comparator, and a first logic unit. The first digital-to-analog converter outputs a first analog signal, the first comparator compares the first analog signal with the analog input signal, and the first logic unit determines the first M-bit code value based on the comparison result of the first comparator. The second analog-to-digital converter includes a second digital-to-analog converter, a second comparator, and a second logic unit. The second digital-to-analog converter outputs a second analog signal, the second comparator compares the second analog signal with the analog input signal, and the second logic unit determines the first N-bit code value or the second N-bit code value based on the comparison result of the second comparator.

[0006] In some embodiments, loading the first M-bit code value onto the first M-bit code value of the second analog-to-digital converter and using the second analog-to-digital converter to convert the analog input signal to obtain the first N-bit code value includes: directly using the first M-bit code value as the first M-bit code value of the second analog-to-digital converter and using the second analog-to-digital converter to convert the analog input signal to obtain the first N-bit code value.

[0007] In some implementations, the first M-bit code value is binary, and the step of adding perturbation to the first M-bit code value to obtain the second M-bit code value includes: randomly increasing or decreasing the first M-bit code value by one least significant bit to obtain the second M-bit code value.

[0008] In some implementations, the first M-bit code value is non-binary, and the step of adding perturbation to the first M-bit code value to obtain the second M-bit code value includes: converting the first M-bit code value into a preset base code value according to a preset weight and adding perturbation to the preset base code value to obtain a perturbed code value; and converting the perturbed code value into an M-bit code value according to the preset weight to serve as the second M-bit code value.

[0009] In some embodiments, the step of converting the first M-bit code value into a preset base code value according to a preset weight and adding a perturbation to the preset base code value to obtain a perturbed code value includes: converting the first M-bit code value into the preset base code value according to the preset weight and randomly increasing or decreasing the preset base code value by one least significant bit to obtain the perturbed code value.

[0010] In some embodiments, loading the second M-bit code value into the first M-bit code value of the second analog-to-digital converter and using the second analog-to-digital converter to convert the analog input signal to obtain the second N-bit code value includes: directly using the second M-bit code value as the first M-bit code value of the second analog-to-digital converter and using the second analog-to-digital converter to convert the analog input signal to obtain the second N-bit code value.

[0011] In some implementations, the steps of loading the first M-bit code value onto the first M-bit code value of the second analog-to-digital converter and converting the analog input signal using the second analog-to-digital converter to obtain the first N-bit code value and the step of adding a perturbation to the first M-bit code value to obtain the second M-bit code value are performed simultaneously.

[0012] In some embodiments, the correction method further includes: using the updated weights as a new capacitance weight relationship and repeating the correction method until the output difference is less than the preset error.

[0013] In some implementations, correcting the capacitor weight relationship to obtain the updated weights includes: correcting the capacitor weight relationship based on the output difference, the iteration step size, the first N-bit code value, and the second N-bit code value to obtain the updated weights.

[0014] In some implementations, the capacitor weight relationship includes N weights, each weight corresponding to one bit. Correcting the capacitor weight relationship based on the output difference, iteration step size, the first N-bit code value, and the second N-bit code value to obtain the updated weight includes: determining the difference between a first code value of a preset bit in the first N-bit code value and a second code value of a preset bit in the second N-bit code value; correcting the weight corresponding to the preset bit based on the output difference, the iteration step size, and the difference; and correcting each weight of the capacitor weight relationship to obtain the updated weight.

[0015] The successive approximation analog-to-digital converter (ADC) of this application includes an M-bit first ADC and an N-bit second ADC, where N is greater than M. The first M bits of the first ADC's capacitance correspond to the first M high-order bits of the second ADC's capacitance. The ADC further includes a digital perturbation introduction module and a processing module. The first ADC is used to acquire an analog input signal and convert the analog input signal to obtain a first M-bit code value. The digital perturbation introduction module is used to add a perturbation to the first M-bit code value to obtain a second M-bit code value. The second ADC is used to acquire the analog input signal, load the first M-bit code value into the first M-bit code value and convert the analog input signal to obtain a first N-bit code value, and load the second M-bit code value into the first M-bit code value and convert the analog input signal to obtain a second N-bit code value. The processing module is used to process the first N-bit code value and the second N-bit code value according to the capacitor weight relationship to obtain the first output code value and the second output code value, determine whether the output difference between the first output code value and the second output code value is greater than a preset error, and when the output difference is greater than the preset error, correct the capacitor weight relationship to obtain the updated weight.

[0016] The circuit structure of this application includes a successive approximation analog-to-digital converter (ADC). The ADC comprises an M-bit first ADC and an N-bit second ADC, where N is greater than M. The first M bits of the first ADC's capacitor correspond to the first M high-order bits of the second ADC's capacitor. The circuit structure also includes a digital perturbation introduction module and a processing module. The first ADC acquires an analog input signal and converts the analog input signal to obtain a first M-bit code value. The digital perturbation introduction module adds a perturbation to the first M-bit code value to obtain a second M-bit code value. The second ADC acquires the analog input signal, loads the first M-bit code value into the first M-bit code value, converts the analog input signal to obtain a first N-bit code value, loads the second M-bit code value into the first M-bit code value, and converts the analog input signal to obtain a second N-bit code value. The processing module is used to process the first N-bit code value and the second N-bit code value according to the capacitor weight relationship to obtain the first output code value and the second output code value, determine whether the output difference between the first output code value and the second output code value is greater than a preset error, and when the output difference is greater than the preset error, correct the capacitor weight relationship to obtain the updated weight.

[0017] In the correction method, analog-to-digital converter, and circuit structure of this application, a perturbation is added to the quantization result (first M-bit code value) of the first analog-to-digital converter, causing the second analog-to-digital converter to generate two sets of output code values ​​for the same analog input signal. Based on the two sets of output code values, it can be determined whether the perturbation affects the output result of the analog-to-digital converter. If so, the capacitor weighting relationship can be corrected, thereby reducing system error and ensuring the linearity of the system. Since the perturbation is added to the first M-bit code value, this perturbation does not directly modify the analog input signal. Therefore, the second N-bit code value after conversion by the second analog-to-digital converter is the actual result, and no additional perturbation removal is required.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 This is a schematic diagram of the circuit structure of some embodiments of this application.

[0021] Figure 2 This is a flowchart illustrating the correction method of some embodiments of this application.

[0022] Figure 3This is a schematic diagram of the circuit structure of some embodiments of this application.

[0023] Figure 4 This is a schematic diagram of the circuit structure of some embodiments of this application.

[0024] Figure 5 This is a schematic diagram of a first analog-to-digital converter according to certain embodiments of this application.

[0025] Figure 6 This is a schematic diagram of a second analog-to-digital converter according to certain embodiments of this application.

[0026] Figures 7 to 14 This is a flowchart illustrating the correction method of some embodiments of this application. Detailed Implementation

[0027] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0028] An ADC (Analog-to-Digital Converter) acts as a bridge between analog and digital signals, converting continuous analog signals into digital signals that can be stored and processed by a computer. It is an indispensable part of today's digital world. It has long been widely used in fields such as communications, medicine, instrumentation, imaging, and audio. With the continuous shrinking of CMOS process dimensions and the rapid development of the communications and information field, the main development direction of ADCs is to pursue higher accuracy, faster speed, and lower power consumption.

[0029] However, the speed and accuracy of an ADC are two key performance indicators that are mutually restrictive, requiring a trade-off when designing an ADC. Therefore, various ADC structures with different performance characteristics have been developed. Among them, a hybrid ADC, the two-step SAR ADC, replaces the high-bit quantization process of the main SAR ADC with a small-capacitance auxiliary ADC, thereby reducing the power consumption of the high-bit capacitors in the main SAR ADC and reducing the comparator voltage domain to lower power consumption. Compared to SAR ADCs, the two-step SAR ADC has the advantage of lower power consumption and is widely used in high-precision, low-power applications. In SAR ADCs, the digital-to-analog converter (DAC) is a crucial component. SAR ADCs typically use capacitor-based DAC modules, which are sufficient for low-to-medium precision applications. However, in high-precision applications, capacitor mismatch cannot be ignored, and the DAC module requires more capacitors as the number of bits increases, leading to higher power consumption.

[0030] In SAR ADCs, the mismatch in the DAC capacitor array severely affects the system's linearity. To obtain the actual weights of the capacitors, a correction algorithm is typically used to correct the weight values ​​of the capacitor array. Analog correction is a commonly used correction algorithm.

[0031] Analog calibration refers to compensating for or eliminating capacitor weight mismatch through analog domain operations. Based on the ADC's operating state during calibration, the calibration algorithm can be further subdivided into front-end calibration and back-end calibration. Analog front-end calibration avoids complex digital circuit design, simplifying the circuit. Its disadvantage is that it requires the added calibration DAC to also have very high accuracy, which not only significantly increases the overall area and power consumption but also makes it difficult to meet the calibration requirements of high-precision ADCs. Furthermore, front-end calibration cannot respond to environmental factors in real time.

[0032] Since the digital output code value of a SAR ADC corresponds one-to-one with the input signal, the result of each comparison must be accurate to ensure the linearity of the SAR ADC. This requires that the capacitor weighting relationship be accurate. In high-precision ADC applications, the mismatch between capacitors can no longer be ignored, which directly affects the linearity of medium- and high-precision SAR ADCs. In addition, the nonlinearity caused by the parasitic capacitance of the sub-DAC capacitor array in the segmented capacitor array will also directly cause the capacitor weighting to be non-ideal. Therefore, in the design of high-precision SAR ADCs, capacitor weighting correction algorithms are often used to ensure the linearity of the system.

[0033] Please see Figure 1 and Figure 2 The correction method of this application can be used in a successive approximation analog-to-digital converter 10. The analog-to-digital converter 10 includes an M-bit first analog-to-digital converter (also called an auxiliary ADC) 12 and an N-bit second analog-to-digital converter (also called a main ADC) 14, where N is greater than M. The first M bits of the capacitance of the first analog-to-digital converter 12 correspond to the first M high-order bits of the capacitance of the second analog-to-digital converter 14. The correction method includes:

[0034] 012: Acquire analog input signal (V) in );

[0035] 014: The analog input signal is converted using the first analog-to-digital converter 12 to obtain the first M-bit code value;

[0036] 016: Load the first M-bit code value into the first M-bit code value (i.e., the high M-bit code value) of the second analog-to-digital converter 14 and use the second analog-to-digital converter 14 to convert the analog input signal to obtain the first N-bit code value;

[0037] 018: Add perturbation (±△) to the first M-bit code value d To obtain the second M-bit code value;

[0038] 022: Load the second M-bit code value into the first M-bit code value of the second analog-to-digital converter 14 and use the second analog-to-digital converter 14 to convert the analog input signal to obtain the second N-bit code value;

[0039] 024: Process the first N-bit code value and the second N-bit code value according to the capacitor weight relationship to obtain the first output code value and the second output code value;

[0040] 026: Determine whether the output difference between the first output code value and the second output code value is greater than the preset error;

[0041] 028: When the output difference is greater than the preset error, correct the capacitor weight relationship to obtain the updated weight.

[0042] Please see Figures 1 to 3 The successive approximation analog-to-digital converter 10 of this application includes an M-bit first analog-to-digital converter 12 and an N-bit second analog-to-digital converter 14, where N is greater than M. The first M bits of the capacitance of the first analog-to-digital converter 12 correspond to the first M high-order bits of the capacitance of the second analog-to-digital converter 14. The analog-to-digital converter 10 also includes a digital perturbation introduction module 20 and a processing module 30. The correction method of this application can be implemented by the analog-to-digital converter 10 of this application. Steps 012 and 014 can be implemented by the first analog-to-digital converter 12, step 018 can be implemented by the digital perturbation introduction module 20, steps 012, 016, and 022 can be implemented by the second analog-to-digital converter 14, and steps 024, 024, and 026 can be implemented by the processing module 30. That is, the first analog-to-digital converter 12 is used to acquire the analog input signal and convert the analog input signal to obtain the first M-bit code value. The digital perturbation introduction module 20 is used to add a perturbation to the first M-bit code value to obtain the second M-bit code value. The second analog-to-digital converter 14 is used to acquire the analog input signal, load the first M-bit code value into the first M-bit code value and convert the analog input signal to obtain the first N-bit code value, and load the second M-bit code value into the first M-bit code value and convert the analog input signal to obtain the second N-bit code value. The processing module 30 is used to process the first N-bit code value and the second N-bit code value according to the capacitor weight relationship to obtain the first output code value and the second output code value, and to determine whether the output difference between the first output code value and the second output code value is greater than a preset error. If the output difference is greater than the preset error, the capacitor weight relationship is corrected to obtain the updated weight.

[0043] The digital disturbance introduction module 20 and the processing module 30 can be integrated into the analog-to-digital converter 10 or independent of it. When the digital disturbance introduction module 20 and the processing module 30 are independent of the analog-to-digital converter 10, the circuit structure 100 includes the analog-to-digital converter 10, the digital disturbance introduction module 20, and the processing module 30. The correction method of this application embodiment can be implemented by the circuit structure 100 of this application embodiment. The specific implementation is basically the same as the embodiment where the digital disturbance introduction module 20 and the processing module 30 are integrated into the analog-to-digital converter 10, and will not be described again in this application.

[0044] The digital perturbation introduction module 20 of this application can specifically be a linear feedback shift register (LFSR). Using the digital perturbation introduction module 20, a perturbation can be added to the first M-bit code value in the digital domain to obtain a second M-bit code value. The processing module 30 of this application can include one or more components selected from the following: a driver board, other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. The driver board can include a central processing unit (CPU).

[0045] In the correction method, analog-to-digital converter 10, and circuit structure 100 of this application, a perturbation is added to the quantization result (first M-bit code value) of the first analog-to-digital converter 12, causing the second analog-to-digital converter 14 to generate two sets of output code values ​​for the same analog input signal. Based on the two sets of output code values, it can be determined whether the perturbation affects the output result of the analog-to-digital converter 10. If so, the capacitor weight relationship can be corrected, thereby reducing system error and ensuring system linearity. Since the perturbation is added to the first M-bit code value, this perturbation does not directly modify the analog input signal. Therefore, the second N-bit code value after conversion by the second analog-to-digital converter 14 is the actual result, and no additional perturbation removal is required. The correction method of this application is digital correction, which refers to eliminating errors by calculating the actual capacitor weight value in the digital domain using an algorithm. If the actual value of the capacitor weight is calculated in the digital domain using an algorithm, then an accurate quantization result can be obtained simply by controlling the actual weight of each bit through the comparator output. This is the core idea of ​​digital correction.

[0046] The successive approximation analog-to-digital converter 10 used in this application can refer to a two-step successive approximation analog-to-digital converter in which the M-bit first analog-to-digital converter 12 can replace the quantization process of the first M bits of the code value of the second analog-to-digital converter 14. That is, the M-bit code value obtained by the first analog-to-digital converter 12 in converting the analog input signal is equivalent to the first M bits of the code value of the second analog-to-digital converter 14.

[0047] The specific values ​​of N and M can be designed according to actual needs and are not specifically limited here. For example, N can be 8 and M can be 5; or N can be 12 and M can be 8. Please refer to [link / reference]. Figure 4 In the embodiments of this application, N is 16 and M is 7 as an example for explanation.

[0048] The output difference can be the difference between the first output code value and the second output code value. An output difference greater than a preset error means the absolute value of the output difference is greater than the preset error; an output difference less than or equal to the preset error means the absolute value of the output difference is less than or equal to the preset error. If the output difference is greater than the preset error, the system can be considered to have a capacitor weight mismatch, indicating a nonlinear system. In this case, the capacitor weight relationship needs to be corrected and updated in the digital domain. If the output difference is less than or equal to the preset error, the system does not have a capacitor weight mismatch or the mismatch is negligible; therefore, no correction or update of the capacitor weight relationship is required.

[0049] In some implementations, the preset error can be 0. When the output difference is not 0 (greater than 0 or less than 0), it can be determined that the output difference is greater than the preset error; when the output difference is 0, it can be determined that the output difference is less than or equal to the preset error. Of course, the preset error can also be a positive number close to 0, and this is not specifically limited here.

[0050] Please see Figures 3 to 6 In some embodiments, the first analog-to-digital converter 12 includes a first digital-to-analog converter 121, a first comparator 123, and a first logic unit 125. The first digital-to-analog converter 121 is used to output a first analog signal, the first comparator 123 is used to compare the first analog signal with an analog input signal, and the first logic unit 125 is used to determine a first M-bit code value based on the comparison result of the first comparator 123. The second analog-to-digital converter 14 includes a second digital-to-analog converter 141, a second comparator 143, and a second logic unit 145. The second digital-to-analog converter 141 is used to output a second analog signal, the second comparator 143 is used to compare the second analog signal with an analog input signal, and the second logic unit 145 is used to determine a first N-bit code value or a second N-bit code value based on the comparison result of the second comparator 143.

[0051] The first analog-to-digital converter 12 and the second analog-to-digital converter 14 can be connected through the first logic unit 125 and the second logic unit 145. The first digital-to-analog converter 121 includes a first capacitor array (M-bit DAC array), and the second digital-to-analog converter 141 includes a second capacitor array (N-bit DAC array). The analog input signal is connected to the first capacitor array and the second capacitor array. To ensure that the quantization result remains accurate after introducing disturbances, redundant capacitors 1411 can be introduced into the second capacitor array.

[0052] This application can employ a fully differential analog-to-digital converter; please refer to the details. Figures 3 to 6 It should be noted that the number of capacitors in the first and second capacitor arrays can be designed according to requirements, and no specific limitation is made here. For example, please refer to... Figure 3 , Figure 3 The M-bit DAC array in the middle can adopt a capacitor array with a Vcm-based structure, in which case the number of capacitors can be M; Figure 3 The N-bit DAC array can also use a Vcm-based capacitor array, in which case the number of capacitors can be N. For another example, please refer to... Figure 5 , Figure 5 The first capacitor array in the process can be a non-Vcm-based capacitor array, in which case the number of capacitors can be M+1.

[0053] The power supply voltage of the first comparator 123 is VH. The first digital-to-analog converter 121 may also include a first switch control module 127 and a first code value output module. The first logic unit 125 controls the first digital-to-analog converter 121 to output a first analog signal through the first switch control module 127. The first code value output module is used to output the first M-bit code value of the first logic unit 125.

[0054] The power supply voltage of the second comparator 143 is VL, where VL < VH. The second digital-to-analog converter 141 may further include a second switch control module 147 and a second code value output module. The second logic unit 145 controls the second digital-to-analog converter 141 to output a second analog signal through the second switch control module 147. The second code value output module is used to output the first N-bit code value or the second N-bit code value of the second logic unit 145.

[0055] The first logic unit 125 controls the first digital-to-analog converter 121 to output the first analog signal. The first comparator 123 starts to compare the first analog signal and the analog input signal under the control of the clock signal. After the comparison is completed, the first logic unit 125 determines the switching of the next capacitor switch according to the comparison result of the first comparator 123, until the first analog-to-digital converter 121 completes the conversion of the analog input signal to obtain the first M-bit code value.

[0056] The first M-bit code value or the second M-bit code value is loaded into the first M-bit code value of the second analog-to-digital converter 14. Then, the second analog-to-digital converter 14 completes the overall conversion of the analog input signal to obtain the first N-bit code value or the second N-bit code value. The method by which the second analog-to-digital converter 14 obtains the first N-bit code value or the second N-bit code value is similar to the method by which the first analog-to-digital converter 12 obtains the first M-bit code value, and will not be described in detail here.

[0057] In some embodiments, the first analog-to-digital converter 12 includes a first sample-and-hold circuit, and the second analog-to-digital converter includes a second sample-and-hold circuit. Both the first and second sample-and-hold circuits are used to sample and hold the analog input signal to obtain the analog input signal. The first sample-and-hold circuit can be combined with the first digital-to-analog converter 121, and the second sample-and-hold circuit can be combined with the second digital-to-analog converter 141.

[0058] It should be noted that this application's Figure 3 , Figure 4 In order to simplify the circuit structure for easy illustration, the operating logic in the processing module 30, the first logic unit 125 and the second logic unit 145 are collectively referred to as SAR logic.

[0059] Loading the first M-bit code value into the first M-bit code value of the second analog-to-digital converter 14 specifically means loading each bit of the first M-bit code value (total M bits) into the corresponding bit of the first M-bit code value (total M bits) of the second analog-to-digital converter 14.

[0060] Please see Figure 7 In some embodiments, step 016 (loading the first M-bit code value into the first M-bit code value of the second analog-to-digital converter 14 and using the second analog-to-digital converter 14 to convert the analog input signal to obtain the first N-bit code value) includes:

[0061] 0161: The first M-bit code value is directly used as the first M-bit code value of the second analog-to-digital converter 14, and the analog input signal is converted by the second analog-to-digital converter 14 to obtain the first N-bit code value.

[0062] In some implementations, the second analog-to-digital converter 14 is used to: directly use the first M-bit code value as the first M-bit code value and convert the analog input signal to obtain the first N-bit code value.

[0063] In this way, the first M bits of the code value of the second analog-to-digital converter 14 can be obtained directly, and the high-bit code value quantization process of the second analog-to-digital converter 14 can be replaced by the first analog-to-digital converter 12, thereby reducing the power consumption of the high-bit capacitor of the second analog-to-digital converter 14.

[0064] Please see Figure 8In some implementations, the first M-bit code value is binary, and step 018 (adding a perturbation to the first M-bit code value to obtain the second M-bit code value) includes:

[0065] 0181: Randomly increase or decrease the first M-bit code value by one least significant bit (LSB) to obtain the second M-bit code value.

[0066] In some implementations, the first M-bit code value is binary, and the digital perturbation introduction module 20 is used to randomly increase or decrease the first M-bit code value by one least significant bit to obtain the second M-bit code value.

[0067] When the first M-bit code value is binary, one least significant bit can be randomly added to or subtracted from the first M-bit code value, thereby performing a random addition or subtraction of 1 in the digital domain, which introduces a 1LSB perturbation. Since the addition or subtraction of 1LSB is random, the non-singularity of the correction matrix can be guaranteed, making the correction result more accurate.

[0068] Please see Figure 9 In some implementations, the first M-bit code value is non-binary, and step 018 (adding a perturbation to the first M-bit code value to obtain the second M-bit code value) includes:

[0069] 0183: Convert the first M-bit code value into a preset base code value according to the preset weight, and add perturbation to the preset base code value to obtain the perturbation code value;

[0070] 0185: Convert the perturbation code value into an M-bit code value according to the preset weight to serve as the second M-bit code value.

[0071] In some implementations, the digital perturbation introduction module 20 is used to: convert the first M-bit code value into a preset base code value according to a preset weight and add perturbation to the preset base code value to obtain a perturbation code value; and convert the perturbation code value into an M-bit code value according to a preset weight to serve as the second M-bit code value.

[0072] When the first M-bit code value is not binary, it can first be converted into a preset base code value according to a preset weight. The preset weight can refer to the weighting relationship of the capacitors in the first analog-to-digital converter 12. Based on the weighting relationship of the capacitors in the first analog-to-digital converter 12, the first M-bit code value can be converted into a preset decimal base code value. After conversion to the preset base code value, a perturbation can be added to the preset base code value to obtain a perturbation code value. Then, the perturbation code value can be converted into an M-bit code value according to the preset weight to serve as the second M-bit code value.

[0073] Please see Figure 10In some embodiments, step 0183 (converting the first M-bit code value into a preset base code value according to a preset weight and adding a perturbation to the preset base code value to obtain a perturbed code value) includes:

[0074] 01831: Convert the first M-bit code value into a preset base code value according to the preset weight, and randomly increase or decrease the preset base code value by 1 least significant bit to obtain the perturbation code value.

[0075] In some implementations, the digital perturbation introduction module 20 is used to: convert the first M-bit code value into a preset base code value according to a preset weight, and randomly increase or decrease the preset base code value by one least significant bit to obtain a perturbation code value.

[0076] The preset base code value is binary or decimal. One least significant bit can be randomly added to or subtracted from the preset base code value, thus performing a random addition or subtraction of 1 in the digital domain, introducing a 1LSB perturbation. Since the addition or subtraction of 1LSB is random, the non-singularity of the correction matrix is ​​guaranteed, resulting in more accurate correction results.

[0077] Loading the second M-bit code value into the first M-bit code value of the second analog-to-digital converter 14 specifically means loading each bit of the second M-bit code value (total M bits) into the corresponding bit of the first M-bit code value (total M bits) of the second analog-to-digital converter 14.

[0078] Please see Figure 11 In some embodiments, step 022 (loading the second M-bit code value into the first M-bit code value of the second analog-to-digital converter 14 and using the second analog-to-digital converter 14 to convert the analog input signal to obtain the second N-bit code value) includes:

[0079] 0221: The second M-bit code value is directly used as the first M-bit code value of the second analog-to-digital converter 14, and the analog input signal is converted by the second analog-to-digital converter 14 to obtain the second N-bit code value.

[0080] In some implementations, the second analog-to-digital converter 14 is used to: directly use the second M-bit code value as the first M-bit code value and convert the analog input signal to obtain the second N-bit code value.

[0081] In this way, the first M bits of the code value of the second analog-to-digital converter 14 can be obtained directly, and the high-bit code value quantization process of the second analog-to-digital converter 14 can be replaced by the first analog-to-digital converter 12, thereby reducing the power consumption of the high-bit capacitor of the second analog-to-digital converter 14.

[0082] In some implementations, the steps of loading the first M-bit code value into the first M-bit code value of the second analog-to-digital converter 14 and converting the analog input signal using the second analog-to-digital converter 14 to obtain the first N-bit code value (step 016) and adding perturbation to the first M-bit code value to obtain the second M-bit code value (step 018) are performed simultaneously.

[0083] In some implementations, while the second analog-to-digital converter 14 loads the first M-bit code value onto the first M-bit code value and converts the analog input signal to obtain the first N-bit code value, the digital perturbation introduction module 20 adds a perturbation to the first M-bit code value to obtain the second M-bit code value.

[0084] Specifically, clock information can be used to ensure that the added perturbation and the conversion of the second analog-to-digital converter 14 to obtain the first N-bit code value are executed simultaneously. In this way, the digital logic with the added perturbation can be performed in parallel with the conversion of the second analog-to-digital converter 14 to obtain the first N-bit code value, thereby ensuring that the speed of the analog-to-digital converter 10 does not decrease due to the correction method.

[0085] Please see Figure 12 In some implementations, the correction method further includes:

[0086] 032: Update the weights as the new capacitor weights and repeat the correction method until the output difference is less than the preset error.

[0087] In some implementations, the analog-to-digital converter 10 or circuit structure 100 is used to: update the weights as a new capacitor weight relationship and repeatedly perform the correction method until the output difference is less than a preset error.

[0088] In this way, by repeatedly executing the correction method to iteratively update the capacitor weight relationship, the actual capacitor weight relationship can be solved, making the final capacitor weight relationship accurate and highly reliable.

[0089] Please see Figure 13 In some implementations, step 028 (correcting the capacitance weight relationship to obtain updated weights) includes:

[0090] 0281: The capacitor weight relationship is corrected based on the output difference, iteration step size, first N-bit code value and second N-bit code value to obtain the updated weight.

[0091] In some implementations, the processing module 30 is used to: correct the capacitor weight relationship based on the output difference, the iteration step size, the first N-bit code value, and the second N-bit code value to obtain the updated weight.

[0092] Specifically, the capacitor weighting relationship can refer to the weighting relationship of the capacitors in the second analog-to-digital converter 14. Processing the first N-bit code value according to the capacitor weighting relationship yields the first decimal output code value, and processing the second N-bit code value according to the capacitor weighting relationship yields the second decimal output code value. The capacitor weighting relationship can be corrected based on the output difference between the first and second output code values, the iteration step size, and the first and second N-bit code values, thereby obtaining updated weights.

[0093] Please see Figure 14 In some implementations, the capacitor weight relationship includes N weights, with one weight corresponding to one bit. Step 0281 (correcting the capacitor weight relationship based on the output difference, iteration step size, first N-bit code value, and second N-bit code value to obtain updated weights) includes:

[0094] 02811: Determine the difference between the first code value of the preset bit in the first N-bit code value and the second code value of the preset bit in the second N-bit code value;

[0095] 02813: Adjust the weights corresponding to the preset positions based on the output difference, iteration step size, and difference correction.

[0096] 02815: Correct the weights of the capacitor weight relationship to obtain updated weights.

[0097] In some implementations, the capacitor weight relationship includes N weights, with each weight corresponding to a bit. The processing module 30 is used to: determine the difference between the first code value of a preset bit in the first N-bit code value and the second code value of a preset bit in the second N-bit code value; correct the weight corresponding to the preset bit based on the output difference, the iteration step size, and the difference; and correct each weight of the capacitor weight relationship to obtain the updated weight.

[0098] Specifically, please refer to [the relevant document] again. Figure 1 For example, by looping n times, the first N-bit code value B output by the second analog-to-digital converter 14 is obtained. 1n The second N-bit code value B 2n The first N-bit code value and the second N-bit code value are processed according to the capacitor weighting relationship to obtain the first output code value D. 1n Second output code value D 2n .

[0099]

[0100]

[0101] Among them, w i (n) represents the weight of the i-th capacitor after the (n-1)-th iteration (n = 1, 2, 3…), and the first output code value D 1n Second output code value D 2n The difference can be obtained by taking the subtraction.

[0102] e = D 1n -D 2n

[0103] By adding a perturbation to the first M-bit code value, and assuming the analog-to-digital converter 10 has sufficient and ideal redundancy range, since the analog input signal remains unchanged, two sets of digital code values ​​are obtained (the first output code value D). 1n Second output code value D 2n Although different, the quantization results calculated through the capacitor weight relationship are consistent, i.e., the output difference e is zero. Conversely, when there is a capacitor weight mismatch error in the capacitors participating in quantization in the analog-to-digital converter 10, the two sets of output code values ​​will have a difference, i.e., the output difference e is not zero. It can be seen that the capacitor weight mismatch error is not eliminated when the output difference e is not zero, and further adjustment is needed until e approaches or equals 0, which means that the capacitor weight approaches or reaches the ideal value. Then, the correction formula can be obtained according to the Least Mean Square (LMS) algorithm.

[0104] w i (n+1)=w i (n)-μe[B 1n (i)-B 2n (i)]

[0105] μ is the iteration step size, which can be calculated according to the correction formula to obtain the actual capacitance weight code value. In one embodiment, μ can be 1*10⁻¹³. i is a preset bit, w i (n+1) represents the corrected weights, w i (n) represents the weights before correction, B 1n (i) is the first code value of a preset bit in the first N-bit code value, B 2n (i) is the second code value of the preset bit in the second N-bit code value. By correcting all N weights in the capacitor weight relationship, a new capacitor weight relationship can be obtained (i.e., updated weights).

[0106] This application introduces digital perturbation and uses the LMS algorithm to correct the capacitor weight relationship. Compared with the correction schemes of related technologies, this application does not need to add additional capacitors to introduce perturbation, but instead processes the code value in the digital domain to introduce perturbation.

[0107] In summary, the LMS correction method based on digital domain jitter corrects the capacitor weight relationship in the correction method, analog-to-digital converter 10, and circuit structure 100 of this application, further reducing the circuit load. By introducing digital domain jitter, this application does not require adding additional capacitors to introduce disturbances, thus reducing the load on the analog circuit. This application adds disturbances to the first M-bit code value, which eliminates the need for the first analog-to-digital converter 12 to perform a second quantization, avoiding power consumption accumulation caused by two quantizations.

[0108] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described herein, as well as the features of those different embodiments or examples, without contradiction.

[0109] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0110] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more executable instructions for implementing a particular logical function or process, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the function involved, as will be understood by those skilled in the art to which embodiments of this application pertain.

[0111] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A correction method for a successive approximation analog-to-digital converter, characterized in that, The analog-to-digital converter (ADC) includes an M-bit first ADC and an N-bit second ADC, where N is greater than M. The first M bits of the first ADC's capacitance correspond to the first M high-order bits of the second ADC's capacitance. The correction method includes: Acquire analog input signals; The analog input signal is converted using the first analog-to-digital converter to obtain a first M-bit code value; The first M-bit code value is loaded into the first M-bit code value of the second analog-to-digital converter, and the analog input signal is converted by the second analog-to-digital converter to obtain the first N-bit code value; A perturbation is added to the first M-bit code value to obtain the second M-bit code value; The second M-bit code value is loaded into the first M-bit code value of the second analog-to-digital converter, and the analog input signal is converted by the second analog-to-digital converter to obtain the second N-bit code value; The first N-bit code value and the second N-bit code value are processed according to the capacitor weight relationship to obtain the first output code value and the second output code value; Determine whether the output difference between the first output code value and the second output code value is greater than a preset error; When the output difference is greater than the preset error, the capacitor weight relationship is corrected to obtain updated weights.

2. The correction method according to claim 1, characterized in that, The first analog-to-digital converter includes a first digital-to-analog converter, a first comparator, and a first logic unit. The first digital-to-analog converter outputs a first analog signal, the first comparator compares the first analog signal with the analog input signal, and the first logic unit determines the first M-bit code value based on the comparison result of the first comparator. The second analog-to-digital converter includes a second digital-to-analog converter, a second comparator, and a second logic unit. The second digital-to-analog converter outputs a second analog signal, the second comparator compares the second analog signal with the analog input signal, and the second logic unit determines the first N-bit code value or the second N-bit code value based on the comparison result of the second comparator.

3. The correction method according to claim 1, characterized in that, The step of loading the first M-bit code value into the first M-bit code value of the second analog-to-digital converter and using the second analog-to-digital converter to convert the analog input signal to obtain the first N-bit code value includes: The first M-bit code value is directly used as the first M-bit code value of the second analog-to-digital converter, and the analog input signal is converted by the second analog-to-digital converter to obtain the first N-bit code value.

4. The correction method according to claim 1, characterized in that, The first M-bit code value is binary, and the step of adding perturbation to the first M-bit code value to obtain the second M-bit code value includes: The first M-bit code value is randomly increased or decreased by one least significant bit to obtain the second M-bit code value.

5. The correction method according to claim 1, characterized in that, The first M-bit code value is non-binary, and the step of adding perturbation to the first M-bit code value to obtain the second M-bit code value includes: The first M-bit code value is converted into a preset base code value according to a preset weight, and a perturbation is added to the preset base code value to obtain a perturbed code value; The perturbation code value is converted into an M-bit code value according to the preset weight to serve as the second M-bit code value.

6. The correction method according to claim 5, characterized in that, The step of converting the first M-bit code value into a preset base code value according to a preset weight and adding a perturbation to the preset base code value to obtain a perturbed code value includes: The first M-bit code value is converted into the preset base code value according to the preset weight, and the preset base code value is randomly increased or decreased by 1 least significant bit to obtain the perturbation code value.

7. The correction method according to any one of claims 1-6, characterized in that, The step of loading the second M-bit code value into the first M-bit code value of the second analog-to-digital converter and using the second analog-to-digital converter to convert the analog input signal to obtain the second N-bit code value includes: The second M-bit code value is directly used as the first M-bit code value of the second analog-to-digital converter, and the analog input signal is converted by the second analog-to-digital converter to obtain the second N-bit code value.

8. The correction method according to claim 1, characterized in that, The steps of loading the first M-bit code value into the first M-bit code value of the second analog-to-digital converter and converting the analog input signal using the second analog-to-digital converter to obtain the first N-bit code value and the step of adding perturbation to the first M-bit code value to obtain the second M-bit code value are performed simultaneously.

9. The correction method according to claim 1, characterized in that, The correction method further includes: The updated weights are used as the new capacitor weights, and the correction method is repeated until the output difference is less than the preset error.

10. The correction method according to claim 1, characterized in that, The step of correcting the capacitor weight relationship to obtain updated weights includes: The updated weights are obtained by correcting the capacitor weight relationship based on the output difference, iteration step size, first N-bit code value, and second N-bit code value.

11. The correction method according to claim 10, characterized in that, The capacitor weight relationship includes N weights, each weight corresponding to one bit. Correcting the capacitor weight relationship based on the output difference, iteration step size, the first N-bit code value, and the second N-bit code value to obtain the updated weights includes: Determine the difference between the first code value of a preset bit in the first N-bit code value and the second code value of the preset bit in the second N-bit code value; The weight corresponding to the preset position is corrected based on the output difference, the iteration step size, and the difference. The updated weights are obtained by correcting the weights of the capacitor weight relationship.

12. A successive approximation analog-to-digital converter, characterized in that, The analog-to-digital converter (ADC) includes an M-bit first ADC and an N-bit second ADC, where N is greater than M. The first M bits of the first ADC's capacitor correspond to the first M high-order bits of the second ADC's capacitor. The ADC also includes a digital disturbance introduction module and a processing module. The first analog-to-digital converter is used to acquire an analog input signal and convert the analog input signal to obtain a first M-bit code value; The digital perturbation introduction module is used to add perturbation to the first M-bit code value to obtain the second M-bit code value; The second analog-to-digital converter is used to acquire the analog input signal, load the first M-bit code value into the first M-bit code value and convert the analog input signal to obtain the first N-bit code value, and load the second M-bit code value into the first M-bit code value and convert the analog input signal to obtain the second N-bit code value. The processing module is used to process the first N-bit code value and the second N-bit code value according to the capacitor weight relationship to obtain the first output code value and the second output code value, determine whether the output difference between the first output code value and the second output code value is greater than a preset error, and when the output difference is greater than the preset error, correct the capacitor weight relationship to obtain the updated weight.

13. A circuit structure, characterized in that, The circuit structure includes a successive approximation analog-to-digital converter (ADC), which includes an M-bit first ADC and an N-bit second ADC, where N is greater than M. The first M bits of the first ADC's capacitor correspond to the first M high-order bits of the second ADC's capacitor. The circuit structure also includes a digital disturbance introduction module and a processing module. The first analog-to-digital converter is used to acquire an analog input signal and convert the analog input signal to obtain a first M-bit code value; The digital perturbation introduction module is used to add perturbation to the first M-bit code value to obtain the second M-bit code value; The second analog-to-digital converter is used to acquire the analog input signal, load the first M-bit code value into the first M-bit code value and convert the analog input signal to obtain the first N-bit code value, and load the second M-bit code value into the first M-bit code value and convert the analog input signal to obtain the second N-bit code value. The processing module is used to process the first N-bit code value and the second N-bit code value according to the capacitor weight relationship to obtain the first output code value and the second output code value, determine whether the output difference between the first output code value and the second output code value is greater than a preset error, and when the output difference is greater than the preset error, correct the capacitor weight relationship to obtain the updated weight.

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