Display substrate and display device

Abstract

A display substrate includes: a substrate, a plurality of sub-pixels, a plurality of data lines, a first wiring layer, a second wiring layer, and a first insulating layer. The substrate includes a display area and a bent region located on one side of the display area. The plurality of sub-pixels are located in the display area, and the plurality of data lines are located in the display area and electrically connected to the plurality of sub-pixels, the plurality of data lines being configured to provide data signals to the plurality of sub-pixels. The first wiring layer is partially disposed in the bent region of the substrate and connected to the plurality of data lines. The second wiring layer is located in the bent region and is disposed on the side of the first wiring layer away from the substrate, and the second wiring layer is connected to the first wiring layer. The first insulating layer is disposed on the side of the second wiring layer away from the substrate. The orthographic projections of the edges of the first insulating layer and the second wiring layer near the display area onto the substrate overlap.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) possess advantages such as ultra-thinness, wide viewing angle, active emission, high brightness, continuously adjustable emission color, low cost, fast response speed, low power consumption, wide operating temperature range, and flexible display capabilities, gradually becoming a promising next-generation display technology. Based on different driving methods, OLEDs can be divided into two types: passive matrix (PM) and active matrix (AM). AMOLEDs are current-driven devices, using independent thin-film transistors (TFTs) to control each sub-pixel, allowing each sub-pixel to emit light continuously and independently. With the rapid development of AMOLEDs, their application scenarios are becoming increasingly complex and demanding. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate and a display device.

[0005] In one aspect, embodiments of this disclosure provide a display substrate, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a first wiring layer, a second wiring layer, and an inorganic insulating layer. The substrate includes a display area and a bent region located on one side of the display area. The plurality of sub-pixels are located in the display area. The plurality of data lines are located in the display area and electrically connected to the plurality of sub-pixels, and are configured to provide data signals to the plurality of sub-pixels. The first wiring layer is partially disposed in the bent region of the substrate and is connected to the plurality of data lines. The second wiring layer is located in the bent region and is disposed on the side of the first wiring layer away from the substrate, and is connected to the first wiring layer. The first insulating layer is disposed on the side of the second wiring layer away from the substrate, and the orthographic projections of the edges of the first insulating layer and the second wiring layer near the display area onto the substrate overlap.

[0006] In some exemplary embodiments, the first routing layer includes a plurality of data leads, which are connected one-to-one with the plurality of data lines. The second routing layer includes a plurality of first data connection lines, which are connected one-to-one with the plurality of data leads. The first insulating layer is in direct contact with at least a portion of the second routing layer.

[0007] In some exemplary embodiments, the display substrate further includes an inorganic insulating layer located between the second wiring layer and the first insulating layer. The inorganic insulating layer includes a first edge in the bending region, and the first edge of the inorganic insulating layer overlaps with the edge of the second wiring layer near the display region in the orthographic projection of the substrate.

[0008] In some exemplary embodiments, the first edge of the inorganic insulating layer is provided with a first wave structure, the first wave structure including a plurality of spaced first notches. At least one of the plurality of first notches has its orthographic projection on the substrate located within the orthographic projection of the corresponding first data connection line on the substrate.

[0009] In some exemplary embodiments, the multiple first data connection lines of the second wiring layer are arranged in an interleaved manner.

[0010] In some exemplary embodiments, the display substrate further includes a third wiring layer located in the bending region and disposed on the side of the first insulating layer away from the substrate. The third wiring layer includes a plurality of second data connection lines, which are connected one-to-one with a plurality of first data connection lines of the second wiring layer. At least one of the second data connection lines has its orthographic projection on the substrate overlapping with the orthographic projection of a corresponding first data connection line on the substrate.

[0011] In some exemplary embodiments, at least one of the plurality of second data connection lines has at least one hole.

[0012] In some exemplary embodiments, the at least one hole is a circular hole or an elliptical hole.

[0013] In some exemplary embodiments, the second wiring layer further includes a plurality of third data connection lines. The plurality of third data connection lines are located on the side of the plurality of first data connection lines away from the display area, and each of the plurality of third data connection lines is connected to one of the plurality of second data connection lines. At least one of the plurality of second data connection lines has its two ends connected to one first data connection line and one third data connection line, respectively.

[0014] In some exemplary embodiments, the multiple third data connection lines of the second wiring layer are arranged in an interleaved manner.

[0015] In some exemplary embodiments, the inorganic insulating layer further includes a second edge in the bending region, the second edge being located on the side of the first edge away from the display area. A cutout region of the inorganic insulating layer is formed between the first edge and the second edge. The second edge of the inorganic insulating layer is in direct contact with at least one third data connection line of the second wiring layer, and the second edge covers the edge of the third data connection line away from the display area.

[0016] In some exemplary embodiments, the second edge of the inorganic insulating layer is provided with a second wave structure, the second wave structure including a plurality of spaced second notches. At least one of the plurality of second notches has its orthographic projection on the substrate located within the orthographic projection of the corresponding third data connection line on the substrate.

[0017] In some exemplary embodiments, the first edge of the inorganic insulating layer is in direct contact with at least one first data connection line of the second wiring layer and covers the edge of the first data connection line near the display area.

[0018] In some exemplary embodiments, within the bending region, along the direction from the bending region to the display region, the distance between the first edge of the inorganic insulating layer and the edge of the second trace layer covered by the first edge is greater than or equal to 5 micrometers.

[0019] In some exemplary embodiments, the first insulating layer includes a plurality of first openings in the bending region. The orthographic projection of at least one of the plurality of first data connection lines onto the substrate includes the orthographic projection of at least one first opening onto the substrate.

[0020] In some exemplary embodiments, the first wiring layer includes: a first data lead layer and a second data lead layer sequentially disposed on the substrate and insulated from each other. The first data lead layer includes a plurality of first data leads, and the second data lead layer includes a plurality of second data leads. The orthographic projections of the first data lead layer and the second data lead layer on the substrate do not overlap, and the first data leads and the second data leads are arranged at intervals.

[0021] In some exemplary embodiments, the first data lead-out layer further includes: a plurality of fourth data connection lines, the plurality of fourth data connection lines being located on the side of the plurality of first data lead-out lines away from the display area, and the plurality of fourth data connection lines being connected to the plurality of first data lead-out lines one-to-one through at least the second routing layer. The second data lead-out layer further includes a plurality of fifth data connection lines, the plurality of fifth data connection lines being located on the side of the plurality of second data lead-out lines away from the display area, and the plurality of fifth data connection lines being connected to the plurality of second data lead-out lines one-to-one through at least the second routing layer.

[0022] In some exemplary embodiments, the display area includes at least: a driving structure layer disposed on the substrate, and a light-emitting element disposed on the driving structure layer; the light-emitting element is connected to the driving structure layer. The driving structure layer includes an active layer, a first gate metal layer, a second gate metal layer, and a source / drain electrode layer sequentially disposed on the substrate. The first data lead layer and the first gate metal layer are co-layered, the second data lead layer and the second gate metal layer are co-layered, and the second trace layer and the source / drain electrode layer are co-layered.

[0023] In some exemplary embodiments, the bending region includes a first region, a second region, and a third region sequentially disposed along a direction away from the display area. The second region includes a composite insulating layer disposed between the substrate and the second wiring layer. The composite insulating layer has a communicating first groove and a second groove. The orthographic projection of the first groove on the substrate includes the orthographic projection of the second groove on the substrate.

[0024] In some exemplary embodiments, the composite insulating layer includes a barrier layer, a buffer layer, a first gate insulating layer, a second gate insulating layer, and an interlayer insulating layer stacked on the substrate. The first groove exposes the buffer layer, and the second groove exposes the substrate.

[0025] In some exemplary embodiments, the first insulating layer at least fills the second groove.

[0026] In some exemplary embodiments, the first insulating layer fills the first groove and the second groove.

[0027] In some exemplary embodiments, the first insulating layer is an organic insulating layer.

[0028] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0029] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0030] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0031] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0032] Figure 2 This is a schematic diagram of the structure of the bending region of a display substrate according to at least one embodiment of the present disclosure;

[0033] Figure 3 for Figure 1 A cross-sectional view of the PP section;

[0034] Figure 4 for Figure 2 A cross-sectional view of the QQ direction;

[0035] Figure 5 This is a schematic diagram of a display substrate after the substrate has been formed in at least one embodiment of the present disclosure;

[0036] Figure 6 This is a schematic diagram of a display substrate after an active layer pattern has been formed in at least one embodiment of the present disclosure;

[0037] Figure 7 This is a schematic diagram of a display substrate after the first gate metal layer and the first data lead-out layer pattern have been formed in at least one embodiment of the present disclosure;

[0038] Figure 8 This is a plan view of the bent area after forming the second data lead-out layer pattern in at least one embodiment of the present disclosure;

[0039] Figure 9 This is a schematic diagram of a display substrate after the second gate metal layer and the second data lead-out layer pattern are formed in at least one embodiment of this disclosure;

[0040] Figure 10 This is a schematic diagram of a display substrate after forming an interlayer insulating layer pattern in at least one embodiment of the present disclosure;

[0041] Figure 11 This is a plan view of the bent area after forming the second wiring layer pattern in at least one embodiment of the present disclosure;

[0042] Figure 12This is a schematic diagram of a display substrate after the formation of source / drain metal layer and second wiring layer patterns in at least one embodiment of this disclosure;

[0043] Figure 13 This is a plan view of the bent region after forming an inorganic insulating layer pattern in at least one embodiment of the present disclosure;

[0044] Figure 14 This is a schematic diagram of a display substrate after an inorganic insulating layer pattern has been formed in at least one embodiment of the present disclosure;

[0045] Figure 15 This is a schematic diagram of a display substrate after EBA and EBB processes in at least one embodiment of this disclosure;

[0046] Figure 16 This is a schematic diagram of a display substrate after the first planarization layer pattern has been formed in at least one embodiment of the present disclosure;

[0047] Figure 17 This is a schematic diagram of a display substrate after the metal conductive layer and the third wiring layer pattern have been formed in at least one embodiment of this disclosure;

[0048] Figure 18 This is a schematic diagram of a display substrate after the second planarization layer pattern has been formed in at least one embodiment of the present disclosure;

[0049] Figure 19 This is a schematic diagram of a display substrate after the encapsulation layer has been formed in at least one embodiment of the present disclosure;

[0050] Figure 20 This is another structural schematic diagram of the bending region of a display substrate according to at least one embodiment of the present disclosure;

[0051] Figure 21 This is a plan view of the bending region after the formation of the inorganic insulating layer in at least one embodiment of the present disclosure;

[0052] Figure 22 This is another structural schematic diagram of the bending region of a display substrate according to at least one embodiment of the present disclosure;

[0053] Figure 23 This is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0054] Figure 24 This is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0055] Figure 25 This is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0056] Figure 26 This is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0057] Figure 27 This is another structural schematic diagram of the bending region of a display substrate according to at least one embodiment of the present disclosure;

[0058] Figure 28 This is a plan view of the bent area after forming the second wiring layer pattern in at least one embodiment of the present disclosure;

[0059] Figure 29 This is a plan view of the bent region after the formation of the first insulating layer pattern in at least one embodiment of the present disclosure;

[0060] Figure 30 This is another structural schematic diagram of the bending region of a display substrate according to at least one embodiment of the present disclosure;

[0061] Figure 31 This is yet another structural schematic diagram of the bending region of a display substrate according to at least one embodiment of the present disclosure;

[0062] Figure 32 for Figure 1 Another cross-sectional view along the PP direction;

[0063] Figure 33 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0064] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0065] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0066] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements, not to limit the quantity. The term “multiple” in this disclosure refers to two or more quantities.

[0067] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0068] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0069] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0070] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0071] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0072] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0073] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0074] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0075] This disclosure provides a display substrate in at least one embodiment, comprising: a substrate, a plurality of sub-pixels, a plurality of data lines, a first wiring layer, a second wiring layer, and a first insulating layer. The substrate includes a display area and a bent region located on one side of the display area. The plurality of sub-pixels are located in the display area. The plurality of data lines are located in the display area and electrically connected to the plurality of sub-pixels, and are configured to provide data signals to the plurality of sub-pixels. The first wiring layer is partially disposed in the bent region of the substrate. The first wiring layer is connected to the plurality of data lines. The second wiring layer is located in the bent region and is disposed on the side of the first wiring layer away from the substrate. The second wiring layer is connected to the first wiring layer. The first insulating layer is disposed on the side of the second wiring layer away from the substrate. The orthographic projections of the edges of the first insulating layer and the second wiring layer near the display area on the substrate overlap.

[0076] The display substrate provided in this embodiment of the present disclosure, by setting the orthographic projection of the first insulating layer on the substrate in the bending area to overlap with the orthographic projection of the edge of the second wiring layer on the side near the display area on the substrate, is beneficial to protect the first wiring layer in the bending area, thereby improving the corrosion resistance of the display substrate and thus extending the service life of the display substrate under extreme environments.

[0077] In some exemplary embodiments, the first wiring layer includes multiple data leads, which are connected one-to-one with multiple data lines. The second wiring layer includes multiple first data connection lines, which are connected one-to-one with multiple data leads. The first insulating layer is in direct contact with at least a portion of the second wiring layer. In this exemplary embodiment, the first insulating layer extends from the display area to the bending area and is in direct contact with at least a portion of the second wiring layer. In some examples, any data lead in the bending area is connected in series with a first data connection line to realize data signal transmission between the display area and the bonding area. However, this embodiment is not limited to this. In some exemplary embodiments, the display substrate of this embodiment further includes an inorganic insulating layer located between the second wiring layer and the first insulating layer. The inorganic insulating layer includes a first edge in the bending area, and the first edge of the inorganic insulating layer overlaps with the edge of the second wiring layer near the display area in the orthographic projection of the substrate. In this exemplary embodiment, the inorganic insulating layer extends from the display area to the bending area and covers the second wiring layer in the bending area near the edge of the display area. This helps to protect the first wiring layer in the bending area, thereby improving the corrosion resistance of the display substrate and thus extending the service life of the display substrate under extreme environments.

[0078] In some exemplary embodiments, the first edge of the inorganic insulating layer is in direct contact with at least one first data connection line of the second wiring layer and covers the edge of the first data connection line near the display area.

[0079] In some exemplary embodiments, the multiple first data connection lines of the second wiring layer are arranged in an alternating pattern. For example, the multiple first data connection lines are arranged in two rows, with the second row of first data connection lines located on the side of the first row of first data connection lines furthest from the display area, and there is a misalignment between the two rows of first data connection lines. However, this embodiment is not limited to this. In some examples, the distance between the multiple first data connection lines of the second wiring layer and the edge of the display area can be the same.

[0080] In some exemplary embodiments, the first edge of the inorganic insulating layer is provided with a first wavy structure, the first wavy structure including a plurality of spaced first notches. At least one of the plurality of first notches has its orthographic projection on the substrate located within the orthographic projection of the corresponding first data connection line on the substrate. In some examples, the plurality of first notches may correspond one-to-one with a plurality of first data connection lines in the second wiring layer, or the plurality of first notches may correspond one-to-one with a portion of the plurality of first data connection lines in the second wiring layer. In this exemplary embodiment, by providing a first wavy structure at the first edge of the inorganic insulating layer, stress concentration in the inorganic insulating layer during bending can be reduced, preventing cracks in the inorganic insulating layer and thus improving the bending effect. However, this embodiment is not limited to this. In some examples, the first edge of the inorganic insulating layer may be a straight edge.

[0081] In some exemplary embodiments, the display substrate of this embodiment may further include a third wiring layer, located in the bending region and disposed on the side of the first insulating layer away from the substrate. The third wiring layer includes a plurality of second data connection lines, which are connected one-to-one with a plurality of first data connection lines of the second wiring layer. The orthographic projection of at least one of the plurality of second data connection lines on the substrate overlaps with the orthographic projection of the corresponding first data connection line on the substrate. In some examples, within the bending region, any data lead-out line is sequentially connected in series with a first data connection line and a second data connection line to realize data signal transmission between the display area and the bonding area. However, this embodiment is not limited to this.

[0082] In some exemplary embodiments, at least one of the plurality of second data connection lines has at least one hole. In some examples, the at least one hole may be circular or elliptical. However, this embodiment is not limited to this.

[0083] In some exemplary embodiments, the second wiring layer may include multiple first data connection lines and multiple third data connection lines. The multiple third data connection lines are located on the side of the multiple first data connection lines away from the display area. The multiple third data connection lines are connected one-to-one with multiple second data connection lines of the third wiring layer. At least one of the multiple second data connection lines has its two ends connected to a first data connection line and a third data connection line, respectively. In some examples, within the bending area, any data lead is connected in series with a first data connection line, a second data connection line, and a third data connection line to achieve data signal transmission between the display area and the bonding area. However, this embodiment is not limited to this.

[0084] In some exemplary embodiments, the multiple third data connection lines of the second wiring layer are arranged in an alternating pattern. For example, the multiple third data connection lines are arranged in two rows, with the second row of third data connection lines located on the side of the first row of third data connection lines furthest from the display area, and there is a misalignment between the two rows of third data connection lines. However, this embodiment is not limited to this. In some examples, the distance between the multiple third data connection lines of the second wiring layer and the edge of the display area can be the same.

[0085] In some exemplary embodiments, the inorganic insulating layer further includes a second edge in the bending region, the second edge of the inorganic insulating layer being located on the side of the first edge away from the display area. A cutout region of the inorganic insulating layer is formed between the first edge and the second edge. The second edge of the inorganic insulating layer is in direct contact with at least one third data connection line of the second wiring layer, and the second edge covers the edge of the third data connection line away from the display area.

[0086] In some exemplary embodiments, the second edge of the inorganic insulating layer is provided with a second wavy structure, the second wavy structure including a plurality of spaced second notches. At least one of the plurality of second notches has its orthographic projection on the substrate located within the orthographic projection of the corresponding third data connection line on the substrate. In some examples, the plurality of second notches may correspond one-to-one with a plurality of third data connection lines of the second wiring layer, or the plurality of second notches may correspond one-to-one with a portion of the plurality of third data connection lines of the second wiring layer. In this exemplary embodiment, by providing a second wavy structure at the second edge of the inorganic insulating layer, stress concentration in the inorganic insulating layer during bending can be reduced, preventing cracks in the inorganic insulating layer and thus improving the bending effect. However, this embodiment is not limited to this. In some examples, the second edge of the inorganic insulating layer may be a straight edge.

[0087] In some exemplary embodiments, within the bending region, along the direction from the bending region to the display region, the distance between the first edge of the inorganic insulating layer and the edge of the second wiring layer covered by the first edge is greater than or equal to 5 micrometers (μm).

[0088] In some exemplary embodiments, the first insulating layer includes a plurality of first openings in the bending region. The orthographic projection of at least one of the plurality of first data connection lines onto the substrate includes the orthographic projection of at least one first opening onto the substrate. In some examples, the plurality of first openings correspond one-to-one with the plurality of first data connection lines of the second wiring layer, and the orthographic projection of one first opening onto the substrate lies within the orthographic projection of the corresponding first data connection line onto the substrate. In some examples, at least one of the plurality of first data connection lines corresponds to two or more first openings, and the orthographic projections of the two or more first openings onto the substrate lie within the orthographic projection of the corresponding first data connection line onto the substrate. In some examples, the orthographic projection of at least one of the plurality of first openings onto the substrate does not overlap with, or only partially overlaps with, the orthographic projection of the first edge of the inorganic insulating layer onto the substrate. However, this embodiment is not limited in this respect.

[0089] In some exemplary embodiments, the first wiring layer includes a first data lead layer and a second data lead layer sequentially disposed on the substrate and insulated from each other. The first data lead layer includes a plurality of first data leads, and the second data lead layer includes a plurality of second data leads. The orthographic projections of the first data lead layer and the second data lead layer on the substrate do not overlap, and the first data leads and the second data leads are arranged at intervals. However, this embodiment is not limited in this respect. For example, the plurality of first data leads and the plurality of second data leads may be disposed on the same layer.

[0090] In some exemplary embodiments, the first data lead-out layer includes: multiple first data lead-out lines and multiple fourth data connection lines, with the multiple fourth data connection lines located on the side of the multiple first data lead-out lines away from the display area. The multiple fourth data connection lines are connected one-to-one with the multiple first data lead-out lines at least through a second routing layer. The second data lead-out layer includes multiple second data lead-out lines and multiple fifth data connection lines, with the multiple fifth data connection lines located on the side of the multiple second data lead-out lines away from the display area. The multiple fifth data connection lines are connected one-to-one with the multiple second data lead-out lines at least through a second routing layer. In some examples, within the bending area, any one first data lead-out line is sequentially connected in series with a first data connection line, a second data connection line, a third data connection line, and a fourth data connection line, and any one second data lead-out line is sequentially connected in series with a first data connection line, a second data connection line, a third data connection line, and a fifth data connection line, thereby realizing data signal transmission between the display area and the bonding area. However, this embodiment is not limited in this respect.

[0091] In some exemplary embodiments, the display area includes at least: a driving structure layer disposed on a substrate, and a light-emitting element disposed on the driving structure layer; the light-emitting element is connected to the driving structure layer. The driving structure layer includes an active layer, a first gate metal layer, a second gate metal layer, and a source / drain electrode layer sequentially disposed on the substrate. The first data lead layer and the first gate metal layer are co-layered, the second data lead layer and the second gate metal layer are co-layered, and the second wiring layer and the source / drain electrode layer are co-layered. However, this embodiment is not limited thereto. In some examples, the first wiring layer and the second gate metal layer may be co-layered, or the first wiring layer and the first gate metal layer may be co-layered.

[0092] In some exemplary embodiments, the display area includes at least: a driving structure layer disposed on a substrate, a metal conductive layer disposed on the driving structure layer, and a light-emitting element disposed on the metal conductive layer; the light-emitting element is connected to the driving structure layer through the metal conductive layer. The driving structure layer includes an active layer, a first gate metal layer, a second gate metal layer, and a source / drain electrode layer sequentially disposed on the substrate. The first data lead layer and the first gate metal layer are co-layered, the second data lead layer and the second gate metal layer are co-layered, the second wiring layer and the source / drain electrode layer are co-layered, and the third wiring layer and the metal conductive layer are co-layered. However, this embodiment is not limited thereto.

[0093] In some exemplary embodiments, the bending region of this embodiment includes a first region, a second region, and a third region sequentially disposed along a direction away from the display area. The second region includes a composite insulating layer disposed between the substrate and the second wiring layer. The composite insulating layer has a communicating first groove and a second groove. The orthographic projection of the first groove onto the substrate includes the orthographic projection of the second groove onto the substrate.

[0094] In some exemplary embodiments, the composite insulating layer may include: a barrier layer, a buffer layer, a first gate insulating layer (GI), a second gate insulating layer, and an interlayer dielectric layer stacked on a substrate. A first groove exposes the buffer layer, and a second groove exposes the substrate.

[0095] In some exemplary embodiments, the first insulating layer at least fills the second groove.

[0096] In some exemplary embodiments, the first insulating layer fills the first groove and the second groove.

[0097] In some exemplary embodiments, the first insulating layer is an organic insulating layer. In other words, the material of the first insulating layer is an organic material.

[0098] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 1 As shown, the display substrate provided in this embodiment includes a display area 100 and a non-display area surrounding the display area 100. The non-display area includes a first fanout area 200 located on one side of the display area 100, a bent area 300 located on the side of the first fanout area 200 away from the display area 100, a bonding area 400 located on the side of the bent area 300 away from the display area 100, and a border area 201 located outside the display area 100 and away from the first fanout area 200. The border area 201 and the first fanout area 200 are connected and surround the display area 100. The first fanout area 200 is located between the display area 100 and the bent area 300, and the bent area 300 is located between the first fanout area 200 and the bonding area 400.

[0099] In some exemplary embodiments, the display area 100 includes at least a plurality of display units (i.e., sub-pixels) 1001, a plurality of gate lines (not shown), and a plurality of data lines 1002. The orthographic projections of the gate lines and data lines 1002 onto the substrate intersect to form a plurality of sub-pixel regions, and one display unit 1001 is disposed within one sub-pixel region. The plurality of data lines 1002 are electrically connected to the plurality of display units 1001 and are configured to provide data signals to the plurality of display units 1001. The plurality of gate lines are electrically connected to the plurality of display units 1001 and are configured to provide scan signals to the plurality of display units 1001. In some examples, a pixel may include three display units, namely a red sub-pixel, a green sub-pixel, and a blue sub-pixel. However, this embodiment is not limited to this. In some examples, a pixel may include four display units, namely a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel.

[0100] In some exemplary embodiments, the bezel region 201 includes at least a gate driving circuit that provides scan signals to a plurality of display units 1001 of the display region 100, and a power line (e.g., a low-voltage power line (VSS)) that transmits voltage signals to the plurality of display units 1001. The first fan-out region 200 includes a data fan-out line, a first power line, and a second power line. The data fan-out line is located in the middle of the first fan-out region 200 and includes multiple data leads configured to connect to the data lines 1002 of the display region 100 in a fan-out routing manner. The first power line is configured to connect to the high-voltage power line (VDD) of the display region 100. The second power line is configured to connect to the low-voltage power line (VSS) of the bezel region 201. In some examples, the first power line and the second power line are disposed on the same layer, while the first power line and the second power line are disposed on a different layer from the data fan-out line. The orthographic projection of the data fan-out line on the substrate overlaps with the orthographic projection of the first power line on the substrate, and the orthographic projection of the data fan-out line on the substrate overlaps with the orthographic projection of the second power line on the substrate. The bending region 300 is configured to bend the bonding region 400 to the back side of the display region 100. The bending region 300 includes at least a plurality of data connection lines configured to connect the plurality of data leads of the first fan-out region 200 to the integrated circuit (IC) of the bonding region 400. In some examples, the bonding region 400 may include: a second fan-out region, an anti-static region, a driver chip region, and a bonding electrode region arranged sequentially along a direction away from the display region 100. The second fan-out region may include a plurality of data connection lines led out in a fan-out routing manner. The anti-static region includes an anti-static circuit and is configured to prevent electrostatic damage to the display substrate by eliminating static electricity. The driver chip area may include integrated circuits configured to connect to multiple data connection lines. The bonding electrode area includes multiple bonding pads configured to bond to an external flexible printed circuit (FPC).

[0101] Figure 2 This is a schematic diagram of a structure of a bent region according to at least one embodiment of the present disclosure. Figure 2 for Figure 1 A magnified view of a portion of region S in the middle. Figure 3 for Figure 1 A cross-sectional view of the PP section. Figure 4 for Figure 2 A cross-sectional view of the QQ axis.

[0102] In some exemplary implementations, such as Figure 1 and Figure 2As shown, in a plane parallel to the display substrate, the display substrate may include a display area 100, a first fan-out area 200 located on one side of the display area 100, a bent area 300 located on the side of the first fan-out area 200 away from the display area 100, and a bonding area 400 located on the side of the bent area 300 away from the display area 100. The bent area 300 includes a first area 301, a second area 302, and a third area 303 sequentially arranged along a direction away from the display area 100. The first area 301 of the bent area 300 is adjacent to the first fan-out area 200, and the third area 303 of the bent area 300 is adjacent to the bonding area 400. The second area 302 of the bent area 300 is located between the first area 301 and the third area 303. The second region 302 of the bending region 300 is provided with a first groove formed by a first mask (EBA MASK, Etch Bending A MASK) process and a second groove formed by a second mask (EBB MASK, Etch Bending BMASK) process. For example... Figure 2 As shown, the first boundary 3111 and the second boundary 3112 are the boundaries of the first groove formed by the EBA MASK process, and the third boundary 3121 and the fourth boundary 3122 are the boundaries of the second groove formed by the EBA MASK process.

[0103] In some exemplary implementations, such as Figure 2 As shown, in a plane parallel to the display substrate, the bending region 300 includes: multiple first data leads 51, multiple second data leads 52, multiple first data connection lines 53, multiple second data connection lines 54, multiple third data connection lines 55, multiple fourth data connection lines 56, and multiple fifth data connection lines 57. The multiple first data leads 51, multiple second data leads 52, multiple first data connection lines 53, multiple second data connection lines 54, multiple third data connection lines 55, multiple fourth data connection lines 56, and multiple fifth data connection lines 57 all extend along a first direction. The multiple first data leads 51 and the multiple second data leads 52 are arranged along a second direction perpendicular to the first direction, and the first data leads 51 and the second data leads 52 are arranged alternately. The multiple first data connection lines 53 are located in a first region 301 of the bending region 300 and are arranged along the second direction. Multiple third data connection lines 55 are located in the third region 303 of the bending region 300 and are arranged along the second direction. Multiple second data connection lines 54 are arranged along the second direction. Multiple fourth data connection lines 56 and multiple fifth data connection lines 57 are both arranged along the second direction, and the fourth data connection lines 56 and the fifth data connection lines 57 are arranged alternately.

[0104] In some exemplary implementations, such as Figure 2As shown, multiple first data leads 51 extend from the first fan-out area 200 to the first region 301 of the bending area 300, and multiple second data leads 52 extend from the first fan-out area 200 to the first region 301 of the bending area 300. The multiple first data leads 51 and multiple second data leads 52 are connected one-to-one with multiple data lines within the display area; for example, any one first data lead 51 or any one second data lead 52 is connected to a data line. The multiple first data leads 51 and multiple second data leads 52 are provided with non-layer insulation, and the first data leads 51 and second data leads 52 are arranged at intervals. The multiple first data leads 51 and multiple second data leads 52 are connected one-to-one with multiple first data connection lines 53. For example, any one first data lead 51 or any one second data lead 52 is connected to a first data connection line 53. Multiple first data connection lines 53 are disposed in the first region 301 of the bending region 300 and are insulated from each other. Multiple third data connection lines 55 are disposed in the third region 303 of the bending region 300 and are insulated from each other. The multiple first data connection lines 53 and the multiple third data connection lines 55 are disposed on the same layer. Multiple second data connection lines 54 extend from the first region 301 of the bending region 300 through the second region 302 to the third region 303 and are insulated from each other. The multiple third data connection lines 55 are disposed in the third region 303 of the bending region 300 and are insulated from each other. The multiple second data connection lines 54 are connected one-to-one with the multiple first data connection lines 51, and the multiple second data connection lines 54 are connected one-to-one with the multiple third data connection lines 55. Multiple fourth data connection lines 56 extend from the third region 303 of the bending region 300 to the binding region 400, and multiple fifth data connection lines 57 extend from the third region 303 of the bending region 300 to the binding region 400. Multiple fourth data connection lines 56 and multiple fifth data connection lines 57 can be connected to integrated circuits within the bonding area 400. The multiple fourth data connection lines 56 and multiple fifth data connection lines 57 are separated by different layers of insulation and are arranged at intervals. The multiple fourth data connection lines 56 are arranged on the same layer as multiple first data leads 51, and the multiple fifth data connection lines 57 are arranged on the same layer as multiple second data leads 52. Any third data connection line 55 is connected to either a fourth data connection line 56 or a fifth data connection line 57. In other words, any first data lead 51 is connected in series with a first data connection line 53, a second data connection line 54, a third data connection line 55, and a fourth data connection line 56; any second data lead 52 is connected in series with a first data connection line 53, a second data connection line 54, a third data connection line 55, and a fifth data connection line 57.The bending area 300 utilizes multiple data leads (including a first data lead and a second data lead) and multiple data connection lines (including a first data connection line to a fifth data connection line) to enable signal transmission between the data lines in the display area and the integrated circuit in the bonding area. In this exemplary embodiment, within the bending area 300, a data signal is transmitted through a first data lead (or a second data lead), a first data connection line, a second data connection line, a third data connection line, and a fourth data connection line (or a fifth data connection line) connected in series. This allows the bending stress during the bending process to be distributed across multiple data connection lines, avoiding stress concentration and reducing the risk of breakage of the data connection lines in the bending area, thereby improving the bending effect.

[0105] In some exemplary implementations, such as Figure 2 As shown, in a plane parallel to the display substrate, the shapes and sizes of multiple first data leads 51, multiple second data leads 52, multiple fourth data connection lines 56, and multiple fifth data connection lines 57 can be the same, for example, all being elongated. However, this embodiment is not limited in this respect. For example, the shapes and sizes of the multiple first data leads and multiple second data leads can be the same, but different from the shapes and sizes of the multiple fourth data connection lines and multiple fifth data connection lines. In some examples, the shapes and sizes of multiple first data connection lines 53 and multiple third data connection lines 55 can be the same, for example, all being rectangles (e.g., rounded rectangles) or polygons. However, this embodiment is not limited in this respect. For example, the shapes and sizes of the multiple first data connection lines can be different from the shapes and sizes of the multiple third data connection lines.

[0106] In some exemplary implementations, such as Figure 2 As shown, in a plane parallel to the display substrate, the orthographic projection of any first data connection line 53 on the substrate overlaps with the orthographic projection of any first data lead-out line 51 or any second data lead-out line 52 on the substrate. The orthographic projection of any second data connection line 54 on the substrate overlaps with the orthographic projections of both a first data connection line 53 and a third data connection line 55 on the substrate. The orthographic projection of any third data connection line 55 on the substrate overlaps with the orthographic projection of any fourth data connection line 56 or any fifth data connection line 57 on the substrate.

[0107] In some exemplary implementations, such as Figure 2As shown, in a plane parallel to the display substrate, at least one of the plurality of second data connection lines 54 includes: a first conductor segment 541, a second conductor segment 542, and a third conductor segment 543 connected sequentially. The first conductor segment 541 is located in a first region 301 of the bending region 300, the second conductor segment 542 is located in a second region 302, and the third conductor segment 543 is located in a third region 303. The orthographic projection of the first conductor segment 541 on the substrate overlaps with the orthographic projection of a first data connection line 53 on the substrate. The orthographic projection of the third conductor segment 543 on the substrate overlaps with the orthographic projection of a third data connection line 55 on the substrate. The average width of the second conductor segment 542 is greater than the average width of the first conductor segment 541 and the average width of the third conductor segment 543. In some examples, the average width of the second data connection line 54 can range from 6 to 10 micrometers. The spacing between two adjacent second data connection lines 54 can range from 8 to 12 micrometers. For example, the average width of the second data connection line 54 can be approximately 8.6 micrometers, and the spacing between two adjacent second data connection lines 54 can be approximately 10 micrometers. The second conductor segment 542 of the second data connection line 54 within the second region 302 can have a perforated pattern. The orthographic projection of the perforated pattern onto the substrate can be located within the second groove defined by the third boundary 3121 and the fourth boundary 3122. The perforated pattern can include multiple holes 5420. The multiple holes 5420 are arranged sequentially along the extension direction of the second data connection line 54, forming a row. The shape and size of the multiple holes 5420 can be the same or different. For example, the multiple holes 5420 can all be circular or elliptical. However, this embodiment does not limit the arrangement, shape, and size of the multiple holes. The perforated pattern provided on the second data connection line 54 can alleviate the stress accumulated on the second data connection line 54 during bending, which is beneficial for releasing stress when the second data connection line 54 is bent, reducing the risk of breakage of the second data connection line 54, thereby improving the bending effect.

[0108] In some exemplary implementations, such as Figure 2 As shown, in a plane parallel to the display substrate, the average widths of multiple first data leads 51, multiple second data leads 52, multiple fourth data connection lines 56, and multiple fifth data connection lines 57 can be the same, and the average widths of multiple first data connection lines 53 and multiple third data connection lines 55 can be the same. The average width of any first data connection line 53 can be greater than the average width of the first conductor segment 541 of a second data connection line 54, and the average width of the first conductor segment 541 of the second data connection line 54 can be greater than the average width of the first data leads 51. However, this embodiment is not limited in this respect.

[0109] In this disclosure, "width" refers to the dimension along the direction of extension perpendicular to the data connection line. "Length" refers to the dimension along the direction of extension of the data connection line.

[0110] In some exemplary implementations, such as Figure 2 As shown, in a plane parallel to the display substrate, the inorganic insulating layer 15 has a first edge 151 and a second edge 152 in the bending region 300. A hollow area of ​​the inorganic insulating layer 15 is formed between the first edge 151 and the second edge 152. The first edge 151 of the inorganic insulating layer 15 is located in the first region 301 of the bending region 300, and the second edge 152 of the inorganic insulating layer 15 is located in the third region 303 of the bending region 300. In the extension direction along the data connection line, the distance between the first edge 151 and the edge of the display area near the bending region 300 is less than the distance between the second edge 152 and the edge of the display area near the bending region 300.

[0111] In some exemplary implementations, such as Figure 2 As shown, the first edge 151 of the inorganic insulating layer 15 is in direct contact with multiple first data connection lines 53 and covers the edges of the multiple first data connection lines 53 near the display area. The first edge 151 of the inorganic insulating layer 15 has a first wave structure, which includes multiple spaced first notches 153. Each of the multiple first notches 153 corresponds one-to-one with a multiple first data connection line 53, and the orthographic projection of a first notch 153 on the substrate lies within the orthographic projection of the corresponding first data connection line 53 on the substrate. The orthographic projection of the first conductor segment 541 of a second data connection line 54 on the substrate can cover the orthographic projection of a first notch 153 on the substrate. The first notch 153 in the first wave structure can be composed of multiple arc segments, or multiple straight segments, or a combination of multiple arc segments and multiple straight segments; this disclosure does not limit the composition. Figure 2 As shown, the first notch 153 can be ∩-shaped. However, this embodiment is not limited to this; for example, the first notch can be... In some examples, the multiple first notches 153 may have the same shape and size. In this exemplary embodiment, by providing a first wave structure at the first edge 151 of the inorganic insulating layer 15 in the bending region 300, the bending stress on the inorganic insulating layer 15 during bending can be dispersed, stress concentration can be avoided, the risk of breakage of the inorganic insulating layer 15 can be reduced, thereby improving the bending effect.

[0112] In some exemplary implementations, such as Figure 2As shown, the second edge 152 of the inorganic insulating layer 15 is in direct contact with multiple third data connection lines 55 and covers the edges of the multiple third data connection lines 55 away from the display area. The second edge 152 of the inorganic insulating layer 15 has a second wave structure, which includes multiple spaced second notches 154. The multiple second notches 154 face the display area. The multiple second notches 154 correspond one-to-one with the multiple third data connection lines 55, and the orthographic projection of a second notch 154 on the substrate lies within the orthographic projection of the corresponding third data connection line 55 on the substrate. The orthographic projection of the third conductor segment 543 of a second data connection line 54 on the substrate can cover the orthographic projection of a second notch 154 on the substrate. The second notch 154 in the second wave structure can be composed of multiple arc segments, or multiple straight segments, or multiple arc segments and multiple straight segments; this disclosure does not limit this. Figure 2 As shown, the second notch 154 can be U-shaped. However, this embodiment is not limited to this. For example, the second notch 154 can be U-shaped. In some examples, the shape and size of multiple second notches 154 can be the same. The shape and size of multiple second notches 154 and multiple first notches 153 can be the same or different. In this exemplary embodiment, by providing a second wave structure at the second edge 152 of the inorganic insulating layer 15 in the bending region 300, the bending stress on the inorganic insulating layer 15 during bending can be dispersed, stress concentration can be avoided, the risk of breakage of the inorganic insulating layer 15 can be reduced, thereby improving the bending effect.

[0113] In some exemplary implementations, such as Figure 2 As shown, along the direction from the bending region 300 to the display region, the first distance L1 between the first edge 151 of the inorganic insulating layer 15 and the edge of the first data connection line 53 covered by the first edge 151 can be greater than or equal to 5 micrometers (μm). Along the direction from the display region to the bending region 300, the second distance L2 between the second edge 152 of the inorganic insulating layer 15 and the edge of the third data connection line 55 covered by the second edge 152 can be greater than or equal to 5 μm. In some examples, the second distance L2 and the first distance L1 can be the same or different. However, this embodiment is not limited to this.

[0114] In some exemplary implementations, such as Figure 3As shown, in a plane perpendicular to the display substrate, the display area 100 includes: a substrate 10, a driving structure layer disposed on the substrate 10, an inorganic insulating layer 15, a first planarization layer 16, a metal conductive layer and a second planarization layer 17 disposed sequentially on the driving structure layer, a light-emitting element disposed on the second planarization layer 17, and an encapsulation layer 42 covering the light-emitting element. The first planarization layer 16 is the first insulating layer in this embodiment, and the first insulating layer is an organic insulating layer. The driving structure layer of the display area 100 includes a plurality of transistors forming a pixel driving circuit and at least one storage capacitor. The pixel driving circuit can be designed as 2T1C (i.e., two thin-film transistors and one capacitor), 3T1C (i.e., three thin-film transistors and one capacitor), or 7T1C (i.e., seven thin-film transistors and one capacitor). Figure 3 The illustration uses a first transistor and a first storage capacitor as an example. The first transistor can be a driving transistor. The driving structure layer of the display area 100 may include: a buffer layer 11 disposed on the substrate 10, an active layer disposed on the buffer layer 11, a first gate insulating layer 12 covering the active layer, a first gate metal layer disposed on the first gate insulating layer 12, a second gate insulating layer 13 covering the first gate metal layer, a second gate metal layer disposed on the second gate insulating layer 13, an interlayer insulating layer 14 covering the second gate metal layer, and a source / drain metal layer disposed on the interlayer insulating layer 14. The active layer may include at least a first active layer 21, the first gate metal layer may include at least a first gate electrode 22 and a first capacitor electrode 25, the second gate metal layer may include at least a second capacitor electrode 26, and the source / drain metal layer may include at least a first source electrode 23 and a first drain electrode 24. The first active layer 21, the first gate electrode 22, the first source electrode 23, and the first drain electrode 24 constitute the first transistor, and the first capacitor electrode 25 and the second capacitor electrode 26 constitute the first storage capacitor. The metal conductive layer may include at least a connection electrode 27. The connecting electrode 27 is connected to the first drain electrode 24 of the first transistor through vias formed in the inorganic insulating layer 15 and the first planarization layer 16. In some embodiments, the source-drain metal layer is referred to as the first source-drain metal layer (SD1), and the metal conductive layer is referred to as the second source-drain metal layer (SD2). The light-emitting element may include an anode 31, a pixel defining layer 34, an organic light-emitting layer 32, and a cathode 33. The anode 31 is connected to the connecting electrode 27 through vias formed in the second planarization layer 17, thereby connecting the anode 31 to the first drain electrode 24 of the first transistor. An isolation pillar layer 41 is provided on the side of the pixel defining layer 34 away from the substrate 10. In some examples, the encapsulation layer 42 may include an inorganic material layer, an organic material layer, and an inorganic material layer stacked sequentially. However, this embodiment is not limited to this.

[0115] In some exemplary implementations, such as Figure 3 and Figure 4As shown, in a plane perpendicular to the display substrate, the first region 301 of the bending region 300 includes: a substrate 10, a buffer layer 11, a first gate insulating layer 12, a first data lead-out layer, a second gate insulating layer 13, a second data lead-out layer, an interlayer insulating layer 14, a second wiring layer, an inorganic insulating layer 15, a first planarization layer 16, a third wiring layer, a second planarization layer 17, a pixel definition layer 34, and an isolation pillar layer 41. The first data lead-out layer includes multiple first data leads ( Figure 3 (Not shown in the image), the second data lead layer includes multiple second data leads ( Figure 3 The diagram shows a second data lead-out line 52. The second routing layer includes multiple first data connection lines ( Figure 3 The diagram shows a first data connection line 53. The third routing layer includes multiple second data connection lines ( Figure 3 The diagram illustrates a second data connection line 54. The orthographic projection of the first data connection line 53 on the substrate 10 overlaps with the orthographic projection of either a first data lead or a second data lead 52 on the substrate. The orthographic projection of the second data connection line 54 on the substrate 10 overlaps with the orthographic projection of the first data connection line 53 on the substrate 10. The first edge 151 of the inorganic insulating layer 15 covers the edge of the first data connection line 53 near the display area 100. The first data connection line 53 is connected to the second data lead 52 through a via formed in the interlayer insulating layer 14, or to the first data lead through a via formed in the interlayer insulating layer 14 and the second gate insulating layer 13. The second data connection line 54 is connected to the first data connection line 53 through a first opening provided in the first planarization layer 16. The orthographic projection of the first planarization layer 16 on the substrate 10 overlaps with the orthographic projection of the first data connection line 53 near the edge of the display area 100 on the substrate 10. The first flattening layer 16 is in direct contact with at least a portion of the first data connection line 53.

[0116] In some exemplary implementations, such as Figure 3As shown, in a plane perpendicular to the display substrate, the second region 302 of the bending region 300 includes: a substrate 10, a composite insulating layer, a first planarization layer 16, a third wiring layer, a second planarization layer 17, a pixel definition layer 34, and an isolation pillar layer 41 sequentially disposed on the substrate 10. The composite insulating layer includes a buffer layer 11, a first gate insulating layer 12, a second gate insulating layer 13, and an interlayer insulating layer 14 sequentially disposed on the substrate 10. The composite insulating layer of the second region 302 has a first groove 311 and a second groove 312. The interlayer insulating layer 14 in the first groove 311 is etched away, and the interlayer insulating layer 14, the second gate insulating layer 13, the first gate insulating layer 12, and the buffer layer 11 in the second groove 312 are all etched away. The orthographic projection of the second groove 312 on the substrate 10 lies within the orthographic projection of the first groove 311 on the substrate 10. A first planarization layer 16, a third routing layer, a second planarization layer 17, a pixel definition layer 34, and an isolation pillar layer 41 are sequentially disposed within the first groove 311 and the second groove 312. The third routing layer includes multiple second data connection lines ( Figure 3 The diagram shows a second data connection line 54.

[0117] In some exemplary implementations, such as Figure 3 As shown, in a plane perpendicular to the display substrate, the third region 303 of the bending region 300 includes: a substrate 10, a buffer layer 11, a first gate insulating layer 12, a first data lead-out layer, a second gate insulating layer 13, a second data lead-out layer, an interlayer insulating layer 14, a second wiring layer, an inorganic insulating layer 15, a first planarization layer 16, a third wiring layer, a second planarization layer 17, a pixel definition layer 34, and an isolation pillar layer 41. The first data lead-out layer includes multiple fourth data connection lines ( Figure 3 (Not shown in the image), the second data lead layer includes multiple fifth data connection lines ( Figure 3 The diagram shows a fifth data connection line 57. The second routing layer includes multiple third data connection lines ( Figure 3 The diagram shows a third data connection line 55. The third routing layer includes multiple second data connection lines ( Figure 3The diagram illustrates a second data connection line 54. The orthographic projection of a third data connection line 55 on the substrate 10 overlaps with the orthographic projection of either a fourth or fifth data connection line 57 on the substrate. Similarly, the orthographic projection of a second data connection line 54 on the substrate 10 overlaps with the orthographic projection of a third data connection line 55 on the substrate 10. The second edge 152 of the inorganic insulating layer 15 covers the edge of the third data connection line 55 away from the display area 100. A third data connection line 55 is connected to the fifth data connection line 57 through a via in the interlayer insulating layer 14, or to the fourth data connection line 56 through a via in the interlayer insulating layer 14 and the second gate insulating layer 13. A second data connection line 54 is connected to the third data connection line 55 through a second opening in the first planarization layer 16.

[0118] In some exemplary embodiments, the structures within the first region 301 and the third region 303 of the bending region 300 are symmetrical to each other, and the axis of symmetry is perpendicular to the extension direction of the data connection line. However, this embodiment is not limited to this. In some examples, the structure within the third region of the bending region 300 may be different from or partially the same as the structure within the first region.

[0119] The structure of the display substrate of this disclosure is illustrated below through an example of the fabrication process of the display substrate. The "patterning process" mentioned in this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping. Deposition can be performed using any one or more methods selected from sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more methods selected from spraying and spin coating; and etching can be performed using any one or more methods selected from dry etching and wet etching. A "thin film" refers to a thin film of a certain material fabricated on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." When the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0120] The phrase "A and B are set in the same layer" in this disclosure means that A and B are formed simultaneously through the same drafting process. "Same layer" does not always mean that the layer thickness or layer height is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0121] In some exemplary embodiments, the fabrication process of the display substrate of this embodiment may include the following steps (1) to (12). Figures 5 to 7 , Figures 9 to 10 , Figure 12as well as Figures 14 to 19 All Figure 1 A cross-sectional view along the PP direction.

[0122] (1) A flexible substrate is prepared on a glass carrier.

[0123] In some exemplary embodiments, the substrate 10 includes a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass carrier plate 1. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer can be made of amorphous silicon (a-Si).

[0124] In some exemplary embodiments, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its fabrication process may include: firstly, coating a layer of polyimide on a glass substrate 1, curing it to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the fabrication of the substrate 10. Figure 5 As shown. After this process, both the display area 100 and the bending area 300 include the substrate 10.

[0125] (2) Prepare an active layer pattern on the substrate.

[0126] In some exemplary embodiments, a first insulating film and an active layer film are sequentially deposited on a substrate 10. The active layer film is patterned using a patterning process to form a buffer layer 11 covering the entire substrate 10, and an active layer pattern disposed on the buffer layer 11. Figure 6 As shown, an active layer pattern is formed in the display area 100, including at least a first active layer 21. After this patterning process, the bending area 300 includes a buffer layer 11 disposed on the substrate 10.

[0127] (3) The first gate metal layer and the first data lead-out layer pattern are prepared on the substrate.

[0128] In some exemplary embodiments, a second insulating film and a first metal film are sequentially deposited on the substrate 10 on which the above structure is formed. The first metal film is patterned using a patterning process to form a first gate insulating layer 12 covering the active layer pattern, and a first gate metal layer pattern and a first data lead-out layer pattern disposed on the first gate insulating layer 12. Figure 7 As shown, a first gate metal layer pattern is formed in display area 100, including at least a first gate electrode 22, a first capacitor electrode 25, multiple gate lines (not shown), and multiple gate leads (not shown). A first data lead layer pattern is formed in bending area 300, including at least multiple first data leads (not shown) and multiple fourth data connection lines (not shown). The multiple first data leads are configured to connect to data lines subsequently formed in display area 100, and the multiple fourth data connection lines are configured to connect to third data connection lines subsequently formed in bending area 300. In some examples, the extension directions of the multiple first data leads and the multiple fourth data connection lines are parallel to each other.

[0129] After this patterning process, the bending region 300 includes a buffer layer 11, a first gate insulating layer 12, and a first data lead-out layer stacked on the substrate 10.

[0130] (4) The second gate metal layer and the second data lead-out layer pattern are prepared on the substrate.

[0131] In some exemplary embodiments, a third insulating film and a second metal film are sequentially deposited on the substrate 10 on which the above structure is formed. The second metal film is patterned using a patterning process to form a second gate insulating layer 13 covering the first gate metal layer pattern, the first data lead layer pattern, and the first gate insulating layer 12, as well as a second gate metal layer pattern and a second data lead layer pattern disposed on the second gate insulating layer 13. Figure 9 As shown, a second gate metal layer pattern is formed in the display area 100, including at least a second capacitor electrode 26, the position of which corresponds to the position of the first capacitor electrode 25. A second data lead layer pattern is formed in the bending area 300, including at least multiple second data leads 52 and multiple fifth data connection lines 57. The multiple second data leads 52 are configured to connect to data lines subsequently formed in the display area 100, and the multiple fifth data connection lines 57 are configured to connect to third data connection lines subsequently formed in the bending area 300. Figure 8As shown, the orthographic projections of the first data lead-out layer and the second data lead-out layer on the substrate 10 do not overlap. The orthographic projections of multiple first data leads 51 and multiple second data leads 52 on the substrate 10 are arranged at intervals, as are the orthographic projections of multiple fourth data connection lines 56 and multiple fifth data connection lines 57 on the substrate 10. In some examples, the extension directions of the multiple second data leads and multiple fifth data connection lines are parallel to the extension directions of the multiple first data leads and multiple fourth data connection lines. In this exemplary embodiment, the disparate layer arrangement of the multiple data leads can reduce the spacing between adjacent data leads and reduce transmission interference between adjacent data leads, thereby improving signal transmission performance.

[0132] After this patterning process, the bending region 300 includes a buffer layer 11, a first gate insulating layer 12, a first data lead-out layer, a second gate insulating layer 13, and a second data lead-out layer stacked on the substrate 10.

[0133] (5) Prepare an interlayer insulating layer pattern on the substrate.

[0134] In some exemplary embodiments, a fourth insulating film is deposited on the substrate 10 on which the above structure is formed, and the fourth insulating film is patterned by a patterning process to form an interlayer insulating layer 14 pattern covering the patterns of the second gate metal layer and the second data lead-out layer. For example... Figure 10 As shown, at least two first vias K1 are formed on the interlayer insulating layer 14 of the display area 100. The interlayer insulating layer 14, the second gate insulating layer 13, and the first gate insulating layer 12 within the two first vias K1 are etched away, exposing the surface of the first active layer 21. Multiple second vias (not shown) and multiple third vias K3 are formed on the interlayer insulating layer 14 of the first region 301 of the bending region 300. The interlayer insulating layer 14 and the second gate insulating layer 13 within any second via are etched away, exposing the surface of a first data lead. The interlayer insulating layer 14 within any third via K3 is etched away, exposing the surface of a second data lead 52. Multiple fourth vias (not shown) and multiple fifth vias K5 are provided on the interlayer insulating layer 14 of the third region 303 of the bending region 300. The interlayer insulating layer 14 and the second gate insulating layer 13 in any fourth via are etched away to expose the surface of a fourth data connection line. The interlayer insulating layer 14 in any fifth via K5 is etched away to expose the surface of a fifth data connection line 57.

[0135] After this patterning process, the bending region 300 includes a buffer layer 11, a first gate insulating layer 12, a first data lead-out layer, a second gate insulating layer 13, a second data lead-out layer, and an interlayer insulating layer 14 stacked on the substrate 10.

[0136] (6) Fabricate source / drain metal layer and second wiring layer patterns on the substrate.

[0137] In some exemplary embodiments, a third metal thin film is deposited on the substrate 10 where the above structure is formed, and the third metal thin film is patterned by a patterning process to form a source / drain metal layer pattern and a second wiring layer pattern on the interlayer insulating layer 14. For example... Figure 12 As shown, a source / drain metal layer pattern is formed in the display area 100, including at least a first source electrode 23, a first drain electrode 24, multiple data lines (not shown), and power line (e.g., VDD and VSS) patterns. The first source electrode 23 and the first drain electrode 24 are connected to the first active layer 21 through a first via K1. Figure 11 As shown, the second routing layer pattern is formed in the bending region 300, and includes at least multiple first data connection lines 53 and multiple third data connection lines 55. The multiple first data connection lines 53 are located in the first region 301, and the multiple third data connection lines 55 are located in the third region 303. The extension directions of the multiple first data connection lines 53 and the multiple third data connection lines 55 are parallel to each other. In some examples, the extension directions of the multiple first data connection lines 53 and the multiple third data connection lines 55 are parallel to the extension direction of the data lead-out lines. Figure 10 and Figure 12 As shown, any first data connection line 53 can be connected to the first data lead through at least one second via (e.g., two second vias), or it can be connected to the second data lead through at least one third via K3 (e.g., two third vias K3). Any third data connection line 55 can be connected to the fourth data connection line through at least one fourth via (e.g., two fourth vias), or it can be connected to the fifth data connection line 57 through at least one fifth via K5 (e.g., two fifth vias K5). In this exemplary embodiment, the first data connection line can be connected to a data lead through multiple vias, thereby increasing the contact area between the first data connection line and the data lead and improving signal transmission stability.

[0138] Thus, the driving structure layer of the display region 100 is fabricated on the substrate 10, as follows: Figure 12 As shown. In the driving structure layer of the display area 100, the first active layer 21, the first gate electrode 22, the first source electrode 23 and the first drain electrode 24 form the first transistor, and the first capacitor electrode 25 and the second capacitor electrode 26 form the first storage capacitor.

[0139] In some exemplary embodiments, the buffer layer 11, the first gate insulating layer 12, the second gate insulating layer 13, and the interlayer insulating layer 14 can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, multiple layers, or composite layers. The buffer layer 11 can be used to improve the water and oxygen resistance of the substrate 10. The first metal thin film, the second metal thin film, and the third metal thin film can be any one or more of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The active layer thin film can be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. In other words, this disclosure is applicable to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0140] (7) Prepare an inorganic insulating layer pattern on the substrate.

[0141] In this embodiment, the inorganic insulating layer 15 is also referred to as a passivation (PVX) layer. In some exemplary embodiments, the inorganic insulating layer 15 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0142] In some exemplary embodiments, a fifth insulating film is deposited on the substrate 10 on which the aforementioned structure is formed, and the fifth insulating film is patterned using a patterning process to form a pattern of the inorganic insulating layer 15. For example... Figure 14 As shown, the inorganic insulating layer 15 covers the source / drain metal layer and the interlayer insulating layer 14 of the display area 100. The inorganic insulating layer 15 has a first edge 151 and a second edge 152 in the bending region 300. The inorganic insulating layer 15 between the first edge 151 and the second edge 152 is etched away, forming a hollow area of ​​the inorganic insulating layer 15. The first edge 151 of the inorganic insulating layer 15 is located in the first region 301, and the second edge 152 is located in the third region 303. The first edge 151 of the inorganic insulating layer 15 covers the edge of the first data connection line 53 near the display area 100. The second edge 152 of the inorganic insulating layer 15 covers the edge of the third data connection line 55 away from the display area 100.

[0143] In some exemplary implementations, such as Figure 13As shown, the first edge 151 of the inorganic insulating layer 15 has a first wave structure, which includes a plurality of spaced first notches 153. Each of the plurality of first notches 153 corresponds one-to-one with a plurality of first data connection lines 53, and the orthographic projection of any first notch 153 on the substrate 10 lies within the orthographic projection of the corresponding first data connection line 53 on the substrate 10. Figure 13 As shown, the first notch 153 can be ∩-shaped. The second edge 152 of the inorganic insulating layer 15 has a second wavy structure, which includes a plurality of spaced second notches 154. Each of the plurality of second notches 154 corresponds one-to-one with a plurality of third data connection lines 55, and the orthographic projection of any second notch 154 on the substrate 10 lies within the orthographic projection of the corresponding third data connection line 55 on the substrate 10. Figure 13 As shown, the second gap 154 ​​can be U-shaped.

[0144] In some exemplary implementations, such as Figure 13 As shown, along the direction away from the display area 100, the first distance between the first edge 151 of the inorganic insulating layer 15 and the edge of the first data connection line 53 covered by the first edge 151 is L1; the second distance between the second edge 152 of the inorganic insulating layer 15 and the edge of the third data connection line 55 covered by the second edge 152 is L2. The first distance L1 can be equal to the second distance L2, and is greater than or equal to 5 μm. In some examples, the distance between the edge of the first notch 153 of the first edge 151 of the inorganic insulating layer 15 near the display area and the edge of the first data connection line 53 covered by the first edge 151 can be greater than or equal to 1.5 μm. However, this embodiment is not limited to this.

[0145] In this exemplary embodiment, the inorganic insulating layer 15 covers the edges of the second wiring layer near the display area and away from the display area, so that the second data lead layer in the bending area is covered by the interlayer insulating layer 14 and the inorganic insulating layer 15, effectively protecting the second data lead layer. When the first edge of the inorganic insulating layer in the bending area does not overlap with the second wiring layer, the thickness of the interlayer insulating layer will become thinner due to over-etching during the etching process of the inorganic insulating layer. During the bending process, due to stress concentration, the thinned interlayer insulating layer is prone to forming microcracks. Under long-term high temperature and high humidity reliable environment, water vapor will seep into the microcracks, causing reliable water and oxygen corrosion of the second data lead, resulting in poor bright lines in the display area. In contrast, in this exemplary embodiment, the first edge of the inorganic insulating layer with the bend area overlaps with the edge of the second wiring layer. This can prevent moisture from seeping in due to over-etching during the etching process of the inorganic insulating layer, which would cause the thickness of the interlayer insulating layer covering the second data lead-out layer to become thinner. This improves the corrosion resistance of the display substrate and thus extends its service life under extreme conditions.

[0146] (8) The buffer layer to the interlayer insulation layer of the bending area is patterned by patterning process, and the first groove and the second groove are formed in the bending area.

[0147] In some exemplary embodiments, on the substrate 10 forming the above structure, the interlayer insulating layer 14 of the second region 302 of the bending region 300 is etched using a first mask (Etch Bending A Mask, abbreviated as EBA Mask) to form a first groove 311. The interlayer insulating layer 14 within the first groove 311 is etched away, exposing the surface of the second gate insulating layer 13. Then, the second gate insulating layer 13, the first gate insulating layer 12, and the buffer layer 11 within the first groove 311 in the second region 302 of the bending region 300 are etched using a second mask (Etch Bending B Mask, abbreviated as EBB Mask) to form a second groove 312. The second gate insulating layer 13, the first gate insulating layer 12, and the buffer layer 11 within the second groove 312 are etched away, exposing the surface of the substrate 10. Figure 15 As shown, the orthographic projection of the first groove 311 on the substrate 10 overlaps the orthographic projection of the second groove 312 on the substrate 10. By using EBA MASK and EBB MASK to create grooves in the bending region 300, the thickness of the bending region 300 can be reduced, thus improving the bending effect.

[0148] After this patterning process, the film structure of the first region 301 and the third region 303 of the display area 100 and the bending area 300 remains unchanged.

[0149] (9) A first planarization (PLN) layer is prepared on the substrate. The first planarization layer is the first insulating layer in this embodiment.

[0150] In some exemplary embodiments, a first planarization film is coated on the substrate 10 forming the above structure to form a first planarization layer 16 covering the entire substrate 10. A plurality of sixth vias K6, a plurality of first openings K7, and a plurality of second openings K8 are formed in the first planarization layer 16 using a patterning process. For example... Figure 16 As shown, multiple sixth vias K6 are formed in the display area 100. The first planarization layer 16 and the inorganic insulating layer 15 within any sixth via K6 are etched away, exposing the surface of the first drain electrode 24 of the first transistor. Multiple first openings K7 are formed in the first region 301 of the bending region 300. The first planarization layer 16 within any first opening K7 is etched away, exposing the surface of a first data connection line 53. Multiple second openings K8 are formed in the third region 303 of the bending region 300. The first planarization layer 16 within any second opening K8 is etched away, exposing the surface of a third data connection line 55. Figure 16 As shown, the orthographic projection of any first opening K7 on the substrate 10 lies within the orthographic projection of the first data connection line 53 on the substrate 10, and the orthographic projection of any second opening K8 on the substrate 10 lies within the orthographic projection of the third data connection line 55 on the substrate 10. In some examples, the orthographic projection of any first opening K7 on the substrate 10 may not overlap with the first edge 151 of the inorganic insulating layer 15, and the orthographic projection of any second opening K8 on the substrate 10 may not overlap with the second edge 152 of the inorganic insulating layer 15. However, this embodiment is not limited to this.

[0151] In some exemplary embodiments, the first planarization layer 16 fills the second groove 312. The first planarization layer 16 can adjust the step thickness formed by the second groove, thereby reducing the risk of breakage of the subsequently formed third wiring layer due to excessive step thickness formed by the second groove. However, this embodiment is not limited to this. In some examples, the first planarization layer 16 can fill both the second groove 312 and the first groove 311.

[0152] (10) Fabricate a metal conductive layer and a third wiring layer pattern on a substrate.

[0153] In some exemplary embodiments, a fourth metal thin film is deposited on the substrate 10 forming the aforementioned structure, and the fourth metal thin film is patterned using a patterning process to form a metal conductive layer pattern and a third wiring layer pattern on the first planarization layer 16. For example... Figure 17As shown, a metallic conductive layer pattern is formed in the display area 100, including at least a connection electrode 27, which is connected to the first drain electrode 24 of the first transistor through a sixth via. In some examples, the metallic conductive layer may also include any one or more of power lines, power leads, and auxiliary cathodes. However, this embodiment is not limited to this. A third wiring layer pattern is formed in the bending area 300, including at least a plurality of second data connection lines 54. The extension directions of the plurality of second data connection lines 54 are parallel to each other. In some examples, the extension directions of the plurality of second data connection lines 54 are parallel to the extension directions of the plurality of first data connection lines 53. Any one of the second data connection lines 54 extends from the first region 301 of the bending area 300 through the second region 302 to the third region 303. The second data connection line 54 is connected to the first data connection line 53 in the first region 301 through a first opening K7, and to the third data connection line 55 in the third region 303 through a second opening K8. In this exemplary embodiment, signal transmission between the first data lead-out line 51 and the fourth data lead-out line 56, and between the second data lead-out line 52 and the fifth data lead-out line 57 are achieved by connecting the first data lead-out line 53, the second data lead-out line 54 and the third data lead-out line 55 in series, thereby realizing signal transmission between the data lines of the display area and the integrated circuit of the bonding area.

[0154] (11) A second planarization layer is prepared on the substrate.

[0155] In some exemplary embodiments, a second planarization film is coated on the substrate 10 forming the above structure to form a second planarization layer 17 covering the entire substrate 10. A plurality of seventh vias K9 are formed in the second planarization layer 17 using a patterning process. For example... Figure 18 As shown, multiple seventh vias K9 are formed in the display area 100. The second planarization layer 17 within any seventh via K9 is etched away, exposing the surface of the connecting electrode 27. In the second region 302 of the bending region 300, the second planarization layer 17 completely fills the first groove 311 and the second groove 312, so that the bending region 300 has a flat surface, that is, the surface of the second planarization layer 17 of the bending region 300 away from the substrate 10 can be flush.

[0156] (12) An anode, a pixel definition layer, an isolation pillar, an organic light-emitting layer, a cathode, and an encapsulation layer are sequentially fabricated on a substrate.

[0157] In some exemplary embodiments, a transparent conductive film is deposited on the substrate 10 on which the aforementioned structure is formed, and the transparent conductive film is patterned using a patterning process to form the anode 31 pattern. For example... Figure 19As shown, the anode 31 pattern is formed on the second planarization layer 17 of the display area 100 and is connected to the connecting electrode 27 through the seventh via. After this patterning process, the film structure of the bending area 300 remains unchanged.

[0158] In some exemplary embodiments, a pixel definition film is coated on the substrate 10 on which the aforementioned structure is formed, and a pixel definition layer (PDL) 34 pattern is formed by masking, exposure, and development processes. For example... Figure 19 As shown, a pixel definition layer 34 is formed in the display area 100 and the bending area 300. Pixel openings are formed in the pixel definition layer 34 of the display area 100, and the pixel definition film within the pixel openings is developed away, exposing the surface of the anode 31. The pixel definition layer 34 of the bending area 300 covers a second planarization layer 17.

[0159] In some exemplary embodiments, an organic material thin film is coated on the substrate 10 on which the aforementioned pattern is formed, and an isolation pillar (PS) layer 41 pattern is formed in the display area 100 and the bending area 300 through a masking, exposure, and development process. Figure 19 As shown, the isolation pillar layer 41 of the display area 100 includes multiple isolation pillars. The isolation pillar layer 41 of the bent area 300 covers the pixel definition layer 34.

[0160] In some exemplary embodiments, an organic light-emitting layer 32 and a cathode 33 are sequentially formed on the substrate 10 on which the aforementioned pattern is formed. For example... Figure 19 As shown, the organic light-emitting layer 32 includes a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, formed within the pixel opening of the display area 100, thus connecting the organic light-emitting layer 32 to the anode 31. Since the anode 31 is connected to the connecting electrode 27, and the connecting electrode 27 is connected to the first drain electrode 24 of the first transistor, the light emission control of the organic light-emitting layer 32 is achieved. A portion of the cathode 33 is formed on the organic light-emitting layer 32. After this patterning process, the film structure of the bending region 300 remains unchanged.

[0161] In some exemplary embodiments, an encapsulation layer 42 is formed on the substrate 10 on which the aforementioned pattern is formed. For example... Figure 19 As shown, the encapsulation layer 42 is formed in the display area 100 and can employ a stacked structure of inorganic / organic / inorganic materials. The organic material layer is disposed between the two inorganic material layers. After this patterning process, the film structure of the bending area 300 remains unchanged.

[0162] In some exemplary embodiments, the first planarization layer, the second planarization layer, the pixel definition layer, and the isolation pillar layer may be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate.

[0163] After the above film structure is prepared, the display substrate can be peeled off from the glass carrier plate 1 by a peeling process.

[0164] The display substrate provided in this exemplary embodiment has an overlap between the orthographic projections of the first insulating layer (i.e., the first planarization layer) and the edge of the second wiring layer near the display area on the substrate in the bending region, and the orthographic projections of the edge of the inorganic insulating layer and the edge of the second wiring layer on the substrate overlap. This is beneficial to protecting the first wiring layer in the bending region, thereby improving the corrosion resistance of the display substrate and thus extending the service life of the display substrate under extreme environments.

[0165] The preparation process of this exemplary embodiment can be realized using existing mature preparation equipment, with minimal modifications to existing processes. It is well compatible with existing preparation processes, simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0166] The structure of the display substrate and its fabrication process in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and increased or decreased as needed. For example, multiple first data leads, multiple second data leads, multiple fourth data connection lines, and multiple fifth data connection lines can be disposed in the same layer as the first gate metal layer, or they can be disposed in the same layer as the second gate metal layer. As another example, the third region of the bending area may not have fourth and fifth data connection lines, and the third data connection lines may extend to the bonding area. Furthermore, the display substrate can be a top-emitting structure or a bottom-emitting structure. Also, the driving transistor can be a top-gate structure or a bottom-gate structure; it can be a single-gate structure or a dual-gate structure. This embodiment is not limited in this respect.

[0167] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0168] Figure 20 This is another structural schematic diagram of the bent region according to at least one embodiment of the present disclosure. Figure 20 for Figure 1 A magnified view of a portion of region S in the middle. Figure 21 This is a plan view of the bending region after the formation of the inorganic insulating layer in at least one embodiment of the present disclosure.

[0169] In some exemplary implementations, such as Figure 20 and Figure 21As shown, the inorganic insulating layer 15 has a first edge 151 and a second edge 152 in the bending region 300. The first edge 151 is located within the first region 301, and the second edge 152 is located within the third region 303. The inorganic insulating layer 15 between the first edge 151 and the second edge 152 is etched away. Both the first edge 151 and the second edge 152 are straight edges. The extension direction of the first edge 151 is parallel to the extension direction of the second edge 152. The first edge 151 covers the edges of multiple first data connection lines 53 near the display area, and the second edge 152 covers the edges of multiple third data connection lines 55 away from the display area. Along the direction from the bending region 300 to the display area, the first distance L1 between the first edge 151 of the inorganic insulating layer 15 and the edges of the first data connection lines 53 covered by the first edge 151 can be greater than or equal to 5 micrometers (μm). Along the direction from the display area to the bending area 300, the second distance L2 between the second edge 152 of the inorganic insulating layer 15 and the edge of the third data connection line 55 covered by the second edge 152 can be greater than or equal to 5 μm. In some examples, the second distance L2 and the first distance L1 can be the same or different. However, this embodiment is not limited to this.

[0170] The structure of the display area 100 and other structures of the bent area 300 in this exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments, and therefore will not be repeated here.

[0171] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0172] Figure 22 This is another structural schematic diagram of the bending region of a display substrate according to at least one embodiment of the present disclosure. Figure 22 for Figure 1 A magnified schematic diagram of a portion of region S. In some exemplary embodiments, such as... Figure 22As shown, in a plane parallel to the display substrate, at least one of the plurality of second data connection lines 54 includes: a first conductor segment 541, a second conductor segment 542, and a third conductor segment 543 connected sequentially. The first conductor segment 541 is located in the first region 301 of the bending region 300, the second conductor segment 542 is located in the second region 302, and the third conductor segment 543 is located in the third region 303. The second data connection line 54 can be a straight line segment. The average widths of the first conductor segment 541, the second conductor segment 542, and the third conductor segment 543 can be substantially the same. In some examples, the average width of the second data connection line 54 can range from 5 to 10 micrometers, and the spacing between two adjacent second data connection lines 54 can range from 9 to 11 micrometers. For example, the average width of the second data connection line 54 can be about 8 micrometers, and the spacing between two adjacent second data connection lines 54 can be about 9 micrometers. The second conductor segment 542 of the second data connection line 54 in the second region 302 can have a cutout pattern. The orthographic projection of the cutout pattern onto the substrate can be located within the second groove defined by the third boundary 3121 and the fourth boundary 3122. The cutout pattern can include multiple holes 5420. The multiple holes 5420 are arranged sequentially along the extension direction of the second data connection line 54, forming a row. The shape and size of the multiple holes 5420 can be the same or different. For example, the multiple holes 5420 can all be circular or elliptical. However, this embodiment does not limit the arrangement, shape, and size of the multiple holes. The cutout pattern provided on the second data connection line 54 can alleviate the stress accumulated on the second data connection line 54 during bending, which is beneficial for releasing stress when the second data connection line 54 is bent, reducing the risk of breakage of the second data connection line 54, thereby improving the bending effect.

[0173] The structure of the display area 100 and other structures of the bent area 300 in this exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments, and therefore will not be repeated here.

[0174] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0175] Figure 23 This is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 23 for Figure 1 Another cross-sectional view along the PP direction. In some exemplary embodiments, such as Figure 23As shown, in a plane perpendicular to the display substrate, both the first region 301 and the third region 303 of the bending region 300 include: a substrate 10, a buffer layer 11, a first gate insulating layer 12, a first data lead-out layer, a second gate insulating layer 13, a second data lead-out layer, an interlayer insulating layer 14, a second wiring layer, an inorganic insulating layer 15, a first planarization layer (i.e., the first insulating layer in this embodiment) 16, a third wiring layer, a second planarization layer 17, a pixel definition layer 34, and an isolation pillar layer 41. The first data lead-out layer includes multiple first data leads located in the first region 301. Figure 23 (not shown in the image) and multiple fourth data connection lines located in the third region 303 ( Figure 23 (Not shown in the image); the second data lead layer includes multiple second data leads located in the first region 301 ( Figure 23 The diagram illustrates a second data lead-out line 52 and multiple fifth data connection lines located in the third region 303. Figure 23 The diagram shows a fifth data connection line 57. The second wiring layer includes multiple first data connection lines located in the first area 301. Figure 23 The diagram illustrates a first data connection line 53 and multiple third data connection lines located in the third region 303. Figure 23 The diagram shows a third data connection line 55. The third routing layer includes multiple second data connection lines ( Figure 23 The diagram shows a second data connection line 54.

[0176] In some exemplary implementations, such as Figure 23As shown, in the first region 301, the first data connection line 53 is connected to the second data lead 52 through multiple vias (e.g., two vias) formed on the interlayer insulating layer 14, or to the first data lead through multiple vias (e.g., two vias) formed on the interlayer insulating layer 14 and the second gate insulating layer 13. The second data connection line 54 is connected to the first data connection line 53 through multiple first openings (e.g., three first openings) formed on the first planarization layer 16. In the third region 303, the third data connection line 55 is connected to the fifth data connection line 57 through multiple vias (e.g., two vias) formed on the interlayer insulating layer 14, or to the fourth data connection line through multiple vias (e.g., two vias) formed on the interlayer insulating layer 14 and the second gate insulating layer 13. The second data connection line 54 is connected to the third data connection line 55 through multiple first openings (e.g., three first openings) formed on the first planarization layer 16. In this exemplary embodiment, the structures within the first region 301 and the third region 303 of the bending region 300 are symmetrical to each other, and the axis of symmetry is perpendicular to the extension direction of the data connection line. However, this embodiment is not limited in this respect. In some examples, the structure within the third region of the bending region may be different from or partially the same as the structure within the first region.

[0177] In some exemplary implementations, such as Figure 23As shown, in a plane perpendicular to the display substrate, the second region 302 of the bending region 300 includes: a substrate 10, a composite insulating layer, a first planarization layer 16, a third wiring layer, a second planarization layer 17, a pixel definition layer 34, and an isolation pillar layer 41 sequentially disposed on the substrate 10. The composite insulating layer includes a buffer layer 11, a first gate insulating layer 12, a second gate insulating layer 13, and an interlayer insulating layer 14 sequentially disposed on the substrate 10. The substrate 10 includes: a first flexible material layer, a first inorganic material layer (also known as a first barrier layer), a semiconductor layer, a second flexible material layer, and a second inorganic material layer (also known as a second barrier layer) sequentially stacked. The second region 302 is provided with a first groove 311 and a second groove 312. The first groove 311 is formed by an EBA MASK process, in which the interlayer insulating layer 14, the second gate insulating layer 13, and the first gate insulating layer 12 within the first groove 311 are etched away, exposing the buffer layer 11. The second groove 312 is formed by an EBA MASK process. The second groove 312 is formed within the first groove 311, and the buffer layer 11 and the second barrier layer of the substrate 10 within the second groove 312 are etched away. The second groove 312 exposes the second flexible material layer of the substrate 10. The orthographic projection of the second groove 312 onto the substrate 10 lies within the orthographic projection of the first groove 311 onto the substrate 10. The second groove 312 is filled with a first planarization layer 16. The first groove 311 is filled with a second planarization layer 17. However, this embodiment is not limited to this. In some examples, during the EBA MASK process, the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, and part of the buffer layer may be etched away.

[0178] The structure of the display area 100 and other structures of the bent area 300 in this exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments, and therefore will not be repeated here.

[0179] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0180] Figure 24 This is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 24 for Figure 1 Another cross-sectional view along the PP direction. In some exemplary embodiments, such as Figure 24As shown, in a plane perpendicular to the display substrate, both the first region 301 and the third region 303 of the bending region 300 include: a substrate 10, a barrier layer 18, a buffer layer 11, a first gate insulating layer 12, a first data lead-out layer, a second gate insulating layer 13, a second data lead-out layer, an interlayer insulating layer 14, a second wiring layer, an inorganic insulating layer 15, a first planarization layer (i.e., the first insulating layer in this embodiment) 16, a third wiring layer, a second planarization layer 17, a pixel definition layer 34, and an isolation pillar layer 41. The first data lead-out layer includes multiple first data leads located in the first region 301. Figure 24 (not shown in the image) and multiple fourth data connection lines located in the third region 303 ( Figure 24 (Not shown in the image); the second data lead layer includes multiple second data leads located in the first region 301 ( Figure 24 The diagram illustrates a second data lead-out line 52 and multiple fifth data connection lines located in the third region 303. Figure 24 The diagram shows a fifth data connection line 57. The second wiring layer includes multiple first data connection lines located in the first area 301. Figure 24 The diagram illustrates a first data connection line 53 and multiple third data connection lines located in the third region 303. Figure 24 The diagram shows a third data connection line 55. The third routing layer includes multiple second data connection lines ( Figure 24 The diagram shows a second data connection line 54.

[0181] In some exemplary implementations, such as Figure 24As shown, in a plane perpendicular to the display substrate, the second region 302 of the bending region 300 includes: a substrate 10, a composite insulating layer, a first planarization layer 16, a third wiring layer, a second planarization layer 17, a pixel definition layer 34, and an isolation pillar layer 41 sequentially disposed on the substrate 10. The composite insulating layer includes a barrier layer 18, a buffer layer 11, a first gate insulating layer 12, a second gate insulating layer 13, and an interlayer insulating layer 14 sequentially disposed on the substrate 10. The substrate 10 may include at least a flexible material layer formed of a flexible material. The composite insulating layer of the second region 302 is provided with a first groove 311 and a second groove 312. The orthographic projection of the second groove 312 on the substrate 10 lies within the orthographic projection of the first groove 311 on the substrate 10. The first groove 311 is formed by an EBA MASK process, in which the interlayer insulating layer 14, the second gate insulating layer 13, and the first gate insulating layer 12 within the first groove 311 are etched away, exposing the buffer layer 11. The second groove 312 is formed by an EBA MASK process. The second groove 312 is formed within the first groove 311. The buffer layer 11 and the barrier layer 18 within the second groove 312 are etched away, exposing the substrate 10. The second groove 312 is filled with a first planarization layer 16. The first groove 311 is filled with a second planarization layer 17. However, this embodiment is not limited to this. In some examples, during the EBA MASK process, the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, and part of the buffer layer may be etched away.

[0182] The structure of the display area 100 and other structures of the bent area 300 in this exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments, and therefore will not be repeated here.

[0183] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0184] Figure 25 This is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 25 for Figure 1 Another cross-sectional view along the PP direction. In some exemplary embodiments, such as Figure 25As shown, in a plane perpendicular to the display substrate, both the first region 301 and the third region 303 of the bending region 300 include: a substrate 10, a barrier layer 18, a buffer layer 11, a first gate insulating layer 12, a first data lead-out layer, a second gate insulating layer 13, a second data lead-out layer, an interlayer insulating layer 14, a second wiring layer, a first planarization layer (i.e., the first insulating layer in this embodiment) 16, a third wiring layer, a second planarization layer 17, a pixel definition layer 34, and an isolation pillar layer 41. The first data lead-out layer includes multiple first data leads located in the first region 301. Figure 25 (not shown in the image) and multiple fourth data connection lines located in the third region 303 ( Figure 25 (Not shown in the image); the second data lead layer includes multiple second data leads located in the first region 301 ( Figure 25 The diagram illustrates a second data lead-out line 52 and multiple fifth data connection lines located in the third region 303. Figure 25 The diagram shows a fifth data connection line 57. The second wiring layer includes multiple first data connection lines located in the first area 301. Figure 25 The diagram illustrates a first data connection line 53 and multiple third data connection lines located in the third region 303. Figure 25 The diagram shows a third data connection line 55. The third routing layer includes multiple second data connection lines ( Figure 25 The diagram illustrates a second data connection line 54. In this exemplary embodiment, by setting the orthographic projection of the first insulating layer on the substrate in the bending area to overlap with the orthographic projection of the edge of the second wiring layer near the display area on the substrate, it is beneficial to protect the first wiring layer in the bending area, thereby improving the corrosion resistance of the display substrate and thus extending the service life of the display substrate under extreme environments.

[0185] In some exemplary implementations, such as Figure 25As shown, in a plane perpendicular to the display substrate, the second region 302 of the bending region 300 includes: a substrate 10, a composite insulating layer, a first planarization layer 16, a pixel definition layer 34, and an isolation pillar layer 41 sequentially disposed on the substrate 10. The composite insulating layer includes a barrier layer 18, a buffer layer 11, a first gate insulating layer 12, a second gate insulating layer 13, and an interlayer insulating layer 14 sequentially disposed on the substrate 10. The substrate 10 includes at least a flexible material layer. The second region 302 is provided with a first groove 311 and a second groove 312. The first groove 311 is formed by an EBA MASK process, in which the interlayer insulating layer 14, the second gate insulating layer 13, and the first gate insulating layer 12 within the first groove 311 are etched away, exposing the buffer layer 11. The second groove 312 is formed by an EBA MASK process, in which the second groove 312 is formed within the first groove 311, in which the buffer layer 11 and the barrier layer 18 within the second groove 312 are etched away, exposing the substrate 10. The second groove 312 is filled with a first planarization layer 16. The first groove 311 is filled with a second planarization layer 17. However, this embodiment is not limited thereto. In some examples, during the EBA MASK process, the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, and part of the buffer layer may be etched away.

[0186] The structure of the display area 100 and other structures of the bent area 300 in this exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments, and therefore will not be repeated here.

[0187] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0188] Figure 26 This is another structural schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 26 for Figure 1 Another cross-sectional view along the PP direction. In some exemplary embodiments, such as Figure 26 As shown, in a plane perpendicular to the display substrate, both the first region 301 and the third region 303 of the bending region 300 include: a substrate 10, a barrier layer 18, a buffer layer 11, a first gate insulating layer 12, a first data lead-out layer, a second gate insulating layer 13, a second data lead-out layer, an interlayer insulating layer 14, a second wiring layer, a first planarization layer (i.e., the first insulating layer in this embodiment) 16, a third wiring layer, a second planarization layer 17, a pixel definition layer 34, and an isolation pillar layer 41. The first data lead-out layer includes multiple first data leads located in the first region 301. Figure 26 (not shown in the image) and multiple fourth data connection lines located in the third region 303 ( Figure 26(Not shown in the image); the second data lead layer includes multiple second data leads located in the first region 301 ( Figure 26 The diagram illustrates a second data lead-out line 52 and multiple fifth data connection lines located in the third region 303. Figure 26 The diagram shows a fifth data connection line 57. The second wiring layer includes multiple first data connection lines located in the first area 301. Figure 26 The diagram illustrates a first data connection line 53 and multiple third data connection lines located in the third region 303. Figure 26 The diagram shows a third data connection line 55. The third routing layer includes multiple second data connection lines ( Figure 26 The diagram illustrates a second data connection line 54. In this exemplary embodiment, by setting the orthographic projection of the first insulating layer on the substrate in the bending area to overlap with the orthographic projection of the edge of the second wiring layer near the display area on the substrate, it is beneficial to protect the first wiring layer in the bending area, thereby improving the corrosion resistance of the display substrate and thus extending the service life of the display substrate under extreme environments.

[0189] In some exemplary implementations, such as Figure 26 As shown, in a plane perpendicular to the display substrate, the second region 302 of the bending region 300 includes: a substrate 10, a composite insulating layer, a first planarization layer 16, a pixel definition layer 34, and an isolation pillar layer 41 sequentially disposed on the substrate 10. The composite insulating layer includes a barrier layer 18, a buffer layer 11, a first gate insulating layer 12, a second gate insulating layer 13, and an interlayer insulating layer 14 sequentially disposed on the substrate 10. The substrate 10 includes at least a flexible material layer. The second region 302 is provided with a first groove 311 and a second groove 312. The first groove 311 is formed by an EBA MASK process, in which the interlayer insulating layer 14, the second gate insulating layer 13, and the first gate insulating layer 12 within the first groove 311 are etched away, exposing the buffer layer 11. The second groove 312 is formed by an EBA MASK process, in which the second groove 312 is formed within the first groove 311, in which the buffer layer 11 and the barrier layer 18 within the second groove 312 are etched away, exposing the substrate 10. However, this embodiment is not limited thereto. In some examples, during the EBA MASK process, the interlayer insulating layer, the second gate insulating layer, the first gate insulating layer, and part of the buffer layer may be etched away. In this exemplary embodiment, both the second groove 312 and the first groove 11 are filled with a first planarization layer 16. The first planarization layer 16 can adjust the step thickness formed by the grooves by filling the first groove 311 and the second groove 312, thereby reducing the risk of the third trace layer breaking due to excessive step thickness formed by the grooves.

[0190] The structure of the display area 100 and other structures of the bent area 300 in this exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments, and therefore will not be repeated here.

[0191] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0192] Figure 27 This is another structural schematic diagram of the bending region of a display substrate according to at least one embodiment of the present disclosure. Figure 27 for Figure 1 A magnified view of a portion of region S in the middle. Figure 28 This is a plan view of the bent area after the second wiring layer pattern is formed in at least one embodiment of the present disclosure. Figure 29 This is a plan view of the bent area after the first insulating layer pattern is formed in at least one embodiment of the present disclosure.

[0193] In some exemplary implementations, such as Figures 27 to 29 As shown, in a plane parallel to the display substrate, the bending region 300 includes: multiple first data leads 51, multiple second data leads 52, multiple first data connection lines 53, multiple second data connection lines 54, multiple third data connection lines 55, multiple fourth data connection lines 56, and multiple fifth data connection lines 57. The multiple first data connection lines 53 are located in the first region 301 of the bending region 300 and are arranged in an alternating manner. The multiple third data connection lines 55 are located in the third region 303 of the bending region 300 and are arranged in an alternating manner. The multiple first data connection lines 53 are arranged in two rows, with the second row of first data connection lines 53 located on the side of the first row of first data connection lines 53 furthest from the display area, and the two rows of first data connection lines 53 are misaligned. The extension directions of the multiple first data connection lines 53 are parallel to each other and do not overlap, and the multiple first data connection lines 53 in each row are arranged sequentially along the direction perpendicular to the extension direction of the data connection lines. Multiple third data connection lines 55 are arranged in two rows. The second row of third data connection lines 55 is located on the side of the first row of third data connection lines 55 furthest from the display area, and the two rows of third data connection lines 55 are misaligned. The extension directions of the multiple third data connection lines 55 are parallel to each other and do not overlap. The multiple third data connection lines 55 in each row are arranged sequentially along the direction perpendicular to the extension direction of the data connection lines. For example... Figure 27 and 29As shown, the multiple first data connection lines 53 and multiple third data connection lines 55 in the bending region 300 overlap with the first insulating layer 16, but do not overlap with the inorganic insulating layer. The first insulating layer 16 has multiple first openings K7 in the first region 301 of the bending region 300 and multiple second openings K8 in the third region 303. A second data connection line 54 can be connected to a first data connection line 53 through three first openings K7 and to a third data connection line 55 through three second openings K8. However, this embodiment is not limited to this. In this exemplary embodiment, by arranging multiple first data connection lines in an alternating manner, the spacing between adjacent first data connection lines can be reduced, and the transmission interference between adjacent first data connection lines can be reduced, thereby improving signal transmission performance. By arranging multiple third data connection lines in an alternating manner, the spacing between adjacent third data connection lines can be reduced, and the transmission interference between adjacent third data connection lines can be reduced, thereby improving signal transmission performance.

[0194] The structure of the display area 100 and other structures of the bent area 300 in this exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments (e.g., with...). Figure 25 or Figure 26 The structure of the embodiments shown is similar, so it will not be described again here.

[0195] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0196] Figure 30 This is another structural schematic diagram of the bending region of a display substrate according to at least one embodiment of the present disclosure. Figure 30 for Figure 1 A magnified schematic diagram of a portion of region S. In some exemplary embodiments, such as... Figure 30As shown, in a plane parallel to the display substrate, the bending region 300 includes: multiple first data leads 51, multiple second data leads 52, multiple first data connection lines 53, multiple second data connection lines 54, multiple third data connection lines 55, multiple fourth data connection lines 56, and multiple fifth data connection lines 57. The multiple first data connection lines 53 are located in the first region 301 of the bending region 300 and are arranged in an alternating pattern. The multiple third data connection lines 55 are located in the third region 303 of the bending region 300 and are arranged in an alternating pattern. The multiple first data connection lines 53 are arranged in two rows, with the second row of first data connection lines 53 located on the side of the first row of first data connection lines 53 furthest from the display area, and the two rows of first data connection lines 53 are misaligned. The multiple third data connection lines 55 are arranged in two rows, with the second row of third data connection lines 55 located on the side of the first row of third data connection lines 55 furthest from the display area, and the two rows of third data connection lines 55 are misaligned. The inorganic insulating layer 15 has a first edge 151 and a second edge 152 in the bending region 300. The first edge 151 is located within the first region 301, and the second edge 152 is located within the third region 303. The inorganic insulating layer 15 between the first edge 151 and the second edge 152 is etched away. Both the first edge 151 and the second edge 152 are straight edges. The extension direction of the first edge 151 is parallel to the extension direction of the second edge 152. The first edge 151 covers the edge of the first row of first data connection lines 53 near the display area, and the second edge 152 covers the edge of the second row of third data connection lines 55 away from the display area.

[0197] The structure of the display area 100 and other structures of the bent area 300 in this exemplary embodiment are similar to the corresponding structures described in the foregoing embodiments (e.g., with...). Figure 2 , Figure 23 or Figure 24 The structure of the embodiments shown is similar, so it will not be described again here.

[0198] The structure of the display substrate in this exemplary embodiment is merely illustrative. In some exemplary embodiments, the corresponding structure can be modified according to actual needs. For example, multiple first data leads, multiple second data leads, multiple fourth data connection lines, and multiple fifth data connection lines can be disposed in the same layer as the first gate metal layer, or they can be disposed in the same layer as the second gate metal layer. Furthermore, the inorganic insulating layer can have a wavy structure at the first and second edges of the bending region. Also, the first edge of the inorganic insulating layer can cover the edges of the first row of first data connection lines and the second row of first data connection lines near the display area. Furthermore, the second edge of the inorganic insulating layer can cover the edges of the second row of third data connection lines and the first row of third data connection lines away from the display area. This embodiment is not limited in this respect.

[0199] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0200] Figure 31 This is another structural schematic diagram of the bending region of a display substrate according to at least one embodiment of the present disclosure. Figure 31 for Figure 1 A magnified view of a portion of region S in the middle. Figure 32 for Figure 1 Another cross-sectional view along the PP direction.

[0201] In some exemplary implementations, such as Figure 31 As shown, in a plane parallel to the display substrate, the bending region 300 includes: multiple first data leads 51, multiple second data leads 52, multiple first data connection lines 53, multiple fourth data connection lines 56, and multiple fifth data connection lines 57. The first data leads 51 are connected to a fourth data connection line 56 via a first data connection line 53, and the second data leads 52 are connected to a fifth data connection line 57 via a first data connection line 53. The inorganic insulating layer 15 has a first edge 151 and a second edge 152 in the bending region 300. A hollow area of ​​the inorganic insulating layer 15 is formed between the first edge 151 and the second edge 152. The first edge 151 of the inorganic insulating layer 15 is located in the first region 301 of the bending region 300, and the second edge 152 of the inorganic insulating layer 15 is located in the third region 303 of the bending region 300. The first edge 151 of the inorganic insulating layer 15 is in direct contact with multiple first data connection lines 53 and covers the edges of the multiple first data connection lines 53 near the display area 100. The second edge 152 covers the edges of the multiple first data connection lines 53 away from the display area. The first edge 151 of the inorganic insulating layer 15 has a first wave structure, which includes multiple spaced first notches 153. Each of the multiple first notches 153 corresponds to one of the multiple first data connection lines 53, and the orthographic projection of at least one first notch 153 on the substrate is located within the orthographic projection of the corresponding first data connection line 53 on the substrate. The second edge 152 of the inorganic insulating layer 15 has a second wave structure, which includes multiple spaced second notches 154. Each of the multiple second notches 154 corresponds to one of the multiple first data connection lines 53, and the orthographic projection of at least one second notch 154 on the substrate is located within the orthographic projection of the corresponding first data connection line 53 on the substrate.

[0202] In some exemplary implementations, such as Figure 32As shown, in a plane perpendicular to the display substrate, the display area 100 includes: a substrate 10, a driving structure layer disposed on the substrate 10, an inorganic insulating layer 15 disposed sequentially on the driving structure layer, a first planarization layer 16, a light-emitting element disposed on the first planarization layer 16, and an encapsulation layer 42 covering the light-emitting element. The driving structure layer of the display area 100 includes a plurality of transistors forming a pixel driving circuit and at least one storage capacitor. The pixel driving circuit can be designed as a 2T1C, 3T1C, or 7T1C. Figure 32 The illustration uses a first transistor and a first storage capacitor as an example. The first transistor can be a driving transistor. The driving structure layer of the display area 100 may include: a buffer layer 11 disposed on the substrate 10, an active layer disposed on the buffer layer 11, a first gate insulating layer 12 covering the active layer, a first gate metal layer disposed on the first gate insulating layer 12, a second gate insulating layer 13 covering the first gate metal layer, a second gate metal layer disposed on the second gate insulating layer 13, an interlayer insulating layer 14 covering the second gate metal layer, and a source / drain metal layer disposed on the interlayer insulating layer 14. The active layer may include at least a first active layer 21, the first gate metal layer may include at least a first gate electrode 22 and a first capacitor electrode 25, the second gate metal layer may include at least a second capacitor electrode 26, and the source / drain metal layer may include at least a first source electrode 23 and a first drain electrode 24. The first active layer 21, the first gate electrode 22, the first source electrode 23, and the first drain electrode 24 constitute the first transistor, and the first capacitor electrode 25 and the second capacitor electrode 26 constitute the first storage capacitor. The light-emitting element may include an anode 31, a pixel defining layer 34, an organic light-emitting layer 32, and a cathode 33. The anode 31 is connected to the first drain electrode 24 of the first transistor through vias formed in the first planarization layer 16 and the inorganic insulating layer 15. An isolation pillar layer 41 is provided on the side of the pixel defining layer 34 away from the substrate 10. In some examples, the encapsulation layer 42 may include a stacked inorganic encapsulation layer, an organic encapsulation layer, and an inorganic encapsulation layer. However, this embodiment is not limited to this.

[0203] In some exemplary implementations, such as Figure 32 As shown, in a plane perpendicular to the display substrate, the first region 301 of the bending region 300 includes: a substrate 10, a buffer layer 11, a first gate insulating layer 12, a first data lead-out layer, a second gate insulating layer 13, a second data lead-out layer, an interlayer insulating layer 14, a second wiring layer, an inorganic insulating layer 15, a first planarization layer 16, a pixel definition layer 34, and an isolation pillar layer 41, sequentially disposed on the substrate 10. The first data lead-out layer includes multiple first data leads ( Figure 32 (Not shown in the image), the second data lead layer includes multiple second data leads ( Figure 32 The diagram shows a second data lead-out line 52. The second routing layer includes multiple first data connection lines ( Figure 32 The diagram illustrates a first data connection line 53. The first data connection line 53 extends from the first region 301 through the second region 302 to the third region 303. The orthographic projection of the end of the first data connection line 53 near the display region 100 on the substrate 10 overlaps with the orthographic projection of a first data lead or a second data lead 52 on the substrate 10. The orthographic projection of the end of the first data connection line 53 away from the display region 100 on the substrate 10 overlaps with the orthographic projection of a fourth data connection line 56 or a fifth data connection line 57 on the substrate 10. The first edge 151 of the inorganic insulating layer 15 covers the edge of the first data connection line 53 near the display region 100, and the second edge 152 covers the edge of the first data connection line 53 away from the display region 100.

[0204] In some exemplary implementations, such as Figure 32 As shown, in a plane perpendicular to the display substrate, the second region 302 of the bending region 300 includes: a substrate 10, a composite insulating layer, a first planarization layer 16, a pixel definition layer 34, and an isolation pillar layer 41 sequentially disposed on the substrate 10. The composite insulating layer includes a buffer layer 11, a first gate insulating layer 12, a second gate insulating layer 13, and an interlayer insulating layer 14 sequentially disposed on the substrate 10. The composite insulating layer of the second region 302 has a first groove 311 and a second groove 312. The interlayer insulating layer 14 in the first groove 311 is etched away, and the interlayer insulating layer 14, the second gate insulating layer 13, the first gate insulating layer 12, and the buffer layer 11 in the second groove 312 are all etched away. The orthographic projection of the second groove 312 on the substrate 10 lies within the orthographic projection of the first groove 311 on the substrate 10. The first planarization layer 16, the pixel definition layer 34, and the isolation pillar layer 41 are sequentially disposed in the first groove 311 and the second groove 312.

[0205] In some exemplary implementations, such as Figure 32 As shown, in a plane perpendicular to the display substrate, the third region 303 of the bending region 300 includes: a substrate 10, a buffer layer 11, a first gate insulating layer 12, a first data lead-out layer, a second gate insulating layer 13, a second data lead-out layer, an interlayer insulating layer 14, a second wiring layer, an inorganic insulating layer 15, a first planarization layer 16, a pixel definition layer 34, and an isolation pillar layer 41, sequentially disposed on the substrate 10. The first data lead-out layer includes multiple fourth data connection lines (…). Figure 32 (Not shown in the image), the second data lead layer includes multiple fifth data connection lines ( Figure 32The diagram illustrates a fifth data connection line 57. In this exemplary embodiment, the structures within the first region 301 and the third region 303 of the bend region 300 are symmetrical to each other, and the axis of symmetry is perpendicular to the extension direction of the data connection line. However, this embodiment is not limited in this respect. In some examples, the structure within the third region of the bend region 300 may be different from or partially the same as the structure within the first region.

[0206] The structure and fabrication process of the display substrate in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and patterning processes can be modified and increased or decreased as needed. For example, multiple first data leads, multiple second data leads, multiple fourth data connection lines, and multiple fifth data connection lines can be disposed in the same layer as the first gate metal layer, or they can be disposed in the same layer as the second gate metal layer. Furthermore, the first and second edges of the inorganic insulating layer in the bending region can be straight edges. Also, the display substrate can be a top-emitting structure or a bottom-emitting structure. Furthermore, the driving transistor can be a top-gate structure or a bottom-gate structure; it can be a single-gate structure or a dual-gate structure. This embodiment is not limited in this respect. The structure (or method) shown in this embodiment can be appropriately combined with the structures (or methods) shown in other embodiments.

[0207] At least one embodiment of this disclosure also provides a method for fabricating a display substrate, comprising: providing a substrate, the substrate including a display area and a bent region located on one side of the display area; forming a plurality of sub-pixels and a plurality of data lines on the substrate in the display area, the plurality of data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; forming a first wiring layer on the substrate, the first wiring layer being partially disposed in the bent region and connected to the plurality of data lines; forming a second wiring layer on the side of the first wiring layer away from the substrate in the bent region, the second wiring layer being connected to the first wiring layer; and forming a first insulating layer on the side of the second wiring layer away from the substrate. The orthographic projections of the edges of the first insulating layer and the second wiring layer near the display area on the substrate overlap.

[0208] In some exemplary embodiments, forming a first wiring layer on a substrate includes: sequentially forming a first data lead layer and a second data lead layer that are mutually insulated from each other on the substrate. The first data lead layer includes a plurality of first data leads, and the second data lead layer includes a plurality of second data leads; at least one first data lead or second data lead is configured to be connected to a data line. The orthographic projections of the first data lead layer and the second data lead layer on the substrate do not overlap, and the first data leads and the second data leads are arranged at intervals.

[0209] In some exemplary embodiments, in the bending region, a second wiring layer is formed on the side of the first wiring layer away from the substrate, including: in the bending region, forming a plurality of parallel and insulated first data connection lines on the side of the first wiring layer away from the substrate, at least one of the first data connection lines being connected to a first data lead or a second data lead.

[0210] In some exemplary embodiments, the fabrication method of this embodiment further includes: forming an inorganic insulating layer on the side of the second wiring layer away from the substrate, the inorganic insulating layer being located between the second wiring layer and the first insulating layer. The inorganic insulating layer includes a first edge in the bending region, and the first edge of the inorganic insulating layer overlaps with the orthographic projection of the edge of the second wiring layer near the display area onto the substrate.

[0211] In some exemplary embodiments, the fabrication method of this embodiment further includes: forming a third wiring layer on the side of the inorganic insulating layer away from the substrate in the bending region. The third wiring layer includes a plurality of second data connection lines. Specifically, forming the second wiring layer on the side of the first wiring layer away from the substrate in the bending region includes: forming a plurality of first data connection lines and a plurality of third data connection lines on the side of the first wiring layer away from the substrate in the bending region. The plurality of third data connection lines are located on the side of the plurality of first data connection lines away from the display area. At least one first data connection line is connected to a first data lead or a second data lead, and both ends of at least one second data connection line are respectively connected to a first data connection line and a third data connection line.

[0212] In some exemplary embodiments, the first data lead-out layer further includes multiple fourth data connection lines, and the second data lead-out layer further includes multiple fifth data connection lines. The multiple fourth data connection lines are located on the side of the multiple first data lead-out lines furthest from the display area, and at least one fourth data connection line is connected to a first data lead-out line via a third data connection line, a second data connection line, and a first data connection line. The multiple fifth data connection lines are located on the side of the multiple second data lead-out lines furthest from the display area, and at least one fifth data connection line is connected to a second data lead-out line via a third data connection line, a second data connection line, and a first data connection line.

[0213] In some exemplary embodiments, the fabrication method of this embodiment further includes: forming an active layer on a substrate of the display area; forming a first gate metal layer in the display area while forming a first data lead-out layer; forming a second gate metal layer in the display area while forming a second data lead-out layer; forming a source / drain electrode layer in the display area while forming a second wiring layer in the bending region; forming a metal conductive layer in the display area while forming a third wiring layer in the bending region; and forming a light-emitting element in the display area. The light-emitting element is connected to the source / drain electrode layer through the metal conductive layer.

[0214] The preparation method of this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0215] Figure 33 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 33 As shown, this embodiment provides a display device 91, including a display substrate 910. The display substrate 910 is the display substrate provided in the aforementioned embodiment. The display substrate 910 can be an OLED display substrate. The display device 91 can be any product or component with display function, such as an OLED display device, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0216] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure and features thereof can be combined to obtain new embodiments.

[0217] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate comprising: a substrate, comprising a display area and a bending area located at one side of the display area; a plurality of sub-pixels located in the display area; a plurality of data lines located in the display area and electrically connected to the plurality of sub-pixels, the plurality of data lines configured to provide data signals to the plurality of sub-pixels; a first trace layer partially disposed in the bending area of the substrate, the first trace layer connected to the plurality of data lines; a second trace layer located in the bending area and disposed on a side of the first trace layer away from the substrate, the second trace layer connected to the first trace layer; a first insulating layer disposed on a side of the second trace layer away from the substrate, a projection of the first insulating layer and the second trace layer on the substrate overlapping at an edge of the display area; an inorganic insulating layer located between the second trace layer and the first insulating layer, the inorganic insulating layer comprising a first edge in the bending area, the first edge of the inorganic insulating layer and the projection of the second trace layer on the substrate overlapping at the edge of the display area; the first trace layer comprising a plurality of data lead-out lines, the plurality of data lead-out lines one-to-one corresponding to the plurality of data lines; the second trace layer comprising a plurality of first data connection lines, the plurality of first data connection lines one-to-one corresponding to the plurality of data lead-out lines; the first edge provided with a first wave structure, the first wave structure comprising a plurality of first notches arranged at intervals, the plurality of first notches one-to-one corresponding to the plurality of first data connection lines, a projection of one first notch on the substrate located within a projection of a corresponding first data connection line on the substrate. 2.The display substrate of claim 1, wherein, at least part of the first insulating layer directly contacts the second trace layer. 3.The display substrate of claim 2, wherein, the plurality of first data connection lines of the second trace layer are arranged alternately. 4.The display substrate of claim 1, further comprising: a third trace layer located in the bending area and disposed on a side of the first insulating layer away from the substrate; the third trace layer comprising a plurality of second data connection lines, the plurality of second data connection lines one-to-one corresponding to the plurality of first data connection lines of the second trace layer; at least one second data connection line of the plurality of second data connection lines partially overlaps with a corresponding first data connection line on the substrate. 5.The display substrate of claim 4, wherein, at least one second data connection line of the plurality of second data connection lines has at least one hole. 6.The display substrate of claim 5, wherein, the at least one hole is a circular hole or an elliptical hole. 7.The display substrate of claim 4, wherein, the second trace layer further comprising a plurality of third data connection lines; the plurality of third data connection lines located on a side of the plurality of first data connection lines away from the display area, the plurality of third data connection lines one-to-one corresponding to the plurality of second data connection lines; both ends of at least one second data connection line of the plurality of second data connection lines are connected to a first data connection line and a third data connection line, respectively. 8.The display substrate of claim 7, wherein, the plurality of third data connection lines of the second trace layer are arranged alternately. 9.The display substrate of claim 7, wherein, The inorganic insulating layer further comprises a second edge located on a side of the first edge away from the display region, and a hollow region of the inorganic insulating layer is formed between the first edge and the second edge of the inorganic insulating layer; The second edge of the inorganic insulating layer is in direct contact with at least one third data connection line of the second trace layer, and the second edge covers an edge of the third data connection line away from the display region. 10.The display substrate of claim 9, wherein, The second edge of the inorganic insulating layer is provided with a second wave structure comprising a plurality of second notches arranged at intervals; The orthographic projection of at least one second notch in the plurality of second notches on the substrate substrate is located within the orthographic projection of the corresponding third data connection line on the substrate substrate. 11.The display substrate of claim 1, wherein, The first edge of the inorganic insulating layer is in direct contact with at least one first data connection line of the second trace layer, and covers an edge of the first data connection line close to the display region. 12.The display substrate of claim 1, wherein, In the bending region, along the direction from the bending region to the display region, the distance between the first edge of the inorganic insulating layer and the edge of the second trace layer covered by the first edge is greater than or equal to 5 microns. 13.The display substrate of claim 2, wherein, The first insulating layer comprises a plurality of first openings in the bending region; The orthographic projection of at least one first data connection line in the plurality of first data connection lines on the substrate substrate comprises the orthographic projection of at least one first opening on the substrate substrate. 14.The display substrate according to any one of claims 1-3, wherein, The first trace layer comprises: a first data lead-out layer and a second data lead-out layer arranged in sequence on the substrate substrate and insulated from each other; the first data lead-out layer comprises a plurality of first data lead-outs, and the second data lead-out layer comprises a plurality of second data lead-outs; The orthographic projection of the first data lead-out layer and the second data lead-out layer on the substrate substrate does not overlap, and the first data lead-out and the second data lead-out are arranged at intervals. 15.The display substrate of claim 14, wherein, The first data lead-out layer further comprises: a plurality of fourth data connection lines located on a side of the plurality of first data lead-outs away from the display region, and the plurality of fourth data connection lines are connected to the plurality of first data lead-outs one by one at least through the second trace layer; The second data lead-out layer further comprises a plurality of fifth data connection lines, the plurality of fifth data connection lines are located on a side of the plurality of second data lead-outs away from the display region, and the plurality of fifth data connection lines are connected to the plurality of second data lead-outs one by one at least through the second trace layer. 16.The display substrate of claim 14, wherein, The display region comprises at least: a driving structure layer arranged on the substrate substrate, and a light emitting element arranged on the driving structure layer; the light emitting element is connected with the driving structure layer; The driving structure layer comprises an active layer, a first gate metal layer, a second gate metal layer and a source-drain electrode layer arranged in sequence on the substrate substrate; The first data lead-out line layer and the first gate metal layer are in a same layer structure, the second data lead-out line layer and the second gate metal layer are in a same layer structure, and the second trace layer and the source-drain electrode layer are in a same layer structure.

17. The display substrate of any one of claims 1-3, wherein, The bending area comprises a first area, a second area and a third area arranged in sequence along a direction away from the display area; the second area comprises a composite insulating layer arranged between the substrate and the second trace layer; the composite insulating layer has a first groove and a second groove in communication; a normal projection of the first groove on the substrate contains a normal projection of the second groove on the substrate. 18.The display substrate of claim 17, wherein, The composite insulating layer comprises a blocking layer, a buffer layer, a first gate insulating layer, a second gate insulating layer and an interlayer insulating layer stacked on the substrate; the first groove exposes the buffer layer, and the second groove exposes the substrate.

19. The display substrate of claim 17, wherein, The first insulating layer is filled at least in the second groove. 20.The display substrate of claim 17, wherein, The first insulating layer fills the first groove and the second groove.

21. The display substrate of any one of claims 1-3, wherein, The first insulating layer is an organic insulating layer.

22. A display device comprising the display substrate according to any one of claims 1 to 21.

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