Method for manufacturing metal gate and method for manufacturing CMOS device

Abstract

The application discloses a preparation method of a metal gate and a preparation method of a CMOS device. The P-type metal work function layer located outside a PMOS region pseudo gate trench and at least a notch in the PMOS region pseudo gate trench is removed, so that the width of the PMOS region pseudo gate trench at least the notch is increased, and the top height of the PMOS region pseudo gate trench is also reduced, thereby greatly reducing the aspect ratio of the PMOS region pseudo gate trench, mainly reducing the aspect ratio of the notch of the PMOS region pseudo gate trench, and then when filling metal into the PMOS region pseudo gate trench as a metal gate electrode layer, it is not easy to cause a void due to overhanging at the top of the PMOS region pseudo gate trench, that is, the filling effect of filling metal into the PMOS region pseudo gate trench is improved, which greatly increases the reliability of the CMOS device and improves the yield of the CMOS device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular, to a preparation method of a metal gate and a preparation method of a CMOS device. BACKGROUND

[0002] With the rapid development of Ultra Large Scale Integrate (ULSI), the critical dimension (CD) of core devices is also continuously reduced in proportion, so that more transistors can be placed on a silicon chip, but at the same time, it will inevitably bring unprecedented challenges to the manufacturing process of integrated circuits.

[0003] Step coverage is an important parameter in the deposition process of integrated circuits. The ideal step coverage refers to the uniform thickness of the film in all directions on the surface of the silicon wafer, also known as conformal step coverage, as shown in Fig. 1(a). However, in the actual process, if the aspect ratio of the trench is relatively large, combined with the non-directional sputtering of the physical vapor deposition process (PVD) itself, it will lead to poor step coverage, so that the deposited material appears uneven thickness at the sharp corners of the top of the trench and the sidewall and bottom of the trench, as shown in Fig. 1(b), which may cause "overhanging" at the top of the trench due to the shadow effect, or even premature sealing at the top to form a void in the trench, as shown in Fig. 1(c), which will greatly affect the reliability and yield of the device.

[0004] For existing CMOS devices, a metal gate is usually prepared by a gate last process. Specifically, a dummy gate is first formed, and then after forming a source region and a drain region and subsequent high-temperature annealing, the dummy gate is removed to form a dummy gate trench, and then a metal gate is prepared in the dummy gate trench. However, when filling metal into the dummy gate trench of the PMOS device and the dummy gate trench of the NMOS device to form a metal gate electrode layer, the PMOS device is more likely to have "overhanging" at the top of its dummy gate trench, or even premature sealing and breaking, thereby producing a void in its dummy gate trench, as shown in Fig. 1(c), which will increase the resistance of the metal gate of the PMOS device, resulting in a decrease in the on-current of the PMOS device. Therefore, how to improve the filling effect of filling metal into the dummy gate trench of the PMOS device has become a technical problem to be solved by those skilled in the art. SUMMARY

[0005] To solve the above technical problems, the present application provides a preparation method of a metal gate and a preparation method of a CMOS device to improve the filling effect of filling metal into the dummy gate trench of the PMOS device.

[0006] To achieve the above object, the embodiment of the present application provides the following technical scheme.

[0007] A preparation method of a metal gate electrode, comprising:

[0008] providing a substrate, the substrate comprising an NMOS region and a PMOS region, the NMOS region and the PMOS region each having a dummy gate trench;

[0009] forming, in sequence, an oxidation interface layer, a high dielectric constant dielectric layer, a cover layer, a barrier layer and a P-type metal work function layer on a side of the substrate having the dummy gate trench;

[0010] removing the P-type metal work function layer corresponding to the NMOS region;

[0011] forming a mask layer on a side of the barrier layer of the NMOS region facing away from the substrate and on a side of the P-type metal work function layer of the PMOS region facing away from the substrate;

[0012] removing the mask layer from outside the dummy gate trench of the PMOS region and at least the notch of the dummy gate trench of the PMOS region, and retaining at least the mask layer at the bottom of the dummy gate trench of the PMOS region;

[0013] removing the P-type metal work function layer not covered by the mask layer;

[0014] removing the remaining mask layer;

[0015] depositing an N-type metal work function layer and an adhesion layer;

[0016] filling the dummy gate trench with metal as a metal gate electrode layer to form a metal gate electrode.

[0017] Optionally, the mask layer comprises a silicon-containing anti-reflective layer (Si-ARC layer).

[0018] Optionally, forming the mask layer on the side of the barrier layer of the NMOS region facing away from the substrate and on the side of the P-type metal work function layer of the PMOS region facing away from the substrate comprises:

[0019] forming the mask layer on the side of the barrier layer of the NMOS region facing away from the substrate and on the side of the P-type metal work function layer of the PMOS region facing away from the substrate by a spin coating process.

[0020] Optionally, removing the mask layer from outside the dummy gate trench of the PMOS region and at least the notch of the dummy gate trench of the PMOS region comprises:

[0021] removing the mask layer outside the dummy gate trench in the PMOS region and at least the notch inside the dummy gate trench in the PMOS region by a selective lithography and etch back process;

[0022] wherein, when performing the selective lithography and etch back process, the etching gas used includes a mixture of nitrogen trifluoride and hydrogen, and the concentration of the nitrogen trifluoride is a preset concentration.

[0023] Optionally, removing the P-type metal work function layer not covered by the mask layer includes:

[0024] removing the P-type metal work function layer not covered by the mask layer by a first wet etching process;

[0025] wherein, when performing the first wet etching process, the solution used is a mixed solution of ammonia, hydrogen peroxide and water, and the required temperature value ranges from 49.5 degrees Celsius to 50.5 degrees Celsius, inclusive.

[0026] Optionally, removing the remaining mask layer includes:

[0027] removing the remaining mask layer by a second wet etching process;

[0028] wherein, when performing the second wet etching process, the solution used is a 5% tetramethylammonium hydroxide solution.

[0029] Optionally, filling the dummy gate trench with metal as a metal gate electrode layer includes:

[0030] filling the dummy gate trench with metal as a metal gate electrode layer by a physical vapor deposition process, or a chemical vapor deposition process, or an atomic layer epitaxy process.

[0031] Optionally, the high dielectric constant dielectric layer includes a hafnium dioxide layer (HfO2 layer);

[0032] the oxide interface layer includes a silicon dioxide layer (SiO2 layer);

[0033] the capping layer includes a titanium nitride layer (TiN layer);

[0034] the barrier layer includes a tantalum nitride layer (TaN layer).

[0035] A method for manufacturing a CMOS device includes:

[0036] providing a substrate;

[0037] performing a shallow trench isolation on the substrate, the shallow trench isolation dividing the substrate into a first part and a second part;

[0038] forming a dummy gate structure on the first part and the second part of the substrate respectively, the dummy gate structure comprising a dummy gate on the surface of the substrate, a protection layer covering the dummy gate away from the surface of the substrate, and a first sidewall on both sides of the dummy gate;

[0039] forming a lightly doped source region and a lightly doped drain region on the substrate on both sides of the dummy gate structure respectively;

[0040] forming a second sidewall on both sides of the dummy gate structure, the second sidewall covering part of the lightly doped source region and part of the lightly doped drain region;

[0041] heavily doping the lightly doped source region and the lightly doped drain region respectively, and forming a metal silicide on the heavily doped source region and the heavily doped drain region respectively;

[0042] forming an interlayer dielectric layer outside the second sidewall, and performing chemical mechanical polishing to remove the protection layer covering the dummy gate away from the surface of the substrate, and open the dummy gate;

[0043] removing the dummy gate to form a dummy gate trench, thus obtaining a substrate, wherein the substrate corresponds to an NMOS region in the first part of the substrate, and the substrate corresponds to a PMOS region in the second part of the substrate, and the NMOS region and the PMOS region have the dummy gate trench respectively;

[0044] based on the substrate, using the preparation method of the metal gate in any one of the above technical solutions to prepare a metal gate, and forming a CMOS device.

[0045] Optionally, the substrate comprises an SOI substrate.

[0046] Compared with the prior art, the above technical solution has the following advantages:

[0047] The preparation method of the metal gate provided in the embodiments of the present application firstly forms, on the side of the substrate having the dummy gate trench, an oxidation interface layer, a high dielectric constant dielectric layer, a cover layer, a barrier layer and a P-type metal work function layer in sequence, and forms a mask layer after removing the P-type metal work function layer corresponding to the NMOS region; then, the mask layer is removed from the PMOS region dummy gate trench outside and at least the slot opening in the PMOS region dummy gate trench, and at least the mask layer at the bottom of the PMOS region dummy gate trench is reserved; secondly, the P-type metal work function layer not covered by the mask layer and the remaining mask layer are removed; finally, an N-type metal work function layer and an adhesion layer are deposited, and the metal is filled into the dummy gate trench as a metal gate electrode layer, so as to form a metal gate. As can be seen, the preparation method of the metal gate provided in the embodiments of the present application removes the P-type metal work function layer located outside the PMOS region dummy gate trench and at least the slot opening in the PMOS region dummy gate trench, so that the width of at least the slot opening in the PMOS region dummy gate trench is increased, and the height of the top of the PMOS region dummy gate trench is also reduced, thereby greatly reducing the aspect ratio of the PMOS region dummy gate trench, mainly reducing the aspect ratio of the slot opening in the PMOS region dummy gate trench, and then when the metal is filled into the PMOS region dummy gate trench as a metal gate electrode layer, it is not easy to cause overhanging at the top of the PMOS region dummy gate trench to form a cavity, that is, the filling effect of filling the metal into the PMOS region dummy gate trench is improved, which greatly increases the reliability of the CMOS device and improves the yield of the CMOS device. BRIEF DESCRIPTION OF DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present application, and other accompanying drawings can be obtained by those skilled in the art without any creative effort on the basis of these accompanying drawings.

[0049] Fig. 1(a) is a schematic diagram of ideal step coverage;

[0050] Fig. 1(b) and Fig. 1(c) are schematic diagrams of non-ideal step coverage, wherein Fig. 1(c) is a schematic diagram of overhanging at the top of the trench and forming a cavity inside the trench;

[0051] Figure 2 Fig. 2 is a schematic diagram of the CMOS device structure after the metal gate is prepared by using the prior method;

[0052] Figure 3 Fig. 3 is a schematic diagram of the flow of the preparation method of the metal gate provided in the embodiments of the present application;

[0053] Figures 4(a)-4(i)The device structure schematic diagram corresponding to each step of the preparation method of the metal gate provided in the embodiments of the present application;

[0054] Figure 5 The flowchart of the preparation method of the CMOS device provided in the embodiments of the present application;

[0055] Figures 6(a)-6(k) The device structure schematic diagram corresponding to each step of the preparation method of the CMOS device provided in the embodiments of the present application. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0057] In the following description, a large number of specific details are set forth in order to facilitate a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and a person of ordinary skill in the art can make similar generalizations without departing from the connotation of the present application, therefore the present application is not limited by the specific embodiments disclosed below.

[0058] Secondly, the present application is described in detail in combination with the schematic diagram, and in the detailed description of the embodiments of the present application, for the convenience of description, the cross-sectional view showing the device structure will be partially enlarged without the general proportion, and the schematic diagram is only an example, which should not limit the protection scope of the present application herein. In addition, the three-dimensional spatial dimensions of length, width and depth should be included in the actual manufacturing.

[0059] As described in the background section, how to improve the filling effect of filling metal into the pseudo-gate trench of the PMOS device becomes a technical problem to be solved by a person of ordinary skill in the art.

[0060] The inventor has found that for the existing CMOS device, when the metal gate is prepared by using the back-gate process, specifically, referring to Figure 2As shown, after the dummy gate is removed to form the dummy gate trench 001, an interlayer 002, a high dielectric constant dielectric layer 003, a titanium nitride cover layer 004, a tantalum nitride barrier layer 005, and a P-type metal work function layer 006 are sequentially formed, then the NMOS region is opened by using a photolithography technology, and the P-type metal work function layer 006 in the NMOS region is etched away by using a chemical reagent, then an N-type metal work function layer 007 and a TiN adhesion layer 008 are deposited, finally, an aluminum metal 009 is filled into the dummy gate trench 001 as a metal gate electrode layer by using a physical vapor deposition (PVD) technology, and the excess aluminum metal 009 is removed by using a chemical mechanical polishing (CMP) process, thereby forming the metal gate of the NMOS device and the metal gate of the PMOS device. As can be seen, referring to Figure 2 As shown, the area outside the dummy gate trench 001 and the area inside the dummy gate trench 001 of the NMOS region (indicated by the dashed line circle) sequentially include, from bottom to top, the interlayer 002, the high dielectric constant dielectric layer 003, the titanium nitride cover layer 004, the tantalum nitride barrier layer 005, the N-type metal work function layer 007, and the TiN adhesion layer 008, while the area outside the dummy gate trench 001 and the area inside the dummy gate trench 001 of the PMOS region (indicated by the solid line circle) sequentially include, from bottom to top, the interlayer 002, the high dielectric constant dielectric layer 003, the titanium nitride cover layer 004, the tantalum nitride barrier layer 005, the P-type metal work function layer 006, the N-type metal work function layer 007, and the TiN adhesion layer 008. Figure 2 Figure 2 As can be seen, the PMOS device has more layers deposited in the dummy gate trench than the NMOS device, and the number of the extra layers is the P-type metal work function layer 006. Therefore, the aspect ratio of the dummy gate trench of the PMOS device is larger than that of the dummy gate trench of the NMOS device, so that when the metal is filled into the dummy gate trench of the PMOS device and the dummy gate trench of the NMOS device to form the metal gate electrode layer, the PMOS device is more likely to have a "hanging" on the top of the dummy gate trench, even to be prematurely sealed and broken, and further to have a cavity in the dummy gate trench, which increases the resistance of the metal gate of the PMOS device and reduces the on-current of the PMOS device.

[0061] Therefore, the embodiment of the present application provides a preparation method of a metal gate, as shown in the figure, which comprises the following steps.

[0062] Therefore, the embodiment of the present application provides a preparation method of a metal gate, as shown in the figure, which comprises the following steps. Figure 3

[0063] ​​S1: A substrate 100 is provided, as shown in FIG4(a), the substrate including an NMOS region 110 and a PMOS region 120, the NMOS region 110 and the PMOS region 120 respectively having a pseudo-gate trench 130.

[0064] S2: An oxide interface layer 140, a high dielectric constant dielectric layer 150, a capping layer 160, a barrier layer 170, and a P-type metal work function layer 180 are sequentially formed on the side of the substrate 100 with the pseudo-gate trench 130, resulting in the structural schematic diagram shown in Figure 4(b).

[0065] It should be noted that in the structural schematic diagram shown in Figure 4(b), the stack composed of the oxide interface layer 140, the high dielectric constant dielectric layer 150, the capping layer 160, and the barrier layer 170 is presented as the first stack 190, and Figure 6 shows an enlarged schematic diagram of the first stack 190.

[0066] Optionally, the oxide interface layer 140 includes a silicon dioxide layer (SiO2 layer);

[0067] The high dielectric constant dielectric layer 150 includes a hafnium dioxide layer, i.e., an HfO2 layer;

[0068] The capping layer 160 includes a titanium nitride layer, i.e., a TiN layer;

[0069] The barrier layer 170 includes a tantalum nitride layer, i.e., a TaN layer.

[0070] It should be noted that the substrate typically includes a silicon substrate. Since the high dielectric constant dielectric layer 150 (such as an HfO2 layer) is prone to poor compatibility with the silicon substrate and will significantly reduce the carrier mobility of the silicon substrate, the oxide interface layer 140 is used to isolate the high dielectric constant dielectric layer 150 and the silicon substrate in the substrate.

[0071] Similarly, the capping layer 160 and the barrier layer 170 also serve the same purpose, namely, to isolate the high dielectric constant dielectric layer 150 from the P-type metal work function layer 180 subsequently deposited on the high dielectric constant dielectric layer 150.

[0072] S3: Remove the P-type metal work function layer 180 corresponding to the NMOS region 110 to obtain the structural schematic diagram shown in Figure 4(c).

[0073] It should be noted that since the P-type metal work function layer 180 only determines the work function difference between the metal and semiconductor in the PMOS device, and thus determines the threshold voltage of the PMOS device, in step S3, the P-type metal work function layer 180 corresponding to the NMOS region is removed, and only the P-type metal work function layer 180 corresponding to the PMOS region is retained.

[0074] S4: Forming a mask layer 200 on the side of the barrier layer 170 of the NMOS region 110 away from the substrate (i.e. the side of the first stack 190 of the NMOS region 110 away from the substrate) and the side of the P-type metal work function layer 180 of the PMOS region 120 away from the substrate, obtaining a structure diagram as shown in Fig. 4(d).

[0075] Specifically, the mask layer 200 includes a silicon-containing anti-reflective layer, i.e. a Si-ARC layer (Silicon Containing Anti-Reflective Coating, Si-ARC for short).

[0076] It should be noted that the Si-ARC layer is an insulating layer rich in Si (the Si content can be greater than 40%), and as the Si content of the Si-ARC layer increases, the Si-ARC layer often has excellent performance in resisting oxide corrosion, because the silanol functional group Si-O-H in the Si-ARC material crosslinks to form a silicon-based ether network structure, which makes the Si-ARC material not easy to be stripped.

[0077] Since the Si-ARC material is in a liquid state under normal conditions, the Si-ARC layer can be filled into the trench by a spin coating process, so that the Si-ARC material has great advantages when filling a trench with high aspect ratio. In view of this, forming the mask layer 200 on the side of the barrier layer 170 of the NMOS region 110 away from the substrate and the side of the P-type metal work function layer 180 of the PMOS region 120 away from the substrate includes:

[0078] The mask layer 200 is formed on the side of the barrier layer 170 of the NMOS region 110 away from the substrate and the side of the P-type metal work function layer 180 of the PMOS region 120 away from the substrate by a spin coating process.

[0079] S5: Removing the mask layer outside the dummy gate trench of the PMOS region 120 and at least the notch in the dummy gate trench of the PMOS region 120, and retaining at least the mask layer at the bottom of the dummy gate trench of the PMOS region, obtaining a structure diagram as shown in Fig. 4(e).

[0080] Specifically, removing the mask layer outside the dummy gate trench of the PMOS region 120 and at least the notch in the dummy gate trench of the PMOS region 120 includes:

[0081] The mask layer outside the dummy gate trench of the PMOS region 120 and at least the notch in the dummy gate trench of the PMOS region 120 is removed by a selective lithography and etching back process;

[0082] In the selective photoetching and etching-back process, the etching gas used includes a mixture of nitrogen trifluoride and hydrogen, and the concentration of the nitrogen trifluoride is a preset concentration.

[0083] It should be noted that in the etching of the mask layer 200 outside the pseudo-gate trench of the PMOS region 120 and at least the opening of the pseudo-gate trench of the PMOS region 120 using the mixture of nitrogen trifluoride and hydrogen, the concentration of the nitrogen trifluoride needs to be controlled. If the concentration of the nitrogen trifluoride is too low, the etching rate will be slow or the etching will not work at all. However, the application does not limit the concentration of the nitrogen trifluoride, which can be determined according to the etching rate and other etching requirements.

[0084] S6: removing the P-type metal work function layer 180 not covered by the mask layer 200 to obtain the structure shown in FIG. 4(f).

[0085] Specifically, removing the P-type metal work function layer 180 not covered by the mask layer 200 includes:

[0086] removing the P-type metal work function layer 180 not covered by the mask layer 200 by a first wet etching process;

[0087] In the first wet etching process, the solution used is a mixture of ammonia, hydrogen peroxide and water, and the required temperature is in the range of 49.5 to 50.5 degrees Celsius, inclusive.

[0088] It should be noted that since the Si-ARC mask layer 200 has strong resistance to oxide corrosion, in step S6, the P-type metal work function layer 180 not covered by the Si-ARC mask layer 200 can be well protected when the P-type metal work function layer 180 not covered by the Si-ARC mask layer 200 is removed using the mixture of ammonia, hydrogen peroxide and water, i.e., the remaining P-type metal work function layer 180 in the pseudo-gate trench of the PMOS region 120 is well protected.

[0089] It should also be noted that in step S6, the P-type metal work function layer 180 not covered by the mask layer 200, i.e., the P-type metal work function layer 180 outside the pseudo-gate trench of the PMOS region 120 and at least the opening of the pseudo-gate trench of the PMOS region 120, is removed, while at least the P-type metal work function layer 180 at the bottom of the pseudo-gate trench of the PMOS region 120 is retained, so that the metal-semiconductor work function difference of the PMOS device remains unchanged, and thus the threshold voltage of the PMOS device remains unchanged.

[0090] It is to be noted that in step S6, the P-type metal work function layer 180 outside the dummy gate trench of the PMOS region 120 is removed, so that the height of the top of the dummy gate trench of the PMOS region is reduced; at the same time, the P-type metal work function layer 180 at least at the notch of the dummy gate trench of the PMOS region 120 is removed, so that the width of the dummy gate trench of the PMOS region 120 at least at the notch is increased. Since when the metal gate electrode layer is formed by filling the metal into the dummy gate trench of the PMOS region 120, the overhanging is prone to occur at the notch of the dummy gate trench of the PMOS region 120, even the early seal is prone to occur, and then the cavity is formed in the dummy gate trench, therefore, in step S5, the mask layer outside the dummy gate trench of the PMOS region 120 and at least at the notch of the dummy gate trench of the PMOS region 120 is removed, and then in step S6, the P-type metal work function layer 180 outside the dummy gate trench of the PMOS region 120 and at least at the notch of the dummy gate trench of the PMOS region 120 which is not covered by the mask layer 200 is removed, so that the width of the dummy gate trench of the PMOS region at least at the notch is increased, and the height of the top of the dummy gate trench of the PMOS region is also reduced, thereby greatly reducing the aspect ratio of the dummy gate trench of the PMOS region, mainly reducing the aspect ratio of the notch of the dummy gate trench of the PMOS region.

[0091] Wherein, how much of the P-type metal work function layer 180 on the sidewall of the dummy gate trench of the PMOS region 120 is reserved depends on the specific circumstances, optionally, only the P-type metal work function layer 180 on the sidewall corresponding to the notch of the dummy gate trench of the PMOS region 120 can be removed; the P-type metal work function layer 180 on the sidewall of the dummy gate trench of the PMOS region 120 can also be removed; the P-type metal work function layer 180 on the sidewall of the dummy gate trench of the PMOS region 120 can also be partially removed, but at least the P-type metal work function layer 180 on the sidewall corresponding to the notch of the dummy gate trench of the PMOS region 120 is removed, and at least the P-type metal work function layer 180 at the bottom of the dummy gate trench of the PMOS region 120 is reserved.

[0092] And, how much of the P-type metal work function layer 180 on the sidewall of the dummy gate trench of the PMOS region 120 is reserved can be determined by adjusting the thickness of the mask layer 200 reserved in the dummy gate trench of the PMOS region 120 in step S5, that is, the smaller the thickness of the mask layer 200 reserved in the dummy gate trench of the PMOS region 120, the less the P-type metal work function layer 180 reserved on the sidewall of the dummy gate trench of the PMOS region 120, and the farther the distance between the P-type metal work function layer 180 reserved on the sidewall of the dummy gate trench of the PMOS region 120 and the notch of the dummy gate trench.

[0093] S7: removing the remaining mask layer 200 to obtain the structure diagram as shown in Fig. 4(g).

[0094] Specifically, removing the remaining mask layer 200 includes:

[0095] removing the remaining mask layer 200 by a second wet etching process;

[0096] Wherein, when performing the second wet etching process, the solution used is a 5% concentration of tetramethylammonium hydroxide solution.

[0097] It should be noted that the remaining mask layer 200 includes the mask layer 200 of the NMOS region 110 and the mask layer 200 in the pseudo gate trench of the PMOS region 120. Since the etching selectivity ratio of the 5% concentration of tetramethylammonium hydroxide (TMAH) solution to the Si-ARC mask layer 200 rich in Si will be relatively high, the Si-ARC mask layer 200 remaining in the deep pseudo gate trench of the PMOS region 120 will be removed without damaging the substrate bottom material, which has an advantage that cannot be compared with general solutions.

[0098] S8: depositing an N-type metal work function layer 210 and an adhesion layer 220 to obtain the structure diagram as shown in Fig. 4(h).

[0099] It should be noted that the N-type metal work function layer 210 and the adhesion layer 220 in Fig. 4(h) are presented as a second stack layer 230, and an enlarged schematic diagram of the second stack layer 230 is given in Fig. 4(h).

[0100] Specifically, the adhesion layer 220 can be a TiN layer or a mixed layer of TiN / Ti, used to increase the adhesion of the metal filled in the pseudo gate trench later and the N-type metal work function layer 210.

[0101] It should be noted that the N-type metal work function layer 210 is located in the pseudo gate trench of the NMOS region 110 to adjust the threshold voltage of the NMOS device, and is also located in the pseudo gate trench of the PMOS region 120 to adjust the threshold voltage of the PMOS device.

[0102] S9: filling metal into the pseudo gate trench as a metal gate electrode layer 240 to form a metal gate, to obtain the structure diagram as shown in Fig. 4(i).

[0103] Optionally, aluminum metal is filled into the pseudo gate trench as a metal gate electrode layer.

[0104] Specifically, filling metal into the pseudo gate trench as a metal gate electrode layer includes:

[0105] The metal is filled into the dummy gate trench as a metal gate electrode layer by a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process, or an atom layer deposition (ALD) process.

[0106] In addition, in the actual process, the excessive metal is removed by a chemical mechanical grinding (CMP) process, and a back-end metal interconnection process and a wafer acceptable test (WAT) process, which are not described herein.

[0107] Therefore, the method for manufacturing the metal gate electrode provided in the embodiments of the present application removes the P-type metal work function layer outside the PMOS region dummy gate trench and at least the trench opening in the PMOS region dummy gate trench, increases the width of the PMOS region dummy gate trench at least at the trench opening, and reduces the height of the top of the PMOS region dummy gate trench, thereby greatly reducing the aspect ratio of the PMOS region dummy gate trench, mainly reducing the aspect ratio of the trench opening of the PMOS region dummy gate trench, and further preventing the metal from being filled into the PMOS region dummy gate trench as the metal gate electrode layer from being suspended at the top of the PMOS region dummy gate trench to form a cavity, i.e., improving the filling effect of the metal filled into the PMOS region dummy gate trench, which greatly increases the reliability of the CMOS device and improves the yield of the CMOS device.

[0108] It should be noted that, considering that the process size of the CMOS device is becoming smaller and smaller, at least one photolithography and etching is required for each layer removed when the metal gate electrode is manufactured, and the photolithography and etching may affect the roughness and defect condition of the interface in the device, and further affect the metal-semiconductor work function difference of the device, while the method for manufacturing the metal gate electrode provided in the embodiments of the present application only removes the P-type metal work function layer outside the PMOS region dummy gate trench and at least at the trench opening in the PMOS region dummy gate trench, and fully utilizes the Si-ARC mask layer as a liquid in a normal state, thereby having a great advantage in filling the trench with a high aspect ratio, the excellent performance of the Si-ARC mask layer in resisting oxidation and corrosion, and the high etching selectivity of the 5% tetramethylammonium hydroxide concentration to the Si-ARC mask layer, so that the method is simple in process, and improves the cavity phenomenon caused by the top suspension of the deposited gate metal of the PMOS device, and further increases the reliability of the CMOS device and improves the yield of the device.

[0109] The embodiments of the present application further provide a method for manufacturing a CMOS device, as shown in Figure 5 The method comprises the following steps.

[0110] S10: providing a substrate 10.

[0111] Optionally, the substrate 10 can be a silicon-on-insulator substrate, i.e. a SOI (Silicon on Insulator) substrate, as shown in FIG. 6(a), which includes a silicon substrate 01, a buried oxide layer (BOX) 02 and a silicon-on-insulator 03 stacked in sequence.

[0112] S20: performing a shallow trench isolation (STI) 20 on the substrate 10, as shown in FIG. 6(b), which divides the substrate 10 into a first part 11 and a second part 12.

[0113] S30: forming a dummy gate structure 30 on the first part 11 and the second part 12 of the substrate respectively, which includes a dummy gate 31 on the surface of the substrate, a protective layer 32 covering the back surface of the dummy gate 31 away from the surface of the substrate 10 and a first side wall 33 on both sides of the dummy gate 31.

[0114] Specifically, the forming process of the dummy gate structure 30 includes:

[0115] S31: forming a dummy gate layer 31 and a protective layer 32 in sequence on one side of the substrate 10 with the shallow trench isolation 20, as shown in FIG. 6(c).

[0116] S32: etching the stack of the dummy gate layer 31 and the protective layer 32 to form the pattern of the dummy gate structure, as shown in FIG. 6(d).

[0117] S33: depositing a first side wall dielectric layer 33, as shown in FIG. 6(e).

[0118] S34: retaining the first side wall dielectric layer 33 on both sides of the structure of the stack of the dummy gate layer 31 and the protective layer 32 after etching, and removing the first side wall dielectric layer 33 in other areas to form the dummy gate structure 30, as shown in FIG. 6(f).

[0119] S40: forming a lightly doped source region 40 and a lightly doped drain region 50 on the substrate on both sides of the dummy gate structure 30 respectively, as shown in FIG. 6(g).

[0120] Specifically, the source region 40 and the drain region 50 are epitaxied on the substrate on both sides of the dummy gate structure 30, and the epitaxied source region 40 and the drain region 50 are lightly doped.

[0121] S50: forming a second side wall 60 on both sides of the dummy gate structure 30, which covers part of the lightly doped source region 40 and part of the lightly doped drain region 50, as shown in FIG. 6(h).

[0122] S60: As shown in Fig. 6(i), the lightly doped source region 40 and the lightly doped drain region 50 are heavily doped respectively, and the metal silicide 70 is formed on the heavily doped source region 40 and the heavily doped drain region 50 respectively.

[0123] S70: As shown in Fig. 6(j), the interlayer dielectric layer 80 is formed outside the second side wall 60, and the chemical mechanical polishing (CMP) is performed to remove the protective layer 32 covering the back surface of the dummy gate 31 away from the surface of the substrate 10, and the dummy gate 31 is opened;

[0124] S80: As shown in Fig. 6(k), the dummy gate 31 is removed to form the dummy gate trench 130, and thus the substrate 100 is obtained, wherein the region of the substrate 100 corresponding to the first part 11 of the substrate 10 is the NMOS region 110, the region of the substrate 100 corresponding to the second part 12 of the substrate 10 is the PMOS region 120, and the NMOS region 110 and the PMOS region 120 have the dummy gate trench 130 respectively.

[0125] S90: Based on the substrate 100, the metal gate is prepared by using the preparation method of the metal gate provided in the foregoing embodiments, and the CMOS device is formed.

[0126] As shown in Fig. 6(k), in the preparation method of the metal gate provided in the embodiments of the present application, the substrate 100 can include the substrate 10, the shallow trench isolation (STI) 20 separating the substrate 10 into the first part corresponding to the NMOS region 110 and the second part corresponding to the PMOS region 120, the dummy gate trench 130 located on the substrate 10 corresponding to the NMOS region 110 and the PMOS region 120, the first side wall 33 and the second side wall 60 located on both sides of the dummy gate trench 130, the source region 40 and the drain region 50 located on the substrate 10 outside the second side wall 60, and the interlayer dielectric layer 80, but the specific structure of the substrate 100 is not limited in the present application, and is determined according to the actual situation.

[0127] Since the preparation method of the metal gate has been described in detail in the foregoing embodiments, no further description is given here.

[0128] It should be noted that when the substrate is an SOI substrate, the CMOS device prepared by using the preparation method of the CMOS device provided in the embodiments of the present application can be a fully-depleted silicon on insulator (FDSOI) device.

[0129] Various portions of the specification are presented in terms of sequences of actions, procedures, steps, logic blocks, processing, and other symbolic representations of operational data mapping or the like that can be described herein in a specific manner for purposes of clarity. The various portions of the specification can be presented in terms of sequences of actions, procedures, steps, logic blocks, processing, and other symbolic representations of operational data mapping or the like that can be described herein in a specific manner for purposes of clarity.

[0130] The above description of disclosed embodiments is presented in terms of a particular sequence of actions, procedures, steps, logic blocks, processing, and other symbolic representations of operational data mapping or the like that can be described herein in a specific manner for purposes of clarity. The various portions of the specification can be presented in terms of sequences of actions, procedures, steps, logic blocks, processing, and other symbolic representations of operational data mapping or the like that can be described herein in a specific manner for purposes of clarity. The various portions of the specification can be presented in terms of sequences of actions, procedures, steps, logic blocks, processing, and other symbolic representations of operational data mapping or the like that can be described herein in a specific manner for purposes of clarity.

Claims

1. A method for fabricating a metal gate, characterized in that, include: A substrate is provided, the substrate including an NMOS region and a PMOS region, the NMOS region and the PMOS region respectively having a pseudo-gate trench; An oxide interface layer, a high dielectric constant dielectric layer, a capping layer, a barrier layer, and a P-type metal work function layer are sequentially formed on one side of the substrate having the pseudo-gate trench. Remove the P-type metal work function layer corresponding to the NMOS region; Masking layers are formed on the side of the barrier layer in the NMOS region facing away from the substrate and on the side of the P-type metal work function layer in the PMOS region facing away from the substrate. The masking layers include a silicon-containing anti-reflection layer (Si-ARC layer). Remove the mask layer outside the pseudo-gate trench in the PMOS region and at least at the opening of the pseudo-gate trench in the PMOS region, and retain at least the mask layer at the bottom of the pseudo-gate trench in the PMOS region. Remove the P-type metal work function layer that is not covered by the mask layer; Remove the remaining mask layer; Deposit an N-type metal work function layer and a binder layer; The pseudo-gate trench is filled with metal as a metal gate electrode layer to form a metal gate. The removal of the mask layer outside the pseudo-gate trench in the PMOS region and at least at the opening of the pseudo-gate trench in the PMOS region includes: The mask layer outside the pseudo-gate trench in the PMOS region and at least at the opening of the pseudo-gate trench in the PMOS region is removed by selective photolithography and etching back process; wherein, when performing the selective photolithography and etching back process, the etching gas used includes a mixture of nitrogen trifluoride and hydrogen, and the concentration of nitrogen trifluoride is a preset concentration. Removing the P-type metal work function layer not covered by the mask layer includes: The P-type metal work function layer not covered by the mask layer is removed by a first wet etching process; wherein, in performing the first wet etching process, the solution used is a mixed solution of ammonia, hydrogen peroxide and water, and the required temperature range is 49.5 degrees Celsius to 50.5 degrees Celsius, including the endpoint value.

2. The method according to claim 1, characterized in that, Forming mask layers on the side of the barrier layer in the NMOS region facing away from the substrate and on the side of the P-type metal work function layer in the PMOS region facing away from the substrate includes: The mask layer is formed on the side of the barrier layer in the NMOS region facing away from the substrate and on the side of the P-type metal work function layer in the PMOS region facing away from the substrate by spin coating.

3. The method according to claim 1, characterized in that, Removing the remaining mask layer includes: The remaining mask layer is removed by a second wet etching process; In the second wet etching process, the solution used is a 5% tetramethylammonium hydroxide solution.

4. The method according to claim 1, characterized in that, Filling the pseudo-gate trench with metal as a metal gate electrode layer includes: Metal is filled into the pseudo-gate trench as a metal gate electrode layer using physical vapor deposition, chemical vapor deposition, or atomic layer epitaxy.

5. The method according to claim 1, characterized in that, The high dielectric constant dielectric layer includes a hafnium dioxide layer (HfO2 layer); The oxide interface layer includes a silicon dioxide layer (SiO2 layer). The capping layer includes a titanium nitride layer (TiN layer). The barrier layer includes a tantalum nitride layer (TaN layer).

6. A method for fabricating a CMOS device, characterized in that, include: Provide a substrate; The substrate is subjected to shallow trench isolation, which divides the substrate into a first part and a second part; A dummy gate structure is formed on a first portion and a second portion of the substrate, respectively. The dummy gate structure includes a dummy gate located on the surface of the substrate, a protective layer covering the dummy gate away from the surface of the substrate, and first sidewalls located on both sides of the dummy gate. Lightly doped source and drain regions are formed on the substrates on both sides of the pseudo-gate structure, respectively. A second sidewall is formed on both sides of the pseudo-gate structure, and the second sidewall covers part of the lightly doped source region and part of the lightly doped drain region; The lightly doped source and drain regions are heavily doped, and metal silicides are formed on the heavily doped source and drain regions respectively. An interlayer dielectric layer is formed on the outer side of the second sidewall, and chemical mechanical polishing is performed to remove the protective layer covering the dummy gate away from the substrate surface, thereby opening the dummy gate. The dummy gate is removed to form a dummy gate trench, thus obtaining the substrate. The region of the substrate corresponding to the first part of the substrate is an NMOS region, and the region of the substrate corresponding to the second part of the substrate is a PMOS region. The NMOS region and the PMOS region each have the dummy gate trench. Based on the substrate, a metal gate is fabricated using the method described in any one of claims 1-5 to form a CMOS device.

7. The method according to claim 6, characterized in that, The substrate includes an SOI substrate.

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