Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the forming method comprising: the substrate includes discrete device regions, the device regions include a first region and a second region spaced apart from each other. In the step of forming a mask layer on the stacked material layers in the first region and the second region, the uniformity of each of the mask layers is relatively high, and the uniformity of the sacrificial mask layer formed between the mask layer in the first region and the mask layer in the second region is relatively high. Since the etching resistance of the sacrificial mask layer is less than that of the mask layer, when etching the stacked material layer using the mask layer and the sacrificial mask layer as masks to form device openings, the uniformity of the removal rates of the plurality of sacrificial mask layers is relatively good, and they are easily removed simultaneously, which is beneficial to making the uniformity of the device openings relatively high, so that the uniformity of the dielectric walls formed in the device openings is relatively high, which is beneficial to improving the electrical performance and the uniformity of the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] In semiconductor manufacturing, with the development trend of very large scale integrated circuits, the feature size of integrated circuits continues to decrease. In order to adapt to smaller feature sizes, the channel length of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) is also continuously shortened accordingly.

[0003] Therefore, in order to better meet the requirements of device size scaling, semiconductor processes have gradually started to transition from planar transistors to three-dimensional transistors with higher efficiency, such as nanowire transistors. In nanowire transistors, the gate surrounds the region where the channel is located from all sides. Compared with planar transistors, the gate of nanowire transistors has a stronger control ability over the channel and can better suppress the short-channel effect.

[0004] In order to further improve the integration of semiconductor structures, Forksheet transistors have been proposed. They are an option after FinFETs and nanowire transistors. Due to their complex bilateral fin-like structures separated by dielectric walls, the uniformity of the dielectric walls is crucial for improving the performance of semiconductor devices. Summary of the Invention

[0005] The problem solved by the embodiments of the present application is to provide a method for forming a semiconductor structure, which is used to improve the uniformity of dielectric walls and optimize the electrical performance of semiconductor structures.

[0006] To solve the above problems, an embodiment of the present application provides a method for forming a semiconductor structure, including: providing a substrate, the substrate including discrete device regions, the device regions including spaced-apart first and second regions, the substrate including an initial substrate and a plurality of stacked material layers located on the initial substrate, the stacked material layers including alternately stacked sacrificial material layers and channel material layers, and the bottommost layer of the stacked material layers being a sacrificial material layer; forming discrete mask layers on the stacked material layers in the first and second regions; in the device regions, forming a sacrificial mask layer between the mask layer in the first region and the mask layer in the second region, the etch resistance of the sacrificial mask layer being less than that of the mask layer; using the mask layer and the sacrificial mask layer as masks to etch the stacked material layers and a partial thickness of the initial substrate to form a device opening between the first and second regions, the step of forming the device opening including: removing the sacrificial mask layer; using the top of the channel material layer as an etch stop position to etch the sacrificial material layer using the mask layer as a mask; using the top of the sacrificial material layer as an etch stop position to etch the channel material layer using the mask layer as a mask; forming a dielectric wall in the device opening.

[0007] Compared with the prior art, the technical solution of the embodiment of the present application has the following advantages:

[0008] In the method for forming a semiconductor structure provided by an embodiment of the present invention, the substrate includes discrete device regions, and each device region includes a first region and a second region spaced apart from each other. In the step of forming a mask layer on the stacked material layers in the first region and the second region, the uniformity of each mask layer is relatively high. Correspondingly, the uniformity of the regions surrounded by the mask layers and the stacked material layers in the first region and the second region is relatively high. The uniformity of the sacrificial mask layer formed between the mask layer in the first region and the mask layer in the second region is relatively high. Since the etching resistance of the sacrificial mask layer is less than that of the mask layer, when etching the stacked material layer using the mask layer and the sacrificial mask layer as masks to form device openings, the uniformity of the removal rates of multiple sacrificial mask layers is relatively good, and they are easily removed simultaneously. Moreover, during the process of forming device openings, the top of the channel material layer is used as the etching stop position, and the sacrificial material layer is etched using the mask layer as a mask; the top of the sacrificial material layer is used as the etching stop position, and the channel material layer is etched using the mask layer as a mask; the tops of both the channel material layer and the sacrificial material layer play a temporary etching stop role. Therefore, the problem of over-etching or under-etching caused by inconsistent etching rates in each device region can be relatively small, which is beneficial to making the uniformity of the device openings relatively high. As a result, the uniformity of the dielectric walls formed in the device openings is relatively high. The dielectric walls can better electrically isolate the semiconductor structures formed subsequently in the first region and the second region, reducing the probability of leakage current between the semiconductor structures formed subsequently in the first region and the second region, which is beneficial to improving the electrical performance and the uniformity of the electrical performance of the semiconductor structure.

[0009] In an alternative embodiment, the substrate further includes an isolation region located between the device regions; in the step of forming the device openings, isolation openings are also formed in the isolation region. The isolation openings are formed by etching the stacked material layer and the initial substrate between the mask layer and the sacrificial mask layer, and the device openings are formed by etching the sacrificial mask layer, the stacked material layer at the bottom of the sacrificial mask layer, and the initial substrate. That is to say, the thickness of the film layer etched in the isolation region is less than the thickness of the film layer etched in the device region. And because the lateral dimension of the isolation region is greater than the lateral dimension of the interval between the first region and the second region, therefore, compared with the device region, the reaction by-products in the isolation region are easily removed quickly, reducing the obstruction of the reaction by-products to the etching process. In summary, it is beneficial to make the depth of the isolation openings greater than the depth of the device openings, so that the isolation structure formed in the isolation openings can better electrically isolate the device regions. Description of the Drawings

[0010] Figures 1 to 4 is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0011] Figures 5 to 17It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present application. Detailed implementation manners

[0012] As can be seen from the background art, there are still problems with poor device performance in currently formed devices. Now, the reasons for poor device performance are analyzed in combination with a method for forming a semiconductor structure.

[0013] Refer to Figures 1 to 4 , which shows a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0014] As Figure 1 shown, a substrate is provided. The substrate includes a device region and an isolation region a. The device region includes a first region I and a second region II spaced apart from each other. The substrate includes an initial substrate 100 and a plurality of stacked material layers 101 located on the initial substrate 100. The stacked material layers 101 include a plurality of sacrificial material layers 1011 and a channel material layer 1012 located on the sacrificial material layers 1011; a mask material layer 102 is formed on the stacked material layers 101; a core layer 103 is formed on the mask material layer 102; a sidewall material layer 104 is conformally coated on the core layer 103 and the mask material layer 102 exposed by the core layer 103. As Figure 2 shown, the sidewall material layer 104 on the top of the core layer 103 is removed by a maskless dry etching process, and the remaining sidewall material layer 104 serves as a sidewall layer 105; after forming the sidewall layer 105, the core layer 103 is removed. As Figure 3 shown, the mask material layer 102 is etched using the sidewall layer 105 as a mask to form a mask layer 106. As Figure 4 shown, the stacked material layers 101 and a part of the thickness of the initial substrate 100 are etched using the mask layer 106 as a mask to respectively form a substrate 107, fins 108 located on the substrate 107, and a stacked structure 109 located on the fins 108. The substrate 107, fins 108, and stacked structure 109 enclose an opening. The opening between the first region I and the second region II serves as a device opening 110, and the opening in the isolation region a serves as an isolation opening 113.

[0015] The isolation region a is used to electrically isolate each of the device regions. To achieve a better electrical isolation effect of the isolation region a from the device regions, during the process of forming the device opening 110, the depth of the isolation opening 113 formed in the isolation region a is greater than the depth of the device opening 110. Therefore, during the step of removing the sidewall material layer 104 on top of the core layer 103 to form the sidewall layer 105, there is no over-etching process, and a portion of the sidewall material layer 104 with a certain thickness is reserved on the mask material layer 102 between the first region I and the second region II as the sidewall barrier layer 111 (as Figure 2 shown). As a result, the process controllability of forming the sidewall layer 105 is poor, leading to inconsistent thicknesses of the sidewall barrier layers 111. Correspondingly, during the process of etching the mask material layer 102 using the sidewall layer 105 as a mask to form the mask layer 106, the mask layer 106 between the first region I and the second region II in some device regions a is completely removed, while in some device regions a, there is still residue of the mask layer 106 between the first region I and the second region II, resulting in poor thickness uniformity of the mask layer 106 between the first region I and the second region II. Consequently, when etching the stacked material layer 101 using the mask layer 106 as a mask to form the device opening 110, the depth uniformity of the formed device opening 110 is poor. Subsequently, when forming an isolation layer in the device opening 110 between the fins 108, due to the uneven depths of the device openings 110, the isolation layer cannot effectively electrically isolate the adjacent fins 108, and there is likely to be leakage current between the fins 108 in the first region I and the fins 108 in the second region in the subsequent process.

[0016] To solve the technical problem, the substrate includes discrete device regions, and the device regions include a first region and a second region spaced apart from each other. In the step of forming a mask layer on the stacked material layers in the first region and the second region, the uniformity of each mask layer is relatively high, and correspondingly, the uniformity of the regions surrounded by the mask layers and the stacked material layers in the first region and the second region is relatively high. The uniformity of the sacrificial mask layer formed between the mask layer in the first region and the mask layer in the second region is relatively high. Since the etching resistance of the sacrificial mask layer is less than that of the mask layer, in the step of etching the stacked material layer using the mask layer and the sacrificial mask layer as masks to form device openings, the uniformity of the removal rates of the plurality of sacrificial mask layers is good, and they are easily removed simultaneously. Moreover, in the process of forming the device openings, the top of the channel material layer is used as the etching stop position, and the sacrificial material layer is etched using the mask layer as a mask; the top of the sacrificial material layer is used as the etching stop position, and the channel material layer is etched using the mask layer as a mask; the tops of the channel material layer and the sacrificial material layer both play a temporary etching stop role, so that the problem of over-etching or under-etching caused by inconsistent etching rates in each device region can be relatively small, which is beneficial to making the uniformity of the device openings relatively high, and thus the uniformity of the dielectric walls formed in the device openings is relatively high. The dielectric walls can electrically isolate the semiconductor structures formed subsequently in the first region and the second region well, reduce the probability of leakage current between the semiconductor structures formed subsequently in the first region and the second region, and are beneficial to improving the electrical performance and the uniformity of the electrical performance of the semiconductor structures.

[0017] To make the above objects, features, and advantages of the embodiments of the present application more obvious and understandable, the following will describe in detail the specific embodiments of the embodiments of the present application with reference to the accompanying drawings.

[0018] Figures 5 to 17 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure according to an embodiment of the present application.

[0019] Refer to Figure 5 , a substrate is provided. The substrate includes discrete device regions, and the device regions include a first region I and a second region II spaced apart from each other. The substrate includes an initial substrate 200 and a plurality of stacked material layers 201 located on the initial substrate 200. The stacked material layers 201 include alternately stacked sacrificial material layers 2011 and channel material layers 2012, and the bottommost layer of the stacked material layers 201 is the sacrificial material layer 2011.

[0020] The substrate provides a process platform for the subsequent formation of a semiconductor structure. In this embodiment, the first region I is used to form a first-type transistor, and the second region II is used to form a second-type transistor. The conduction types of the first-type transistor and the second-type transistor are different. Specifically, the first-type transistor is a PMOS (Positive Channel Metal Oxide Semiconductor), and the second-type transistor is an NMOS (Negative channel Metal Oxide Semiconductor). In other embodiments, the first transistor can also be an NMOS, and the second transistor can also be a PMOS.

[0021] The initial substrate 200 is used to provide a process platform for the subsequent formation of a Forksheet transistor.

[0022] In this embodiment, the initial substrate 200 is a silicon substrate. In other embodiments, the material of the initial substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the initial substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0023] The stacked material layer 201 prepares for the subsequent formation of a stacked structure. Specifically, the channel material layer 2012 prepares for the subsequent formation of a channel layer, and the sacrificial material layer 2011 prepares for the subsequent formation of a sacrificial layer.

[0024] In this embodiment, the material of the channel material layer 2012 includes silicon; the material of the sacrificial material layer 2011 includes silicon germanide. In other embodiments, the material of the channel material layer can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the sacrificial material layer can correspondingly also be silicon.

[0025] It should be noted that the bottom of the stacked material layer 201 is the sacrificial material layer 2011. The sacrificial material layer 2011 occupies a spatial position for the subsequent formation of a gate structure. When the semiconductor structure is working, the bottom channel layer can be surrounded by the gate structure, and the bottom channel layer can be better controlled by the gate structure, which is beneficial to optimizing the electrical performance of the semiconductor structure.

[0026] In this embodiment, in the step of providing the substrate, the top three film layers in the stacked material layer 201 are sequentially used as the first film layer, the second film layer, and the third film layer from top to bottom. Specifically, the first film layer is the sacrificial material layer 2011, the second film layer is the channel material layer 2012, and the third film layer is the sacrificial material layer 2011. In other embodiments, the first film layer can also be the channel material layer, the second film layer is the sacrificial material layer, and the third film layer is the channel material layer.

[0027] The top sacrificial material layer 2011 is used as the top sacrificial material layer 207, and the thickness of the top sacrificial material layer 207 is greater than that of the sacrificial material layer 2011. The top sacrificial material layer 207 occupies a spatial position for the subsequently formed gate structure, so that the thickness of the gate structure formed subsequently on the topmost channel layer is larger, making it easier to meet the process requirements. When the semiconductor structure operates, the topmost channel layer can be better controlled by the gate structure, which is beneficial to optimizing the electrical performance of the semiconductor structure.

[0028] It should be noted that in the step of providing the substrate, the substrate further includes an isolation region A located between the device regions. The isolation region A is located between the device regions and is used for electrically isolating adjacent device regions.

[0029] Taking the direction parallel to the substrate surface and perpendicular to the intersection line of the device region and the isolation region A as the transverse direction, the transverse dimension of the isolation region A is greater than the transverse interval between the first region I and the second region II.

[0030] Subsequently, discrete mask layers are formed on the stacked material layer 201 in the first region I and the second region II. In the device region, a sacrificial mask layer is formed between the mask layer in the first region and the mask layer in the second region. The etching resistance of the sacrificial mask layer is less than that of the mask layer. Using the mask layer and the sacrificial mask layer as masks, the stacked material layer and a part of the thickness of the initial substrate are etched to form a device opening in the first region I and the second region II, and an isolation opening is formed in the isolator A. The isolation opening is formed by etching the stacked material layer and the initial substrate between the mask layer and the sacrificial mask layer. The device opening is formed by etching the sacrificial mask layer, the stacked material layer at the bottom of the sacrificial mask layer, and the initial substrate. That is to say, the thickness of the etched film layer in the isolation region A is less than that in the device region, and because the transverse dimension of the isolation region A is greater than the transverse dimension of the interval between the first region I and the second region II, compared with the device region, the reaction by-products in the isolation region A are easily removed quickly, reducing the obstruction of the reaction by-products to the etching process. In summary, it is beneficial to make the depth of the isolation opening greater than that of the device opening, so that the isolation structure formed in the isolation opening can better electrically isolate the device region.

[0031] Reference Figures 6 to 8 , discrete mask layers 202 are formed on the stacked material layer 201 in the first region I and the second region II (as Figure 8 shown).

[0032] The mask layer 202 serves as a mask for subsequently etching the stacked material layer 201 and a part of the thickness of the initial substrate 200 to form a device opening.

[0033] In this embodiment, the mask layer 202 is a stacked structure. Specifically, the material of the mask layer 202 includes: the mask layer includes a first mask sub-layer 2021, a second mask sub-layer 2022 located on the first mask sub-layer 2021, and a third mask sub-layer 2023 located on the second mask sub-layer 2022.

[0034] Specifically, the first mask sub-layer 2021 includes a silicon oxide layer; the second mask sub-layer 2022 includes a silicon nitride layer; the third mask sub-layer 2023 includes a silicon oxide layer.

[0035] Specifically, the step of forming the mask layer 202 on the stacked material layer 201 in the first region I and the second region II includes:

[0036] As Figure 6 shown, a mask material layer 203 is formed on the stacked material layer 201;

[0037] In this embodiment, the mask material layer 203 includes a first mask material sub-layer 2031, a second mask material sub-layer 2032 located on the first mask material sub-layer 2031, and a third mask material sub-layer 2033 located on the second mask material sub-layer 2032.

[0038] Continuing to refer to Figure 6 , a core layer 204 is formed on the mask material layer 203.

[0039] The core layer 204 provides a process space for the subsequent formation of the sidewall layer. Specifically, the material of the core layer 204 includes: one or more of amorphous silicon, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, boron nitride silicon, and boron nitride carbon silicon. In this embodiment, the material of the core layer 204 includes silicon nitride.

[0040] Continuing to refer to Figure 6 , a sidewall material layer 205 is conformally coated on the core layer 204 and the mask material layer 203 exposed by the core layer 204.

[0041] The sidewall material layer 205 prepares for the formation of the sidewall layer. Specifically, the sidewall material layer 205 conformally covers the core layer 204 and the mask material layer 203 exposed by the core layer 204.

[0042] Specifically, the material of the sidewall material layer 205 includes: amorphous silicon. Amorphous silicon is a commonly used dielectric material in the process, with a relatively low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and process cost of forming the sidewall material layer 205.

[0043] Refer to Figure 7, taking the top of the mask material layer 203 as the removal stop position, removing the sidewall material layer 205 on the top of the core layer 204 and the surface of the mask material layer 203, and the remaining sidewall material layer 205 on the sidewall of the core layer 204 serves as the sidewall layer 206. The sidewall layer 206 is prepared for etching the mask material layer 203 subsequently to form a mask layer.

[0044] In this embodiment, a maskless dry etching process is used to remove the sidewall material layer 205 on the top of the core layer 204 and the surface of the mask material layer 203.

[0045] The method for forming a semiconductor structure further includes: after forming the sidewall layer 206, removing the core layer 204. Removing the core layer 204 is prepared for etching the mask material layer 203 using the sidewall layer 206 as a mask subsequently to form a mask layer.

[0046] As Figure 8 shown, etching the mask material layer 203 using the sidewall layer 206 as a mask to form a mask layer 202. The mask layer 202 serves as an etching mask for etching the stacked material layer 201 subsequently.

[0047] In this embodiment, the mask material layer 203 is etched using a dry etching process with the sidewall layer 206 as a mask to form a mask layer 202. The dry etching process has anisotropic etching characteristics, has good etching profile controllability, can obtain a quite accurate pattern conversion, is beneficial to making the morphology of the mask layer 202 meet the process requirements, and is also beneficial to improving the removal efficiency of the mask material layer 203. And during the dry etching process, the top of the stacked material layer 201 can be used as an etching stop position to reduce the damage to other film layer structures. During the dry etching process, by replacing the etching gas, the first mask sub-layer 2021, the second mask sub-layer 2022, and the third mask sub-layer 2023 can be etched in the same etching equipment, simplifying the process steps.

[0048] It should be noted that in the step of forming the mask layer 202 on the stacked material layer 201 in the first region I and the second region II, the mask layer 202 is formed in a single etching step, and the uniformity of each mask layer 202 is relatively high. Correspondingly, the uniformity of the regions surrounded by the mask layer 202 and the stacked material layer 201 in the first region I and the second region II is relatively high.

[0049] The method for forming a semiconductor structure further includes: after forming the mask layer 202, removing the sidewall layer 206.

[0050] Remove the sidewall layer 206 to prepare for etching the stacked material layer 201 using the mask layer 202 as a mask to form a stacked structure. In the step of forming the mask layer 202, the thickness uniformity of each sidewall layer 206 is usually poor. By removing the sidewall layer 206 with poor uniformity and using the mask layer 202 with better uniformity as the etching mask for etching the stacked material layer 201, it is beneficial to improve the uniformity of the stacked structure, and correspondingly beneficial to improve the uniformity of the device openings formed in the first region I and the second region II subsequently. In this embodiment, the sidewall layer 206 is removed by a wet etching process.

[0051] Reference Figure 9 and Figure 10 , in the device region, a sacrificial mask layer 208 is formed between the mask layer 202 in the first region I and the mask layer 202 in the second region II. The etch resistance of the sacrificial mask layer 208 is less than that of the mask layer 202. In the subsequent process, the sacrificial mask layer 208 and the mask layer 202 are used together as the etching mask for etching the stacked material layer 201.

[0052] Because the uniformity of the regions surrounded by the mask layer 202 and the stacked material layer 201 in the first region I and the second region II is relatively high, correspondingly, the uniformity of forming the sacrificial mask layer 208 between the mask layer 202 in the first region I and the mask layer 202 in the second region II is relatively high.

[0053] In the subsequent step of etching the stacked material layer 201 using the sacrificial mask layer 208 as a mask, the etching rates of the sacrificial mask layer 208 and the top sacrificial material layer 207 should neither be too large nor too small. If the etching selectivity is too large, the sacrificial mask layer 208 is consumed prematurely, and the sacrificial mask layer 208 cannot function well as a mask. During the process of etching the top sacrificial material layer 207 in the isolation region A, the top sacrificial material layer 207 between the first region I and the second region II is also etched and removed. Subsequently, when etching the stacked material layer 201 and a part of the thickness of the initial substrate 200 to form a device opening in the device region, it is easy to cause the depth of the formed device opening to be too large. Subsequently, a dielectric wall is formed in the device opening, and correspondingly, the dielectric wall is prone to have pores. In addition, when the depth of the device opening is too large, the stress of the dielectric wall on the formed fins and the stacked structure is relatively large, and the stacked structure is prone to bending or tilting. If the etching selectivity is too small, the sacrificial mask layer 208 is not easily removed, and correspondingly, the top sacrificial material layer 207 between the mask layer 202 in the first region and the second region II is not easily removed, which is likely to cause the depth of the device opening to be too small. Subsequently, the dielectric wall formed in the device opening cannot electrically isolate the fins and the stacked structure in the first region I and the second region II well, and there is likely to be a leakage current situation between the fins in the first region I and the second region II. In this embodiment, the etching selectivity of the sacrificial mask layer 208 to the top sacrificial material layer 207 is 1 to 15.

[0054] In this embodiment, the material of the sacrificial mask layer 208 is the same as that of the sacrificial material layer 2011, that is to say, the material of the sacrificial mask layer 208 is the same as that of the top sacrificial material layer 207. The material of the sacrificial mask layer 208 includes silicon germanide. Correspondingly, in the subsequent step of etching the top sacrificial material layer 207 using the mask layer 202 as a mask, the removal rates of the mask layer 202 and the top sacrificial material layer 207 are the same.

[0055] Specifically, in the device area, the step of forming the sacrificial mask layer 208 between the mask layer 202 in the first region I and the mask layer 202 in the second region II includes: forming a sacrificial mask material layer 209 on the mask layer 202 and the stacked material layer 201 exposed by the mask layer 202; removing the sacrificial mask material layer 209 on the top of the mask layer 202 and the surface of the stacked material layer 201; the remaining sacrificial mask material layer 209 between the mask layer 202 in the first region I and the mask layer 202 in the second region II serves as the sacrificial mask layer 208.

[0056] In this embodiment, the atomic layer deposition process is used to form the sacrificial mask material layer 209. The atomic layer deposition process includes performing multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the sacrificial mask material layer 209, enabling the sacrificial mask material layer 209 to conformally cover the sidewalls of the mask layer 202, the top of the mask layer 202, and the surface of the stacked material layer 201; in addition, the atomic layer deposition process has good gap filling performance and step coverage, correspondingly improving the conformal coverage ability of the sacrificial mask material layer 209. In other embodiments, the chemical vapor deposition process can also be used to form the sacrificial mask material layer.

[0057] It should be noted that in the step of forming the sacrificial mask material layer 209, twice the thickness of the sacrificial mask material layer 209 is greater than the lateral spacing between the mask layer 202 in the first region I and the mask layer 202 in the second region II. Thus, in the device area, the space between the first region I and the second region II can be filled with the sacrificial mask material layer 209, which is beneficial to improving the formation quality of the sacrificial mask layer 208.

[0058] Specifically, the isotropic etching process is used to remove the sacrificial mask material layer 209 on the top of the mask layer 202 and the surface of the stacked material layer 201. During the process of etching the sacrificial mask material layer 209 using the isotropic etching process, the exposed areas of the sacrificial mask material layer 209 on the top, sidewalls of the mask layer 202, and the surface of the stacked material layer 201 are too large and are easily removed, while only the top of the sacrificial mask material layer 209 between the mask layer 202 is exposed and is difficult to be removed during the isotropic etching process and is retained to form the sacrificial mask layer 208.

[0059] It should be noted that in the step of forming the sacrificial mask layer 208, the sacrificial mask material layer 209 on the sidewall of the mask layer 202 close to the isolation region A is also removed.

[0060] In this embodiment, the isotropic etching process includes an isotropic dry etching process, and the corresponding etching gas includes HCl. In other embodiments, the isotropic dry etching process may also adopt a wet etching process, and the corresponding etching solution includes a hydrogen chloride solution.

[0061] Reference Figures 11 to 16 , using the mask layer 202 and the sacrificial mask layer 202 as masks to etch the stacked material layer 201 and a part of the thickness of the initial substrate 200, a device opening 303 is formed between the first region I and the second region II (as Figure 14 shown), and the steps of forming the device opening 303 include: removing the sacrificial mask layer 202; using the top of the channel material layer 2012 as the etching stop position and using the mask layer 202 as a mask to etch the sacrificial material layer 2011; using the top of the sacrificial material layer 2011 as the etching stop position and using the mask layer 202 as a mask to etch the channel material layer 2012.

[0062] The substrate includes discrete device regions, and the device regions include spaced-apart first regions I and second regions II. In the step of forming the mask layer 202 on the stacked material layer 201 of the first regions I and the second regions II, the uniformity of each mask layer 202 is relatively high, and correspondingly, the uniformity of the regions surrounded by the mask layer 202 and the stacked material layer 201 of the first regions I and the second regions II is relatively high. The uniformity of the sacrificial mask layer 202 formed between the mask layer 202 of the first regions I and the mask layer 202 of the second regions II is relatively high. Since the etching resistance of the sacrificial mask layer 202 is less than that of the mask layer 202, when etching the stacked material layer 201 using the mask layer 202 and the sacrificial mask layer 202 as masks to form the device opening 303, the uniformity of the removal rates of the multiple sacrificial mask layers 202 is good, and they are easily removed simultaneously. Moreover, in the process of forming the device opening 303, taking the top of the channel material layer 2012 as the etching stop position, etching the sacrificial material layer 2011 using the mask layer 202 as a mask; taking the top of the sacrificial material layer 2011 as the etching stop position, etching the channel material layer 2012 using the mask layer 202 as a mask; the tops of the channel material layer 2012 and the sacrificial material layer 2011 both play a temporary etching stop role, thereby enabling the problem of over-etching or under-etching caused by inconsistent etching rates of each device region to be relatively small, which is beneficial to making the uniformity of the device opening 303 relatively high, so that the uniformity of the dielectric wall formed in the device opening 303 is relatively high. The dielectric wall can better electrically isolate the semiconductor structures formed subsequently in the first regions I and the second regions II, reduce the probability of leakage current between the semiconductor structures formed subsequently in the first regions I and the second regions II, and is beneficial to improving the electrical performance and the uniformity of the electrical performance of the semiconductor structure.

[0063] Specifically, in the step of etching the stacked material layer 201 and a partial thickness of the initial substrate 200 using the mask layer 202 and the sacrificial mask layer 208 as masks, a stacked structure 302, as well as a substrate 300 and fins 301 located on the substrate 300, are respectively formed. The substrate 300, the fins 301, and the stacked structure 302 enclose an opening, and the opening located in the device region serves as the device opening 303.

[0064] In this embodiment, the stacked material layer 201 and a part of the thickness of the initial substrate 200 are etched using the mask layer 202 as a mask by a dry etching process to form a device opening 303. The dry etching process has anisotropic etching characteristics and good etching profile controllability, can obtain a quite accurate pattern conversion, is beneficial to making the morphology of the stacked structure 302 meet the process requirements, and is also beneficial to improving the removal efficiency of the stacked material layer 201. By replacing the etching gas, the sacrificial material layer 2011 and the channel material layer 2012 can be etched in the same etching equipment, which simplifies the process steps. Moreover, in the step of etching the sacrificial material layer 2011, the top of the channel material layer 2012 can be used as the etching stop position, and in the process of etching the channel material layer 2012, the top of the sacrificial material layer 2011 can be used as the etching stop position, which can make the formation quality of the device opening 303 better.

[0065] The steps of etching the stacked material layer 201 and a part of the thickness of the initial substrate 200 using the mask layer 202 and the sacrificial mask layer 208 as masks to form the device opening 303 include: using the top of the initial substrate 200 in the device region as the etching stop position, etching the bottommost sacrificial material layer 2011 in the device region using the mask layer 202 as a mask, taking the remaining channel material layer 2012 as the channel layer 3022, taking the remaining sacrificial material layer 2011 as the sacrificial layer 3021, and taking the channel layer 3022 and the sacrificial layer 3021 as the stacked structure 302; after forming the stacked structure 302, etching the initial substrate 200 using the mask layer 202 as a mask to form the device opening 303.

[0066] During the formation of the device opening 303, using the top of the initial substrate 200 as the etching stop position plays a temporary etching stop role, which can make the problems of over-etching or under-etching caused by inconsistent etching rates in each device region smaller, is beneficial to making the uniformity of the device opening 303 higher, and thus the uniformity of the dielectric wall formed in the device opening 303 is higher. The dielectric wall can better electrically isolate the semiconductor structures formed in the first region I and the second region II subsequently, reduce the probability of leakage current between the semiconductor structures formed in the first region I and the second region II subsequently, and is beneficial to improving the electrical performance and the uniformity of the electrical performance of the semiconductor structure.

[0067] In this embodiment, the remaining channel material layer 2012 is used as the channel layer 3022, and the remaining sacrificial material layer 2011 is used as the sacrificial layer 3021.

[0068] In the method for forming a semiconductor structure, in the step of etching the stacked material layer 201 and a part of the thickness of the initial substrate 200 using the mask layer 202 and the sacrificial mask layer 202 as masks to form the device opening 303, the stacked material layer 201 and a part of the thickness of the initial substrate 200 are etched using the mask layer 202 and the sacrificial mask layer 202 as masks to form the isolation opening 212, and the depth of the isolation opening 212 is greater than the depth of the device opening 303, so that the isolation structure formed in the isolation opening 212 can better electrically isolate the device regions.

[0069] Subsequently, an isolation structure is formed in the isolation opening 212, and the isolation structure is used to electrically isolate adjacent device regions.

[0070] In this embodiment, the step of forming the isolation opening 212 includes:

[0071] As Figure 11 and Figure 12 shown, in the isolation region A, in the step of etching the first film layer with the top of the second film layer as the etching stop position, a part of the thickness of the first film layer between the first region I and the second region II is etched. In this embodiment, the material of the first film layer is the sacrificial material layer 2011, referring to the top sacrificial material layer 207, and the material of the second film layer is the channel material layer 2012. Correspondingly, in the step of etching the top sacrificial material layer 207 with the top of the channel material layer 2012 as the etching stop position, a part of the thickness of the top sacrificial material layer 207 between the first region I and the second region II is etched.

[0072] As Figure 12 shown, in the isolation region A, the second film layer is etched using the mask layer 202 with the top of the third film layer as the etching stop position.

[0073] When the top sacrificial material layer 207 in the isolation region A is removed, a part of the thickness of the top sacrificial material layer 207 between the first region I and the second region II still remains, and because the channel material layer 2012 and the sacrificial material layer 2011 have an etching selectivity ratio, therefore, when etching the second film layer in the isolation region A, that is, in the process of etching the channel material layer 2012, it is more difficult to etch the top sacrificial material layer 207 between the first region I and the second region II. Correspondingly, the top sacrificial material layer 207 in the device region remains.

[0074] As Figure 13As shown, in isolation region A, in the step of etching and removing the third film layer, the first film layer between the first region I and the second region II is removed, a first opening 210 is formed in the isolation region A, and a second opening 213 is formed in the device region. That is, the top sacrificial material layer 207 between the first region I and the second region II is removed. Thus, in the step of etching and removing the third film layer of the isolation region A, the first opening 210 is deeper than the second opening 213 by a dimension D, where D is the sum of the thicknesses of a sacrificial material layer 2011 and a channel material layer 2012. Subsequently, the stacked material layer 201 and the initial substrate 200 are continuously etched using the mask layer 202 as a mask, and the depths of the first opening 210 and the second opening 213 differ by D, which is beneficial for making the depth of the subsequent formed isolation opening greater than the depth of the device opening.

[0075] Correspondingly, as Figure 14 shown, using the bottommost channel material layer 2012 in the device region as an etching stop layer, during the process of etching the sacrificial material layer 2011, the top of the initial substrate 200 in the isolation region A is used as the etching stop position to etch the bottommost sacrificial material layer 2012 in the isolation region A. A third opening 214 is formed in the isolation region A, and a fourth opening 215 is formed between the first region I and the second region II.

[0076] In the step of etching the bottommost sacrificial material layer 2012 in the isolation region A, using the top of the isolation region A as the etching stop position is beneficial for preventing the problem of under-etching or over-etching from easily occurring in the third opening 214 in each isolation region A, making the morphology uniformity of each third opening 214 relatively high, which is beneficial for making the uniformity of the subsequent formed isolation openings relatively high. And because the depth difference between the first opening 210 (as Figure 13 shown) and the second opening 213 (as Figure 13 shown) is D, and because during the process of etching the stacked material layer 201, the tops of the channel material layer 2012 and the sacrificial material layer 2011 are continuously used as the etching stop positions. Therefore, the third opening 214 is deeper than the fourth opening 215 by a dimension D, which is beneficial for making the depth of the subsequent formed isolation opening greater than the depth of the device opening, so that the isolation structure formed in the isolation opening can better electrically isolate the device region.

[0077] As Figure 15 shown, in the step of etching the bottommost channel material layer 2012 and the sacrificial material layer 2011 in the device region using the mask layer 202 as a mask, using the top of the initial substrate 200 as the etching stop position, a fifth opening 216 is formed between the first region I and the second region II.

[0078] During the process of forming the fifth opening 216, taking the top of the initial substrate 200 as the etching stop position, it is not easy to have problems of under-etching or over-etching, resulting in a high topography uniformity of each fifth opening 216, which is beneficial to making the uniformity of the subsequent formed device openings relatively high. Consequently, the uniformity of the dielectric walls formed in the device openings 303 is relatively high. The dielectric walls can better electrically isolate the semiconductor structures formed in the first region I and the second region II subsequently, reducing the probability of leakage current between the semiconductor structures formed in the first region I and the second region II subsequently, and being beneficial to improving the electrical performance and the uniformity of the electrical performance of the semiconductor structures.

[0079] It should be noted that during the process of forming the fifth opening 216, the initial substrate 200 in the isolation region A is etched using the mask layer 202 as a mask. Specifically, in the steps of forming the fifth opening 216, the remaining channel material layer 2012 serves as the channel layer 3022, the remaining sacrificial layer 2011 serves as the sacrificial layer 3021, and the stacked channel layer 3022 and sacrificial layer 3021 serve as the stacked structure 302.

[0080] As Figure 16 shown, the initial substrate 200 is etched using the mask layer 202 as a mask to form the device opening 303 and the isolation opening 212.

[0081] The depth of the formed isolation opening 212 is greater than the depth of the device opening 303, so that the isolation structure formed in the isolation opening 212 can better electrically isolate the device region.

[0082] In other embodiments, in the method for forming a semiconductor structure, in the step of providing a substrate, the first film layer is a channel material layer.

[0083] Correspondingly, the steps of etching the stacked material layer using the mask layer and the sacrificial mask layer as masks to form a stacked structure include: taking the top of the sacrificial material layer as the etching stop position, etching the topmost channel material layer using the mask layer and the sacrificial mask layer as masks, with the etching rate of the channel material layer being greater than the etching rate of the sacrificial mask layer; taking the top of the channel material layer as the etching stop position, etching the topmost sacrificial material layer using the mask layer and the sacrificial mask layer as masks, and removing the sacrificial mask layer during the process of etching the topmost sacrificial material layer; taking the top of the sacrificial material layer as the etching stop position, etching the channel material layer using the mask layer as a mask; taking the top of the channel material layer as the etching stop position, etching the sacrificial material layer using the mask layer as a mask. Taking the top of the initial substrate as the etching stop position, etching the bottommost sacrificial material layer using the mask layer as a mask.

[0084] The method for forming a semiconductor structure further includes: after forming the isolation opening 212 and the device opening 303, removing the mask layer 202.

[0085] Removing the mask layer 202 increases the process window for forming the subsequent dielectric wall.

[0086] As Figure 17 shown, the method for forming the semiconductor structure further includes: forming a dielectric wall 304 in the device opening 303. The dielectric wall 304 is used to electrically isolate the first region I and the second region II, so that it is not easy for leakage to occur between the semiconductor structures in the subsequent first region I and the second region II, improving the electrical performance of the semiconductor structure.

[0087] In the step of forming the dielectric wall 304 in the device opening 303, the dielectric wall 304 includes a bottom dielectric wall 3041 located between the fins 301 and a top dielectric wall 3042 located between the stacked structures 302, and the stress of the bottom dielectric wall 3041 is less than the stress of the top dielectric wall 3042.

[0088] The stress of the bottom dielectric wall 3041 is less than the stress of the top dielectric wall 3042, so that the stress on the stacked structure composed of the fins 301 and the stacked structure 302 is small, making the stacked structure not easy to bend or tilt, which is beneficial to improving the electrical performance of the semiconductor structure.

[0089] In this embodiment, the bottom dielectric wall 3041 includes silicon oxide. The stress of silicon oxide is small, so that the stress of the bottom dielectric wall 3041 on the fins 301 is small, and the fins 301 are not easy to bend or tilt. Correspondingly, the stacked structure composed of the fins 301 and the stacked structure 302 is not easy to bend or tilt, having a good topography, and silicon oxide is a commonly used dielectric material in the process, with the characteristics of simple formation process and low cost.

[0090] Specifically, the material of the top dielectric wall 3042 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, boron nitride silicon, and boron nitride carbon silicon. In this embodiment, the material of the top dielectric wall 3042 includes silicon nitride.

[0091] The step of forming the dielectric wall 304 includes: forming an isolation material layer (not shown in the figure) covering the device opening 303 and the isolation opening 212; back-etching a part of the thickness of the isolation material layer, and the remaining isolation material layer located between the first region I and the second region II serves as the bottom dielectric wall 3041, and the top surface of the bottom dielectric wall 3041 is lower than or flush with the top wall of the fins 301; after forming the bottom dielectric wall 3041, forming a conformal dielectric material layer covering the remaining isolation opening 212 and the remaining device opening 303; removing the remaining dielectric material layer exposed in the device opening 303, and the dielectric material layer located in the device opening 303 serves as the top dielectric wall 3042.

[0092] It should be noted that in the step of forming the dielectric wall 304 in the device opening 303, an isolation structure 305 is formed in the isolation opening 212. Specifically, in the step of back-etching a part of the thickness of the isolation material layer to form the bottom dielectric wall 3041, the remaining isolation material layer located in the isolation opening 212 serves as the isolation structure 305.

[0093] In this embodiment, the isolation material layer is formed by a Flowable Chemical Vapor Deposition (FCVD) process.

[0094] In this embodiment, a dry etching process is used to back-etch a part of the thickness of the isolation material layer, and the remaining isolation material layer serves as the bottom dielectric wall 3041. The dry etching process has an anisotropic etching characteristic. In this embodiment, an atomic layer deposition process is used to form the dielectric material layer. In other embodiments, a chemical vapor deposition process can also be used to form the dielectric material layer.

[0095] Specifically, an isotropic etching process is used to remove the dielectric material layer exposed in the device opening 303. During the process of removing the dielectric material layer exposed in the device opening 303 by using the isotropic etching process, too much of the dielectric material layer on the sidewalls and the top of the stacked structure 302 is exposed and is easily removed, while only the top of the dielectric material layer in the device opening 303 is exposed and is difficult to be removed during the isotropic etching process and is easily retained to form the top dielectric wall 3042.

[0096] In this embodiment, the isotropic etching process includes a wet etching process. The material of the dielectric material layer is silicon nitride, and the corresponding wet etching solution includes phosphoric acid.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, the substrate including discrete device regions, the device regions including spaced-apart first and second regions, the substrate including an initial substrate and a plurality of stacked material layers on the initial substrate, the stacked material layers including alternately stacked sacrificial material layers and channel material layers, and the bottommost layer of the stacked material layers being a sacrificial material layer; Forming discrete mask layers on the stacked material layers in the first and second regions; In the device regions, forming a sacrificial mask layer between the mask layer in the first region and the mask layer in the second region, the sacrificial mask layer having an etching resistance less than that of the mask layer; Etching the stacked material layers and a partial thickness of the initial substrate using the mask layer and the sacrificial mask layer as masks to form device openings, the step of forming the device openings including: removing the sacrificial mask layer; etching the sacrificial material layer using the mask layer as a mask with the top of the channel material layer as an etching stop position; etching the channel material layer using the mask layer as a mask with the top of the sacrificial material layer as an etching stop position; Forming a dielectric wall in the device openings.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of providing the substrate, the substrate further includes an isolation region between the device regions; with the direction parallel to the substrate surface and perpendicular to the intersection line of the device regions and the isolation region as the lateral direction, the lateral dimension of the isolation region is greater than the lateral spacing between the first and second regions; In the step of etching the stacked material layers and a partial thickness of the initial substrate using the mask layer and the sacrificial mask layer as masks to form device openings, etching the stacked material layers and a partial thickness of the initial substrate using the mask layer and the sacrificial mask layer as masks to form isolation openings, the depth of the isolation openings being greater than the depth of the device openings; In the step of forming a dielectric wall in the device openings, forming an isolation structure in the isolation openings.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, In the step of providing the substrate, the top three film layers in the stacked material layers are sequentially used as a first film layer, a second film layer, and a third film layer from top to bottom; The step of forming the isolation openings includes: In the isolation region, when etching the first film layer with the top of the second film layer as an etching stop position, a partial thickness of the first film layer between the first and second regions is etched; In the isolation region, when etching and removing the third film layer, the first film layer between the first and second regions is removed.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The step of etching the stacked material layers and a partial thickness of the initial substrate using the mask layer and the sacrificial mask layer as masks to form device openings includes: Using the bottommost channel material layer in the device region as an etching stop layer, when etching the sacrificial material layer, using the top of the initial substrate in the isolation region as an etching stop layer to etch the bottommost sacrificial material layer in the isolation region; In the step of etching the bottommost channel material layer and the sacrificial material layer in the device region using the mask layer as a mask, using the top of the initial substrate as an etching stop position.

5. The method for forming a semiconductor structure according to claim 3, characterized in that, The first film layer is a sacrificial material layer or a channel material layer; In the step of etching the stacked material layer using the sacrificial mask layer and the mask layer as masks, the etching selectivity between the sacrificial mask layer and the first film layer is 1 to 15.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, The first film layer is a sacrificial material layer. The topmost sacrificial material layer is used as the top sacrificial material layer, and the thickness of the top sacrificial material layer is greater than the thickness of the sacrificial material layer.

7. The method for forming a semiconductor structure according to claim 1, characterized in that, In the step of forming the sacrificial mask layer, the material of the sacrificial mask layer is the same as that of the sacrificial material layer.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the sacrificial mask layer includes silicon germanide.

9. The method for forming a semiconductor structure according to claim 1, characterized in that, In the device region, the step of forming a sacrificial mask layer between the mask layer in the first region and the mask layer in the second region includes: Forming a sacrificial mask material layer on the mask layer and the stacked material layer exposed by the mask layer; removing the sacrificial mask material layer on the top of the mask layer and the surface of the stacked material layer, and the remaining sacrificial mask material layer located between the mask layer in the first region and the mask layer in the second region is used as the sacrificial mask layer.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The sacrificial mask material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.

11. The method for forming a semiconductor structure according to claim 9, characterized in that, In the step of forming the sacrificial mask material layer, twice the thickness of the sacrificial mask material layer is greater than the lateral spacing between the mask layer in the first region and the mask layer in the second region.

12. The method for forming a semiconductor structure according to claim 9, characterized in that, An isotropic etching process is used to remove the sacrificial mask material layer on the top of the mask layer and the surface of the stacked material layer.

13. The method for forming a semiconductor structure according to claim 1, wherein, The step of etching the stacked material layer and a partial thickness of the initial substrate using the mask layer and the sacrificial mask layer as masks to form a device opening includes: Using the top of the initial substrate in the device region as the etching stop position, etching the bottommost sacrificial material layer in the device region using the mask layer as a mask, using the remaining channel material layer as the channel layer, using the remaining sacrificial material layer as the sacrificial layer, and using the stacked sacrificial layer and channel layer as the stacked structure; After forming the stacked structure, etching the initial substrate using the mask layer as a mask to form the device opening.

14. The method for forming a semiconductor structure according to claim 1, wherein, Using the mask layer and the sacrificial mask layer as masks, a dry etching process is used to etch the stacked material layer and a partial thickness of the initial substrate to form the device opening between the first region and the second region.

15. The method for forming a semiconductor structure according to claim 1, wherein, In the step of etching the stacked material layer and a partial thickness of the initial substrate using the mask layer and the sacrificial mask layer as masks, a stacked structure, as well as a substrate and fins located on the substrate, are respectively formed. The substrate, fins, and the stacked structure enclose an opening, and the opening located in the device region is used as the device opening; In the step of forming a dielectric wall in the device opening, the dielectric wall includes a bottom dielectric wall located between the fins and a top dielectric wall located between the stacked structures, and the stress of the bottom dielectric wall is less than the stress of the top dielectric wall.

16. The method for forming a semiconductor structure according to claim 15, wherein, The material of the bottom dielectric wall includes silicon oxide.

17. The method for forming a semiconductor structure according to claim 15, wherein, The material of the top dielectric wall includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, boron nitride silicon, and boron nitride carbon silicon.

18. The method for forming a semiconductor structure according to claim 1, wherein, The step of forming a mask layer on the stacked material layer in the first region and the second region includes: Form a mask material layer on the stacked material layer; form a core layer on the mask material layer; Conformally coat a spacer material layer on the core layer and the mask material layer exposed by the core layer; using the top of the mask material layer as the removal stop position, remove the spacer material layer on the top of the core layer and the surface of the mask material layer, and the remaining spacer material layer on the sidewall of the core layer serves as the spacer layer; after forming the spacer layer, remove the core layer; use the spacer layer as a mask to etch the mask material layer to form a mask layer; The method for forming the semiconductor structure further includes: after forming the mask layer, removing the spacer layer.

19. The method for forming a semiconductor structure according to claim 18, wherein, Use a maskless dry etching process to remove the spacer material layer on the top of the core layer and the mask material layer.

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