Semiconductor Structure and Method of Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The semiconductor structure includes: a substrate; a channel structure, discrete on the substrate in a device region; a power rail line, in the substrate in a power rail region; a gate structure, spanning across the channel structure; source / drain doping regions, in the channel structure on both sides of the gate structure; an interlayer dielectric layer, on the side of the gate structure; a power rail contact plug, penetrating through a partial thickness of the interlayer dielectric layer at the top of the power rail line, and in full contact with the top surface of the power rail line along the longitudinal direction; a source / drain contact layer, in the interlayer dielectric layer and in contact with the source / drain doping regions, and spanning across the power rail line in a projection plane parallel to the substrate. The full contact of the power rail contact plug with the top surface of the power rail line along the longitudinal direction increases the longitudinal dimension of the power rail contact plug and the contact area between the power rail contact plug and the power rail line, which is beneficial to reducing the resistance of the power rail contact plug and the contact resistance with the power rail line.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] Logic chips are composed of standard cells. The size of a standard cell depends on the metal pitch, the standard cell height, the polysilicon pitch, and whether it is a single diffusion barrier (SDB) or a double diffusion barrier (DDB). For many years, chip scaling has been driven by the scaling of the metal pitch (MP) and the polysilicon pitch (PP). However, MP scaling faces challenges such as lithography process limits and increased resistance, and due to device issues, polysilicon pitch scaling has slowed down. The introduction of design-technology co-optimization (DTCO) has made compressing the standard cell height the main scaling option. As the cell height gradually shrinks, the number of fins of each individual device in each cell also gradually decreases, which will also lead to a decrease in the drive current.

[0003] The widths of the power rails (VDD and VSS) of a standard cell are usually weighted into the value of the MP. The power rails supply power to different components of the chip and are generally provided by metal layers in the back-end-of-line (BEOL) process. However, the power rails occupy a relatively large amount of space.

[0004] To meet the continuous need for logic chip scaling, when the metal pitch is very tight, in order to optimize the power supply capacity, one current method is to move the power rails down into the substrate to form buried power rails (BPR).

[0005] In the buried power rail structure, the power rails are buried in the substrate and penetrate into the shallow trench isolation (STI) module, which is beneficial to releasing the wiring resources of the interconnection; moreover, the buried power rails provide a lower resistance local current distribution for the technology that increases the BEOL resistance by using pitch scaling; in addition, the buried power rails are also beneficial to reducing the influence of the grid-like distribution of VDD, VSS, word lines, and bit lines on wiring congestion and resistance degradation, and improving the write margin and read speed.

[0006] However, the performance of current devices still needs to be improved. Summary of the Invention

[0007] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which are beneficial to reducing the resistance of the power rail contact plugs and the contact resistance between the power rail lines and the power rail contact plugs, and optimizing the performance of the semiconductor structure.

[0008] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate including a plurality of discrete device regions and a power rail region located between the device regions; a channel structure disposed on the substrate of the device regions; a power rail line located in the substrate of the power rail region, both the power rail line and the channel structure extending in a lateral direction, and a direction perpendicular to the lateral direction being a longitudinal direction; a gate structure located on the substrate and spanning the channel structure; source / drain doping regions located in the channel structure on both sides of the gate structure; an interlayer dielectric layer located on the side of the gate structure and covering the source / drain doping regions and the power rail line; a power rail contact plug penetrating a partial thickness of the interlayer dielectric layer at the top of the power rail line, and in the longitudinal direction, the power rail contact plug being in full contact with the top surface of the power rail line; a source / drain contact layer located in the interlayer dielectric layer at the top of the source / drain doping region and in contact with the source / drain doping region, the source / drain contact layer being located on the power rail contact plug and covering the top surface of the power rail contact plug, and in a projection plane parallel to the substrate, the source / drain contact layer spanning the power rail line.

[0009] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate including a plurality of discrete device regions and a power rail region located between the device regions, a discrete channel structure being formed on the substrate of the device regions, a power rail line being formed in the substrate of the power rail region, both the power rail line and the channel structure extending in a lateral direction, a direction perpendicular to the lateral direction being a longitudinal direction, a gate structure being formed on the substrate and spanning the channel structure, source / drain doping regions being formed in the channel structure on both sides of the gate structure, and an interlayer dielectric layer covering the source / drain doping regions and the power rail line being formed on the side of the gate structure; forming an interconnect trench penetrating the interlayer dielectric layer at the top of the source / drain doping region and a conductive via located at the bottom of the interconnect trench and penetrating the interlayer dielectric layer on the top of the power rail line, in a projection plane parallel to the substrate, the interconnect trench spanning the power rail line, and in the longitudinal direction, the bottom of the conductive via exposing the entire top surface of the power rail line; filling the conductive via and the interconnect trench to form a power rail contact plug filled in the conductive via and a source / drain contact layer filled in the interconnect trench, in the longitudinal direction, the power rail contact plug being in full contact with the top surface of the power rail line, and the source / drain contact layer being in contact with the source / drain doping region.

[0010] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0011] In the semiconductor structure provided by the embodiment of the present invention, the power rail contact plug penetrates through a partial thickness of the interlayer dielectric layer at the top of the power rail line. Along the longitudinal direction, the top surface of the power rail contact plug is in full contact with the top surface of the power rail line. Compared with the situation where the power rail contact plug only contacts a partial top surface of the power rail line along the longitudinal direction, the embodiment of the present invention increases the size of the power rail contact plug along the longitudinal direction and the contact area between the power rail contact plug and the power rail line. Furthermore, it is beneficial to reduce the resistance of the power rail contact plug and the contact resistance between the power rail line and the power rail contact plug, optimizing the performance of the semiconductor structure.

[0012] In an optional solution, the semiconductor structure of the embodiment of the present invention further includes: a dividing layer that penetrates through the source-drain contact layer located between the power rail contact plug and the adjacent channel structure. The dividing layer divides the source-drain contact layer along the longitudinal direction. By providing the dividing layer, based on design requirements, the source-drain contact layer is disconnected from the power rail contact plug that does not need to be electrically connected. Moreover, the embodiment of the present invention can also adjust the size and position of the dividing layer to adjust the distance between the dividing layer and the power rail contact plug, such that the source-drain contact layer connected to the power rail contact plug also extends to the other side of the power rail contact plug. Furthermore, it is beneficial to increase the volume of the power rail contact plug and the connected source-drain contact layer, correspondingly reducing the resistance of the power rail contact plug and the source-drain contact layer, and improving the performance of the semiconductor structure.

[0013] In the method for forming the semiconductor structure provided by the embodiment of the present invention, an interconnect groove and a conductive via located at the bottom of the interconnect groove and penetrating through the interlayer dielectric layer on the top of the power rail line are formed. On the projection plane parallel to the substrate, the interconnect groove straddles the power rail line. Along the longitudinal direction, the entire top surface of the power rail line is exposed at the bottom of the conductive via. Compared with the situation where only a partial top surface of the power rail line is exposed by the conductive via along the longitudinal direction, the embodiment of the present invention increases the size of the power rail line exposed by the conductive via and the opening size of the conductive via. Thus, in the step of forming the power rail contact plug filled in the conductive via, the size of the power rail contact plug along the longitudinal direction and the contact area between the power rail contact plug and the power rail line are increased. Furthermore, it is beneficial to reduce the resistance of the power rail contact plug and the contact resistance between the power rail line and the power rail contact plug, optimizing the performance of the semiconductor structure.

[0014] In addition, in the method for forming a semiconductor structure provided by an embodiment of the present invention, interconnected interconnect grooves and conductive vias are first formed, so that in the same step, through a filling process, a power rail contact plug filled in the conductive via and a source / drain contact layer filled in the interconnect groove can be formed. The power rail contact plug and the source / drain contact layer are correspondingly an integrated structure, which is beneficial to reducing the contact resistance between the power rail contact plug and the source / drain contact layer and improving the performance of the semiconductor structure.

[0015] In an optional solution, the method for forming a semiconductor structure according to an embodiment of the present invention further includes: after forming the source / drain contact layer and the power rail contact plug, forming a dividing layer that penetrates the source / drain contact layer located between the power rail contact plug and an adjacent channel structure, and the dividing layer longitudinally divides the source / drain contact layer; or, in the step of forming the interconnect groove and the conductive via, a dividing layer is formed at the bottom of the interconnect groove between the conductive via and an adjacent channel structure, and the dividing layer protrudes from the bottom of the interconnect groove and longitudinally divides the interconnect groove; by forming the dividing layer, based on design requirements, the source / drain contact layer is disconnected from the power rail contact plug that does not need to be electrically connected. Moreover, in an embodiment of the present invention, the distance between the dividing layer and the power rail contact plug can also be adjusted by adjusting the size and position of the dividing layer, so that the source / drain contact layer connected to the power rail contact plug also extends on the interlayer dielectric layer on the other side of the power rail contact plug, which is beneficial to increasing the volume of the power rail contact plug and the connected source / drain contact layer, correspondingly reducing the resistance of the power rail contact plug and the source / drain contact layer, and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figures 1 to 2 is a schematic structural diagram of a semiconductor structure;

[0017] [[ID=1'2]] Figures 3 to 4 is a schematic structural diagram of an embodiment of the semiconductor structure of the present invention;

[0018] Figures 5 to 17 is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0019] As can be seen from the background art, the performance of current devices still needs to be improved. The reason why the performance of the device still needs to be improved is analyzed in combination with a semiconductor structure. Figures 1 to 2 shows a schematic structural diagram of a semiconductor structure. Among them, Figure 1 is a top view, Figure 2 is Figure 1 a cross-sectional view along the yy direction.

[0020] As Figure 1 and Figure 2As shown, the semiconductor structure includes: a substrate 10, including a device region 10a and a power rail region 10b; fins 11, discrete on the substrate 10 in the device region 10a; an isolation structure 12, located on the substrate 10 exposed by the fins 11, the top surface of the isolation structure 12 being lower than the top surface of the fins 11; a power rail line 13, located in the substrate 10 and the isolation structure 12 in the power rail region 10b, both the power rail line 13 and the fins 11 extending along the transverse direction (such as Figure 1 shown by the X direction in Figure 1 ), and the direction perpendicular to the transverse direction is the longitudinal direction (such as shown by the Y direction in ); a gate structure 14, located on the isolation structure 12 and spanning the fins 11; source / drain doping regions 15, located in the fins 11 on both sides of the gate structure 14; an interlayer dielectric layer 16, located on the isolation structure 12 on the side of the gate structure 14 and covering the source / drain doping regions 15; a power rail contact plug 17, penetrating the interlayer dielectric layer 16 above the power rail line 13 and contacting a part of the top surface of the power rail line 13; a source / drain contact layer 18, penetrating the interlayer dielectric layer 16 above the source / drain doping regions 15, and in the longitudinal direction, the source / drain contact layer 18 contacting the power rail contact plug 17.

[0021] The power rail contact plug 17 is used to electrically connect the power rail line 13 with an external circuit or other interconnect structures.

[0022] However, the power rail contact plug 17 only contacts a part of the top surface of the power rail line 13, the contact area between the power rail contact plug 17 and the power rail line 13 is small, and as the device size is gradually scaled down, the critical dimension (CD) of the power rail contact plug 17 is also getting smaller. At the same time, since the power rail line 13 is buried in the substrate 10 and the isolation structure 12, in order to make the power rail contact plug 17 contact the isolation structure 12, the depth of the power rail contact plug 17 is also relatively large, resulting in an increasing aspect ratio of the power rail contact plug 17. The resistance of the power rail contact plug 17 is high, and the contact resistance between the power rail contact plug 17 and the power rail line 13 is large, resulting in poor performance of the formed device.

[0023] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure, including a power rail contact plug. The power rail contact plug penetrates through a partial thickness interlayer dielectric layer on the top of the power rail line. Along the longitudinal direction, the power rail contact plug is in full contact with the top surface of the power rail line. Compared with the situation where the power rail contact plug only contacts a partial top surface of the power rail line along the longitudinal direction, the embodiment of the present invention increases the size of the power rail contact plug along the longitudinal direction and the contact area between the power rail contact plug and the power rail line, thereby being beneficial to reducing the resistance of the power rail contact plug and the contact resistance between the power rail line and the power rail contact plug, and optimizing the performance of the semiconductor structure.

[0024] To make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following will describe the specific embodiments of the present invention in detail with reference to the drawings. Refer to Figure 3 and Figure 4 , Figure 3 is a top view, Figure 4 is Figure 3 a cross-sectional view along the yy direction, showing a schematic structural diagram of an embodiment of the semiconductor structure of the present invention.

[0025] As Figure 3 and Figure 4 shown, in this embodiment, the semiconductor structure includes: a substrate 100, including a plurality of discrete device regions 100a and a power rail region 100b located between the device regions 100a; a channel structure 110, discrete on the substrate 100 of the device region 100a; a power rail line 120, located in the substrate 100 of the power rail region 100b. Both the power rail line 120 and the channel structure 110 extend along the transverse direction (as shown by the X direction in Figure 3 ), and the direction perpendicular to the transverse direction is the longitudinal direction (as shown by the Y direction in Figure 3 ); a gate structure 130, located on the substrate 100 and spanning across the channel structure 110; source / drain doping regions 140, located in the channel structure 110 on both sides of the gate structure 130; an interlayer dielectric layer 150, located on the side of the gate structure 130 and covering the source / drain doping regions 140 and the power rail line 120; a power rail contact plug 200, penetrating through a partial thickness interlayer dielectric layer 150 on the top of the power rail line 120. Along the longitudinal direction, the power rail contact plug 200 is in full contact with the top surface of the power rail line 120; a source / drain contact layer 210, located in the interlayer dielectric layer 150 on the top of the source / drain doping regions 140 and in contact with the source / drain doping regions 140. The source / drain contact layer 210 is located on the power rail contact plug 200 and covers the top surface of the power rail contact plug 200. On a projection plane parallel to the substrate 100, the source / drain contact layer 210 spans across the power rail line 120.

[0026] The substrate 100 is used to provide a process platform for the formation of a semiconductor structure. In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials suitable for process requirements or easy to integrate, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide.

[0027] The device region 100a is used to form field effect transistors, such as one or both of PMOS transistors and NMOS transistors. The power rail region 100b is used to arrange power rail lines 120.

[0028] During device operation, the channel structure 110 is used to provide a conductive channel for the field effect transistor. In this embodiment, the number of channel structures 110 is multiple, and the multiple channel structures 110 are arranged in parallel at intervals.

[0029] As an example, the channel structure 110 is a fin. Correspondingly, the device region 100a is used to form a fin field effect transistor (FinFET). In this embodiment, the material of the fin is the same as the material of the substrate 100, and the material of the fin is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the material of the fin may also be different from the material of the substrate.

[0030] In some other embodiments, the channel structure may also be a channel structure layer spaced from the substrate. The channel structure layer includes one or more channel layers arranged at intervals, and the gate structure covers a part of the top of the channel structure and surrounds the channel layer. Correspondingly, the device region is used to form a gate-all-around (GAA) transistor or a forksheet transistor.

[0031] In this embodiment, the semiconductor structure further includes: an isolation structure 115, located on the substrate 100 and covering a part of the sidewalls of the channel structure 110. The top surface of the isolation structure 115 is lower than the top surface of the channel structure 110.

[0032] The isolation structure 115 is used to isolate adjacent channel structures 110, and the isolation structure 115 is also used to isolate the substrate 100 from the gate structure 130. In this embodiment, the channel structure 110 is a fin, and the part of the fin exposed from the isolation structure 115 is used as an active fin, and the active fin is used to provide a conductive channel during device operation.

[0033] In this embodiment, the isolation structure 115 is a shallow trench isolation (STI) structure, and the material of the isolation structure 115 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride.

[0034] In this embodiment, the power rail line 120 is used to supply power to different components of the chip. In this embodiment, the power rail line 120 is located in the substrate 100 of the power rail region 100b. The power rail line 120 is a buried power rail (BPR), which is beneficial to releasing the wiring resources of the backend interconnection and reducing the height of standard cells to meet the continuous need for logic chip scaling. In addition, the buried power rail adopts the technology of pitch scaling to increase the resistance of the Back End of Line (BEOL), which is also beneficial to providing a lower resistance local current distribution.

[0035] The power rail line 120 is in a strip structure. The power rail line 120 is parallel to the extending direction of the channel structure 110, and there is a gap between the power rail line 120 and the channel structure 110.

[0036] The material of the power rail line 120 is a conductive material. In this embodiment, the material of the power rail line 120 is a metal material, such as one or more of Co, W, Ni, and Ru. By selecting these materials, the resistivity of the power rail line 120 is low, which is beneficial to improving the RC delay and increasing the processing speed of the chip.

[0037] In this embodiment, the power rail line 120 is located in the substrate 100 and the isolation structure 115 of the power rail region 100b.

[0038] In this embodiment, the gate structure 130 is located on the isolation structure 115. Therefore, the top surface of the power rail line 120 is lower than the top surface of the isolation structure 115, so as to prevent the gate structure 130 from contacting the power rail line 120.

[0039] [[ID=ID=]]

[0040] Correspondingly, in this embodiment, the semiconductor structure further includes: a covering dielectric layer 160 (refer to Figure 6 ), which is located in the isolation structure 115 and covers the top of the power rail line 120.

[0041] ​The covering dielectric layer 160 is used to isolate the power rail line 120 from the gate structure 130, or to isolate the power rail line 120 from other conductive structures located on the isolation structure 115.

[0042] The material of the covering dielectric layer 160 is a dielectric material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride. In this embodiment, the material of the covering dielectric layer 160 is the same as that of the isolation structure 115, which is beneficial to improving process compatibility.

[0043] In this embodiment, the top surface of the covering dielectric layer 160 is flush with the top surface of the isolation structure 115.

[0044] In this embodiment, the semiconductor structure further includes: an insulating layer 125, located between the power rail line 120 and the substrate 100, between the power rail line 120 and the isolation structure 115, and between the covering dielectric layer 160 and the isolation structure 115.

[0045] The insulating layer 125 is used to achieve insulation between the power rail line 120 and the substrate 100. Therefore, the material of the insulating layer 125 is an insulating material, such as materials like silicon oxide, silicon oxynitride, or silicon nitride.

[0046] [[ID=Q15]]The gate structure 130 serves as a device gate and is used to control the opening or closing of a conductive channel during device operation. In this embodiment, the gate structure 130 is located on the isolation structure 115.

[0047] In this embodiment, the channel structure 110 is a fin, and the gate structure 130 correspondingly straddles the fin and covers part of the top and part of the sidewalls of the fin. In other embodiments, when the channel structure is a channel structure layer spaced apart from the substrate and the channel structure layer includes one or more spaced-apart channel layers, the gate structure correspondingly surrounds the channel layer.

[0048] In this embodiment, the extending direction of the gate structure 130 (as shown by the Y direction in Figure 3 is perpendicular to the extending directions of the channel structure 110 and the power rail line 120, that is, the gate structure 130 extends longitudinally.

[0049] In this embodiment, the gate structure 130 is a metal gate structure. The gate structure 130 includes a gate dielectric layer (not shown in the figure), a work function layer (not shown in the figure) located on the gate dielectric layer, and a gate electrode layer (not shown in the figure) located on the work function layer.

[0050] In other embodiments, according to actual process requirements, the gate structure can also be a polysilicon gate structure.

[0051] It should be noted that in the actual process, a gate cap layer (not shown in the figure) may also be formed on the top of the gate structure 130. The gate cap layer is used to protect the top of the gate structure 130 to reduce the probability of damage to the gate structure 130.

[0052] The source / drain doping regions 140 are used to provide a carrier source when the device is operating. In this embodiment, the source / drain doping regions 140 are located in the fins on both sides of the gate structure 130. In this embodiment, when forming an NMOS transistor, the source / drain doping regions 140 include a stress layer doped with N-type ions; when forming a PMOS transistor, the source / drain doping regions 140 include a stress layer doped with P-type ions.

[0053] The interlayer dielectric layer 150 is used to isolate adjacent devices, and the interlayer dielectric layer 150 is also used to electrically isolate adjacent conductive structures. In this embodiment, the interlayer dielectric layer 150 is located on the isolation structure 115 on the side of the gate structure 130, and the interlayer dielectric layer 150 also covers the covering dielectric layer 160.

[0054] The material of the interlayer dielectric layer 150 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 150 is silicon oxide.

[0055] The power rail contact plug (Via-Buried Power Rail, VBPR) 200 is in contact with the power rail line 120, so that an electrical connection is achieved between the power rail line 120 and an external circuit or other interconnect structures, and thus power is supplied to different components of the chip.

[0056] In this embodiment, the longitudinal power rail contact plug 200 is in full contact with the top surface of the power rail line 120. Compared with the case where the longitudinal power rail contact plug only contacts a part of the top surface of the power rail line, this embodiment increases the longitudinal dimension of the power rail contact plug 200 and the contact area between the power rail contact plug 200 and the power rail line 120. Therefore, it is beneficial to reduce the resistance of the power rail contact plug 200 and the contact resistance between the power rail line 120 and the power rail contact plug 200, and optimize the performance of the semiconductor structure.

[0057] In this embodiment, the fact that the longitudinal power rail contact plug 200 is in full contact with the top surface of the power rail line 12 means that, in the longitudinal direction, the dimension of the power rail line 120 in contact with the power rail contact plug 200 is the same as the width of the power rail line 120 in the longitudinal direction, so that the top surface of the power rail line 120 in the longitudinal direction can be completely covered by the power rail contact plug 200, and thus the power rail contact plug 200 and the power rail line 120 obtain a maximum contact area and the power rail contact plug 200 obtains a maximum longitudinal dimension.

[0058] In this embodiment, the power rail contact plug 200 penetrates through the overlying dielectric layer 160 and the interlayer dielectric layer 150 on the top of the power rail line 120.

[0059] The source / drain contact layer 210 is in contact with the source / drain doped region 140, so as to electrically connect the source / drain doped region 140 with an external circuit or other interconnect structures.

[0060] In this embodiment, the source / drain contact layer 210 is located on the power rail contact plug 200 and covers the top surface of the power rail contact plug 200, so that the source / drain contact layer 210 is electrically connected to the power rail line 120 through the power rail contact plug 200. Furthermore, when the device is operating, the source / drain doped region 140 can be powered through the power rail line 120.

[0061] In this embodiment, the source / drain contact layer 210 extends along the longitudinal direction, and the extension direction of the source / drain contact layer 210 is perpendicular to the extension direction of the power rail line 120.

[0062] In this embodiment, on the projection plane parallel to the substrate 100, the source / drain contact layer 210 straddles the power rail line 120, and the extension direction of the source / drain contact layer 210 is perpendicular to the extension direction of the power rail line for the 120. At the same time, the source / drain contact layer 210 is located on the power rail contact plug 200 and covers the top surface of the power rail contact plug 200. Thus, the position of the power rail contact plug 200 can be accurately positioned through the positions of the source / drain contact layer 210 and the power rail line 120, such that the power rail contact plug 200 is located at the overlapping position of the patterns of the source / drain contact layer 210 and the power rail line 120.

[0063] In this embodiment, the source / drain contact layer 210 and the power rail contact plug 200 are formed by a dual damascene process. The source / drain contact layer 210 and the power rail contact plug 200 are of an integrated structure, which is beneficial to further reducing the resistance of the source / drain contact layer 210 and the power rail contact plug 200, as well as the contact resistance, improving the contact performance of the source / drain contact layer 210 and the power rail contact plug 200, and further improving the performance of the semiconductor structure.

[0064] Therefore, the source / drain contact layer 210 and the power rail contact plug 200 are made of the same material. The source / drain contact layer 210 and the power rail contact plug 200 are made of a conductive material. In this embodiment, the source / drain contact layer 210 and the power rail contact plug 20 are made of a metal material, such as one or several of W, Co, Cu, Ru, and Ni.

[0065] It should be noted that for the sake of illustration and description, in this embodiment, the power rail line 120 is located between two adjacent device regions 100a as an example. Channel structures 110 and source / drain doping regions 140 located in the channel structures 110 are provided on both sides of the power rail line 120. However, the positional relationship between the power rail line 120, the channel structures 110, and the source / drain doping regions 140 is not limited to this.

[0066] For example: In other embodiments, in the longitudinal direction, the power rail line has a channel structure provided on only one side and no channel structure on the other side. When the power rail line has a channel structure provided on only one side, on the projection plane parallel to the substrate, the source / drain contact layer straddles the power rail line, enabling the source / drain contact layer to also extend into the interlayer dielectric layer on the other side of the power rail line, correspondingly increasing the volume of the source / drain contact layer. And the source / drain contact layer and the power rail line are of an integrated structure, thus facilitating reducing the resistance between the source / drain contact layer and the power rail line and optimizing the performance of the semiconductor structure.

[0067] As an example, the semiconductor structure further includes: a splitting layer 230 that penetrates the source / drain contact layer 210 located between the power rail contact plug 200 and the adjacent channel structure 110, and the splitting layer 230 longitudinally splits the source / drain contact layer 210.

[0068] By providing the splitting layer 230, based on design requirements, the source / drain contact layer 210 is disconnected from the power rail contact plug 200 that does not need to be electrically connected. Moreover, in this embodiment, the distance d between the splitting layer 230 and the power rail contact plug 200 can be adjusted by adjusting the size w and position of the splitting layer 230, such that the source / drain contact layer 210 connected to the power rail contact plug 200 also extends to the other side of the power rail contact plug 200. Furthermore, this is conducive to increasing the volume of the power rail contact plug 200 and the connected source / drain contact layer 210, correspondingly reducing the resistance of the power rail contact plug 200 and the source / drain contact layer 210, and enhancing the performance of the semiconductor structure.

[0069] To ensure the splitting function of the splitting layer 230, the material of the splitting layer 230 is a dielectric material. In this embodiment, the splitting layer 230 can be a single-layer or multi-layer structure, and the material of the splitting layer 230 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon carbon oxide.

[0070] It should be noted that the width w of the splitting layer 230 along the longitudinal direction should not be too small or too large. If the width w of the splitting layer 230 along the longitudinal direction is too small, it is easy to reduce the splitting effect of the splitting layer 230 on the source-drain contact layer 210; if the width w of the splitting layer 230 along the longitudinal direction is too large, it is easy to cause the splitting layer 230 to occupy too large an area. Therefore, in this embodiment, the width w of the splitting layer 230 along the longitudinal direction is 5 nm to 30 nm.

[0071] It should also be noted that in this embodiment, the semiconductor structure including the splitting layer 230 is taken as an example for illustration. In other embodiments, according to actual process requirements, the semiconductor structure may not include the splitting layer, or the splitting layer may be provided only in the source-drain contact layer in some regions.

[0072] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 5 to 17 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0073] Reference Figure 5 and Figure 6 , Figure 5 is a top view, Figure 6 is <> Figure 5 is a cross-sectional view along the yy direction. A substrate 100 is provided, which includes a plurality of discrete device regions 100a and power rail regions 100b located between the device regions 100a. Discrete channel structures 110 are formed on the substrate 100 of the device regions 100a, and power rail lines 120 are formed in the substrate 100 of the power rail regions 100b. Both the power rail lines 120 and the channel structures 110 extend along the transverse direction (as shown by the X direction in Figure 5 ), and the direction perpendicular to the transverse direction is the longitudinal direction (as shown by the Y direction in Figure 5 ). A gate structure 130 spanning the channel structures 110 is formed on the substrate 100, source-drain doping regions 140 are formed in the channel structures 110 on both sides of the gate structure 130, and an interlayer dielectric layer 150 covering the source-drain doping regions 140 and the power rail lines 120 is formed on the side of the gate structure 130.

[0074] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0075] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials suitable for process requirements or easy to integrate, such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

[0076] The device region 100a is used to form field effect transistors, such as one or both of PMOS transistors and NMOS transistors. The power rail region 100b is used to arrange the power rail lines 120.

[0077] During device operation, the channel structure 110 is used to provide a conductive channel for the field effect transistor. In this embodiment, the number of channel structures 110 is multiple, and the multiple channel structures 110 are arranged in parallel at intervals.

[0078] As an example, the channel structure 110 is a fin. Correspondingly, the device region 100a is used to form a fin field effect transistor (FinFET). In this embodiment, the material of the fin is the same as the material of the substrate 100, and the material of the fin is silicon. In other embodiments, the material of the fin can also be a semiconductor material suitable for forming a fin, such as germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium, and the material of the fin can also be different from the material of the substrate.

[0079] In some other embodiments, the channel structure can also be a channel structure layer spaced from the substrate. The channel structure layer includes one or more spaced channel layers, and the gate structure covers a part of the top of the channel structure and surrounds the channel layer. Correspondingly, the device region is used to form a gate-all-around (GAA) transistor or a forksheet transistor.

[0080] In this embodiment, an isolation structure 115 covering a part of the sidewalls of the channel structure 110 is further formed on the substrate 100. The top surface of the isolation structure 115 is lower than the top surface of the channel structure 110.

[0081] The isolation structure 115 is used to isolate adjacent channel structures 110, and the isolation structure 115 is also used to isolate the substrate 100 from the gate structure 130. In this embodiment, the channel structure 110 is a fin, and the part of the fin exposed from the isolation structure 115 is used as an active fin, and the active fin is used to provide a conductive channel during device operation.

[0082] In this embodiment, the isolation structure 115 is a shallow trench isolation (STI) structure, and the material of the isolation structure 115 is an insulating material, such as one or more of silicon oxide, silicon oxynitride and silicon nitride.

[0083] The power rail line 120 is used to supply power to different components of the chip. In this embodiment, the power rail line 120 is located in the substrate 100 of the power rail region 100b. The power rail line 120 is a buried power rail (BPR), which is beneficial to releasing the wiring resources of the backend interconnection and reducing the height of standard cells to meet the continuous need for logic chip scaling. In addition, the buried power rail uses the technology of pitch scaling to increase the resistance of the backend of line (BEOL), which is also beneficial to providing a lower resistance local current distribution.

[0084] In this embodiment, the power rail line 120 has a strip-shaped structure. The power rail line 120 is parallel to the extending direction of the channel structure 110, and there is a gap between the power rail line 120 and the channel structure 110.

[0085] The material of the power rail line 120 is a conductive material. In this embodiment, the material of the power rail line 120 is a metal material, including one or more of Co, W, Ni, and Ru. By selecting these materials, the resistivity of the power rail line 120 is low, which is beneficial to improving the RC delay and increasing the processing speed of the chip.

[0086] In this embodiment, the power rail line 120 is located in the substrate 100 and the isolation structure 115 of the power rail region 100b.

[0087] In this embodiment, the gate structure 130 is located on the isolation structure 115. Therefore, the top surface of the power rail line 120 is lower than the top surface of the isolation structure 115, thereby preventing the gate structure 130 from contacting the power rail line 120.

[0088] Correspondingly, in this embodiment, a covering dielectric layer 160 is further formed in the isolation structure 115 on the top of the power rail line 120.

[0089] The covering dielectric layer 160 is used to isolate the power rail line 120 from the gate structure 130, or to isolate the power rail line 120 from other conductive structures located on the isolation structure 115. The material of the covering dielectric layer 160 is a dielectric material, such as one or more of silicon oxide, silicon oxynitride, and silicon nitride. In this embodiment, the material of the covering dielectric layer 160 is the same as that of the isolation structure 115, which is beneficial to improving the process compatibility.

[0090] In this embodiment, the top surface of the covering dielectric layer 160 is flush with the top surface of the isolation structure 115.

[0091] In this embodiment, an insulating layer 125 is further formed between the power rail line 120 and the substrate 100, between the power rail line 120 and the isolation structure 115, and between the covering dielectric layer 160 and the isolation structure 115.

[0092] The insulating layer 125 is used to insulate the power rail line 120 from the substrate 100. Therefore, the material of the insulating layer 125 is an insulating material, such as silicon oxide, silicon oxynitride, or silicon nitride, etc.

[0093] The gate structure 130 serves as a device gate and is used to control the opening or closing of the conductive channel during device operation. In this embodiment, the gate structure 130 is located on the isolation structure 115.

[0094] In this embodiment, the channel structure 110 is a fin, and the gate structure 130 correspondingly straddles the fin and covers part of the top and part of the sidewalls of the fin. In other embodiments, when the channel structure is a channel structure layer spaced from the substrate and the channel structure layer includes one or more spaced channel layers, the gate structure correspondingly surrounds the channel layer.

[0095] In this embodiment, the extending direction of the gate structure 130 (as Figure 5 shown by the Y direction in the figure) is perpendicular to the extending directions of the channel structure 110 and the power rail line 120, that is, the gate structure 130 extends longitudinally.

[0096] In this embodiment, the gate structure 130 is a Metal Gate structure. The gate structure 130 includes a gate dielectric layer (not shown in the figure), a work function layer (not shown in the figure) located on the gate dielectric layer, and a gate electrode layer (not shown in the figure) located on the work function layer.

[0097] In other embodiments, according to the actual process, the gate structure can also be a polysilicon gate structure.

[0098] It should be noted that in the actual process, a gate cap layer (not shown in the figure) can also be formed on the top of the gate structure 130. The gate cap layer is used to protect the top of the gate structure 130 to reduce the probability of damage to the gate structure 130.

[0099] The source / drain doping region 140 is used to provide a carrier source during device operation. In this embodiment, the source / drain doping region 140 is located in the fins on both sides of the gate structure 130. In this embodiment, when forming an NMOS transistor, the source / drain doping region 140 includes a stress layer doped with N-type ions; when forming a PMOS transistor, the source / drain doping region 140 includes a stress layer doped with P-type ions.

[0100] The interlayer dielectric layer 150 is used to isolate adjacent devices, and the interlayer dielectric layer 150 is also used for electrically isolating adjacent conductive structures. In this embodiment, the interlayer dielectric layer 150 is located on the isolation structure 115 on the side of the gate structure 130, and the interlayer dielectric layer 150 also covers the covering dielectric layer 160.

[0101] The material of the interlayer dielectric layer 150 is an insulating material. In this embodiment, the material of the interlayer dielectric layer 150 is silicon oxide.

[0102] It should be noted that for the convenience of illustration and description, in this embodiment, only the substrate 100, the isolation structure 115, the covering dielectric layer 160, and the interlayer dielectric layer 150 are shown in the cross-sectional schematic diagram.

[0103] Reference Figures 7 to 9 , an interconnect trench 300 (as shown in Figure 9 ) that penetrates the top of the source-drain doped region 140 is formed, and a conductive via 310 (as shown in Figure 9 ) that is located at the bottom of the interconnect trench 300 and penetrates the interlayer dielectric layer 150 on the top of the power supply track line 120. In the projection plane parallel to the substrate 100, the interconnect trench 300 straddles the power supply track line 120, and the entire top surface of the power supply track line 120 is exposed at the bottom of the conductive via 310 along the longitudinal direction.

[0104] The conductive via 310 is used to provide a spatial position for forming a power rail contact plug.

[0105] The entire top surface of the power supply track line 120 is exposed at the bottom of the conductive via 310 along the longitudinal direction. Compared with the case where only a part of the top surface of the power supply track line is exposed at the bottom of the conductive via, in this embodiment, the top area of the power supply track line 120 exposed along the longitudinal direction is increased, and the size of the conductive via 310 along the longitudinal direction is increased. Therefore, in the subsequent step of forming a power rail contact plug filled in the conductive via 310, the power rail contact plug can be in full contact with the top surface of the power supply track line 120 along the longitudinal direction, which is beneficial to increasing the size of the power rail contact plug and the contact area between the power rail contact plug and the power supply track line 120.

[0106] In this embodiment, the entire top surface of the power supply track line 120 is exposed at the bottom of the conductive via 310 along the longitudinal direction. That is to say, in the longitudinal direction, the size of the power supply track line 120 exposed by the conductive via 310 is the same as the width of the power supply track line 120 in the longitudinal direction.

[0107] In this embodiment, in the step of forming the conductive via 310, the conductive via 310 penetrates the covering dielectric layer 160 and the interlayer dielectric layer 150 on the top of the power supply track line 120.

[0108] The interconnecting groove 300 is used to provide a spatial position for forming the source-drain contact layer. The bottom of the interconnecting groove 300 exposes the source-drain doping region 140, so that the subsequent source-drain contact layer can contact the source-drain doping region 140.

[0109] In this embodiment, the interconnecting groove 300 extends along the longitudinal direction, and the extending direction of the interconnecting groove 300 is perpendicular to the extending direction of the power supply track line 120.

[0110] In this embodiment, on the projection plane parallel to the substrate 100, the interconnecting groove 300 straddles the power supply track line 120, and the extending direction of the interconnecting groove 300 is perpendicular to the extending direction of the power supply track line 120. At the same time, the conductive via 310 is located at the bottom of the interconnecting groove 300 and penetrates through the interlayer dielectric layer 150 on the top of the power supply track line 120. Thus, through the positions of the interconnecting groove 300 and the power supply track line 120, the position of the conductive via 310 can be accurately positioned, so that the conductive via 310 is located at the overlapping position of the pattern of the interconnecting groove 300 and the pattern of the power supply track line 120.

[0111] In this embodiment, the conductive via 310 is connected to the interconnecting groove 300, so that the subsequent source-drain contact layer formed in the interconnecting groove 300 and the power supply rail contact plug formed in the conductive via 310 are of an integrated structure, which is beneficial to further reducing the resistance of the source-drain contact layer and the power supply rail contact plug, as well as the contact resistance, and improving the contact performance of the source-drain contact layer and the power supply rail contact plug.

[0112] In this embodiment, the conductive via 310 and the interconnecting groove 300 are formed by a dual damascene process. For example: the conductive via 310 and the interconnecting groove 300 can be formed by using a trench first process, or a via first process, or a trench and via all in one process.

[0113] Specifically, in this embodiment, taking the formation of the conductive via 310 and the interconnecting groove 300 by using a trench first process as an example, an explanation is given.

[0114] As an example, the steps of forming the interconnecting groove 300 and the conductive via 310 include: forming the interconnecting groove 300 that penetrates through a partial thickness of the interlayer dielectric layer 150 on the top of the source-drain doping region 140; forming the conductive via 310 that penetrates through the interlayer dielectric layer 150 at the bottom of the interconnecting groove 300.

[0115] By first forming the interconnect trench 300 and then forming the conductive via 310, during the process of forming the conductive via 310, etching can be self-aligned along the transverse direction with the position of the interconnect trench 300, which is beneficial to reducing the process difficulty of forming the conductive via 310 and increasing the process window of forming the conductive via 310, so as to facilitate the precise positioning of the position of the conductive via 310.

[0116] Specifically, in this embodiment, the process of forming the interconnect trench 300 includes the following steps.

[0117] As Figure 7 and Figure 8 shown, Figure 7 is a top view, Figure 8 is Figure 7 a cross-sectional view along the yy direction. A hard mask layer 155 is formed on the interlayer dielectric layer 150. A mask opening 50 located above the source-drain doping region 140 is formed in the hard mask layer 155. The mask opening 50 extends longitudinally. On the projection plane parallel to the substrate 100, the mask opening 50 straddles the power rail line 120.

[0118] The hard mask layer 155 is used as an etching mask for forming the interconnect trench. The mask opening 50 is used to define the pattern and position of the interconnect trench. For the convenience of schematic illustration and explanation, the pattern and position of the mask opening 50 are schematically shown by a solid line frame in Figure 7 .

[0119] In order to ensure that the hard mask layer 155 can act as an etching mask, the hard mask layer 155 is made of a material having an etching selectivity with respect to the material of the interlayer dielectric layer 150. For example: the material of the hard mask layer 155 can be titanium nitride, titanium oxide, silicon nitride or other materials. As an example, the material of the hard mask layer 155 is titanium nitride.

[0120] On the projection plane parallel to the substrate 100, the mask opening 50 straddles the power rail line 120. Correspondingly, on the projection plane parallel to the substrate 100, the region where the mask opening 50 intersects and coincides with the power rail line 120 defines the formation region of the conductive via.

[0121] As Figure 9 shown, using the hard mask layer 155 as a mask, the interlayer dielectric layer 150 is etched to a partial thickness along the mask opening 50 to form the interconnect trench 300. The interconnect trench 300 exposes the source-drain doping region 140.

[0122] Specifically, an anisotropic dry etching process can be employed to etch the interlayer dielectric layer 150 with a thickness of the portion exposed by the etching mask opening 50. The anisotropic dry etching process has the characteristic of anisotropic etching, which is beneficial to improving the control of the profile morphology of the interconnect trench 300 and precisely controlling the depth of the interconnect trench 300.

[0123] Correspondingly, in this embodiment, the step of forming the conductive via 310 includes: as Figure 9 shown, taking the hard mask layer 155 as the etching stop layer along the transverse direction, etching the interlayer dielectric layer 150 at the bottom of a part of the interconnect trench 300 to form the conductive via 310.

[0124] In the step of forming the conductive via 310, the etching process has a high etching selectivity for the interlayer dielectric layer 150 and the hard mask layer 155, so that the etching process can use the hard mask layer 155 as the etching stop layer along the transverse direction, and then self-alignment of etching can be achieved along the transverse direction, reducing the difficulty of forming the conductive via 310 and being beneficial to precisely positioning the position of the conductive via 310.

[0125] Specifically, an anisotropic dry etching process can be adopted to etch the interlayer dielectric layer 150 at the bottom of a part of the interconnect trench 300 to form the conductive via 310, thereby improving the control of the profile of the conductive via 310.

[0126] Refer to Figure 10 and Figure 11 , Figure 10 which is a top view, Figure 11 and Figure 10 is a cross-sectional view along the yy direction. The conductive via 310 and the interconnect trench 300 are filled to form a power rail contact plug 200 filled in the conductive via 310 and a source / drain contact layer 210 filled in the interconnect trench 300. Along the longitudinal direction, the power rail contact plug 200 is in full contact with the top surface of the power rail line 120, and the source / drain contact layer 210 is in contact with the source / drain doping region 140.

[0127] The power rail contact plug (Via-Buried Power Rail, VBPR) 200 is in contact with the power rail line 120, so that electrical connection is achieved between the power rail line 120 and an external circuit or other interconnect structures, and then power is supplied to different components of the chip.

[0128] In this embodiment, the longitudinal power rail contact plug 200 is in full contact with the top surface of the power rail line 120. Compared with the case where the longitudinal power rail contact plug only contacts a part of the top surface of the power rail line, in this embodiment, the longitudinal dimension of the power rail contact plug 200 and the contact area between the power rail contact plug 200 and the power rail line 120 are increased. Thereby, it is beneficial to reduce the resistance of the power rail contact plug 200 and the contact resistance between the power rail line 120 and the power rail contact plug 200, optimizing the performance of the semiconductor structure.

[0129] In addition, in this embodiment, the interconnected grooves 300 and the conductive vias 310 are formed first, so that subsequently, in the same step, through a filling process, the power rail contact plug 200 filled in the conductive via 310 and the source / drain contact layer 210 filled in the interconnected groove 300 can be formed. The power rail contact plug 200 and the source / drain contact layer 210 are of an integrated structure, which is beneficial to reducing the contact resistance between the power rail contact plug 200 and the source / drain contact layer 210 and improving the performance of the semiconductor structure.

[0130] In this embodiment, the fact that the longitudinal power rail contact plug 200 is in full contact with the top surface of the power rail line 120 means that in the longitudinal direction, the dimension of the power rail line 120 in contact with the power rail contact plug 200 is the same as the width of the power rail line 120 in the longitudinal direction, so that the top surface of the power rail line 120 in the longitudinal direction can be completely covered by the power rail contact plug 200, thereby enabling the power rail contact plug 200 and the power rail line 120 to obtain a maximized contact area and enabling the power rail contact plug 200 to obtain a maximized dimension in the longitudinal direction.

[0131] In this embodiment, the power rail contact plug 200 penetrates through the capping dielectric layer 160 and the interlayer dielectric layer 150 on the top of the power rail line 120.

[0132] The source / drain contact layer 210 is in contact with the source / drain doping region 140, so as to electrically connect the source / drain doping region 140 with an external circuit or other interconnect structures.

[0133] In this embodiment, the source / drain contact layer 210 is located on the power rail contact plug 200 and covers the top surface of the power rail contact plug 200, so that the source / drain contact layer 210 is electrically connected to the power rail line 120 through the power rail contact plug 200. Thus, when the device is operating, the source / drain doping region 140 can be powered through the power rail line 120.

[0134] In this embodiment, the source / drain contact layer 210 extends longitudinally, and the extending direction of the source / drain contact layer 210 is perpendicular to the extending direction of the power rail line 120.

[0135] In this embodiment, on the projection plane parallel to the substrate 100, the source-drain contact layer 210 straddles the power supply track line 120, and the extending direction of the source-drain contact layer 210 is perpendicular to the extending direction of the power supply track line 120. Meanwhile, the source-drain contact layer 210 is located on the power supply rail contact plug 200 and covers the top surface of the power supply rail contact plug 200. Thus, the position of the power supply rail contact plug 200 can be accurately positioned through the positions of the source-drain contact layer 210 and the power supply track line 120, such that the power supply rail contact plug 200 is located at the overlapping position of the pattern of the source-drain contact layer 210 and the pattern of the power supply track line 120.

[0136] For this reason, the source-drain contact layer 210 and the power supply rail contact plug 200 are made of the same material. The source-drain contact layer 210 and the power supply rail contact plug 200 are made of a conductive material. In this embodiment, the source-drain contact layer 210 and the power supply rail contact plug 200 are made of a metal material, such as one or more of W, Co, Cu, Ru, and Ni.

[0137] In this embodiment, the steps of forming the source-drain contact layer 210 and the power supply rail contact plug 200 include: filling a conductive material (not shown in the figure) in the conductive through-hole 310 and the interconnecting groove 300, and the conductive material is also formed on the interlayer dielectric layer 150; adopting a planarization process to remove the conductive material on the interlayer dielectric layer 150, and the remaining conductive material in the conductive through-hole 310 serves as the power supply rail contact plug 200, and the remaining conductive material in the interconnecting groove 300 serves as the source-drain contact layer 210.

[0138] In this embodiment, the process of forming the conductive material may include one or more of physical vapor deposition process, chemical vapor deposition process, and electroless plating process.

[0139] In this embodiment, the planarization process may be a chemical mechanical planarization (CMP) process.

[0140] It should be noted that in this embodiment, in the step of removing the conductive material on the interlayer dielectric layer 150, the hard mask layer 155 is also removed by adopting a planarization process.

[0141] It should also be noted that for the convenience of illustration and description, in this embodiment, taking the power supply track line 120 being located between two adjacent device regions 100a as an example, channel structures 110 and source-drain doping regions 140 in the channel structures 110 are formed on both sides of the power supply track line 120. However, the positional relationship between the power supply track line 120, the channel structures 110, and the source-drain doping regions 140 is not limited to this.

[0142] For example, in other embodiments, in the longitudinal direction, the power rail line is provided with a channel structure on only one side, and not on the other side. When the power rail line is provided with a channel structure on only one side, the source-drain contact layer spans the power rail line on a projection plane parallel to the substrate, enabling the source-drain contact layer to extend into the interlayer dielectric layer on the other side of the power rail line, thereby increasing the volume of the source-drain contact layer. The source-drain contact layer and the power rail line are an integrated structure, thereby facilitating reduced resistance between the source-drain contact layer and the power rail line, thereby optimizing the performance of the semiconductor structure.

[0143] refer to Figures 12 to 17 In this embodiment, the method for forming the semiconductor structure further includes: after forming the source-drain contact layer 210 and the power rail contact plug 200, forming a partition layer 230 that penetrates the source-drain contact layer 210 located between the power rail contact plug 200 and the adjacent channel structure 110, and the partition layer 230 partitions the source-drain contact layer 210 in the longitudinal direction.

[0144] By forming the partition layer 230, the source-drain contact layer 210 can be disconnected from the power rail contact plug 200 that does not need to be electrically connected, based on design requirements. Moreover, this embodiment can also adjust the size w and position of the partition layer 230 and the distance d between the partition layer 230 and the power rail contact plug 200, so that the source-drain contact layer 210 connected to the power rail contact plug 200 also extends to the other side of the power rail contact plug 200. This helps to increase the volume of the power rail contact plug 200 and the connected source-drain contact layer 210, correspondingly reducing the resistance of the power rail contact plug 200 and the source-drain contact layer 210, and improving the performance of the semiconductor structure.

[0145] To ensure the segmentation effect of the segmentation layer 230, the material of the segmentation layer 230 is a dielectric material. In this embodiment, the segmentation layer 230 can be a single layer or a multilayer structure, and the material of the segmentation layer 230 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and silicon oxycarbide.

[0146] It should be noted that the width w of the partition layer 230 along the longitudinal direction should not be too small or too large. If the width w of the partition layer 230 along the longitudinal direction is too small, the partition layer 230's partitioning effect on the source-drain contact layer 210 will be reduced. If the width w of the partition layer 230 along the longitudinal direction is too large, the partition layer 230 will occupy too large an area. Therefore, in this embodiment, the width w of the partition layer 230 along the longitudinal direction is 5 nm to 30 nm.

[0147] The specific steps of forming the separation layer 230 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0148] like Figures 12 to 15 As shown, a dividing groove 240 is formed through the source-drain contact layer 210 between the power rail contact plug 200 and the adjacent channel structure 110. The dividing groove 240 laterally penetrates the source-drain contact layer 210. The dividing groove 240 is used to provide a space for forming a dividing layer 230.

[0149] As an example, the steps of forming the dividing groove 240 include: Figure 12 and Figure 13 As shown, Figure 12 For top view, Figure 13 for Figure 12 In the cross-sectional view along the yy direction, a cutting mask layer 250 is formed on the interlayer dielectric layer 150 and the source-drain contact layer 210. A cutting opening 260 is formed in the cutting mask layer 250, which is located above the source-drain contact layer 210 between the power rail contact plug 200 and the adjacent channel structure 110. The cutting opening 260 spans the source-drain contact layer 210; Figure 14 and Figure 15 As shown, Figure 14 For top view, Figure 15 for Figure 14 In the cross-sectional view along the yy direction, the cutting mask layer 250 is used as a mask to remove the source-drain contact layer 210 exposed by the cutting opening 260 , thereby forming the dividing groove 240 penetrating the source-drain contact layer 210 .

[0150] The cutting mask layer 250 is used as an etching mask for forming the dividing grooves 240 .

[0151] In this embodiment, the cutting mask layer 250 is made of titanium nitride.

[0152] The cutting opening 260 is used to define the position and size of the cutting of the source-drain contact layer 210. Figure 12 The shape and position of the cutting opening 260 are schematically shown in a solid line frame.

[0153] In this embodiment, along the horizontal direction, the cutting opening 260 is also located above the interlayer dielectric layer 150 adjacent to the source-drain contact layer 210 , which helps to reduce the requirement on the dimensional accuracy of the cutting opening 260 along the horizontal direction.

[0154] In this embodiment, a gate cap layer (not shown) can be formed on the top of the gate structure 130. Even if the cutting opening 260 is still located above the gate structure 130, when the source-drain contact layer 210 below the cutting opening 260 is subsequently etched, the gate cap layer can protect the gate structure 130, thereby preventing the gate structure 130 from being damaged.

[0155] In this embodiment, the process of forming the dividing groove 240 includes one or both of dry etching and wet etching processes. As an example, the dry etching and wet etching processes are sequentially used to etch the source-drain contact layer 210 exposed by the cutting opening 260 to form the dividing groove 240.

[0156] As Figure 16 and Figure 17 shown, Figure 16 is a top view, Figure 17 is Figure 16 a cross-sectional view along the yy direction. A dielectric material is filled in the dividing groove 240 to form the dividing layer 230.

[0157] In this embodiment, the process of filling the dielectric material in the dividing groove 240 includes one or more of chemical vapor deposition process, flowing chemical vapor deposition process, and atomic layer deposition process. The gap filling ability of the deposition process is strong, which is beneficial to improving the filling quality of the dividing layer 230 in the dividing groove 240, thereby ensuring the dividing effect of the dividing layer 230 on the source-drain contact layer 210.

[0158] It should be noted that in this embodiment, taking the formation of the dividing layer 230 after the formation of the source-drain contact layer 210 and the power rail contact plug 200 as an example for illustration.

[0159] In other embodiments, in the step of forming the interconnecting groove and the conductive via, a dividing layer is formed at the bottom of the interconnecting groove between the conductive via and the adjacent channel structure. The dividing layer protrudes from the bottom of the interconnecting groove and longitudinally divides the interconnecting groove. Correspondingly, after the formation of the source-drain contact layer and the power rail contact plug, the source-drain contact layer is longitudinally divided by the dividing layer.

[0160] It should also be noted that in this embodiment, taking the formation method of the semiconductor structure including the formation of the dividing layer 230 as an example for illustration. In other embodiments, according to actual process requirements, the dividing layer may not be formed, or a dividing layer may be formed only in the source-drain contact layer of some regions.

[0161] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising a plurality of discrete device regions and a power rail region located between the device regions; A channel structure is separated on the substrate of the device area; A power rail line is located in the substrate of the power rail area, wherein the power rail line and the channel structure both extend in a horizontal direction, and a direction perpendicular to the horizontal direction is a longitudinal direction; a gate structure, located on the substrate and spanning the channel structure; Source and drain doping regions are located in the channel structure on both sides of the gate structure; an interlayer dielectric layer, located on a side of the gate structure and covering the source and drain doped regions and the power rail line; a power rail contact plug, penetrating a partial thickness interlayer dielectric layer on top of the power rail line, wherein along the longitudinal direction, the power rail contact plug is in full contact with the top surface of the power rail line; A source-drain contact layer is located in the interlayer dielectric layer on top of the source-drain doped region and contacts the source-drain doped region. The source-drain contact layer is located on the power rail contact plug and covers the top surface of the power rail contact plug. On a projection plane parallel to the substrate, the source-drain contact layer spans the power rail line.

2. The semiconductor structure according to claim 1, wherein The source-drain contact layer and the power rail contact plug are an integrated structure.

3. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a partitioning layer penetrating the source-drain contact layer between the power rail contact plug and the adjacent channel structure, wherein the partitioning layer partitions the source-drain contact layer in a longitudinal direction.

4. The semiconductor structure according to claim 3, wherein: Along the longitudinal direction, the width of the dividing layer is 5 nm to 30 nm.

5. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes an isolation structure located on the substrate and covering a portion of the sidewall of the channel structure; the power rail line is located in the substrate and the isolation structure in the power rail region.

6. The semiconductor structure according to claim 5, wherein: The top surface of the power rail line is lower than the top surface of the isolation structure; The semiconductor structure further includes: a covering dielectric layer, located in the isolation structure and covering the top of the power rail line; The power rail contact plug penetrates the cover dielectric layer and the interlayer dielectric layer on top of the power rail line.

7. The semiconductor structure according to claim 1, wherein: The channel structure is a fin, the gate structure spans the fin and covers part of the top and part of the sidewall of the fin; alternatively, the channel structure is a channel structure layer spaced apart from the substrate, the channel structure layer includes one or more spaced apart channel layers; the gate structure surrounds the channel layer.

8. A method for forming a semiconductor structure, characterized in that: include: A substrate is provided, comprising a plurality of discrete device regions and a power rail region located between the device regions, wherein discrete channel structures are formed on the substrate in the device regions, and power rail lines are formed in the substrate in the power rail region, wherein the power rail lines and the channel structures both extend in a lateral direction, with a direction perpendicular to the lateral direction being a longitudinal direction, and a gate structure is formed on the substrate, spanning the channel structures, and source-drain doped regions are formed in the channel structures on both sides of the gate structure, and an interlayer dielectric layer covering the source-drain doped regions and the power rail lines is formed on the sides of the gate structure; forming an interconnection trench penetrating the interlayer dielectric layer at the top of the source / drain doped region, and forming a conductive through hole at the bottom of the interconnection trench and penetrating the interlayer dielectric layer at the top of the power rail line, wherein on a projection plane parallel to the substrate, the interconnection trench spans the power rail line, and along the longitudinal direction, the bottom of the conductive through hole exposes the entire top surface of the power rail line; The conductive through-holes and interconnection grooves are filled to form power rail contact plugs filled in the conductive through-holes and source-drain contact layers filled in the interconnection grooves. Along the longitudinal direction, the power rail contact plugs are in full contact with the top surface of the power rail line, and the source-drain contact layers are in contact with the source-drain doped regions.

9. The method for forming a semiconductor structure according to claim 8, wherein: The method for forming a semiconductor structure further includes: after forming the source-drain contact layer and the power rail contact plug, forming a partition layer penetrating the source-drain contact layer between the power rail contact plug and the adjacent channel structure, wherein the partition layer partitions the source-drain contact layer in a longitudinal direction; Alternatively, in the step of forming the interconnection groove and the conductive through-hole, a partition layer is formed at the bottom of the interconnection groove and located between the conductive through-hole and the adjacent channel structure. The partition layer protrudes from the bottom of the interconnection groove and partitions the interconnection groove in the longitudinal direction.

10. The method for forming a semiconductor structure according to claim 9, wherein: After forming the source-drain contact layer and the power rail contact plug, forming the partition layer; The step of forming the partition layer includes: forming a partition groove penetrating the source-drain contact layer between the power rail contact plug and the adjacent channel structure, wherein the partition groove penetrating the source-drain contact layer in a transverse direction; The dividing grooves are filled with a dielectric material to form the dividing layer.

11. The method for forming a semiconductor structure according to claim 10, wherein: The step of forming the segmentation groove includes: forming a cutting mask layer on the interlayer dielectric layer and the source-drain contact layer, wherein a cutting opening is formed in the cutting mask layer and is located above the source-drain contact layer between the power rail contact plug and the adjacent channel structure, and the cutting opening spans the source-drain contact layer; using the cutting mask layer as a mask, removing the source-drain contact layer exposed by the cutting opening to form the segmentation groove penetrating the source-drain contact layer.

12. The method for forming a semiconductor structure according to claim 10, wherein: The process of forming the dividing grooves includes one or both of dry etching and wet etching.

13. The method for forming a semiconductor structure according to claim 10, wherein: The process of filling the dielectric material in the dividing grooves includes one or more of a chemical vapor deposition process, a flow chemical vapor deposition process and an atomic layer deposition process.

14. The method for forming a semiconductor structure according to claim 9, wherein: In the step of forming the partition layer, the material of the partition layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride and silicon oxycarbide.

15. The method for forming a semiconductor structure according to claim 9, wherein: Along the longitudinal direction, the width of the dividing layer is 5 nm to 30 nm.

16. The method for forming a semiconductor structure according to claim 8, wherein: The steps of forming the interconnection groove and the conductive through hole include: forming an interconnection groove penetrating a partial thickness interlayer dielectric layer at the top of the source and drain doping region; and forming a conductive through hole penetrating the interlayer dielectric layer at the bottom of the interconnection groove.

17. The method for forming a semiconductor structure according to claim 16, wherein: The step of forming the interconnection trench comprises: forming a hard mask layer on the interlayer dielectric layer, wherein a mask opening is formed in the hard mask layer and is located above the source and drain doped regions, wherein the mask opening extends in a longitudinal direction and crosses the power rail line on a projection plane parallel to the substrate; using the hard mask layer as a mask, etching a portion of the thickness of the interlayer dielectric layer along the mask opening to form the interconnection trench; The step of forming the conductive through hole includes: using the hard mask layer as an etching stop layer in the lateral direction, etching the interlayer dielectric layer at the bottom of the interconnection groove portion to form the conductive through hole.

18. The method for forming a semiconductor structure according to claim 8, wherein: In the step of providing a substrate, an isolation structure covering a portion of the sidewalls of the channel structure is further formed on the substrate; the power rail line is located in the substrate and the isolation structure in the power rail area.

19. The method for forming a semiconductor structure according to claim 18, wherein: In the step of providing the substrate, the top surface of the power rail line is lower than the top surface of the isolation structure; a covering dielectric layer located on top of the power rail line is also formed in the isolation structure; In the step of forming the conductive through hole, the conductive through hole penetrates the covering dielectric layer and the interlayer dielectric layer on the top of the power rail line.

20. The method for forming a semiconductor structure according to claim 8, wherein: In the step of providing a substrate, the channel structure is a fin, and the gate structure spans the fin and covers a portion of the top and a portion of the sidewall of the fin; Alternatively, the channel structure is a channel structure layer spaced apart from the substrate, and the channel structure layer includes one or more spaced apart channel layers; the gate structure surrounds the channel layer.

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