Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and its formation method are disclosed. The semiconductor structure includes: a substrate; a gate structure located on the substrate, parallel to the substrate surface, with the gate structure extending laterally and perpendicular to the extending direction as longitudinally; source / drain doped layers located within the substrate on both sides of the gate structure; and a source / drain stack located on multiple source / drain doped layers, the source / drain stack including source / drain plugs and source / drain interconnect structures mounted on the source / drain plugs. In this embodiment, the source / drain stack includes source / drain plugs and source / drain interconnect structures mounted on the source / drain plugs, meaning that the source / drain plugs and source / drain interconnect structures are an integral structure. The adhesion between the source / drain interconnect structures and the source / drain plugs is strong, resulting in high strength. Furthermore, because the source / drain interconnect structures and source / drain plugs are an integral structure, the on-resistance between them is low, which helps to reduce the power consumption of the semiconductor structure, improve current characteristics, and optimize the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and a substrate. These interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit.

[0004] The contact hole plugs in the transistor structure include a gate plug located on top of the gate structure for connecting the gate structure to external circuits, a source plug located on top of the source / drain doped layer, and a source / drain interconnect structure for connecting the source / drain doped layer to external circuits. The formation quality of the gate plug, source / drain plug, and source / drain interconnect structure is positively correlated with the performance of the semiconductor structure. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which makes it less likely for the gate plug and the source-drain interconnect structure and the source-drain plug to be bridged, thereby optimizing the electrical performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate; a gate structure located on the substrate and parallel to the surface of the substrate, wherein the extension direction of the gate structure is lateral and the extension direction perpendicular to the gate structure is longitudinal; source / drain doped layers located within the substrate on both sides of the gate structure; and a source / drain stack located on the plurality of source / drain doped layers, wherein the source / drain stack includes source / drain plugs and source / drain interconnect structures standing on the source / drain plugs.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, and source / drain doped layers are formed in the substrate on both sides of the gate structure; forming a source / drain stack on the source / drain doped layers, the source / drain stack comprising: source / drain plugs connecting multiple source / drain doped layers between the gate structures and source / drain interconnect structures standing on the source / drain plugs.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] The semiconductor structure provided in this embodiment of the invention includes: a substrate; a gate structure located on the substrate, parallel to the surface of the substrate, the gate structure extending laterally and perpendicularly to the extending direction of the gate structure in a longitudinal direction; source / drain doped layers located within the substrate on both sides of the gate structure; and a source / drain stack located on multiple source / drain doped layers, the source / drain stack including source / drain plugs and source / drain interconnect structures standing on the source / drain plugs. In this embodiment of the invention, the source / drain stack includes source / drain plugs and source / drain interconnect structures standing on the source / drain plugs, that is, the source / drain plugs and source / drain interconnect structures are an integral structure. Compared with the case where the source / drain plugs and source / drain interconnect structures are separate, the adhesion between the source / drain interconnect structures and source / drain plugs is stronger, and the corresponding strength is higher. Furthermore, because the source / drain interconnect structures and source / drain plugs are an integral structure, the on-resistance between the source / drain interconnect structures and source / drain plugs is smaller, which is beneficial for reducing the power consumption of the semiconductor structure, improving current characteristics, and optimizing the electrical performance of the semiconductor structure.

[0010] In an optional embodiment, the semiconductor structure includes: a gate plug, which is mounted on the gate structure; and a protective layer located on the top of the source-drain plug, on the lateral sidewalls of the source-drain interconnect structure, and on the longitudinal sidewalls of the gate plug. The protective layer electrically isolates the gate plug from the source-drain interconnect structure and the source-drain plug, making it less likely for the gate plug to bridge with the source-drain interconnect structure and the source-drain plug, which is beneficial for improving the electrical performance of the semiconductor structure.

[0011] In an optional embodiment of the semiconductor structure formation method provided by this invention, a source / drain plug connecting multiple source / drain doped layers, a source / drain interconnect structure standing on the source / drain plug, and a first dielectric layer located on the gate structure are formed between the gate structure; a protective layer is formed on the sidewalls of the source / drain interconnect structure and the first dielectric layer, and on the top of the source / drain plug; the first dielectric layer between the protective layers is etched to form a groove exposing the gate structure; and a gate plug is formed in the groove. In this embodiment of the invention, during the process of forming a protective layer on the sidewalls of the source / drain interconnect structure and the first dielectric layer, and on the top of the source / drain plug, and during the etching of the first dielectric layer between the protective layers to form a groove exposing the gate structure, the protective layer defines the formation area of ​​the groove, making it less likely for the formed groove to expose the source / drain interconnect structure and the source / drain plug. Consequently, the gate plug formed in the groove is less likely to bridge with the source / drain interconnect structure and the source / drain plug, which is beneficial for improving the electrical performance of the semiconductor structure. Attached Figure Description

[0012] Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0013] Figures 6 to 8 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0014] Figures 9 to 31 This is a schematic diagram of the structure corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Implementation

[0015] As the background technology shows, the devices currently being fabricated still suffer from poor performance. This paper analyzes the reasons for this poor performance by examining a semiconductor structure fabrication method.

[0016] refer to Figures 1 to 5 The diagram shows a schematic representation of each step in a method for forming a semiconductor structure.

[0017] like Figure 1 As shown, a substrate is provided, the substrate including a substrate (not shown), a fin 1 disposed on the substrate, a gate structure 2 spanning the fin 1, a source / drain doped layer 3 located in the fin 1 on both sides of the gate structure 2, and an interlayer dielectric layer 4 covering the source / drain doped layer 3, and a gate capping layer 9 is formed on the top of the gate structure 2.

[0018] like Figure 2 As shown, the interlayer dielectric layer 4 on the source / drain doped layer 3 is etched to form a source / drain opening (not shown in the figure) exposing the source / drain doped layer 3; a first metal material layer (not shown in the figure) is formed in the source / drain opening; a portion of the thickness of the first metal material layer is etched back to form a source / drain plug 5 and a first opening located on the source / drain plug 5; a source / drain capping layer 6 is formed in the first opening.

[0019] like Figures 3 to 5 As shown, Figure 4 for Figure 3 Cross-sectional view at BB. Figure 5 for Figure 3 Cross-sectional view at AA. A dielectric layer 8 is formed covering the source / drain capping layer 6 and the gate capping layer 9; the dielectric layer 8 and the gate capping layer 9 are etched to form a second opening exposing the gate structure 2; a gate plug 10 is formed in the second opening (e.g., ...). Figure 4 (As shown); the dielectric layer 8 and the source / drain cap layer 6 are etched to form a third opening exposing the source / drain plug 5, and a source / drain interconnect structure 7 is formed in the third opening (as shown). Figure 5 (As shown).

[0020] Subsequently, a back-end metal interconnect structure is formed, connecting the gate plug 10 and the source-drain interconnect structure 7. The gate plug 10 connects the gate structure 2 to the back-end metal interconnect structure, and the source-drain interconnect structure 7 connects the source-drain doped layer 3 to the back-end metal interconnect structure. Typically, the dielectric layer 8 and the gate cap layer 7 are relatively thick. During the formation of the second opening, reaction byproducts are not easily removed in time, resulting in a large angle between the sidewall of the second opening and the normal to the substrate surface. In other words, the bottom dimension of the second opening is small, and the top dimension is large. During the formation of the third opening, due to the large thickness of both the dielectric layer 8 and the source-drain cap layer 6, the angle between the sidewall of the third opening and the normal to the substrate surface is also large. This makes it easy for the top of the gate plug 10 to be exposed during the third opening. Consequently, the source-drain interconnect structure 7 formed in the third opening is prone to bridging with the gate plug 10, leading to poor electrical performance of the semiconductor structure.

[0021] To address the aforementioned technical problem, the semiconductor structure includes a source / drain stack comprising a source / drain plug and a source / drain interconnect structure mounted on the source / drain plug. In other words, the source / drain plug and the source / drain interconnect structure are integrated. Compared to cases where the source / drain plug and the source / drain interconnect structure are separate components, the adhesion between the source / drain interconnect structure and the source / drain plug is stronger, resulting in higher strength. Furthermore, because the source / drain interconnect structure and the source / drain plug are integrated, no barrier layer is formed between them, leading to lower on-resistance. This is beneficial for reducing power consumption, improving current characteristics, and optimizing the electrical performance of the semiconductor structure.

[0022] In the method for forming the semiconductor structure, a source / drain plug connecting multiple source / drain doped layers, a source / drain interconnect structure standing on the source / drain plug, and a first dielectric layer located on the gate structure are formed between the gate structure; a protective layer is formed on the sidewalls of the source / drain interconnect structure and the first dielectric layer, and on the top of the source / drain plug; the first dielectric layer between the protective layers is etched to form a groove exposing the gate structure; and a gate plug is formed in the groove. In this embodiment of the invention, during the process of etching the first dielectric layer between the protective layers to form a groove exposing the gate structure, the protective layer defines the formation area of ​​the groove, making it less likely for the formed groove to expose the source / drain interconnect structure and the source / drain plug. Consequently, the gate plug formed in the groove is less likely to bridge with the source / drain interconnect structure and the source / drain plug, which is beneficial for improving the electrical performance of the semiconductor structure.

[0023] Figures 6 to 8 , Figure 7 for Figure 6 Cross-sectional view at BB. Figure 8 for Figure 6 The cross-sectional view at EE is a schematic diagram of the semiconductor structure according to an embodiment of the present invention.

[0024] The semiconductor structure includes: a substrate; a gate structure 101 located on the substrate and parallel to the surface of the substrate, wherein the extension direction of the gate structure 101 is lateral and the extension direction perpendicular to the gate structure 101 is longitudinal; source / drain doped layers 102 located in the substrate on both sides of the gate structure 101; and a source / drain stack located on a plurality of source / drain doped layers 102, wherein the source / drain stack includes source / drain plugs 109 and source / drain interconnect structures 110 standing on the source / drain plugs 109.

[0025] In the semiconductor structure provided by the embodiments of the present invention, the source-drain stack includes a source-drain plug 109 and a source-drain interconnect structure 110 standing on the source-drain plug 109. That is, the source-drain plug 109 and the source-drain interconnect structure 110 are an integral structure. Compared with the case where the source-drain plug and the source-drain interconnect structure are separate, the adhesion between the source-drain interconnect structure 110 and the source-drain plug 109 is stronger, and the corresponding strength is higher. Moreover, because the source-drain interconnect structure 110 and the source-drain plug 109 are an integral structure, the on-resistance between the source-drain interconnect structure 110 and the source-drain plug 109 is smaller, which is beneficial to reduce the power consumption of the semiconductor structure, improve the current characteristics, and optimize the electrical performance of the semiconductor structure.

[0026] The source / drain plug 109 is used to connect multiple source / drain doped layers 102.

[0027] The extension direction of the gate structure 101 is defined as the lateral direction (x), which is parallel to the surface of the substrate 100, and the direction perpendicular to the lateral direction is defined as the longitudinal direction (y).

[0028] Specifically, the source / drain plug 109 includes a conductive layer 112 and a barrier layer 113 located at the bottom and longitudinal sidewalls of the conductive layer 112. The source / drain interconnect structure 110 includes the conductive layer 112 and the barrier layer 113 located at the longitudinal sidewalls of the conductive layer 112.

[0029] It should be noted that the number of source-drain interconnect structures 110 can be one or more, depending on process requirements. Furthermore, the location of the source-drain interconnect structure 110 on the source-drain plug 109 needs to be determined based on actual process requirements, and is typically located in the active area.

[0030] The conductive layer 112 in the source-drain interconnect structure 110 and the conductive layer 112 in the source-drain plug 109 are in direct contact. Compared with the case where a barrier layer is formed between the conductive layers of the source-drain interconnect structure and the conductive layers of the source-drain plug, the on-resistance between the source-drain interconnect structure 110 and the source-drain plug 109 is smaller, which is beneficial to reduce the power consumption of the semiconductor structure, improve the current characteristics, and optimize the electrical performance of the semiconductor structure. In addition, no barrier layer 113 is formed between the source-drain interconnect structure 110 and the source-drain plug 109, which is beneficial to improve the adhesion between the source-drain interconnect structure 110 and the source-drain plug 109.

[0031] The barrier layer 113 prevents ions in the conductive layer 112 from easily diffusing into the source / drain doped layer 102 and the gate structure 101 below the barrier layer 113. When the semiconductor structure is working, the source / drain doped layer 102 can provide greater stress for communication, thereby increasing the migration rate of charge carriers in the channel. This also makes the gate structure 101 have stronger control over the channel.

[0032] In this embodiment, the material of the barrier layer 113 is TaN. In other embodiments, the material of the barrier layer 113 can be one or more of Ta, Ti, TiN, ZrN, and ZrTiN.

[0033] Specifically, the conductive layer 112 is made of one or more of Cu, Co, W, Ta, TaN, Ti, and TiN. In other embodiments, the conductive layer 112 is made of copper. Copper has low resistivity, which helps to improve the signal delay of the later-stage RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance between the source / drain plug 109 and the source / drain doped layer 102, thereby reducing power consumption.

[0034] The semiconductor structure further includes a gate plug 122, which is mounted on the gate structure 101.

[0035] The gate plug 122 is used to electrically connect the gate structure 101 to other interconnect structures or external circuits.

[0036] In this embodiment, the gate plug 122 is located above the gate structure 101 between the source and drain doped layers 102 and is located in the active area. That is to say, the gate plug 122 is an active gate contact hole plug (COAG). Therefore, it is beneficial to save chip area, further reduce chip size, and improve the integration of semiconductor structure.

[0037] In this embodiment, the gate plug 122 is made of copper. Copper has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the gate plug 122, thereby reducing power consumption. In other embodiments, the gate plug 122 may also be made of tungsten or cobalt.

[0038] The semiconductor structure further includes a protective layer 118 located on the lateral sidewall of the source-drain interconnect structure 110 and the longitudinal sidewall of the gate plug 122.

[0039] The protective layer 118 electrically isolates the gate plug 122 from the source-drain interconnect structure 110, thereby making it less likely for the gate plug 122 to bridge with the source-drain interconnect structure 110. The protective layer 118 defines the formation area of ​​the gate plug 122, which also improves the alignment accuracy between the gate plug 122 and the gate structure 101, thus improving the electrical performance of the semiconductor structure.

[0040] Specifically, the protective layer 118 is also located on top of the source / drain plug 109.

[0041] Therefore, the protective layer 118 is also used to electrically isolate the gate plug 122 from the source-drain plug 109, so that the gate plug 122 is less likely to bridge with the source-drain plug 109, which is beneficial to improving the electrical performance of the semiconductor structure.

[0042] The protective layer 118 electrically isolates the gate plug 122 from the source-drain interconnect structure 110 and the source-drain plug 109, making it less likely for the gate plug 122 to bridge with the source-drain interconnect structure 110 and the source-drain plug 109, which is beneficial to improving the electrical performance of the semiconductor structure.

[0043] In this embodiment, the material of the protective layer 118 includes one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbonate, silicon carbide, silicon carbonitride, aluminum nitride, and aluminum oxide. In this embodiment, the material of the protective layer 118 includes silicon nitride. Silicon nitride is a commonly used dielectric material in manufacturing processes and has high etching resistance.

[0044] It should be noted that the protective layer 118 should not be too thick or too thin. If the protective layer 118 is too thick, excessive processing materials and time are required to form it, resulting in low formation efficiency and wasted resources. In this embodiment, the material of the protective layer 118 includes silicon nitride, which is a material with high stress. If the protective layer 118 is too thick, it will disrupt the stress balance between the original design of the protective layer and the first dielectric layer 111, the source-drain interconnect structure 110, and the source-drain plug 109, leading to poor electrical performance of the semiconductor structure. If the protective layer 118 is too thin, it cannot effectively electrically isolate the gate plug 122 from the source-drain interconnect structure 110 and the source-drain plug 109. The gate plug 122 is prone to bridging with the source-drain interconnect structure 110 or the source-drain plug 109, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the protective layer 118 is 2 nanometers to 6 nanometers.

[0045] The substrate includes: a substrate 100; and fins 104 disposed on the substrate 100. Accordingly, the semiconductor structure is exemplified by a FinFET (Fin Field-Effect Transistor). In other embodiments, the substrate may also be a planar substrate, and the semiconductor structure may also be a planar transistor (MOSFET). In other embodiments, the substrate further includes a plurality of suspended channel layers located on the fins, the channel layers being spaced apart in the normal direction of the substrate surface; accordingly, the semiconductor structure is a gate-all-around (GAA) transistor.

[0046] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0047] In this embodiment, the material of the fin 104 is the same as the material of the substrate 100, including silicon.

[0048] The substrate further includes an isolation layer located on the substrate 100 on the side of the fin 104, and the isolation layer covers a portion of the sidewall of the fin 104. In this embodiment, "parallel to the surface of the substrate" specifically refers to "parallel to the surface of the substrate 100", with the extension direction of the fin 104 being longitudinal ( Figure 6 middle y direction).

[0049] The isolation layer is used to isolate the gate structure 101 and the substrate 100.

[0050] In this embodiment, the material of the isolation layer includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the isolation layer; in addition, silicon oxide has a low dielectric constant, which also helps to improve the role of the subsequent isolation layer in isolating adjacent devices.

[0051] The gate structure 101 spans the fin 104 and covers part of the top wall and part of the sidewall of the fin 104. In this embodiment, parallel to the substrate surface, specifically referring to the surface of the substrate 100, the extending direction of the gate structure 101 is lateral ( Figure 6 (in the x-direction), the lateral direction is perpendicular to the longitudinal direction.

[0052] When the semiconductor structure is in operation, the gate structure 101 is used to turn the channel on or off.

[0053] Specifically, the gate structure 101 includes a work function layer 1011 and a metal gate layer 1012 located on the work function layer 1011.

[0054] When the semiconductor structure is working, the work function layer 1011 is used to regulate the threshold voltage of the transistor.

[0055] In this embodiment, the metal gate layer 1012 is made of a magnesium-tungsten alloy. In other embodiments, the metal gate layer is made of one or more of Co, Ru, and W.

[0056] It should be noted that a sidewall layer 106 is formed on the sidewall of the gate structure 101.

[0057] The sidewall layer 106 is used to electrically isolate the source / drain doped layer 102 and the gate structure 101. Furthermore, the sidewall layer 106 is used to make the source / drain plug 109 less likely to bridge with the gate structure 101, which is beneficial to improving the electrical performance of the semiconductor structure. In addition, the sidewall layer 106 is also used to make the gate plug 122 less likely to bridge with the source / drain plug 109 and the source / drain interconnect structure 110, which is beneficial to improving the electrical performance of the semiconductor structure.

[0058] The sidewall layer 106 is made of a low-k dielectric material, which helps to reduce the capacitive coupling effect between the gate structure 101 and the source / drain plug 109 and improve the electrical performance of the semiconductor structure.

[0059] The sidewall layer 106 is made of materials including SiON, SiBCN, SiCN, carbon-doped SiN, or oxygen-doped SiN. In this embodiment, the sidewall layer 106 is made of silicon nitride containing C or O.

[0060] It should be noted that the semiconductor structure further includes a gate cap layer 107, located on the gate structure 101.

[0061] The gate cap layer 107 is used to protect the top of the gate structure 101 from damage. When the semiconductor structure is working, it helps to improve the control capability of the gate structure 101 over the channel, thereby improving the electrical performance of the semiconductor structure.

[0062] In this embodiment, the gate cap layer 107 is made of a dielectric material. Specifically, the material of the gate cap layer 107 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the gate cap layer 107 includes silicon nitride.

[0063] When the semiconductor structure is in operation, the source and drain doped layers 102 are used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0064] Specifically, the source and drain doped layers 102 are located in the fins 104 on both sides of the gate structure 101.

[0065] In this embodiment, the semiconductor structure is an NMOS (Negative Channel Metal Oxide Semiconductor), and the source / drain doped layer 102 is made of silicon carbide or silicon phosphide doped with N-type ions. This embodiment uses N-type ions to replace silicon atoms in the crystal lattice by doping silicon carbide or silicon phosphide. The more N-type ions incorporated, the higher the majority carrier concentration and the stronger the conductivity. In this embodiment, the N-type ions include phosphorus, arsenic, or antimony.

[0066] In other embodiments, the semiconductor structure is a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doping layers are made of silicon germanide doped with P-type ions. In this embodiment, by doping silicon germanide with P-type ions, the P-type ions replace the positions of silicon atoms in the crystal lattice. The more P-type ions incorporated, the higher the majority carrier concentration, and the stronger the conductivity. In this embodiment, the P-type ions include boron, gallium, or indium.

[0067] The semiconductor structure further includes a first dielectric layer 111 located on the gate structure 101 on the side of the gate plug 122.

[0068] The first dielectric layer 111 defines the formation region of the source-drain interconnect structure 110 and the source-drain plug 109. The first dielectric layer 111 is also used to electrically isolate the source-drain interconnect structure 110. In addition, the first dielectric layer 111 also defines the formation region of the gate plug 122.

[0069] In this embodiment, the material of the first dielectric layer 111 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material, which helps to reduce the difficulty and cost of forming the first dielectric layer 111 and improve process compatibility.

[0070] The semiconductor structure includes a second dielectric layer 120 located on the source / drain plug 109 on the side of the source / drain interconnect structure 110.

[0071] The second dielectric layer 120 is used for electrical isolation of adjacent devices.

[0072] In this embodiment, the material of the second dielectric layer 120 includes silicon oxide.

[0073] Correspondingly, Figures 9 to 31 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0074] refer to Figures 9 to 11 , Figure 10 for Figure 9 Cross-sectional view at CC Figure 11 for Figure 9 A cross-sectional view at DD shows a substrate on which a gate structure 101 is formed, and active / drain doped layers 102 are formed in the substrate on both sides of the gate structure 101.

[0075] The substrate provides the technological basis for the subsequent formation of semiconductor structures.

[0076] In this embodiment, the step of providing the substrate includes a substrate 100 and fins 104 discretely disposed on the substrate 100. Accordingly, the subsequent semiconductor structure formed is exemplified by a FinFET (Fin Field-Effect Transistor). In other embodiments, the substrate may also be a planar substrate, and the corresponding semiconductor structure may be a planar transistor (MOSFET). In some other embodiments, the substrate further includes a channel stack located on the fins, the channel stack including a sacrificial layer and a channel layer located on the sacrificial layer; correspondingly, the subsequent semiconductor structure is a gate-all-around transistor (GAA).

[0077] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates.

[0078] In this embodiment, the material of the fin 104 is the same as that of the substrate 100, including silicon. In this embodiment, the extension direction of the fin 104 is longitudinal (y direction in the figure), parallel to the surface of the substrate 100.

[0079] The substrate further includes: an isolation layer 105 (such as...) Figure 10 As shown, the substrate 100 is located on the side of the fin 104, and the isolation layer 105 covers part of the sidewall of the fin 104.

[0080] The isolation layer 105 is used to isolate the gate structure 101 and the substrate 100.

[0081] In this embodiment, the material of the isolation layer 105 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the isolation layer 105. In addition, silicon oxide has a low dielectric constant, which also helps to improve the function of the subsequent isolation layer 105 in isolating adjacent devices.

[0082] The gate structure 101 spans the fin 104 and covers part of the top wall and part of the side wall of the fin 104. In this embodiment, the extension direction of the gate structure 101 is transverse (x direction in the figure), parallel to the surface of the substrate 100, and the transverse direction is perpendicular to the longitudinal direction.

[0083] When the semiconductor structure is in operation, the gate structure 101 is used to turn the channel on or off.

[0084] Specifically, the gate structure 101 includes a work function layer 1011 and a metal gate layer 1012 located on the work function layer 1011.

[0085] When the semiconductor structure is working, the work function layer 1011 is used to regulate the threshold voltage of the transistor.

[0086] In this embodiment, the metal gate layer 1012 is made of a magnesium-tungsten alloy. In other embodiments, the metal gate layer 1012 is made of one or more of Co, Ru, and W.

[0087] It should be noted that a sidewall layer 106 is formed on the sidewall of the gate structure 101.

[0088] The sidewall layer 106 is used to electrically isolate the source / drain doped layer 102 and the gate structure 101. Furthermore, during the subsequent formation of the source / drain openings exposing the source / drain doped layer 102, the sidewall layer 106 defines the formation position of the source / drain openings, making it less likely that the source / drain plugs subsequently formed in the source / drain openings will bridge with the gate structure, thus improving the electrical performance of the semiconductor structure. Additionally, during the subsequent formation of a first dielectric layer on the gate structure 101, and during the etching of the first dielectric layer to form a groove exposing the gate structure 101, the sidewall layer 106 defines the formation position of the groove, making it less likely that the gate plugs subsequently formed in the grooves will bridge with the source / drain plugs, further improving the electrical performance of the semiconductor structure.

[0089] The sidewall layer 106 is made of a low-k dielectric material, which helps to reduce the capacitive coupling effect between the gate structure 101 and the source / drain doped layer 102 and improve the electrical performance of the semiconductor structure.

[0090] The sidewall layer 106 is made of materials including SiON, SiBCN, SiCN, carbon-doped SiN, or oxygen-doped SiN. In this embodiment, the sidewall layer 106 is made of silicon nitride containing C or O.

[0091] It should be noted that, in the step of providing the substrate, a gate cap layer 107 is formed on the gate structure 101.

[0092] In the step of providing the substrate, the gate cap layer 107 is used to protect the top of the gate structure 101 from damage. When the semiconductor structure is working, it helps to improve the control capability of the gate structure 101 over the channel, thereby improving the electrical performance of the semiconductor structure.

[0093] In this embodiment, the gate cap layer 107 is made of a dielectric material. Specifically, the material of the gate cap layer 107 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the gate cap layer 107 includes silicon nitride.

[0094] When the semiconductor structure is in operation, the source and drain doped layers 102 are used to provide stress to the channel and improve the migration rate of carriers in the channel.

[0095] Specifically, the source and drain doped layers 102 are formed in the fins 104 on both sides of the gate structure 101.

[0096] In this embodiment, the semiconductor structure is used to form an NMOS (Negative Channel Metal Oxide Semiconductor), and the source / drain doped layer 102 is made of silicon carbide or silicon phosphide doped with N-type ions. This embodiment uses N-type ions to replace silicon atoms in the crystal lattice by doping silicon carbide or silicon phosphide. The more N-type ions incorporated, the higher the majority carrier concentration and the stronger the conductivity. In this embodiment, the N-type ions include phosphorus, arsenic, or antimony.

[0097] In other embodiments, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor). The source and drain doping layers are made of silicon germanide doped with p-type ions. In this embodiment, p-type ions are doped into silicon germanide to replace the positions of silicon atoms in the crystal lattice. The more p-type ions doped, the higher the majority carrier concentration and the stronger the conductivity. In this embodiment, the p-type ions include boron, gallium, or indium.

[0098] In the step of providing the substrate, an interlayer dielectric layer 103 is formed on the substrate exposed by the gate structure 101, and the interlayer dielectric layer 103 covers the sidewall of the gate structure 101.

[0099] Interlayer dielectric layer 103 is used for electrical isolation of adjacent devices.

[0100] In this embodiment, the material of the interlayer dielectric layer 103 is an insulating material. Specifically, the material of the interlayer dielectric layer 103 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the interlayer dielectric layer 103.

[0101] refer to Figures 12 to 20 A source-drain stack is formed on the source-drain doped layer 102, the source-drain stack including: source-drain plugs 109 (e.g., connecting multiple source-drain doped layers 102 between the gate structures 101) Figure 20 (as shown) and the source-drain interconnect structure 110 (as shown) standing on the source-drain plug 109. Figure 20 (As shown).

[0102] The source / drain plug 109 is used to connect multiple source / drain doped layers 102, and the source / drain interconnect structure 110 is used to connect the source / drain plug 109 to the subsequent metal interconnect structure.

[0103] In this embodiment, the source / drain plug 109 includes a conductive layer 112 (such as...). Figure 20 (as shown) and a barrier layer 113 located at the bottom and longitudinal sidewalls of the conductive layer 112 (as shown) Figure 20 (As shown). The source-drain interconnect structure 110 includes: the conductive layer 112 and the barrier layer 113 located on the longitudinal sidewall of the conductive layer 112.

[0104] It should be noted that the number of source-drain interconnect structures 110 can be one or more, depending on process requirements. Furthermore, the location of the source-drain interconnect structure 110 on the source-drain plug 109 needs to be determined based on actual process requirements, and is typically located in the active area.

[0105] The conductive layer 112 in the source-drain interconnect structure 110 and the conductive layer 112 in the source-drain plug 109 are in direct contact. Compared with the case where a barrier layer is formed between the conductive layers of the source-drain interconnect structure and the conductive layers of the source-drain plug, the on-resistance between the source-drain interconnect structure 110 and the source-drain plug 109 is smaller, which is beneficial to reduce the power consumption of the semiconductor structure, improve the current characteristics, and optimize the electrical performance of the semiconductor structure. In addition, no barrier layer 113 is formed between the source-drain interconnect structure 110 and the source-drain plug 109, and the adhesion between the source-drain interconnect structure 110 and the source-drain plug 109 is high.

[0106] Specifically, the material of the conductive layer 112 includes one or more of Cu, Co, W, Ta, TaN, Ti, and TiN. In this embodiment, the material of the conductive layer 112 includes copper. Copper has low resistivity, which is beneficial for improving the signal delay of the later-stage RC circuit and increasing the processing speed of the chip. It also helps to reduce the resistance of the source / drain plugs 109 and the source / drain doped layer 102, thereby reducing power consumption.

[0107] The barrier layer 113 prevents ions in the conductive layer 112 from easily diffusing into the source / drain doped layer 102 and the gate structure 101 below the barrier layer 113. When the semiconductor structure is working, the source / drain doped layer 102 can provide greater stress for communication, thereby increasing the migration rate of charge carriers in the channel. This also makes the gate structure 101 have stronger control over the channel.

[0108] In this embodiment, the material of the barrier layer 113 is TaN. In other embodiments, the material of the barrier layer can be one or more of Ta, Ti, TiN, ZrN, and ZrTiN.

[0109] The method for forming the semiconductor structure includes: after providing a substrate and before forming the source-drain stack, forming a first dielectric layer 111 on the gate structure 101 (e.g., ...). Figure 13 (As shown).

[0110] The first dielectric layer 111 defines the formation region of the source-drain interconnect structure 110 and the source-drain plug 109. The first dielectric layer 111 is also used to electrically isolate the source-drain interconnect structure 110. In addition, the first dielectric layer 111 also defines the formation region of the subsequent gate plug.

[0111] In this embodiment, the material of the first dielectric layer 111 includes silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material, which helps to reduce the difficulty and cost of forming the first dielectric layer 111 and improve process compatibility.

[0112] Specifically, the steps for forming the first dielectric layer 111 include:

[0113] like Figure 12 As shown, a first dielectric material layer 202 is formed on the interlayer dielectric layer 103 and the gate structure 101.

[0114] The first dielectric material layer 202 prepares for the subsequent formation of the first dielectric layer, which is used to electrically isolate the subsequently formed source / drain plugs and source / drain interconnect structures from other film layers.

[0115] In this embodiment, the first dielectric material layer 202 is made of an insulating material. Specifically, the first dielectric material layer 202 is made of silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility.

[0116] like Figure 13 As shown, the first dielectric material layer 202 and the interlayer dielectric layer 103 are etched to form source and drain openings 201 that expose the source and drain doped layer 102. The remaining first dielectric material layer 202 located on top of the gate structure 101 serves as the first dielectric layer 111.

[0117] In this embodiment, a dry etching process is used to etch the first dielectric material layer 202 and the interlayer dielectric layer 103 to form source / drain openings 201 exposing the source / drain doped layer 102. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which helps to ensure that the morphology of the source / drain openings 201 meets process requirements. Furthermore, during the formation of the source / drain openings 201 using the dry etching process, the top of the source / drain doped layer 102 can be used as the etching stop point, reducing damage to other film layers.

[0118] Specifically, the step of forming source / drain plugs 109 connecting multiple source / drain doped layers 102 between the gate structures 101 and source / drain interconnect structures 110 standing on the source / drain plugs 109 includes:

[0119] like Figures 14 to 16 As shown, Figure 15 for Figure 14 Cross-sectional view at CC Figure 16 for Figure 14 In the cross-sectional view at DD, a first metal layer 115 is formed in the source-drain opening 201.

[0120] The first metal layer 115 prepares for the subsequent formation of the source / drain plug 109 and the source / drain interconnect structure 110.

[0121] The step of forming the first metal layer 115 includes: conformally covering a barrier material layer 117 in the source / drain opening 201; forming a conductive material layer 116 on the barrier material layer 117 exposed in the source / drain opening 201, wherein the barrier material layer 117 and the conductive material layer 116 serve as the first metal layer 115.

[0122] In this embodiment, atomic layer deposition (ALD) is used to form the barrier material layer 117. ALD involves multiple deposition cycles, facilitating precise control of the thickness of the barrier material layer 117 and improving its thickness uniformity. Furthermore, ALD offers good gap-filling performance and step coverage, thereby enhancing the conformal coverage of the barrier material layer 117 and ensuring that the thickness of the barrier material layer 117 on the sidewall of the source / drain opening 201 matches the thickness of the barrier material layer 117 at the bottom of the source / drain opening 201. In other embodiments, physical vapor deposition (PVD) or chemical vapor deposition (CVD) can also be used to form the barrier material layer.

[0123] In this embodiment, the conductive material layer 116 is formed using an electrochemical plating (ECP) process. Electrochemical plating offers advantages such as simple operation, fast deposition rate, and low cost.

[0124] like Figures 17 to 20 As shown, Figure 18 for Figure 17 Cross-sectional view at CC Figure 19 for Figure 17 Cross-sectional view at DD Figure 20 for Figure 17 Cross-sectional view at EE. The first metal layer 115 is etched to form the source / drain plug 109 and the source / drain interconnect structure 110 standing on the source / drain plug 109.

[0125] In this embodiment, a dry etching process is used to etch the first metal layer 115 to form the source / drain plug 109 and the source / drain interconnect structure 110 standing on the source / drain plug 109. The dry etching process has anisotropic etching characteristics and good control over the etching profile, which is beneficial to ensuring that the morphology of the source / drain plug 109 and the source / drain interconnect structure 110 meets the process requirements. Furthermore, by controlling the etching time during the dry etching process of the first metal layer 115, the thickness of the source / drain interconnect structure 110 can be precisely controlled.

[0126] In this embodiment, the step of etching the first metal layer 115 to form the source / drain plug 109 and the source / drain interconnect structure 110 standing on the source / drain plug 109 includes: forming a shielding layer (not shown in the figure) on the first metal layer 115; and etching the first metal layer 115 with the shielding layer as a mask to form the source / drain plug 109 and the source / drain interconnect structure 110.

[0127] The shielding layer is made of a material that can act as a mask and is easy to remove, which can reduce damage to the source / drain plug 109 and the source / drain interconnect structure 110 when the shielding layer is removed in the future.

[0128] The shielding layer includes an organic material layer, a bottom anti-reflective coating on the organic material layer, and a photoresist layer on the bottom anti-reflective coating.

[0129] The organic material layer includes: ODL material or spin-coated carbon (SOC) material; the bottom anti-reflective coating includes: BARC material, DARC material or APF material.

[0130] The method for forming the semiconductor structure further includes: after forming the source-drain interconnect structure 110 and the source-drain plug 109, removing the shielding layer. Timely removal of the shielding layer helps to prevent the organic material layer in the shielding layer from contaminating the machine.

[0131] In this embodiment, the masking layer is removed using an ashing process.

[0132] refer to Figures 21 to 26 , Figure 21 and Figure 24 Based on Figure 18 A schematic diagram of the cross-section. Figure 22 and Figure 25 Based on Figure 19 A schematic diagram of the cross-section. Figure 23 and Figure 26 Based on Figure 20 A schematic diagram of the cross-section.

[0133] A protective layer 118 is formed on the sidewalls of the source-drain interconnect structure 110 and the first dielectric layer 111, and on the top of the source-drain plug 109.

[0134] In the semiconductor structure formation method provided in this embodiment of the invention, a source / drain plug 109 connecting multiple source / drain doped layers 102, a source / drain interconnect structure 110 standing on the source / drain plug 109, and a first dielectric layer 111 located on the gate structure 101 are formed between the gate structure 101; a protective layer 118 is formed on the sidewalls of the source / drain interconnect structure 110 and the first dielectric layer 111, and on the top of the source / drain plug 109; subsequently, the first dielectric layer 111 between the protective layers 118 is etched to form a groove exposing the gate structure 101; and a gate plug is formed in the groove. In this embodiment of the invention, a protective layer 118 is formed on the sidewalls of the source-drain interconnect structure 110 and the first dielectric layer 111, and on the top of the source-drain plug 109. During the process of etching the first dielectric layer 111 between the protective layers 118 to form a groove exposing the gate structure 101, the protective layer 118 defines the formation area of ​​the groove, making it difficult for the formed groove to expose the source-drain interconnect structure 110 and the source-drain plug 109. Correspondingly, the gate plug formed in the groove is less likely to bridge with the source-drain interconnect structure 110 and the source-drain plug 109, which is beneficial to improving the electrical performance of the semiconductor structure.

[0135] Specifically, the steps for forming the protective layer 118 include:

[0136] like Figures 21 to 23 As shown, a protective material layer 119 (e.g., forming a conformal covering of the source / drain plug 109 and the source / drain interconnect structure 110 located on the source / drain plug 109) is formed. Figure 21 (As shown).

[0137] Subsequently, the protective material layer 119 on top of the first dielectric layer 111 is removed, leaving the remaining protective material layer 119 located on the sidewalls of the source-drain interconnect structure 110, the first dielectric layer 111, and the top of the source-drain plug 109 as a protective layer. During the subsequent etching of the first dielectric layer 111 between the protective layers to form a groove exposing the gate structure 101, the protective layers limit the groove formation area, making it difficult for the groove to expose the source-drain interconnect structure 110 and the source-drain plug 109.

[0138] During the process of etching the first dielectric layer 111 between the protective layers to form a groove exposing the gate structure 101, the protective layers are more difficult to etch than the first dielectric layer 111. This greater difficulty in etching the protective layers makes it less likely for the source-drain interconnect structure 110 and the source-drain plug 109 to be exposed.

[0139] During the process of etching the first dielectric layer 111 between the protective layers to form a groove 121 exposing the gate structure 101, the gate cap layer 107 is also etched. The protective layer is more difficult to etch than the gate cap layer 107.

[0140] Specifically, the material of the protective material layer 119 includes one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbonate, silicon oxyhydrogen oxycarbonate, silicon carbide, silicon carbonitride, aluminum nitride, and aluminum oxide. In this embodiment, the material of the protective material layer 119 includes silicon nitride. Silicon nitride is a commonly used dielectric material in processes and has high etching resistance.

[0141] In this embodiment, the protective material layer 119 is formed using atomic layer deposition (ALD). ALD involves multiple deposition cycles, facilitating precise control of the thickness of the protective material layer 119 and improving its thickness uniformity. Furthermore, ALD offers good gap-filling performance and step coverage, thereby enhancing the conformal coverage capability of the protective material layer 119, enabling it to conformally cover the source-drain interconnect structure 110 and the first dielectric layer 111. In other embodiments, the protective material layer can also be formed using chemical vapor deposition (CVD).

[0142] It should be noted that the protective material layer 119 should not be too thick or too thin. If the protective material layer 119 is too thick, it will require too much processing material and time to form the protective material layer 119, resulting in low formation efficiency and wasted resources. The subsequent removal of the protective material layer 119 on top of the first dielectric layer 111 will take too long and be difficult. In this embodiment, the material of the protective material layer 119 includes silicon nitride, which is a material with high stress. If the protective material layer 119 is too thick, it will disrupt the stress balance between the original protective layer and the first dielectric layer 111, the source-drain interconnect structure 110, and the source-drain plug 109, resulting in poor electrical performance of the semiconductor structure. If the protective material layer 119 is too thin, the subsequently formed protective layer will also be too thin. During the subsequent etching of the first dielectric layer 111 between the protective layers 118 to form a groove exposing the gate structure 101, the groove will easily expose the source-drain interconnect structure 110 and the source-drain plug 109. Consequently, the gate plug formed in the groove will easily bridge with the source-drain interconnect structure 110 and the source-drain plug 109, resulting in poor electrical performance of the semiconductor structure. In this embodiment, the thickness of the protective material layer 119 is 2 nanometers to 6 nanometers.

[0143] like Figures 24 to 26 As shown, the protective material layer 119 on top of the first dielectric layer 111 is removed, and the remaining protective material layer 119 located on the sidewall of the source-drain interconnect structure 110 and the first dielectric layer 111 serves as a protective layer 118.

[0144] Remove the protective material layer 119 on top of the first dielectric layer 111 to prepare for the subsequent formation of grooves in the first dielectric layer 111.

[0145] It should be noted that the method for forming the semiconductor structure further includes: after forming the protective material layer 119, and before forming the protective layer, forming a second dielectric layer 120 on the source-drain interconnect structure 110 that exposes the source-drain plug 109.

[0146] During the process of removing the protective material layer 119 on top of the first dielectric layer 111, the second dielectric layer 120 protects the source / drain plug 109 from accidental damage, allowing the source / drain plug 109 to better connect the multiple source / drain doped layers 102 to the source / drain interconnect structure 110.

[0147] In this embodiment, the material of the second dielectric layer 120 includes silicon oxide.

[0148] In this embodiment, a planarization process is used to remove the protective material layer 119 on top of the first dielectric layer 111.

[0149] Specifically, the planarization process includes chemical mechanical planarization (CMP). CMP is a global surface planarization technique that, while removing the protective material layer 119 from the top surface of the first dielectric layer 111, ensures that the top surfaces of the first dielectric layer 111 and the second dielectric layer 120 have high flatness. This provides a highly flat surface for subsequent etching processes to form grooves, thereby improving the accuracy of pattern transfer.

[0150] refer to Figure 27 and Figure 28 As shown, Figure 27 The first dielectric layer 111 and the second dielectric layer 120 are not shown in the diagram. Figure 28 for Figure 27 In the cross-sectional view at BB, the first dielectric layer 111 between the protective layers 118 is etched to form a groove 121 exposing the gate structure 101.

[0151] The groove 121 provides process space for the subsequent formation of the gate plug, and the groove 121 exposes the protective layer 118.

[0152] In this embodiment, a dry etching process is used to etch the first dielectric layer 111 between the protective layers 118, forming a groove 121 exposing the gate structure 101. The dry etching process has anisotropic etching characteristics, good control over the etching profile, and can achieve fairly accurate pattern transformation, which is beneficial for ensuring that the morphology of the groove 121 meets process requirements and also helps to improve the removal efficiency of the first dielectric layer. During the formation of the groove 121 using the dry etching process, the top of the gate structure 101 can be used as the etching stop position.

[0153] During the etching process of the first dielectric layer 111 between the protective layers 118 to form a groove 121 exposing the gate structure 101, the etching gas used includes HF.

[0154] It should be noted that during the process of etching the first dielectric layer 111 between the protective layers 118 to form the groove 121 exposing the gate structure 101, the gate cap layer 107 is also etched. The protective layer 118 is more difficult to etch than the gate cap layer 107, making it difficult for the groove 121 to expose the source-drain plug 109 and the source-drain interconnect structure 110.

[0155] refer to Figures 29 to 31 , Figure 29 The first dielectric layer 111 and the second dielectric layer 120 are not shown in the diagram. Figure 30 for Figure 29 Cross-sectional view at BB. Figure 31 for Figure 29 In the cross-sectional view at EE, a gate plug 122 is formed in the recess 121.

[0156] The gate plug 122 is used to electrically connect the gate structure 101 to the subsequent metal interconnect structure or external circuit. In this embodiment, the gate plug 122 is formed above the gate structure 101 between the source and drain doped layers 102 and is located in the active area. That is, the gate plug 122 is an active gate contact hole plug (COAG). Therefore, the portion of the gate structure 101 located in the isolation region is eliminated, which helps to save chip area, further reduce chip size, and improve the integration of semiconductor structure.

[0157] In this embodiment, the gate plug 122 is made of copper. Copper has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the gate plug 122, thereby reducing power consumption. In other embodiments, the gate plug may also be made of tungsten or cobalt.

[0158] The step of forming the gate plug 122 includes: forming a rear conductive material layer (not shown in the figure) in the first dielectric layer 111, the source-drain interconnect structure 110, the second dielectric layer 120 and the groove 121; removing the rear conductive material layer exposed in the groove 121, and the remaining rear conductive material layer in the groove 121 serves as the gate plug 122.

[0159] In this embodiment, the downstream conductive material layer is formed using an electrochemical plating (ECP) process.

[0160] In this embodiment, a chemical mechanical polishing process is used to remove the rear conductive material layer that exposes the groove 121, which helps to improve the flatness of the top surface of the gate plug 122.

[0161] In this embodiment, in the step of removing the rear conductive material layer that exposes the groove 121, the top of the first dielectric layer 111 and the second dielectric layer 120 is taken as the stop position for planarization, thereby reducing damage to other film layers.

[0162] While the embodiments of the present invention have been disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the embodiments of the present invention. Therefore, the scope of protection of the embodiments of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A gate structure is located on the substrate, parallel to the surface of the substrate, and the extension direction of the gate structure is transverse, while the extension direction perpendicular to the gate structure is longitudinal. Source and drain doped layers are located within the substrate on both sides of the gate structure; A source-drain stack is located on a plurality of said source-drain doped layers, the source-drain stack including source-drain plugs and source-drain interconnect structures standing on said source-drain plugs; The semiconductor structure includes: a gate plug, which is mounted on the gate structure; A protective layer is located on the lateral sidewall of the source-drain interconnect structure and the longitudinal sidewall of the gate plug.

2. The semiconductor structure as described in claim 1, characterized in that, The protective layer is also located on top of the source / drain plug.

3. The semiconductor structure as described in claim 1, characterized in that, The material of the protective layer includes one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbonate, silicon oxyhydrogen oxycarbonate, silicon carbide, silicon carbonitride, aluminum nitride, and aluminum oxide.

4. The semiconductor structure as described in claim 1, characterized in that, The thickness of the protective layer is 2 nanometers to 6 nanometers.

5. The semiconductor structure as described in claim 1, characterized in that, The source / drain plug includes: a conductive layer and a barrier layer located at the bottom and longitudinal sidewalls of the conductive layer; The source-drain interconnect structure includes: the conductive layer and the barrier layer located on the longitudinal sidewall of the conductive layer.

6. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure includes: a first dielectric layer located on the gate structure on the gate plug side; The semiconductor structure further includes a second dielectric layer located on the source / drain plug on the side of the source / drain interconnect structure.

7. The semiconductor structure as described in claim 1, characterized in that, The substrate includes: Substrate; Fins, respectively, are disposed on the substrate; An isolation layer is located on the substrate on the side of the fin, and the isolation layer covers a portion of the sidewall of the fin.

8. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided on which a gate structure is formed, and active and drain doped layers are formed in the substrate on both sides of the gate structure. A source-drain stack is formed on the source-drain doped layers, the source-drain stack comprising: a source-drain plug connecting multiple source-drain doped layers between the gate structures and a source-drain interconnect structure standing on the source-drain plug; The method for forming the semiconductor structure includes: after providing a substrate, before forming the source-drain stack, forming a first dielectric layer on the gate structure; The method for forming the semiconductor structure further includes: after forming the first dielectric layer, forming a protective layer on the sidewalls of the source-drain interconnect structure and the first dielectric layer, and on the top of the source-drain plug; etching the first dielectric layer between the protective layers to form a groove exposing the gate structure; and forming a gate plug in the groove.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing the substrate, an interlayer dielectric layer is formed on the substrate exposed by the gate structure, and the interlayer dielectric layer covers the sidewalls of the gate structure; The step of forming the first dielectric layer includes: forming a first dielectric material layer on the interlayer dielectric layer and the gate structure; The first dielectric material layer and the interlayer dielectric layer are etched to form source and drain openings that expose the source and drain doped layers. The remaining first dielectric material layer located on top of the gate structure serves as the first dielectric layer. The step of forming a source-drain plug connecting multiple source-drain doped layers and a source-drain interconnect structure standing on the source-drain plug between the gate structures includes: forming a first metal layer in the source-drain opening; The first metal layer is etched to form the source / drain plug and the source / drain interconnect structure standing on the source / drain plug.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first dielectric material layer and the interlayer dielectric layer are etched using a dry etching process to form source and drain openings that expose the source and drain doped layers.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming the first metal layer includes: conformally covering a barrier material layer in the source-drain opening; forming a conductive material layer on the barrier material layer exposed in the source-drain opening, wherein the barrier material layer and the conductive material layer serve as the first metal layer.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, The first metal layer is etched using a dry etching process to form the source / drain plug and the source / drain interconnect structure standing on the source / drain plug.

13. The method for forming a semiconductor structure as described in claim 8, characterized in that, The material of the protective layer includes one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbonate, silicon oxyhydrogen oxycarbonate, silicon carbide, silicon carbonitride, aluminum nitride, and aluminum oxide.

14. The method for forming a semiconductor structure as described in claim 8, characterized in that, The thickness of the protective layer is 2 nanometers to 6 nanometers.

15. The method for forming a semiconductor structure as described in claim 8, characterized in that, The steps for forming the protective layer include: A protective material layer is formed to conformally cover the source / drain plug and the source / drain interconnect structure located on the source / drain plug; The protective material layer on top of the first dielectric layer is removed, and the remaining protective material layer located on the sidewalls of the source-drain interconnect structure and the first dielectric layer, and on top of the source-drain plug, serves as a protective layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The protective material layer is formed using atomic layer deposition or chemical vapor deposition processes.

17. The method for forming a semiconductor structure as described in claim 15, characterized in that, The protective material layer on top of the first dielectric layer is removed by planarization.

18. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method for forming the semiconductor structure further includes: after forming the protective material layer and before forming the protective layer, forming a second dielectric layer on the source-drain plug exposed in the source-drain interconnect structure.

19. The method for forming a semiconductor structure as described in claim 8, characterized in that, The first dielectric layer between the protective layers is etched using a dry etching process to form a groove that exposes the gate structure.

20. The method for forming a semiconductor structure as described in claim 8, characterized in that, During the process of etching the first dielectric layer between the protective layers to form a groove exposing the gate structure, the protective layer is more difficult to etch than the first dielectric layer. In the step of providing the substrate, a gate cap layer is formed on the gate structure; During the process of etching the first dielectric layer between the protective layers to form a groove exposing the gate structure, the gate cap layer is also etched. The protective layer is more difficult to etch than the gate cap layer.

21. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of providing a substrate, the substrate includes: a substrate and fins disposed on the substrate; The substrate further includes an isolation layer located on the substrate on the side of the fin, and the isolation layer covers a portion of the sidewall of the fin.

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