Non-volatile memory cells

Abstract

The present invention discloses a memory cell of a non-volatile memory, comprising: an N-type region, an N-type well region, a P-type well region, a first P-type doped region, a second P-type doped region, and a first N-type doped region. The N-type well region and the P-type well region are formed in the N-type region. The first P-type doped region and the second P-type doped region are located on the surface of the N-type well region. A gate layer is located above the surface of the N-type well region between the first P-type doped region and the second P-type doped region. The first N-type doped region is located on the surface of the P-type well region. The gate layer extends to the P-type well region, and a first side of the gate layer is adjacent to the first N-type doped region.

Description

Technical Field

[0001] The present invention relates to a memory, and in particular to a storage unit of a non-volatile memory. Background Art

[0002] As is known to all, non-volatile memory can still retain its data content after power is turned off. Generally speaking, after the non-volatile memory is manufactured and shipped, the user can program the non-volatile memory to record data in the non-volatile memory.

[0003] Please refer to Figure 1 , which shows a schematic diagram of a memory cell array of a conventional non-volatile memory. The memory cell array 100 includes m×n memory cells c11 to cmn, and the memory cell array 100 is connected to m word lines WL1 to WLm, n bit lines BL1 to BLn, and m control lines CL1 to CLm. Furthermore, each memory cell c11 to cmn includes a floating gate transistor. The floating gate transistor is an n-type dual gate floating gate transistor, including a control gate terminal, a floating gate, a first drain / source terminal, and a second drain / source terminal. The floating gate is in a floating state (floating) and is not connected to any terminal.

[0004] In the n memory cells c11-c1n in the first column, the control gate terminal of the floating gate transistor is connected to word line WL1, the first drain / source terminal of the floating gate transistor is connected to control line CL1, and the second drain / source terminal of the floating gate transistor is connected to the corresponding n bit lines BL1-BLn. In the n memory cells c21-c2n in the second column, the control gate terminal of the floating gate transistor is connected to word line WL2, the first drain / source terminal of the floating gate transistor is connected to control line CL2, and the second drain / source terminal of the floating gate transistor is connected to the corresponding n bit lines BL1-BLn. Similarly, in the n memory cells cm1-cmn in the mth column, the control gate terminal of the floating gate transistor is connected to word line WLm, the first drain / source terminal of the floating gate transistor is connected to control line CLm, and the second drain / source terminal of the floating gate transistor is connected to the corresponding n bit lines BL1-BLn.

[0005] Basically, by applying appropriate bias voltages to word lines WL1-WLm, bit lines BL1-BLn, and control lines CL1-CLm, programming, erasing, or reading operations can be performed on memory cells c11-cmn in memory cell array 100. For example, by applying an activated voltage to word line WL1 and an inactivated voltage to the other word lines WL2-WLm, the first column connected to word line WL1 becomes the selected column, and programming, erasing, or reading operations can be performed on n memory cells c11-c1n in the selected column.

[0006] Furthermore, Figure 1 The memory cell array 100 in the embodiment is described using n-type double-gate floating gate transistors as an example. In practice, p-type double-gate floating gate transistors can also be used to form memory cells and form a memory cell array of a non-volatile memory. Summary of the Invention

[0007] The present invention provides a non-volatile memory cell. The transistor in the memory cell is a single-gate floating-gate transistor. Furthermore, properly designed bias voltages enable the memory cell to properly perform programming, erasing, or reading operations. Similarly, properly designed bias voltages also enable the memory cell array to properly perform programming, erasing, or reading operations.

[0008] The present invention is a memory cell of a non-volatile memory, comprising: an N-type region; an N-type well region and a P-type well region formed in the N-type region; a first P-type doped region and a second P-type doped region located on the surface of the N-type well region; a gate layer located above the surface of the N-type well region between the first P-type doped region and the second P-type doped region, and the gate layer extends from the N-type well region to the P-type well region; and a first N-type doped region located on the surface of the P-type well region, and the first N-type doped region is adjacent to a portion of the gate layer. a first side; wherein the gate layer, the N-type well region, the first p-type doped region, and the second p-type doped region form a p-type transistor; the gate layer, the P-type well region, and the first n-type doped region form a transistor capacitor, and the transistor capacitor and the p-type transistor share the gate layer; and the N-type region and the P-type well region form a diode; wherein a first drain / source terminal of the p-type transistor is connected to a bit line, a second drain / source terminal of the p-type transistor is connected to a source line, and the P-type well region and the n-type doped region are connected to a word line.

[0009] The present invention is a memory cell of a non-volatile memory, comprising: an N-type region; an N-type well region and a P-type well region formed in the N-type region; a first P-type doped region and a second P-type doped region located on the surface of the N-type well region; a gate layer located above the surface of the N-type well region between the first P-type doped region and the second P-type doped region; and a first N-type doped region located on the surface of the P-type well region, wherein the gate layer extends to the P-type well region, the gate layer is located above the first N-type doped region, and the gate layer is located above the P-type well region. The gate layer is a comb-shaped gate layer; wherein the gate layer, the N-type well region, the first p-type doped region and the second p-type doped region form a p-type transistor; the gate layer, the P-type well region and the first n-type doped region form a transistor capacitor, the transistor capacitor and the p-type transistor share the gate layer, and the N-type region and the P-type well region form a diode; wherein a first drain / source terminal of the p-type transistor is connected to a bit line, a second drain / source terminal of the p-type transistor is connected to a source line, and the n-type doped region is connected to a word line.

[0010] In order to better understand the above and other aspects of the present invention, preferred embodiments are given below with reference to the accompanying drawings for detailed description as follows: BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic diagram of a memory cell array of a conventional non-volatile memory;

[0012] Figures 2A to 2N A flowchart of manufacturing a memory cell array according to a first embodiment of the present invention and a cross-sectional view along dotted lines ab in each manufacturing process;

[0013] Figures 3A to 3C 1 is a cross-sectional view, an equivalent circuit, and a schematic diagram of a memory cell array according to a first embodiment of the present invention;

[0014] Figure 4 is a schematic diagram of a storage unit according to a second embodiment of the present invention;

[0015] 5A to 5D Schematic diagram of bias voltages for various operations of a memory cell according to a first embodiment of the present invention;

[0016] Figures 6A to 6H A flowchart of manufacturing a memory cell according to a third embodiment of the present invention and a cross-sectional view along dotted line ef in each manufacturing process; and

[0017] Figure 7A and Figure 7B 1 is a cross-sectional view of a memory cell according to a third embodiment of the present invention and a schematic diagram of an equivalent circuit.

[0018] Explanation of symbols

[0019] 100: memory cell array

[0020] 110,610: Isolation structure

[0021] 111,112,121,122,611: Gate layer

[0022] 115: Gate oxide layer

[0023] 131,132,133,134,135,136,141,142,143,144,631,632: p-type doped regions

[0024] 141,152,633: n-type doped region

[0025] 161,162,163,164,165,166,167,168,169,170,661,662,663: Metal wires DETAILED DESCRIPTION

[0026] Please refer to Figures 2A to 2N , which illustrates a fabrication flow chart of a memory cell array according to a first embodiment of the present invention, along with cross-sectional views along dashed lines ab during each fabrication process. Furthermore, the following description uses a non-volatile memory cell array consisting of 2×2 memory cells. Of course, the present invention is not limited to this embodiment; those skilled in the art can construct a non-volatile memory cell array consisting of m×n memory cells based on the teachings of the present invention.

[0027] like Figure 2A and Figure 2B As shown, a deep N-type well region (DNW for short) is formed on a p-type semiconductor substrate (substrate, p_sub).

[0028] like Figure 2C and Figure 2D As shown, the isolation structure forming step is performed. Figure 2C As shown, after the isolation structure 110 is formed in the deep N-type well region DNW, the isolation structure 110 defines region A, region B, region C1, and region C2 on the surface of the deep N-type well region DNW.

[0029] like Figure 2E and Figure 2FAs shown, a well region formation step is performed. A mask is designed to expose only region B, and a P-type well region PW formation step is performed on region B. A P-type well region PW is formed beneath the surface of region B. Furthermore, a mask is designed to expose only regions C1 and C2, and N-type well regions NW1 and NW2 formation steps are performed on regions C1 and C2. N-type well regions NW1 and NW2 are formed beneath the surfaces of regions C1 and C2, respectively. N-type well regions NW1, NW2, and P-type well region PW are formed within a deep N-type well region DNW. Furthermore, deep N-type well region DNW, N-type well regions NW1, and NW2 are of the same N-type.

[0030] like Figure 2G and Figure 2H As shown, a gate structure forming step is performed to form gate layers 111, 112, 121, and 122, wherein the gate layers 111, 112, 121, and 122 are polysilicon gate layers. Figure 2G As shown, gate layer 111 and gate layer 112 cover the surface of N-type well region NW1, and gate layer 111 and gate layer 112 divide N-type well region NW1 into three parts. Gate layer 111 and gate layer 112 extend to P-type well region PW and cover P-type well region PW. Similarly, gate layer 121 and gate layer 122 cover the surface of N-type well region NW2, and gate layer 121 and gate layer 122 divide N-type well region NW2 into three parts. Gate layer 121 and gate layer 122 extend to P-type well region PW and cover P-type well region PW. Furthermore, as Figure 2H As shown, in addition to the gate layer 111, the gate structure further includes a gate oxide layer 115 located below the gate layer 111. Similarly, gate oxide layers are also located below the other gate layers 112, 121, and 122.

[0031] like Figure 2I and Figure 2J As shown, the p-type doping region formation step is performed. A cross-hatch mask is designed to expose the N-type well regions NW1 and NW2 and expose a portion of the P-type well region PW. Next, ion implantation is performed to complete the p-type doping region formation step. As a result, the portion of the N-type well region NW1 not covered by the two gate layers 111 and 112 forms p-type doping regions (p+) 131, 132, and 133; the portion of the N-type well region NW2 not covered by the two gate layers 121 and 122 forms p-type doping regions (p+) 134, 135, and 136; and the portion of the P-type well region PW not covered by the mask and the four gate layers 111, 112, 121, and 122 forms p-type doping regions (p+) 141, 142, 143, and 144.

[0032] In addition, if Figure 2J As shown, the gate layer 111 between the two p-type doped regions (p+) 131 and 132 (i.e., the gate layer 111 covering the N-type well region NW1) also forms a p-type gate layer (p+). Similarly, the first side of the gate layer 111 is adjacent to the p-type doped region (p+) 142, and the gate layer 111 on the first side (i.e., the first portion of the gate layer 111 covering the P-type well region PW) also forms a p-type gate layer (p+).

[0033] like Figure 2K and Figure 2L As shown, the n-type doping region formation step is performed. A cross-slash mask is designed to expose region A (i.e., the deep N-type well region DNW) and a portion of the P-type well region PW. Next, ion implantation is performed to complete the n-type doping region formation step. As a result, an n-type doping region (n+) 151 is formed in the deep N-type well region DNW; an n-type doping region (n+) 152 is formed in the portion of the P-type well region PW that is not covered by the mask and the four gate layers 111, 112, 121, and 122, so that the P-type well region PW includes p-type doping regions (p+) 141 to 144 and an n-type doping region (n+) 152.

[0034] In addition, if Figure 2L As shown, the second side of the gate layer 111 is adjacent to the n-type doped region (n+) 152, and the gate layer 111 on the second side (i.e., the second portion of the gate layer 111 covering the p-type well region PW) forms an n-type gate layer (n+). In other words, the gate layer 111 of the memory cell of the first embodiment includes a p-type gate layer (p+) and an n-type gate layer (n+). That is, the gate layer 111 on the n-type well region NW1 includes the p-type gate layer (p+), and the gate layer 111 on the p-type well region PW includes the p-type gate layer (p+) and the n-type gate layer (n+). Furthermore, the p-type gate layer (p+) of the gate layer 111 on the p-type well region PW is adjacent to the p-type doped region (p+) 142, and the n-type gate layer (n+) of the gate layer 111 on the p-type well region PW is adjacent to the n-type doped region (n+) 152.

[0035] like Figure 2M and Figure 2N As shown in FIG, after the metal contact step is performed, the memory cell array of the present invention is formed. Figure 2M As shown, metal wires 161 and 169 are formed to contact n-type doped regions (n+) 151 and 152 respectively; metal wires 162 to 168 are respectively in contact with p-type doped regions (p+) 131 to 136 and p-type doped region 142. In addition, in subsequent processes, metal wires 168 and metal wires 169 will be connected to each other. Therefore, Figure 2MThe memory cell array in the embodiment includes four memory cells with the same structure. Figure 2N A cross-sectional view of a storage unit.

[0036] exist Figure 2N In the memory cell, the metal wire 168 is designed to be connected to the P-type well region PW via the p-type doped region (p+) 142. Since the P-type well region PW is very wide, all four memory cells share this P-type well region PW. In other embodiments, the metal wire can also be designed to be in other p-type doped regions (p+). For example, the metal wire 170 is designed to be connected to the P-type well region PW via the p-type doped region (p+) 141, so as to replace the metal wire 168. Similarly, the metal wire 161 is connected to the deep N-type well region DNW via the n-type doped region (n+) 151. Those skilled in the art can also design the metal wire in other locations and connect it to the deep N-type well region DNW via the n-type doped region (n+) to replace the metal wire 161.

[0037] In other words, in Figure 2M In the cross-sectional view along the bc dashed line, the storage unit will be similar to Figure 2N , but lacks the n-type doped region (n+) 151, metal wires 168 and 161. In fact, Figure 2M The four memory cells share the same P-type well region PW and deep N-type well region DNW. Therefore, the bias voltages of the deep N-type well region DNW and the P-type well region PW can be controlled by using the metal wires 161 and 168.

[0038] Please refer to Figures 3A to 3C , which depicts a cross-sectional view of a memory cell according to a first embodiment of the present invention, an equivalent circuit (the equivalent circuit of the diode formed by the junction between the deep N-type well region DNW and the p-type semiconductor substrate p_sub is omitted here) and a memory cell array. Figure 3A and Figure 3B As shown, the memory cell includes a p-type transistor Mp, an n-type transistor Mn and a diode D. The p-type transistor Mp and the n-type transistor Mn share a gate layer 111. The N-type well region NW1, the p-type doped region 131, the p-type doped region 132 and the gate layer 111 constitute the p-type transistor Mp, and the gate layer 111 is a floating gate layer (floating gate layer), that is, the p-type transistor Mp is a single-gate floating gate transistor. Furthermore, the metal wire 162 is connected to the p-type doped region 131, and the metal wire 162 serves as the bit line BL1; the metal wire 163 is connected to the p-type doped region 132, and the metal wire 163 serves as the source line SL1; the metal wire 161 is connected to the deep N-type well region DNW via the n-type doped region n+ (151), and the metal wire 161 serves as the deep N-type well region terminal T DNWTherefore, the first drain / source terminal of the p-type transistor Mp is connected to the bit line BL1, the second drain / source terminal of the p-type transistor Mp is connected to the source line SL1, and the body terminal of the p-type transistor Mp is connected to the deep N-type well region terminal T DNW .

[0039] Furthermore, the p-type well region PW, the n-type doped region 152, and the gate layer 111 form an n-type transistor Mn. Metal wire 169 is connected to the n-type doped region 152 and serves as word line WL1. Metal wire 168 is connected to the p-type well region PW via the p-type doped region 142 and is also connected to word line WL1. Therefore, in the n-type transistor Mn, the n-type doped region 152 can be considered as two n-type doped regions merged together. Therefore, the drain and source terminals of the n-type transistor Mn are connected to each other and to word line WL1, and the body terminal of the n-type transistor Mn is also connected to word line WL. This connection relationship of the n-type transistor Mn makes the n-type transistor Mn a transistor capacitor. That is, the memory cell includes the p-type transistor Mp, the transistor capacitor, and the diode D. The first terminal of the transistor capacitor is the gate layer 111, and the second terminal of the transistor capacitor (i.e., the p-type doped region 142 and the n-type doped region 152) is connected to the word line WL1.

[0040] Furthermore, the P-type well region PW and the deep N-type well region DNW form a pn junction, forming a diode D. That is, the anode of diode D is connected to the body terminal of the n-type transistor Mn, and the cathode of diode D is connected to the body terminal of the p-type transistor Mp. Furthermore, the deep N-type well region DNW forms a pn junction with the p-type semiconductor substrate p_sub, also forming another diode connected back-to-back with diode D.

[0041] like Figure 3C As shown, the memory cell array includes four memory cells c11, c12, c21, and c22 with the same structure. The memory cell array is connected to source lines SL1-SL2, bit lines BL1-BL4, and word line WL1.

[0042] Taking memory cell c11 as an example, the two drain / source terminals and the body terminal of transistor Mn are connected to each other and to word line WL1. Transistor Mp is connected to the gate terminal 111 of transistor Mn. The first drain / source terminal of p-type transistor Mp is connected to bit line BL1, the second drain / source terminal of p-type transistor Mp is connected to source line SL1, and the body terminal of p-type transistor Mp is connected to the deep N-type well region terminal T DNWThe anode of the diode D is connected to the body terminal of the n-type transistor Mn, and the cathode of the diode D is connected to the body terminal of the p-type transistor Mp.

[0043] Similarly, the memory cells c12, c21, and c22 have similar connection relationships, which will not be described here. In addition, in the four memory cells, the body terminals of the p-type transistors Mp are all connected to the N-type well terminal T DNW , the body of the p-type transistor Mp is connected to the word line WL1. Figure 3C In the memory cell array, the source lines SL1 and SL2 can be connected to each other. Figure 3C The memory cell array can share one source line.

[0044] Furthermore, the memory cell of the first embodiment is fabricated on a p-type semiconductor substrate (p_sub). Of course, the present invention is not limited thereto, and the memory cell can also be fabricated on an n-type semiconductor substrate (n_sub). Figure 4 , which illustrates a memory cell according to a second embodiment of the present invention. Compared to the memory cell of the first embodiment, the memory cell is formed directly on an n-type semiconductor substrate (n_sub). Otherwise, the memory cell structures of the first and second embodiments are similar, and the memory cells of the first and second embodiments have the same equivalent circuits.

[0045] Please refer to 5A to 5D , which is a schematic diagram of bias voltages for various operations of the memory cell according to the first embodiment of the present invention. Of course, the various bias voltages of the memory cell according to the first embodiment are also applicable to the memory cell according to the second embodiment.

[0046] like Figure 5A As shown, during programming, the word line WL and the deep N-type well region end T DNW Receive the programming voltage Vpgm, that is, the body terminals of the p-type transistor Mp and the n-type transistor Mn receive the programming voltage Vpgm. Furthermore, the source line SL receives the source line voltage V SL , the bit line BL receives the ground voltage (0V). Wherein, the programming voltage Vpgm is greater than the source line voltage V SL , source line voltage V SL is greater than the voltage received by the bit line BL (ie, the ground voltage (0V)). For example, the programming voltage Vpgm is 9V, and the source line voltage V SL is 4V.

[0047] In the n-type transistor Mn, because the bit line WL and the p-type well region PW receive a programming voltage Vpgm of 9V, the programming voltage Vpgm is coupled to the gate layer 111, causing the voltage on the gate layer 111 to be approximately the programming voltage Vpgm of 9V. Furthermore, because the gate layer 111 is at the programming voltage Vpgm, the p-type transistor Mp is turned off. Because the bit line BL receives a ground voltage, a band-to-band tunneling-induced hot electron injection (BBHE) effect occurs between the p-type doped region 131 and the gate layer 111, causing electrons to be injected from the p-type doped region 131 into the gate layer 111. Therefore, performing programming operations using the BBHE effect can cause less damage to the gate oxide layer 115; and, the p-type doped region (p+) 142 and the n-type doped region (n+) 152 included in the P-type well region PW can provide sufficient capacitance during the programming operation to improve / maintain the charge coupling ratio, thereby increasing the electron injection efficiency and improving the programming efficiency.

[0048] Please refer to Figure 5B and Figure 5C , which is a schematic diagram of a memory cell read operation. During the read operation, the word line WL receives the word line voltage V WL , deep N-type well region end T DNW Receive deep N-type well voltage V DNW , the source line SL receives the read voltage Vr, and the bit line BL receives the ground voltage (0V). DNW is greater than or equal to the read voltage Vr, and the read voltage Vr is greater than the word line voltage V WL , word line voltage V WL is greater than the ground voltage (0V). For example, the deep N-type well voltage V DNW With the read voltage Vr being 2V, the word line voltage V WL is 1V.

[0049] like Figure 5B As shown, when the gate layer 111 stores electrons, the p-type transistor Mp is turned on, and a large read current Ir is generated between the source line SL and the bit line BL. Figure 5CAs shown, when the gate layer 111 is not storing electrons, the p-type transistor Mp is turned off, generating a nearly zero read current Ir between the source line SL and the bit line BL. In other words, during a read operation, the memory cell's storage state can be determined based on the magnitude of the read current Ir. For example, when the read current Ir is large, the memory cell is confirmed to be in the first storage state, storing electrons. When the read current Ir is very small, the memory cell is confirmed to be in the second storage state, not storing electrons.

[0050] like Figure 5D As shown, during the erase operation, the word line WL receives the word line voltage V WL , deep N-type well region end T DNW , the source line SL and the bit line BL receive the erase voltage V ERS Among them, the erase voltage V ERS Greater than the word line voltage V WL And the word line voltage V WL Less than the ground voltage (0V). For example, the erase voltage V ERS is 9V, the character line voltage V WL is -9V. At this time, Fowler-Nordheim tunneling (FN tunneling) occurs between the gate layer 111 and the channel of the p-type transistor Mp, and electrons are ejected from the gate layer 111 to the N-type well region NW1 of the p-type transistor Mp. Based on this, the p-type doped region (p+) 142 and the n-type doped region (n+) 152 included in the P-type well region PW can provide sufficient capacitance during the erase operation to improve the erase efficiency. In one embodiment, the p-type semiconductor substrate p_sub can receive a substrate voltage during the erase operation, and the substrate voltage is less than the erase voltage V ERS , for example, the substrate voltage is -20V.

[0051] The bias voltages of the various actions described above can be used to control any memory cell in the memory cell array, and perform programming, reading, and erasing operations on the selected memory cell.

[0052] Please refer to Figures 6A to 6H , which illustrates a manufacturing flow chart of a memory cell according to a third embodiment of the present invention and a cross-sectional view along dotted line ef in each manufacturing process.

[0053] The initial process steps for the memory cell of the second embodiment are similar to those of the first embodiment. First, a deep N-type well region DNW is formed on a p-type semiconductor substrate p_sub. Next, an isolation structure 610 is formed within the deep N-type well region DNW, separating the surface of the deep N-type well region DNW into two regions. Next, a secondary well region formation step is performed, forming a P-type well region PW and an N-type well region NW in each of the two regions.

[0054] like Figure 6A and Figure 6B As shown, a gate structure formation step is performed and a gate layer 611 is formed. According to the third embodiment of the present invention, the gate layer 611 is a comb gate layer, and the gate layer 611 is a polysilicon gate layer. The gate layer 611 covers the surface of the N-type well region NW, and the gate layer 611 divides the N-type well region NW into two parts. The gate layer 611 extends to the P-type well region PW and covers the P-type well region PW. Furthermore, the gate layer 611 covering the P-type well region PW includes a plurality of finger-like branches, each of which has a gap between them. In addition, in addition to the gate layer 611, the gate structure also includes a gate oxide layer 615 located below the gate layer 611.

[0055] like Figure 6C and Figure 6D As shown, the p-type doping region forming step is performed. P-type doping regions (p+) 631 and 632 are formed in the portion of the N-type well region NW not covered by the gate layer 611. Figure 6D As shown, the gate layer 611 between the two p-type doped regions (p+) 631 and 632 also forms a p-type gate layer (p+).

[0056] like Figure 6E and Figure 6F As shown, the n-type doped region formation step is performed. An n-type doped region (n+) 633 is formed in the portion of the P-type well region PW not covered by the gate layer 611. Similarly, the gate layer 611 covering the P-type well region forms an n-type gate layer (n+). In other words, the gate layer 611 of the memory cell of the third embodiment includes a p-type gate layer (p+) and an n-type gate layer (n+).

[0057] According to the third embodiment of the present invention, since the finger-shaped branches of the gate layer 611 are very narrow, the n-type gate layer (n+) formed between each finger-shaped branch will diffuse and overlap, thereby forming a merged n-type doped region (merged n+ doped region). In other words, the n-type doped region 633 is located below the finger-shaped branches of the gate layer 611 and below the surface between the finger-shaped branches.

[0058] like Figure 6G and Figure 6H As shown in FIG, after the metal contact step is performed, the memory cell array of the present invention is formed. Figure 6G and Figure 6H As shown, metal wires 661 and 662 are formed to contact the p-type doped regions (p+) 631 and 632 respectively. A metal wire 663 is formed to contact the n-type doped region (n+) 663.

[0059] in addition, Figures 6A to 6H Only the manufacturing process of a single memory cell is shown. Of course, those skilled in the art can apply the manufacturing process disclosed in the first embodiment to the third embodiment and manufacture the memory cell of the third embodiment into a memory cell array. Similar to the memory cell of the first embodiment, since the P-type well region PW is wider, the P-type well region PW can be connected to a metal wire (not shown) via a p-type doped region (p+) and connected to the word line WL. Similarly, the deep N-type well region DNW can be connected to another metal wire (not shown) via an n-type doped region (n+) as the deep N-type well region terminal T DNW .

[0060] Please refer to Figure 7A and Figure 7B , which shows a cross-sectional view and an equivalent circuit of a memory cell according to a third embodiment of the present invention (the equivalent circuit of the diode formed by the junction of the deep N-type well region DNW and the p-type semiconductor substrate p_sub is omitted). Figure 7A As shown, the memory cell includes a p-type transistor Mp and a transistor capacitor C. The N-type well region NW, the p-type doped region 631, the p-type doped region 632 and the gate layer 611 constitute the p-type transistor Mp, and the gate layer 611 is a floating gate layer (floating gate layer), that is, the p-type transistor Mp is a single-gate floating gate transistor. Furthermore, the metal wire 661 is connected to the p-type doped region 631, and the metal wire 661 serves as the bit line BL; the metal wire 662 is connected to the p-type doped region 632, and the metal wire 662 serves as the source line SL. Therefore, the first drain / source terminal of the p-type transistor Mp is connected to the bit line BL, and the second drain / source terminal of the p-type transistor Mp is connected to the source line SL. In addition, the body terminal of the p-type transistor Mp is connected to the deep N-type well region terminal T DNW .

[0061] Furthermore, the P-type well region PW, the n-type doped region 633, and the gate layer 611 form a transistor capacitor C. The first end of the transistor capacitor C is the gate layer 611, and the second end of the transistor capacitor C is the n-type doped region 633. A metal wire 663 is connected to the n-type doped region 633, and the metal wire 663 serves as a word line WL. Therefore, the second end of the transistor capacitor C is connected to the word line WL.

[0062] In addition, the P-type well region PW and the deep N-type well region DNW form a pn junction, forming a diode D. That is, the anode of the diode D is connected to the body terminal of the n-type transistor Mn, and the cathode of the diode D is connected to the body terminal of the p-type transistor Mp.

[0063] Basically, in the memory cell of the third embodiment, since gate layer 611 is a comb gate layer, a merged n-type doped region (n+) 633 is formed. Therefore, n-type doped regions (n+) 633 are also formed beneath the finger-shaped branches of gate layer 611. This provides a sufficient effective capacitance value for transistor capacitor C and improves the charge coupling ratio, further facilitating programming and erasing operations. Furthermore, the equivalent circuit of the third embodiment is the same as that of the first embodiment, so the bias voltages for programming, reading, and erasing operations in the third embodiment are the same as those in the memory cell of the first embodiment. This will not be further elaborated here.

[0064] Furthermore, the memory cell of the third embodiment is fabricated on a p-type semiconductor substrate (p_sub). Of course, the present invention is not limited thereto, and the memory cell may also be fabricated on an n-type semiconductor substrate (n_sub) similar to the second embodiment.

[0065] In summary, while the present invention has been disclosed in conjunction with the preferred embodiments described above, they are not intended to limit the present invention. Persons skilled in the art may make various modifications and alterations without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A storage unit of a non-volatile memory, comprising: N-type region; An N-type well region and a P-type well region are formed in the N-type region; A first p-type doping region and a second p-type doping region are located on a surface of the N-type well region; a gate layer located above a surface of the N-type well region between the first p-type doping region and the second p-type doping region, and the gate layer extends from the N-type well region to the P-type well region; as well as a first n-type doped region, located on a surface of the P-type well region, and adjacent to a first side of the gate layer; wherein the gate layer, the N-type well region, the first p-type doped region, and the second p-type doped region form a p-type transistor; the gate layer, the P-type well region, and the first n-type doped region form a transistor capacitor, the transistor capacitor and the p-type transistor share the gate layer; and the N-type region and the P-type well region form a diode; wherein the first drain / source terminal of the p-type transistor is connected to a bit line, the second drain / source terminal of the p-type transistor is connected to a source line, and the p-type well region and the first n-type doped region are connected to a word line; The gate layer is a floating gate layer, and the gate layer covering the P-type well region includes a p-type gate layer and an n-type gate layer; In which, the surface of the P-type well region also includes a third p-type doped region; the gate layer extends to the P-type well region, and the second side of the gate layer is adjacent to the third p-type doped region; the first side of the gate layer is the n-type gate layer; and the second side of the gate layer is the p-type gate layer, and the third p-type doped region is connected to the word line.

2. The storage unit of the non-volatile memory according to claim 1, During a programming action, the word line receives a programming voltage, the source line receives a source line voltage, the bit line receives a ground voltage, the body terminal of the p-type transistor receives the programming voltage, and the p-type well region receives the programming voltage via the third p-type doped region. The programming voltage is greater than the source line voltage, and the source line voltage is greater than the ground voltage.

3. The memory cell of the non-volatile memory as claimed in claim 2 , wherein during the programming operation, a band-to-band tunneling-induced hot electron injection effect occurs between the first p-type doped region and the gate layer, and a plurality of electrons are injected from the first p-type doped region into the gate layer.

4. The memory cell of the non-volatile memory as claimed in claim 2 , wherein during a read operation, the word line receives a word line voltage, the source line receives a read voltage, the bit line receives a ground voltage, the body terminal of the p-type transistor receives a deep N-type well voltage, the P-type well receives the word line voltage via the third p-type doped region, the deep N-type well voltage is greater than or equal to the read voltage, the read voltage is greater than the word line voltage, and the word line voltage is greater than the ground voltage.

5. The memory cell of the non-volatile memory as claimed in claim 4, wherein during the read operation, a read current is generated between the source line and the bit line; and the storage state of the memory cell is determined according to the magnitude of the read current.

6. The memory cell of the non-volatile memory as claimed in claim 2 , wherein during an erase operation, the word line receives a word line voltage, the source line receives an erase voltage, the bit line receives the erase voltage, a terminal of the p-type transistor receives the erase voltage, the p-type well region receives the word line voltage via the third p-type doped region, the erase voltage is a positive voltage, and the word line voltage is a negative voltage.

7. The memory cell of the non-volatile memory as claimed in claim 6, wherein during the erase operation, an FN tunneling effect occurs between the gate layer and the channel of the p-type transistor, and a plurality of electrons exit from the gate layer to the N-type well region of the p-type transistor.

Images