Light emitting display apparatus and multi-screen display apparatus including the same

Abstract

A light emitting display apparatus and a multi-screen display apparatus including the same are disclosed. The light emitting display apparatus includes a substrate, a light emitting device layer including a light emitting device disposed on the substrate, a weir pattern portion disposed at an edge portion of the substrate, an encapsulation layer disposed on the light emitting device layer and including an organic material disposed in an inner region surrounded by the weir pattern portion, and a device isolation portion disposed at the edge portion of the substrate to isolate the light emitting device, wherein the weir pattern portion includes a discontinuous weir pattern disposed along the edge portion of the substrate.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0153377, filed on November 17, 2020, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] The present invention relates to a light-emitting display device and a multi-screen display device including the light-emitting display device. Background Technology

[0004] Unlike liquid crystal displays (LCDs), light-emitting displays, being self-emissive, do not require a separate light source, allowing them to be manufactured in a thinner and lighter form factor. Furthermore, light-emitting displays operate at low voltage, resulting in reduced power consumption. In addition, light-emitting displays excel in color reproduction, response time, viewing angle, and contrast, making them a highly anticipated next-generation display technology.

[0005] Light-emitting display devices display images based on the light emitted by a light-emitting device layer, which includes light-emitting devices, disposed between two electrodes. In this case, the light emitted by the light-emitting devices is released to the outside through the electrodes and the substrate.

[0006] The light-emitting display device includes a display panel configured to display an image. The display panel may include a display area comprising a plurality of pixels for displaying the image, and a border area surrounding the display area.

[0007] Related light-emitting display devices require a bezel or mechanism to cover the bezel area located at the boundary (or periphery) of the display panel. Furthermore, these devices often have a large bezel width due to the presence of the bezel. Moreover, when the bezel width of the light-emitting display device decreases below a certain limit, the light-emitting device deteriorates due to the penetration of external foreign matter, such as moisture or humidity, thus reducing its reliability.

[0008] Recently, multi-screen luminescent display devices that achieve large screens by arranging luminescent display devices in a grid pattern have been commercialized.

[0009] However, in multi-screen emissive display devices of related technologies, the border areas or borders of each of the multiple emissive display devices create boundary portions such as seams between adjacent emissive display devices. When an image is displayed on the entire screen of a multi-screen emissive display device, the boundary portions cause a sense of discontinuity (or non-discontinuity) in the image, which reduces the viewer's immersion in the image. Summary of the Invention

[0010] Therefore, the present invention aims to provide a light-emitting display device and a multi-screen display device including the light-emitting display device that substantially overcome one or more problems caused by the limitations and disadvantages of related technologies.

[0011] One aspect of the present invention aims to provide a light-emitting display device having a narrow bezel width and preventing the reliability of the light-emitting device from being reduced due to moisture penetration, and a multi-screen display device including the light-emitting display device.

[0012] Another aspect of the present invention aims to provide a light-emitting display device having a zero bezel and preventing the reliability of the light-emitting device from being reduced due to moisture penetration, and a multi-screen display device including the light-emitting display device.

[0013] Other advantages and features of the invention will be set forth in part in the description which follows, some of which will become apparent to those skilled in the art upon review of the following description or will be learned by practice of the invention. These objects and other advantages of the invention may be realized and obtained by means of the structures specifically pointed out in the specification, its claims, and the accompanying drawings.

[0014] To achieve these and other advantages and in accordance with the intent of the invention, as embodied and generally described herein, a light-emitting display device includes: a substrate; a light-emitting device layer including light-emitting devices disposed on the substrate; a weir pattern portion disposed on an edge portion of the substrate; an encapsulation layer disposed on the light-emitting device layer and including an organic material disposed in an inner region surrounded by the weir pattern portion; and a device isolation portion disposed on an edge portion of the substrate to isolate the light-emitting devices, the weir pattern portion including a discontinuous weir pattern disposed along the edge portion of the substrate.

[0015] In another aspect of the invention, a light-emitting display device includes: a substrate; a device isolation portion including a first device isolation pattern and a second device isolation pattern disposed on an edge portion of the substrate to have an eaves structure; a light-emitting device layer disposed on the substrate; a weir pattern portion disposed between the first device isolation pattern and the second device isolation pattern; and an encapsulation layer including an organic material disposed on the light-emitting device layer and disposed in an inner region surrounded by the weir pattern portion, the light-emitting device layer including a light-emitting device including an isolation region isolated by the device isolation portion, and the weir pattern portion including: a first weir pattern including a plurality of linear weir patterns spaced apart from each other; and a second weir pattern filling between and disposed on the plurality of linear weir patterns.

[0016] In another aspect of the invention, a multi-screen display device includes: a plurality of display devices disposed along at least one of a first direction and a second direction intersecting the first direction, each of the plurality of display devices including a light-emitting display device, the light-emitting display device including: a substrate; a light-emitting device layer including light-emitting devices disposed on the substrate; a weir pattern portion disposed on an edge portion of the substrate; an encapsulation layer disposed on the light-emitting device layer and including an organic material disposed in an inner region surrounded by the weir pattern portion; and a device isolation portion disposed on an edge portion of the substrate to isolate the light-emitting devices, the weir pattern portion including a discontinuous weir pattern disposed along the edge portion of the substrate.

[0017] In another aspect of the invention, a multi-screen display device includes: a plurality of display devices disposed along at least one of a first direction and a second direction intersecting the first direction, each of the plurality of display devices including a light-emitting display device, the light-emitting display device including: a substrate; a device isolation portion including a first device isolation pattern and a second device isolation pattern disposed on an edge portion of the substrate to have an eaves structure; a light-emitting device layer disposed on the substrate; a weir pattern portion disposed between the first device isolation pattern and the second device isolation pattern; and an encapsulation layer including an organic material disposed on the light-emitting device layer and disposed in an inner region surrounded by the weir pattern portion, the light-emitting device layer including a light-emitting device including an isolation region isolated by the device isolation portion, and the weir pattern portion including: a first weir pattern including a plurality of linear weir patterns spaced apart from each other; and a second weir pattern filling between the plurality of linear weir patterns and disposed on the plurality of linear weir patterns.

[0018] According to embodiments of the present invention, a light-emitting display device having a narrow bezel width and preventing the reliability of the light-emitting device from being reduced due to moisture penetration, and a multi-screen display device including the light-emitting display device, can be provided.

[0019] According to embodiments of the present invention, a light-emitting display device having zero bezel and preventing the reliability of the light-emitting device from being reduced due to moisture penetration, and a multi-screen display device including the light-emitting display device, can be provided.

[0020] According to embodiments of the present invention, the reliability reduction of the light-emitting device caused by lateral penetration of moisture or humidity due to loss or absence of device isolation portions can be prevented or minimized.

[0021] According to some embodiments of the present invention, a display device without a border or with a zero border and a multi-screen display device including the display device can be provided.

[0022] According to some embodiments of the present invention, a multi-screen display device for displaying images without a sense of discontinuity can be provided.

[0023] It should be understood that the foregoing general description and the following detailed description of the invention are illustrative and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0024] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and form a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0025] Figure 1 This is a diagram illustrating a light-emitting display device according to an embodiment of the present invention.

[0026] Figure 2 It is a diagram Figure 1 The equivalent circuit diagram of a sub-pixel is shown below.

[0027] Figure 3 It is along Figure 1 The cross-sectional view shown is taken by line I-I'.

[0028] Figure 4 It is along Figure 1 The cross-sectional view taken by line II-II' shown.

[0029] Figure 5 yes Figure 3 An enlarged view of region "B1" shown.

[0030] Figure 6 yes Figure 3 An enlarged view of region "B2" shown.

[0031] Figure 7 It is along Figure 1 Another cross-sectional view taken by line I-I' shown.

[0032] Figure 8 It is along Figure 1 Another cross-sectional view taken from line II-II' shown.

[0033] Figure 9 It is along Figure 1 Another cross-sectional view taken by line I-I' shown.

[0034] Figure 10 It is along Figure 1Another cross-sectional view taken from line II-II' shown.

[0035] Figure 11 It is along Figure 1 Another cross-sectional view taken by line I-I' shown.

[0036] Figure 12 It is along Figure 1 Another cross-sectional view taken from line II-II' shown.

[0037] Figure 13 It is along Figure 1 Another cross-sectional view taken by line I-I' shown.

[0038] Figure 14 It is along Figure 1 Another cross-sectional view taken from line II-II' shown.

[0039] Figure 15 This is a plan view illustrating a light-emitting display device according to another embodiment of the present invention.

[0040] Figure 16 This is a schematic side view illustrating a light-emitting display device according to another embodiment of the present invention.

[0041] Figure 17 yes Figure 15 An enlarged view of region "B3" shown.

[0042] Figure 18 yes Figure 15 Another enlarged view of area "B3" shown.

[0043] Figure 19 It is a diagram Figure 15 The front perspective view of the light-emitting display device shown.

[0044] Figure 20 It is a diagram Figure 15 A diagram showing the rear surface of the light-emitting display device.

[0045] Figure 21 yes Figure 19 An enlarged view of region "B4" shown.

[0046] Figure 22 It is a diagram Figure 15 and Figure 19 The circuit diagram for one pixel is shown.

[0047] Figure 23 It is a diagram Figure 19 and Figure 21 The diagram shows the gate drive circuitry set in the display area shown.

[0048] Figure 24 It is along Figure 19 The cross-sectional view taken by line III-III' shown.

[0049] Figure 25 yes Figure 24 An enlarged view of area "B5" shown.

[0050] Figure 26 It is along Figure 19 The cross-sectional view shown is taken from line IV-IV'.

[0051] Figure 27 This is an illustration of a multi-screen display device according to an embodiment of the present invention.

[0052] Figure 28 It is along Figure 27 The cross-sectional view shown is taken by line V-V'. Detailed Implementation

[0053] Reference will now be made in detail to embodiments of the invention, some examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or constructions relevant to this document will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the gist of the inventive concept. The described processing steps and / or the sequence of operations are exemplary; however, the order of steps and / or operations is not limited to those set forth herein, but may vary according to those known in the art, except for steps and / or operations that must occur in a particular order. Similar reference numerals refer to similar elements throughout. The names of the various elements used in the following description are chosen solely for ease of writing and may therefore differ from those used in actual products.

[0054] The advantages and features of the invention, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure of the invention comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art.

[0055] The shapes, sizes, proportions, angles, and quantities disclosed in the accompanying drawings for the purpose of describing embodiments of the invention are merely examples, and therefore the invention is not limited to the details illustrated. The same reference numerals refer to the same elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention. Where the terms "comprising," "having," and "including" are used in the description herein, additional parts may be added unless "only" is used.

[0056] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0057] When describing positional relationships, for example, when the positional relationship between two parts is described as “on top of,” “above,” “below,” and “after,” one or more additional parts may be placed between the two parts, unless more restrictive terms such as “exactly” or “directly” are used.

[0058] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “exactly” or “directly” are used.

[0059] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0060] In describing the elements of the present invention, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are used only to distinguish the corresponding element from other elements, and they do not limit the nature, order, or priority of the corresponding elements. It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, the element may be directly on or directly connected to the other element or layer, or there may be an intermediate element or layer. Furthermore, it should be understood that when an element is disposed above or below another element, it may indicate that the elements are disposed in direct contact with each other, but it may also indicate that the elements are disposed without direct contact with each other.

[0061] The term "at least one" should be understood to include any one and all combinations of one or more of the relevant listed elements. For example, "at least one of the first element, the second element, and the third element" means all combinations of two or more elements selected from the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0062] As used herein, the term "around" includes at least partially surrounding one or more of the relevant elements and completely enclosing one or more of the relevant elements. Similarly, the term "cover" as used herein includes at least partially covering one or more of the relevant elements and completely covering one or more of the relevant elements. For example, when an encapsulation layer surrounds a weir pattern, this can be interpreted as the encapsulation layer at least partially surrounding the weir pattern. However, in some embodiments, the encapsulation layer may completely enclose the weir pattern. The meaning of the term "around" as used herein may be further specified based on the relevant figures and embodiments. In this invention, the terms "around," "at least partially surrounding," "completely enclosing," etc., are used. Based on the definition of "around" as set forth above, when the term "around" is used only in embodiments, it can refer to either at least partially surrounding one or more of the relevant elements or completely enclosing one or more of the relevant elements. The same applies to the term "cover."

[0063] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The embodiments of the present invention can be implemented independently of each other or implemented jointly in an interdependent relationship.

[0064] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When adding reference numerals to elements in each drawing, similar reference numerals may refer to similar elements even if the same element is shown in other drawings. Furthermore, for ease of description, the scale of each element shown in the drawings differs from the actual scale, and therefore the invention is not limited to the scale shown in the drawings.

[0065] Figure 1 This is an illustration of a light-emitting display device according to an embodiment of the present invention. Figure 2 It is a diagram Figure 1 The equivalent circuit diagram of a sub-pixel is shown below.

[0066] Reference Figure 1 and Figure 2 According to an embodiment of the present invention, a light-emitting display device may include a light-emitting display panel 1 and a panel driving unit or circuit 3.

[0067] The light-emitting display panel 1 may include a substrate 10, a display area AA, a non-display area IA, multiple pixels P, a device isolation portion 15, and a weir pattern portion 17.

[0068] The substrate 10 can be a glass substrate, or a thin glass substrate or plastic substrate that can be bent or flexed.

[0069] The display area AA can be an area for displaying an image, and therefore can be referred to as a first area, a display portion, an active area, or an active portion. For example, the display area AA can be provided on the remaining portion of the substrate 10 except for the edge portion.

[0070] The non-display area IA can be an area where no image is displayed, and therefore can be referred to as a second area, a non-display portion, a non-active area, or a non-active portion. For example, the non-display area IA can be disposed at the edge of the substrate 10 to surround the display area AA.

[0071] Each of the multiple pixels P can be individually set in the corresponding pixel region of the multiple pixel regions defined in the display area AA. The multiple pixel regions can be defined by multiple pixel driving lines set in the display area AA.

[0072] Each of the plurality of pixels P can be disposed in a corresponding pixel region of the substrate 10 and can display an image corresponding to the data signal based on the scan signal and data signal provided by the adjacent pixel driving line.

[0073] Each of a plurality of pixels P may include a plurality of subpixels SP that are adjacent to each other. A subpixel SP can be defined as the smallest unit area that actually emits light. For example, at least three subpixels that are adjacent to each other can constitute a pixel P or a unit pixel P for displaying a color image.

[0074] According to one embodiment of the present invention, a pixel P may include first to third sub-pixels SP arranged adjacent to each other along a first direction X. In this case, the first sub-pixel may be a red sub-pixel, the second sub-pixel may be a green sub-pixel, and the third sub-pixel may be a blue sub-pixel. However, embodiments of the present invention are not limited thereto. According to one embodiment of the present invention, a light-emitting device layer disposed in each of the first to third sub-pixels SP may emit common light of the same color. For example, the common light may be white light, but embodiments of the present invention are not limited thereto, and may be blue light. Each of the first to third sub-pixels SP may further include a wavelength conversion member for converting white light (or blue light) into light of a different color. For example, the wavelength conversion member may include at least one of a color filter layer and a quantum dot layer.

[0075] According to another embodiment of the present invention, pixel P may include first to fourth sub-pixels SP arranged adjacent to each other along at least one of a first direction X and a second direction Y. In this case, the first sub-pixel may be a red sub-pixel, the second sub-pixel may be a white sub-pixel, the third sub-pixel may be a blue sub-pixel, and the fourth sub-pixel may be a green sub-pixel. However, embodiments of the present invention are not limited thereto. According to one embodiment of the present invention, the light-emitting device layer disposed in each of the first to fourth sub-pixels SP may emit common light of the same color. For example, the common light may be white light, but embodiments of the present invention are not limited thereto, and may be blue light. Each of the first, third, and fourth sub-pixels SP may further include a wavelength conversion member for converting white light (or blue light) into light of a different color. For example, the wavelength conversion member may include at least one of a color filter layer and a quantum dot layer. For example, the second sub-pixel may include a step height compensation layer instead of a wavelength conversion member.

[0076] Subpixels SP can be connected to adjacent pixel driving lines and can display images corresponding to data signals based on scan signals and data signals provided through the pixel driving lines.

[0077] According to one embodiment of the present invention, a sub-pixel SP can be connected to a gate line GL, a data line DL, a pixel driving power line PL, and a reference voltage line RL. For example, in response to a scan signal provided through the gate line GL, the sub-pixel SP can emit light using the data current flowing from the pixel driving power line PL to the common electrode CE based on the voltage difference between the data voltage provided through the data line DL and the reference voltage provided through the reference voltage line RL, thereby displaying an image.

[0078] Gate line GL may be disposed in the display area AA of substrate 10. For example, gate line GL may extend along a first direction X. According to an embodiment of the present invention, gate line GL may include a first gate line GLa and a second gate line GLb arranged parallel to each other along the first direction X.

[0079] The data line DL can be disposed in the display area AA of the substrate 10 to intersect the gate line GL. For example, the data line DL can extend along a second direction Y that intersects the first direction X.

[0080] The pixel driving power line PL can be arranged parallel to the data line DL in the display area AA of the substrate 10.

[0081] A reference voltage line RL can be provided parallel to the data line DL in the display area AA of the substrate 10. For example, one reference voltage line RL can be provided for each pixel P disposed in the first direction X. In this case, one reference voltage line RL can be connected to multiple sub-pixels SP constituting one pixel P. Optionally, the reference voltage line RL can be omitted based on the driving (or operation) scheme of pixel P.

[0082] A common electrode CE may be disposed in the display area AA of the substrate 10 and electrically connected to each of the sub-pixels SP of the plurality of pixels P. For example, the common electrode CE may be commonly connected to each of the plurality of sub-pixels SP.

[0083] The common electrode CE can be electrically connected to multiple pixel common voltage lines CVL disposed parallel to the data lines DL in the display area AA of the substrate 10. For example, each of the multiple pixel common voltage lines CVL can be electrically connected to the common electrode CE in the display area AA. For example, each of the multiple pixel common voltage lines CVL can be electrically connected to the common electrode CE between at least two or more adjacent pixels P disposed in the display area AA, or in the boundary region between at least two or more adjacent pixels P. For example, a pixel common voltage line CVL can be electrically connected to the common electrode CE through at least two or more linear (or electrode) contacts.

[0084] According to one embodiment of the present invention, a sub-pixel SP may include a light-emitting device ED and a pixel circuit PC.

[0085] The light-emitting device (ED) can be implemented between the pixel electrode (or anode electrode) PE, which is electrically connected to the pixel circuit PC, and the common electrode (or cathode electrode) CE. The ED can emit light using the data current supplied from the pixel circuit PC and can emit light with a brightness corresponding to the data current. For example, the pixel electrode PE disposed in each of the plurality of sub-pixels SP, the light-emitting device disposed in each of the plurality of sub-pixels SP and a portion of the non-display area IA, and the common electrode CE disposed above the light-emitting device can be referred to as a light-emitting device layer, but embodiments of the present invention are not limited thereto.

[0086] According to one embodiment, a light-emitting device (ED) may include an organic light-emitting layer. The ED may be sandwiched between a hole-functional layer and an electron-functional layer. The ED can emit light with a brightness corresponding to the data current by emitting light based on the data current supplied from the pixel circuit PC.

[0087] The pixel circuit PC can respond to the scan signal provided through the adjacent gate line GL and provide the light-emitting device ED with a data current corresponding to the difference voltage between the data voltage provided through the adjacent data line DL and the reference voltage provided through the adjacent reference voltage line RL.

[0088] A light-emitting device ED according to one embodiment may include a first switching thin-film transistor Tsw1, a second switching thin-film transistor Tsw2, a driving thin-film transistor Tdr, and a storage capacitor Cst. In the following description, the thin-film transistor may be referred to as a TFT.

[0089] At least one of the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr can be an amorphous silicon (a-Si) TFT, a polycrystalline silicon (poly-Si) TFT, an oxide TFT, or an organic TFT. For example, in a pixel circuit PC, some of the TFTs in the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr can be TFTs comprising a semiconductor layer (or active layer) of low-temperature polycrystalline silicon (LTPS) with excellent response characteristics, and the other TFTs in the first switching TFT Tsw1, the second switching TFT Tsw2, and the driving TFT Tdr can be TFTs comprising a semiconductor layer (or active layer) of oxide with excellent off-current characteristics.

[0090] The first switching TFT Tsw1 may include: a gate electrode connected to a first gate line GLa in the gate line GL; a first electrode (source / drain) connected to an adjacent data line DL; and a second electrode (drain / source) connected to the gate node n1 of the driving TFT Tdr. The first switching TFT Tsw1 may transmit a data voltage provided through the adjacent data line DL to the gate node n1 of the driving TFT Tdr based on a first scan signal provided to the first gate line GLa.

[0091] The second switch TFT Tsw2 may include: a gate electrode connected to a second gate line GLb in the gate line GL; a first electrode (source / drain) connected to the source node n2 of the driving TFT Tdr; and a second electrode (drain / source) connected to an adjacent reference voltage line RL. The second switch TFT Tsw2 may transmit a reference voltage provided through the adjacent reference voltage line RL to the source node n2 of the driving TFT Tdr based on a second scan signal provided to the second gate line GLb.

[0092] A storage capacitor Cst may be formed between the gate node n1 and the source node n2 of the driving TFT Tdr. According to one embodiment, the storage capacitor Cst may include a first capacitor electrode connected to the gate node n1 of the driving TFT Tdr, a second capacitor electrode connected to the source node n2 of the driving TFT Tdr, and a dielectric layer formed in the overlapping region between the first and second capacitor electrodes. The storage capacitor Cst may be charged with the voltage difference between the gate node n1 and the source node n2 of the driving TFT Tdr, and the driving TFT Tdr may be turned on or off based on the charged voltage.

[0093] The driving TFT Tdr may include: a gate electrode (or gate node n1) connected to the second electrode (drain / source) of the first switching TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst; a first electrode (source / drain) (or source node n2) connected to the first electrode (source / drain) of the second switching TFT Tsw2, the second capacitor electrode of the storage capacitor Cst, and the pixel electrode PE of the light-emitting device ED; and a second electrode (drain / source) (or drain node) connected to the pixel driving power line PL. The driving TFT Tdr can be turned on based on the voltage of the storage capacitor Cst and the amount of current flowing to the light-emitting device ED through the pixel driving power line PL, which is supplied with the pixel driving voltage EVdd, can be controlled.

[0094] The device isolation portion 15 can be implemented at the edge of the substrate 10. For example, the device isolation portion 15 can be provided at the edge of the substrate 10 to surround the outermost pixel P provided in the display area AA. For example, the device isolation portion 15 can be provided along the non-display area IA of the substrate 10, thereby having a closed loop shape (or closed loop shape) around the display area AA. The device isolation portion 15 can isolate (or separate) the light-emitting device ED located outside the display area AA or in the non-display area IA to block lateral moisture transport paths, thereby preventing, reducing, or minimizing the reliability reduction of the light-emitting device ED caused by lateral moisture or humidity penetration. The device isolation portion 15 can additionally isolate (or separate) the common electrode CE, in which case the end of the common electrode CE isolated by the device isolation portion 15 can be implemented to cover the end of the light-emitting device ED isolated by the device isolation portion 15. For example, the device isolation portion 15 can be referred to as a moisture penetration blocking portion, a moisture penetration prevention portion, a groove pattern portion, a cliff pattern portion, an eaves structure, etc. For example, the device isolation portion 15 can be defined as the light-emitting device layer 13 (see Figure 3 ) isolation areas, isolation lines, disconnected areas or disconnected lines.

[0095] According to an embodiment of the present invention, the device isolation portion 15 may include at least two or more device isolation patterns 15a to 15d. For example, the device isolation portion 15 may include first to fourth device isolation patterns 15a to 15d.

[0096] Each of at least two or more device isolation patterns 15a to 15d may have a closed loop shape surrounding the display area AA. For example, a first device isolation pattern 15a may be disposed adjacent to the display area AA, a second device isolation pattern 15b may be disposed around the first device isolation pattern 15a, a third device isolation pattern 15c may be disposed around the second device isolation pattern 15b, and a fourth device isolation pattern 15d may be disposed around the third device isolation pattern 15c.

[0097] Each of at least two or more device isolation patterns 15a to 15d may include an eaves structure for isolating (or separating) the light-emitting device ED. For example, each of at least two or more device isolation patterns 15a to 15d may include an eaves structure implemented by an insulating layer and a metal pattern layer (or metal layer) on the insulating layer. For example, the eaves structure may be referred to by terms such as undercut structure or cliff structure.

[0098] According to one embodiment of the present invention, light-emitting devices (EDs) formed on at least two or more device isolation patterns 15a to 15d can be automatically isolated (or separated) by the roof structure of the device isolation patterns 15a to 15d during the deposition process, without the need for a separate isolation (or separation) process. Furthermore, the common electrode (CE) deposited on the light-emitting devices (EDs) can be automatically isolated (or separated) by the roof structure of the device isolation patterns 15a to 15d during the deposition process.

[0099] The dam pattern portion 17 can be implemented on the edge portion of the substrate 10. For example, the dam pattern portion 17 can be disposed on the edge portion of the substrate 10 to surround the outermost pixel P disposed in the display area AA. For example, the dam pattern portion 17 can be disposed along the non-display area IA of the substrate 10, thereby having a closed loop shape surrounding the display area AA. The dam pattern portion 17 can prevent the diffusion or overflow of the encapsulation layer disposed on the substrate 10 to cover the display area AA. For example, the encapsulation layer can be disposed on the light-emitting device layer and may include organic material disposed in the inner region surrounded by the dam pattern portion 17. Therefore, the dam pattern portion 17 can prevent the organic material of the encapsulation layer from diffusing or overflowing toward the edge portion of the substrate 10.

[0100] The weir pattern portion 17 may be disposed within the device isolation portion 15. For example, the weir pattern portion 17 may be implemented on the substrate 10 to surround and be surrounded by at least one or more of the at least two or more device isolation patterns 15a to 15d. For example, the weir pattern portion 17 may be disposed between two adjacent device isolation patterns among the two or more device isolation patterns 15a to 15d. For example, based on the weir pattern portion 17, the two or more device isolation patterns 15a to 15d may be divided into a first device isolation portion (or inner device isolation portion) and a second device isolation portion (or outer device isolation portion). The first device isolation portion may be disposed between the display area AA and the weir pattern portion 17. The second device isolation portion may be disposed between the weir pattern portion 17 and the end (or outer surface) of the substrate 10.

[0101] According to one embodiment of the present invention, the weir pattern portion 17 can be implemented as a closed-loop shape to surround the first device isolation pattern 15a, and can be implemented to be surrounded by the second to fourth device isolation patterns 15b to 15d. In this case, the first device isolation pattern 15a can be a first device isolation portion, and the second to fourth device isolation patterns 15b to 15d can be second device isolation portions.

[0102] The weir pattern portion 17 may include a structure (or structural element) for preventing the loss (or removal) of the metal pattern layer of the eaves structure during the formation (or manufacture) of at least two or more device isolation patterns 15a to 15d of the device isolation portion 15. According to one embodiment of the invention, the weir pattern portion 17 may include discontinuous weir patterns and continuous weir patterns.

[0103] Discontinuous weir patterns can be implemented to prevent the loss (or removal) of the metal pattern layer of the roof structure. For example, discontinuous weir patterns can be referred to by terms such as intermittent weir patterns or dotted-line weir patterns.

[0104] According to one embodiment of the invention, a discontinuous weir pattern may include multiple line dam patterns or multiple segments of a weir layer separated from each other, surrounding a display area AA. For example, the multiple line dam patterns may be separated from each other, thus having a predetermined or selected length and a predetermined or selected gap space therebetween. According to another embodiment of the invention, a discontinuous weir pattern may include multiple line dam patterns surrounding the display area AA and weir breaks disposed between the multiple line dam patterns.

[0105] According to one embodiment of the present invention, the device isolation portion 15 can be formed (or manufactured) after a process of manufacturing a discontinuous weir pattern. For example, when forming (or manufacturing) at least two or more device isolation patterns 15a to 15d of the device isolation portion 15, the discontinuous weir pattern provides a path for the patterning material (or etchant) required for patterning (or etching) the insulating layer to move between the inside and outside of the weir pattern portion 17, thereby preventing or minimizing over-etching of the insulating layer beneath the metal pattern layer due to the patterning material, thereby preventing, reducing or minimizing the loss (or removal) of the metal pattern layer when forming the eaves structure of at least two or more device isolation patterns 15a to 15d. Therefore, at least two or more device isolation patterns 15a to 15d of the device isolation portion 15 can include a normal eaves structure without loss of the metal pattern layer due to over-etching of the insulating layer, thus enabling normal performance of the function of the isolated optical device ED.

[0106] According to the comparative example, when the weir pattern portion 17 does not include discontinuous weir patterns, the patterning material (or etchant) is confined to both the interior and exterior of the weir pattern portion 17. For this reason, the metal pattern layer of the roof structure is lost (or removed) due to over-etching of the insulating layer, thus preventing the formation of device isolation patterns 15a to 15d. Without the formation of device isolation patterns 15a to 15d, the reliability of the light-emitting device (ED) is reduced due to lateral moisture or humidity penetration because the ED is not isolated. For example, the patterning material (or etchant) is confined to the interior of the weir pattern portion 17, and for this reason, the metal pattern layer of the first device isolation pattern 15a is lost (or removed) due to over-etching of the insulating layer, thus preventing the formation of the first device isolation pattern 15a.

[0107] Continuous weir patterns can be applied over discontinuous weir patterns. For example, continuous weir patterns can fill the gaps (or gaps) between linear weir patterns of discontinuous weir patterns and can be applied over linear weir patterns. Continuous weir patterns can prevent the diffusion or overflow of the encapsulation layer.

[0108] According to one embodiment of the present invention, a continuous weir pattern may have a different cross-sectional structure than a discontinuous weir pattern. For example, a continuous weir pattern may include a plurality of protruding patterns filling the break portions (or gap spaces) between linear weir patterns of a discontinuous weir pattern, and a closed-loop line pattern disposed on the linear weir pattern and the plurality of protruding patterns. For example, the plurality of protruding patterns may each protrude from the closed-loop line pattern toward the break portion.

[0109] According to an embodiment of the present invention, the light-emitting display panel 1 may further include a plurality of pad portions PP.

[0110] Each of the plurality of pad portions PP may be disposed at an edge portion of the substrate 10 along the first direction X. For example, this edge portion of the substrate 10 may be referred to as a first edge portion, an upper edge portion, a first non-display area, an upper non-display area, a first peripheral area, a first peripheral portion, etc.

[0111] Each of the plurality of pad portions PP according to an embodiment of the present invention may include a data pad electrically connected to a data line DL via a link line, a reference voltage pad electrically connected to a reference voltage line via a link line, and a pixel common voltage pad electrically connected to a pixel common voltage line via a link line.

[0112] Each of the first and last pad portions of the plurality of pad portions PP may include a plurality of gate pads.

[0113] According to one embodiment, the light-emitting display panel 1 may further include a gate driving circuit 50.

[0114] The gate driving circuit 50 can provide gate signals to the gate lines based on gate control signals (or scan control signals) provided from the driving circuit unit 3 via multiple gate pads connected to the interconnects and pad portions PP. According to one embodiment, the gate driving circuit 50 can be directly implemented in the non-display area IA of the substrate 10 along with the TFT manufacturing process of the pixel circuit PC that implements the sub-pixel SP. For example, the gate driving circuit 50 can be disposed in at least one of two non-display areas IA of the substrate 10 that face each other. According to another embodiment, the gate driving circuit 50 can be implemented as an IC, in which case the gate driving circuit 50 can be mounted on the substrate 10 and connected to the gate lines, or it can be mounted on a flexible circuit film and connected to the gate lines via the gate pads of the substrate 10.

[0115] The driving circuit unit 3 can be connected to the pad portion PP disposed on an edge portion of the substrate 10, and can enable each sub-pixel SP to display an image corresponding to the video data provided from the display driving system.

[0116] According to one embodiment, the drive circuit unit 3 may include a plurality of flexible circuit films 31, a plurality of data drive integrated circuits (ICs) 33, a printed circuit board (PCB) 35, a timing controller 37, and a power supply circuit unit 39.

[0117] Each of the plurality of flexible circuit films 31 can be attached to the PCB 35 and the pad portion PP provided on the substrate 10. For example, one edge portion (or output bonding portion) of each of the plurality of flexible circuit films 31 can be attached to the pad portion PP provided on the substrate 10 by using a film attachment process using an anisotropic conductive film. Another edge portion (or input bonding portion) of each of the plurality of flexible circuit films 31 can be attached to the PCB 35 by using a film attachment process using anisotropic conductive film.

[0118] Each of the plurality of data driver ICs 33 can be individually mounted on a corresponding flexible circuit film 31 among the plurality of flexible circuit films 31. Each of the plurality of data driver ICs 33 can receive pixel data and data control signals provided from a timing controller 37, convert the pixel data into a pixel-based analog data voltage according to the data control signals, and provide the analog data voltage to a corresponding data line DL. For example, each of the plurality of data driver ICs 33 can generate a plurality of gray level voltages using a plurality of reference gamma voltages provided from a PCB 35, and can select the gray level voltage corresponding to the pixel data from the plurality of gray level voltages as the pixel-based data voltage, and output the selected data voltage.

[0119] Furthermore, each of the plurality of data driver ICs 33 can utilize multiple reference gamma voltages to generate the pixel common voltage (or cathode voltage) and pixel driving voltage (or anode voltage) required for driving (or emitting light) the sub-pixel SP. As an example, each of the plurality of data driver ICs 33 can select a predetermined or selected reference gamma voltage or a predetermined or selected gray level voltage from multiple reference gamma voltages or multiple gray level voltages as the pixel driving voltage and the pixel common voltage, and output the pixel driving voltage and the pixel common voltage.

[0120] Furthermore, each of the multiple data driver ICs 33 can additionally generate and output a reference voltage based on the driving (or operation) method of each pixel P. For example, each of the multiple data driver ICs 33 can select a predetermined or selected reference gamma voltage or a predetermined or selected gray level voltage from multiple reference gamma voltages or multiple gray level voltages as a reference voltage and output the reference voltage. For example, the pixel driving voltage, the pixel common voltage, and the reference voltage can have different voltage levels.

[0121] Each of the multiple data driver ICs 33 can sequentially sense the feature value of the driving TFT included in each sub-pixel SP through multiple reference voltage lines RL disposed on the substrate 10, generate sensing raw data corresponding to the sensed value, and provide the sensing raw data to the timing controller 37.

[0122] PCB 35 can be connected to another edge portion of each of the multiple flexible circuit films 31. PCB 35 can transmit signals and voltages between the components of the drive circuit unit 3.

[0123] The timing controller 37 can be mounted on the PCB 35 and can receive image data and timing synchronization signals from the display driver system via a user connector located on the PCB 35. Alternatively, the timing controller 37 may not be mounted on the PCB 35, but may be implemented in the display driver system or mounted on a separate control board connected between the PCB 35 and the display driver system.

[0124] The timing controller 37 can arrange video data based on timing synchronization signals to match the pixel arrangement structure set in the display area AA, and can provide the generated pixel data to each of the multiple data driver ICs 33.

[0125] According to one embodiment, when pixel P includes a white sub-pixel SP, timing controller 37 can extract white pixel data based on digital video data (i.e., red input data, green input data, and blue input data to be provided to the corresponding pixel P respectively), reflect the offset data based on the extracted white pixel data in each of the red input data, green input data, and blue input data to calculate red pixel data, green pixel data, and blue pixel data, and arrange the calculated red pixel data, green pixel data, blue pixel data, and white pixel data according to the pixel arrangement structure, and provide the arranged pixel data to each data driver IC 33. For example, timing controller 37 can convert red input data, green input data, and blue input data into four-color (e.g., red, green, blue, and white) data based on the data conversion method disclosed in Korean Patent Application Publication No. 10-2013-0060476 or No. 10-2013-0030598, all of which are incorporated herein by reference.

[0126] The timing controller 37 can generate each of a data control signal and a gate control signal based on the timing synchronization signal, control the driving timing of each data driver IC 33 based on the data control signal, and control the driving timing of the gate driver circuit 50 based on the gate control signal. For example, the timing synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a master clock (or dot clock).

[0127] According to one embodiment, the data control signal may include a source start pulse, a source shift clock, and a source output signal. According to one embodiment, the gate control signal may include a start signal (or a gate start pulse), multiple shift clocks, etc.

[0128] The timing controller 37 can drive each of the data driver IC 33 and the gate driver circuit 50 based on an external sensing mode during a predetermined or selected external sensing period, generate compensation data for compensating for characteristic variations of the driving TFT of each sub-pixel SP based on the raw sensing data provided from the data driver IC 33, and modulate pixel data based on the generated compensation data. For example, the timing controller 37 can drive each of the data driver IC 33 and the gate driver circuit 50 based on an external sensing mode during each external sensing period corresponding to the blanking period (or vertical blanking period) of the vertical synchronization signal. For example, the external sensing mode can be executed during the power-on process of the display device, the power-off process of the display device, the process of powering off the display device after a long period of driving, or the blanking period of a frame set in real time or periodically.

[0129] According to one embodiment, the timing controller 37 can store the raw sensing data of each sub-pixel provided by the data driver IC 33 in a storage circuit based on an external sensing mode. Furthermore, in display mode, the timing controller 37 can correct the pixel data to be provided to each sub-pixel based on the raw sensing data stored in the storage circuit and can provide the corrected pixel data to the data driver IC 33. Here, the raw sensing data of each sub-pixel may include sequential variation information relating to each of the driving TFTs and light-emitting devices disposed in the respective sub-pixel. Therefore, in external sensing mode, the timing controller 37 can sense the characteristic values ​​(e.g., threshold voltage or mobility) of the driving TFTs disposed in each sub-pixel SP and, based on this, correct the pixel data to be provided to each sub-pixel P, thereby minimizing or preventing image quality degradation caused by deviations in the characteristic values ​​of the driving TFTs of multiple sub-pixels SP. The external sensing mode of the light-emitting display device is a technique known to those skilled in the art, and therefore its detailed description is omitted or can be simplified. For example, the light-emitting display device according to the present invention can sense the characteristic values ​​of the driving TFTs disposed in each sub-pixel SP based on the sensing modes disclosed in Korean Patent Application Publications No. 10-2016-0093179, No. 10-2017-0054654 or No. 10-2018-0002099, all of which are incorporated herein by reference.

[0130] The power supply circuit unit 39 can be mounted on the PCB 35 and can use externally supplied input power to generate various source voltages required for displaying an image on pixel P, and provide the generated source voltages to the corresponding circuits. For example, the power supply circuit unit 39 can generate and output the required logic source voltages for driving each of the timing controller 37 and the data driver IC 33, multiple reference gamma voltages provided to the data driver IC 33, and at least one gate drive voltage and at least one gate common voltage required for driving the gate drive circuit 50. The gate drive voltage and the gate common voltage can have different voltage levels.

[0131] Figure 3 It is along Figure 1 The cross-sectional view shown is taken by line I-I'. Figure 4 It is along Figure 1 The cross-sectional view taken by line II-II' shown in the figure. Figure 5 yes Figure 3 An enlarged view of region "B1" shown. Figure 6 yes Figure 3 An enlarged view of region "B2" shown.

[0132] Reference Figures 1 to 6 According to an embodiment of the present invention, a light-emitting display device may include a circuit layer 11, a planarization layer 12, a light-emitting device layer 13, a dam 14, a device isolation portion 15, a weir pattern portion 17, and an encapsulation layer 19 above a substrate 10.

[0133] The circuit layer 11 may be disposed on the substrate 10. The circuit layer 11 may be referred to as a pixel array layer, a pixel array portion, a TFT array layer, or a TFT array portion.

[0134] Reference Figures 1 to 3 and Figure 5 According to one embodiment, the circuit layer 11 may include a buffer layer 11a, a circuit array layer 11b, and a plurality of pad portions PP.

[0135] The buffer layer 11a prevents materials such as hydrogen from diffused from the substrate 10 into the circuit array layer 11b during the high-temperature processes of TFT manufacturing. Furthermore, the buffer layer 11a prevents external moisture or humidity from penetrating into the light-emitting device layer 13. According to one embodiment, the buffer layer 11a may comprise silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiON), or multiple layers thereof, but embodiments of the present invention are not limited thereto. For example, the buffer layer 11a may comprise a first buffer layer BL1 disposed on the substrate 10 and comprising SiNx, and a second buffer layer BL2 disposed on the first buffer layer BL1 and comprising SiOx.

[0136] The circuit array layer 11b may include a pixel circuit PC, which includes a driving TFT Tdr disposed in each of a plurality of pixel regions PA above the buffer layer 11a.

[0137] The driving TFT Tdr disposed in each pixel region PA may include an active layer ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer 11c, a first electrode (source / drain) SD1, a second electrode (drain / source) SD2, and a passivation layer 11d.

[0138] An active layer ACT can be disposed on the buffer layer 11a in each pixel region PA. The active layer ACT may include a channel region overlapping with the gate electrode GE, and a first electrode (source / drain) region and a second electrode (drain / source) region that are parallel to each other and sandwiched between the channel regions. The active layer ACT may be conductive in the conductivity process, and thus can be used as a bridge line in a jumping structure that directly connects lines in the display area AA or electrically connects lines disposed on different layers.

[0139] The gate insulating layer GI can be disposed in the channel region of the active layer ACT. The gate insulating layer GI can insulate the active layer ACT from the gate electrode GE.

[0140] The gate electrode GE may be disposed above the gate insulating layer GI. The gate electrode GE and the channel region of the active layer ACT may overlap therebetween, provided that the gate insulating layer GI is present between them. According to one embodiment, the gate electrode GE may have a single-layer structure or a multi-layer structure including at least one of molybdenum (Mo), titanium (Ti), Mo-Ti alloy (MoTi), and copper (Cu).

[0141] An interlayer insulating layer 11c may be disposed on the substrate 10 to cover the gate electrode GE and the active layer ACT. The interlayer insulating layer 11c can electrically insulate (or isolate) the gate electrode GE from the source / drain electrodes SD1 and SD2.

[0142] According to one embodiment, the interlayer insulating layer 11c may be provided only on the remaining portion of the substrate 10 except for the edge portion, but the embodiments of the present invention are limited thereto.

[0143] The first electrode (source / drain) SD1 can be disposed on the interlayer insulating layer 11c overlapping the first electrode (source / drain) region of the active layer ACT, and can be electrically connected to the first electrode (source / drain) region of the active layer ACT through a first electrode (source / drain) contact hole disposed in the interlayer insulating layer 11c. For example, the first electrode (source / drain) SD1 can be the source electrode for driving the TFT Tdr, and the first electrode (source / drain) region of the active layer ACT can be a source region.

[0144] The second electrode (drain / source) SD2 can be disposed on the interlayer insulating layer 11c overlapping the second electrode (drain / source) region of the active layer ACT, and can be electrically connected to the second electrode (drain / source) region of the active layer ACT through a second electrode (drain / source) contact hole disposed in the interlayer insulating layer 11c. For example, the second electrode (drain / source) SD2 can be the drain electrode of the TFT Tdr, and the second electrode (drain / source) region of the active layer ACT can be the drain region.

[0145] The passivation layer 11d may be disposed above the substrate 10 to cover the pixel circuit PC including the driving TFT Tdr. The passivation layer 11d may support the weir pattern portion 17.

[0146] According to one embodiment, when no interlayer insulating layer 11c is provided at the edge portion of the substrate 10, the passivation layer 11d provided at the edge portion of the substrate 10 can directly contact the buffer layer 11a. The passivation layer 11d according to one embodiment may include silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride oxide (SiON), or multiple layers thereof, but embodiments of the present invention are not limited thereto. For example, the passivation layer 11d may be referred to as a protective layer, circuit protective layer, insulating layer, circuit insulating layer, etc.

[0147] Each of the first switch TFT Tsw1 and the second switch TFT Tsw2 constituting the pixel circuit PC can be formed together with the driving TFT Tdr, and therefore their detailed description can be omitted or simplified.

[0148] According to one embodiment, the circuit layer 11 may further include a lower metal layer BML disposed between the substrate 10 and the buffer layer 11a.

[0149] The lower metal layer BML may further include a light-shielding pattern LSP, which is disposed below the active layer ACT of each of the TFTs Tdr, Tsw1 and Tsw2 constituting the pixel circuit PC.

[0150] The light-shielding pattern LSP can be disposed in an island shape between the substrate 10 and the active layer ACT. The light-shielding pattern LSP blocks light incident on the active layer ACT through the substrate 10, thereby preventing or minimizing threshold voltage variations of each TFT caused by external light. Optionally, the light-shielding pattern LSP can be electrically connected to the first electrode (source / drain) SD1 of the corresponding TFT, and thus can be used as the lower gate electrode of the corresponding TFT. In this case, characteristic variations of each TFT caused by light and threshold voltage variations of each TFT caused by bias voltage can be reduced, minimized, or prevented.

[0151] The lower metal layer BML can be used as a line arranged parallel to each other among the gate line GL, data line DL, pixel drive power line PL, pixel common voltage line CVL, and reference voltage line RL. Furthermore, the lower metal layer BML can be used as multiple interconnects LL electrically connected to multiple pad electrodes PPe disposed in the pad portion PP. According to one embodiment, the lower metal layer BML can be deposited above the substrate 10 and then patterned by a patterning process as the data line DL, pixel drive power line PL, pixel common voltage line CVL, reference voltage line RL, light-shielding pattern LSP, and interconnects LL. According to another embodiment, the lower metal layer BML can be deposited above the substrate 10 and then patterned by a patterning process as the gate line GL, light-shielding pattern LSP, and interconnects LL.

[0152] Each of the plurality of pad portions PP may be disposed on an edge portion of the substrate 10 and may be electrically connected to the interconnect LL. Each of the plurality of pad portions PP may include a plurality of pad electrodes PPe.

[0153] Each of the plurality of pad electrodes PPe can be electrically connected to the interconnect LL through a pad contact hole PCH passing through the passivation layer 11d, the interlayer insulating layer 11c, and the buffer layer 11a, but the embodiments of the present invention are not limited thereto. As one embodiment, when the interconnect LL is disposed above the buffer layer 11a, the pad electrode PPe can be electrically connected to the interconnect LL through a pad contact hole PCH passing through the passivation layer 11d and the interlayer insulating layer 11c. As another embodiment, when the interconnect LL is disposed above the interlayer insulating layer 11c, the pad electrode PPe can be electrically connected to the interconnect LL through a pad contact hole PCH passing through the passivation layer 11d.

[0154] The planarization layer 12 may be disposed above the substrate 10 and may provide a flat surface above the circuit layer 11. The planarization layer 12 may cover the circuit layer 11 including the driving TFTs Tdr disposed in each of a plurality of pixel regions PA. According to one embodiment, the planarization layer 12 may include acrylic resin, epoxy resin, phenolic resin, polyamide-based resin or polyimide-based resin, etc., but embodiments of the present invention are not limited thereto.

[0155] According to one embodiment, the planarization layer 12 can be formed to cover the remaining circuit layers 11 except for the pad portion PP and the passivation layer 11d of the circuit layer 11 provided at the edge portion of the substrate 10. Therefore, the passivation layer 11d of the circuit layer 11 provided at the edge portion of the substrate 10 can be exposed and not covered by the planarization layer 12. For example, the planarization layer 12 can be provided between the passivation layer 11d and the light-emitting device layer 13 or below the light-emitting device layer 13.

[0156] The light-emitting device layer 13 may be disposed above the planarization layer 12. According to one embodiment, the light-emitting device layer 13 may include a pixel electrode PE, a light-emitting device ED, and a common electrode CE.

[0157] The pixel electrode PE can be referred to as the anode electrode, reflective electrode, lower electrode, or first electrode of the light-emitting device ED.

[0158] A pixel electrode PE may be disposed in a first region of the substrate 10. The pixel electrode PE may be disposed above a planarization layer 12 overlapping the light-emitting region EA of each of a plurality of pixel regions PA defined in the first region of the substrate 10. The pixel electrode PE may be patterned and disposed in an island shape in each pixel region PA and may be electrically connected to the first electrode (source / drain) SD1 of the driving TFT Tdr of the corresponding pixel circuit PC. For example, one side of the pixel electrode PE may extend onto the first electrode (source / drain) SD1 of the driving TFT Tdr and may be electrically connected to the first electrode (source / drain) SD1 of the driving TFT Tdr through an electrode contact hole ECH disposed in the planarization layer 12.

[0159] The pixel electrode PE can be a metallic material with a low work function and excellent reflectivity.

[0160] According to one embodiment of the present invention, the pixel electrode PE may have a bilayer structure including a first pixel electrode layer (or a first metal layer) PEL1 and a second pixel electrode layer (or a second metal layer) PEL2. The first pixel electrode layer PEL1 and the second pixel electrode layer PEL2 may be deposited sequentially on top of the planarization layer 12 and then simultaneously patterned, but the embodiments of the present invention are not limited thereto.

[0161] The first pixel electrode layer PEL1 may be disposed above the planarization layer 12. The second pixel electrode layer PEL2 may be disposed (or stacked) above the first pixel electrode layer PEL1. According to one embodiment, the pixel electrode PE may include a stacked structure of indium tin oxide (ITO) (or indium zinc oxide (IZO)) and Mo-Ti alloy (MoTi). For example, the pixel electrode PE may be formed as a bilayer structure of ITO / MoTi or IZO / MoTi.

[0162] According to one embodiment, the first pixel electrode layer PEL1 can be used as an adhesive layer corresponding to the planarization layer 12 and can also be used as an auxiliary electrode for a light-emitting device ED. The first pixel electrode layer PEL1 may include indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of the present invention are not limited thereto.

[0163] According to one embodiment, a second pixel electrode layer PEL2 may be disposed (or stacked) above a first pixel electrode layer PEL1. For example, the second pixel electrode layer PEL2 may serve as a reflector and may perform the function of reducing the resistance of the pixel electrode PE. The second pixel electrode layer PEL2 may include one or more materials selected from aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), and Mo-Ti alloy (MoTi), but embodiments of the present invention are not limited thereto.

[0164] According to another embodiment of the present invention, the pixel electrode PE may have a three-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 above the first pixel electrode layer PEL1, and a third pixel electrode layer (or a third metal layer) above the second pixel electrode layer PEL2. The first pixel electrode layer PEL1, the second pixel electrode layer PEL2, and the third pixel electrode layer may be deposited sequentially on the planarization layer 12 and then simultaneously patterned, but the embodiments of the present invention are not limited thereto.

[0165] The third pixel electrode layer can be used as an electrode for a light-emitting device (ED) and may include ITO or IZO. For example, the pixel electrode PE can be formed as a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

[0166] According to another embodiment, the pixel electrode PE may have a four-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 above the first pixel electrode layer PEL1, a third pixel electrode layer (or a third metal layer) above the second pixel electrode layer PEL2, and a fourth pixel electrode layer (or a fourth metal layer) above the third pixel electrode layer. The first to fourth pixel electrode layers may be deposited sequentially on the planarization layer 12 and then simultaneously patterned, but the embodiments of the present invention are not limited thereto.

[0167] In a four-layer pixel electrode PE, the first pixel electrode layer can serve as an adhesive layer corresponding to the planarization layer 12 and as an auxiliary electrode for the light-emitting device ED. The first pixel electrode layer may include one or more materials selected from ITO, Mo, and MoTi. The second pixel electrode layer can function to reduce the resistance of the pixel electrode PE and may include Cu. The third pixel electrode layer can serve as a reflector and may include one or more materials selected from Al, Ag, Mo, Ti, and MoTi. The fourth pixel electrode layer can serve as an electrode for the light-emitting device ED and may include ITO or IZO. For example, according to another embodiment, the pixel electrode PE can be formed as a four-layer structure of ITO / Cu / MoTi / ITO.

[0168] The pixel electrode PE can be used as a metal layer to realize multiple pad electrodes disposed in each of the multiple pad portions PP. For example, the multiple pad electrodes can be formed together with the pixel electrode PE from the same material as the pixel electrode PE.

[0169] The light-emitting device (ED) may be disposed above a first region of the substrate 10 and in at least a portion of a second region of the substrate 10. The ED may be formed above the pixel electrode PE and may directly contact the pixel electrode PE. The pixel electrode PE may be disposed below (or beneath) the ED. For example, the pixel electrode PE may be disposed between the planarization layer 12 and the ED.

[0170] According to one embodiment, the light-emitting device (ED) may be a common layer formed jointly in each of a plurality of sub-pixels (SPs) without being distinguished by sub-pixel SPs. The ED may respond to current flowing between the pixel electrode (PE) and the common electrode (CE) to emit white light (or blue light). According to one embodiment, the ED may include an organic light-emitting layer, or may include a stacked or combined structure of an organic light-emitting layer and a quantum dot light-emitting layer.

[0171] An organic light-emitting device according to one embodiment may include two or more organic light-emitting portions for emitting white light. For example, the organic light-emitting device may include a first organic light-emitting portion and a second organic light-emitting portion for emitting white light based on a combination of a first light and a second light. For example, the first organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer. The second organic light-emitting portion may include at least one or more of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer for emitting a second light that combines with the first light from the first organic light-emitting portion to produce white light.

[0172] The organic light-emitting layer according to an embodiment of the present invention may further include at least one or more functional layers for improving luminous efficiency and / or lifetime. For example, the functional layers may be disposed above and / or below the light-emitting layer, respectively.

[0173] The common electrode CE may be referred to as the cathode electrode, transparent electrode, upper electrode, or second electrode. The common electrode CE may be formed above the light-emitting device ED and may be in direct contact with the light-emitting device ED or may be electrically in direct contact with the light-emitting device ED. The common electrode CE may include a transparent conductive material that transmits light emitted from the light-emitting device ED.

[0174] According to one embodiment of the present invention, the common electrode CE can be formed as a single-layer or multi-layer structure comprising at least one material selected from graphene and a transparent conductive material with relatively high work function. For example, the common electrode CE may comprise a metal oxide such as ITO or IZO, or may comprise a combination of oxide and metal, such as ZnO:Al or SnO2:Sb.

[0175] In addition, the light-emitting device layer 13 may further include a capping layer disposed above the common electrode CE. The capping layer can improve the light emission efficiency by adjusting the refractive index of the light emitted from the light-emitting device layer 13.

[0176] The dam 14 may be disposed above the planarization layer 12 to define a pixel region PA above the substrate 10. The dam 14 may be disposed above the planarization layer 12 to cover the edge portion of the pixel electrode PE. The dam 14 may define a light-emitting region EA (or opening portion) of each of the plurality of sub-pixels SP and may electrically isolate the pixel electrodes PE disposed in adjacent sub-pixels SP. The dam 14 may be formed to cover the electrode contact hole ECH disposed in each of the plurality of pixel regions PA. The dam 14 may be covered by the light-emitting layer of the light-emitting device layer 13. For example, the light-emitting layer may be disposed above the dam 14 and above the pixel electrode PE of each of the plurality of sub-pixels SP. The meaning of "defined" should be understood to include bordering. For example, the dam 14 may define the boundary between the pixel region PA, the light-emitting region EA, or the pixel region PA and the light-emitting region EA.

[0177] According to one embodiment, the dam 14 may be formed of a transparent material, such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. For example, according to one embodiment, the dam 14 may be a transparent dam.

[0178] According to another embodiment, the dam portion 14 can be an opaque material comprising a light-absorbing material or a black pigment such as carbon black, for example, polyamide-based resin, acrylic-based resin, benzocyclobutene (BCB), etc. For example, according to another embodiment, the dam portion 14 can be a black dam portion.

[0179] Refer again Figure 3 and Figure 6 The device isolation portion 15 may be disposed in a second region surrounding the first region of the substrate 10. For example, the second region of the substrate 10 may be an edge portion of the substrate 10 or an edge portion of the outermost pixel. The first region of the substrate 10 may be any portion other than the second region.

[0180] The device isolation portion 15 can be implemented to isolate the light-emitting device ED disposed in the second region. The device isolation portion 15 can be implemented to prevent moisture or humidity from penetrating the substrate 10 in the lateral direction, so as to prevent the light-emitting device ED from being degraded due to the lateral penetration of moisture or humidity. The device isolation portion 15 can isolate (or separate) the light-emitting device ED of the light-emitting device layer 13 at least once at a position near the weir pattern portion 17, thereby preventing the lateral penetration of moisture or humidity. For example, the device isolation portion 15 can be defined as an isolation region, isolation line, break region, or break line of the light-emitting device ED.

[0181] The device isolation portion 15 may be implemented near the weir pattern portion 17 to include an isolation structure (or separation structure or cutting structure) for isolating (or separating) the light-emitting devices ED disposed near the weir pattern portion 17 or for completely isolating (or separating) the light-emitting devices ED and the common electrode CE. The isolation structure according to an embodiment of the invention may include at least one of an eaves structure (or cliff structure), a tip structure (or protruding tip structure), and an undercut structure. Therefore, the light-emitting devices ED and the common electrode CE disposed near the weir pattern portion 17 can be isolated (or separated) during the deposition process via the eaves structure of the device isolation portion 15 without a separate process.

[0182] The device isolation portion 15 can be implemented on the interlayer insulating layer 11c on the substrate 10 to surround the display area AA. For example, the device isolation portion 15 can be implemented as a closed loop shape on the interlayer insulating layer 11c to surround the display area AA one-dimensionally.

[0183] According to an embodiment of the present invention, the device isolation portion 15 may include at least two or more device isolation patterns 15a to 15d. For example, the device isolation portion 15 may include first to fourth device isolation patterns 15a to 15d.

[0184] The first device isolation pattern 15a may be implemented as a closed loop shape on the interlayer insulating layer 11c closest to the display area AA. The second device isolation pattern 15b may be implemented as a closed loop shape on the interlayer insulating layer 11c to surround the first device isolation pattern 15a. The third device isolation pattern 15c may be implemented as a closed loop shape on the interlayer insulating layer 11c to surround the second device isolation pattern 15b. The fourth device isolation pattern 15d may be implemented as a closed loop shape on the interlayer insulating layer 11c to surround the third device isolation pattern 15c. Each of the first to fourth device isolation patterns 15a to 15d may include an eaves structure for isolating (or separating) the light-emitting device ED.

[0185] Each of the first to fourth device isolation patterns 15a to 15d according to an embodiment of the present invention may include a first trench structure TS1, a metal pattern layer MPL, and a second trench structure TS2.

[0186] The first trench structure TS1 can be implemented by a passivation layer 11d. The first trench structure TS1 can be formed by performing a patterning process on the passivation layer 11d disposed in the non-display area IA. For example, the first trench structure TS1 can be formed by performing a patterning process on the passivation layer 11d using an etching process. For example, the first trench structure TS1 can be referred to as a first isolation structure or a first tapered structure.

[0187] According to an embodiment of the present invention, the lateral surface of the first trench structure TS1 can be implemented as an inclined structure or a conical structure. The bottom surface of the first trench structure TS1 can directly contact the top surface (or surface) of the interlayer insulating layer 11c, and the top surface of the first trench structure TS1 can be disposed above the bottom surface of the first trench structure TS1 and can have a width narrower than the bottom surface. The lateral surface of the first trench structure TS1 can be formed to be inclined between the top surface and the bottom surface. In the first trench structure TS1, the included angle between the bottom surface and the lateral surface can be an acute angle, and the included angle between the top surface and the lateral surface can be an obtuse angle. For example, the cross-section of the first trench structure TS1 cut along the width direction can have a trapezoidal cross-section structure in which its top surface is narrower than its bottom surface.

[0188] A metal pattern layer (MPL) may be disposed on the first trench structure TS1. The metal pattern layer (MPL) may have at least a two-layer structure identical to the pixel electrode PE. For example, the metal pattern layer (MPL) may include a first metal layer formed together with the first pixel electrode layer PEL1 of the pixel electrode PE and in direct contact with the top surface of the first trench structure TS1, and a second metal layer formed together with the second pixel electrode layer PEL2 of the pixel electrode PE and formed (or stacked) on the first metal layer.

[0189] The metal patterned layer MPL may have a width wider than the top surface of the first trench structure TS1. The metal patterned layer MPL may have a width greater than or equal to the width of the bottom surface of the first trench structure TS1. For example, the lateral surface of the metal patterned layer MPL may be implemented as an inclined structure or a conical structure. For example, a metal patterned layer MPL cut along the width direction may have the same trapezoidal shape as the first trench structure TS1 cut along the width direction of the first trench structure TS1. Relative to the width direction (or the cross-sectional direction), each of one edge portion and the other edge portion of the metal patterned layer MPL may protrude beyond the outer side of the lateral surface of the first trench structure TS1.

[0190] The lateral surface of the first trench structure TS1 may have an undercut structure relative to the metal pattern layer MPL. For example, the boundary portion between the first trench structure TS1 and the metal pattern layer MPL, or the upper lateral surface of the first trench structure TS1, may be undercut relative to the metal pattern layer MPL. Based on the undercut structure, the metal pattern layer MPL may protrude beyond the outer side of the lateral surface of the first trench structure TS1 and may cover the lateral surface of the first trench structure TS1. Therefore, the metal pattern layer MPL may have an eaves structure relative to the first trench structure TS1.

[0191] The second trench structure TS2 can be disposed on the metal pattern layer MPL. For example, the second trench structure TS2 can be referred to by terms such as a second isolation structure or a second tapered structure.

[0192] The second trench structure TS2 may include organic materials. According to one embodiment of the invention, the second trench structure TS2 may include the same material as the embankment 14, but embodiments of the invention are not limited thereto. For example, the second trench structure TS2 may include embankment material that was not patterned (or removed) during a patterning process performed on the embankment material but remained on the metal pattern layer MPL. The second trench structure TS2 may be implemented having the same height (or thickness) as the embankment 14.

[0193] The bottom surface of the second trench structure TS2 may have the same width as the top surface of the metal patterned layer MPL. In the second trench structure TS2, the top surface may be narrower than or equal to the width of the bottom surface. For example, the lateral surfaces of the second trench structure TS2 may be implemented as inclined or tapered structures. For example, the angle between the bottom surface and the lateral surface of the second trench structure TS2 may be the same as the angle between the bottom surface and the lateral surface of the metal patterned layer MPL, but embodiments of the present invention are not limited thereto.

[0194] The device isolation portion 15 according to an embodiment of the present invention may further include a plurality of groove patterns 15e.

[0195] Each of the plurality of groove patterns 15e may be disposed on both sides of each of the first to fourth device isolation patterns 15a to 15b. For example, each of the plurality of groove patterns 15e may be disposed between the first to fourth device isolation patterns 15a to 15b.

[0196] Each of the plurality of groove patterns 15e may be a portion of the passivation layer 11d obtained by performing a patterning process on the passivation layer 11d to form an undercut structure between the metal patterning layer MPL and the first trench structure TS1 of each of the first to fourth device isolation patterns 15a to 15b. The first trench structure TS1 may be implemented by the passivation layer 11d. Each of the plurality of groove patterns 15e may expose the interlayer insulating layer 11c disposed near each of the first to fourth device isolation patterns 15a to 15b.

[0197] The device isolation portion 15, including the first to fourth device isolation patterns 15a to 15b, can isolate (or separate) the light-emitting device ED, or can isolate (or separate) the light-emitting device ED and the common electrode CE. For example, the light-emitting device ED of the light-emitting device layer 13 formed (or deposited) on the device isolation portion 15 can be automatically isolated (or separated) by the undercut structure (or roof structure) of each of the first to fourth device isolation patterns 15a to 15b during the deposition process without a separate disconnection process. Therefore, the light-emitting device ED can include an isolation region isolated by the device isolation portion 15.

[0198] According to one embodiment of the present invention, the deposition material of the light-emitting device ED, including the organic light-emitting device, can have linearity, so that based on the undercut structure (or roof structure) of each of the first to fourth device isolation patterns 15a to 15b, the deposition material will not be deposited on the lateral surface of the first trench structure TS1 covered by the metal pattern layer MPL. Therefore, the light-emitting device ED formed (or deposited) on the first to fourth device isolation patterns 15a to 15b can be isolated (or separated) between the first trench structure TS1 and the metal pattern layer MPL. Therefore, the light-emitting device ED disposed near the weir pattern portion 17 can be automatically isolated (or separated) by the first to fourth device isolation patterns 15a to 15b of the device isolation portion 15, thus eliminating the need for a separate patterning process to isolate (or separate) the light-emitting device ED.

[0199] The deposited material of the light-emitting device ED disposed in the non-display area IA can be isolated (or separated) by the first to fourth device isolation patterns 15a to 15b of the device isolation portion 15. The isolated (or separated) deposited material EDs of the light-emitting device EDs can be disposed in an island shape in each of the plurality of groove patterns 15e and in an island shape covering the lateral surface of the metal pattern layer MPL and the top and lateral surfaces of the first trench structure TS1 in each of the first to fourth device isolation patterns 15a to 15b. Therefore, the light-emitting devices EDs disposed in the non-display area IA can be isolated from the light-emitting devices ED disposed in the display area AA, and thus the lateral moisture transport path of the substrate 10 can be blocked by the first to fourth device isolation patterns 15a to 15b of the device isolation portion 15.

[0200] Optionally, during the deposition process based on the deposition method, the common electrode CE disposed on the light-emitting device ED can be automatically isolated (or separated) by the first to fourth device isolation patterns 15a to 15b of the device isolation portion 15, or can be formed to surround the light-emitting device ED isolated by the first to fourth device isolation patterns 15a to 15b of the device isolation portion 15.

[0201] According to one embodiment of the present invention, when a common electrode CE is deposited by a sputtering process, the common electrode CE can be formed to surround light-emitting devices EDs isolated by first to fourth device isolation patterns 15a to 15b of the device isolation portion 15. For example, the common electrode CE disposed on the device isolation portion 15 can be deposited on the lateral surface of the first trench structure TS1 covered by the undercut structure (or eaves structure) of each of the first to fourth device isolation patterns 15a to 15b, thus surrounding the lateral surface of the first trench structure TS1 of each of the first to fourth device isolation patterns 15a to 15b, the first to fourth device isolation patterns 15a to 15b surround the isolated light-emitting devices EDs disposed in the non-display area IA and are exposed through the isolated light-emitting devices EDs. Therefore, the common electrode CE can be implemented to cover the entire device isolation portion 15.

[0202] According to another embodiment of the present invention, when a common electrode CE is deposited by chemical vapor deposition (CVD) instead of sputtering, the common electrode CE can be automatically isolated (or separated) by the first to fourth device isolation patterns 15a to 15b of the device isolation portion 15. For example, the common electrode CE disposed on the device isolation portion 15 can be isolated at the lateral surface of the first trench structure TS1 covered by the undercut structure (or eaves structure) of each of the first to fourth device isolation patterns 15a to 15b. For example, the common electrode CE disposed on the first to fourth device isolation patterns 15a to 15b can be electrically disconnected from the common electrode CE disposed on the plurality of groove patterns 15e.

[0203] Refer again Figure 1 , Figure 3 , Figure 4 and Figure 6 The weir pattern portion 17 may be disposed on the circuit layer 11 in the edge portion of the substrate 10. For example, the weir pattern portion 17 may be disposed on the passivation layer 11d of the circuit layer 11 to have a closed loop shape surrounding the display area AA. The weir pattern portion 17 may prevent the diffusion or overflow of the encapsulation layer 19 disposed on the substrate 10 to cover the display area AA.

[0204] The weir pattern portion 17 may be disposed between two adjacent device isolation patterns among at least two or more device isolation patterns 15a to 15d. For example, the weir pattern portion 17 may be implemented as a closed loop shape to surround the first device isolation pattern 15a, and may be implemented to be surrounded by the second to fourth device isolation patterns 15b to 15d. For example, the weir pattern portion 17 may be disposed between the first device isolation pattern 15a and the second device isolation pattern 15b of the device isolation portion 15.

[0205] The weir pattern portion 17 may include a structure (or structural material) used to prevent the loss (or removal) of the metal pattern layer of the eaves structure when forming (or manufacturing) the device isolation portion 15.

[0206] According to an embodiment of the present invention, the weir pattern portion 17 may include a first weir pattern 17a and a second weir pattern 17b.

[0207] The first dam pattern 17a may be disposed on the passivation layer 11d located between the first device isolation pattern 15a and the second device isolation pattern 15b in the device isolation portion 15. For example, the first dam pattern 17a may be formed before the process of forming (or manufacturing) the device isolation portion 15. For example, the first dam pattern 17a may be formed between the process of forming the planarization layer 12 and the process of forming the pixel electrode PE.

[0208] The first weir pattern 17a may include organic materials. According to one embodiment of the invention, the first weir pattern 17a may be formed together with the planarization layer 12 using the same material as the planarization layer 12, but embodiments of the invention are not limited thereto. For example, the first weir pattern 17a may be formed using the same material as the dike portion 14. For example, the first weir pattern 17a may have the same height (or thickness) as the planarization layer 12.

[0209] When forming (or manufacturing) the device isolation portion 15, the first dam pattern 17a may include a structure (or structural element) for preventing the loss (or removal) of the metal pattern layer of the eaves structure. For example, the first dam pattern 17a may be referred to by terms such as lower dam pattern, discontinuous dam pattern, interrupted dam pattern, dotted-line dam pattern, etc.

[0210] The first weir pattern 17a may include multiple linear weir patterns 17a1 and multiple pattern break portions 17a2.

[0211] Multiple linear weir patterns 17a1 may be spaced apart from each other to have a shape surrounding multiple outermost pixels disposed in the display area AA. The multiple linear weir patterns 17a1 may be configured to be spaced apart from each other along the edge portion of the substrate 10. For example, the multiple linear weir patterns 17a1 may be disposed on the passivation layer 11d to have a predetermined or selected length and a predetermined or selected gap space (or interval). The same structure can be described in a different manner as follows: multiple segments 17a1 of the weir are arranged in a line, each segment 17a1 separated from another segment 17a1. Spaces 17a2 are disposed between the segments, and the combination of 17a1 and 17a2 constitutes a discontinuous weir pattern 17a.

[0212] Multiple pattern break portions 17a2 (or groove portions) may be provided between multiple linear weir patterns 17a1. The multiple pattern break portions 17a2 may have a length less than or equal to the length of the linear weir pattern 17a1. For example, the length of the pattern break portion 17a2 or the length of the gap space between two adjacent linear weir patterns 17a1 may be less than or equal to the length of the linear weir pattern 17a1.

[0213] When forming (or manufacturing) the device isolation portion 15 after the process of manufacturing the first weir pattern 17a, the plurality of pattern break portions 17a2 provide a path for the patterning material (or etchant) required for patterning (or etching) the passivation layer 11d to move between the inside and outside of the first weir pattern 17a, thereby preventing, reducing, or minimizing over-etching of the passivation layer 11d beneath the metal patterned layer MPL caused by the patterning material (or etchant). Therefore, when forming (or manufacturing) the device isolation portion 15, the pattern break portions 17a2 of the first weir pattern 17a can prevent, reduce, or minimize the loss (or removal) of the metal patterned layer MPL used for the roof structure.

[0214] The second weir pattern 17b may be disposed on the first weir pattern 17a to have a closed-loop shape. The second weir pattern 17b may have a different cross-sectional structure than the first weir pattern 17a. The second weir pattern 17b may fill between the linear weir patterns 17a1 of the first weir pattern 17a and may be disposed on the linear weir patterns 17a1. For example, the second weir pattern 17b may fill each of a plurality of pattern break portions 17a2 disposed between the linear weir patterns 17a1. The second weir pattern 17b may prevent diffusion or overflow of the encapsulation layer 19. For example, the second weir pattern 17b may be referred to by terms such as upper weir pattern (or intermediate weir pattern), continuous weir pattern, successive weir pattern, etc. For example, the second weir pattern 17b may be manufactured after the process of forming (or manufacturing) the device isolation portion 15. For example, the device isolation portion 15 may be formed between the process of manufacturing the first weir pattern 17a and the process of manufacturing the second weir pattern 17b. The meaning of "filling" should be understood to include complete filling, overfilling, or partial filling. For example, the second weir pattern 17b may completely or overfill the pattern break portion 17a2, meaning that no other material besides the mentioned material is used to fill the pattern break portion 17a2. In such an example, the second weir pattern 17b is in direct physical contact with the linear weir pattern 17a1. In another configuration, the second weir pattern 17b may partially fill the pattern break portion 17a2, for example, when another layer of material is inserted in the pattern break portion 17a2 between the second weir pattern 17b and the linear weir pattern 17a1. Regarding the pattern break portion 17a2, the filled pattern break portion 17a2 may include a variety of configurations. For example, the pattern break portion 17a2 may have the second weir pattern 17b therein, and may also have a material, layer, or other layer besides the second weir pattern 17b therein that can cause the hole (e.g., the pattern break portion 17a2) to be filled. It may also include the mentioned material as the final material used to complete the filling of the hole. On the other hand, the terms "completely filled" or "overfilled" mean that no other material besides the mentioned material is used to fill the hole.

[0215] The second weir pattern 17b may include the same material as the first weir pattern 17a or the same material as the planarization layer 12, but embodiments of the present invention are not limited thereto. For example, the second weir pattern 17b may have a height (or thickness) greater than or equal to that of the planarization layer 12, or it may have a height (or thickness) greater than or equal to that of the first weir pattern 17a. For example, the total height of the first weir pattern 17a and the second weir pattern 17b may be two or more times the height (or thickness) of the planarization layer 12, but embodiments of the present invention are not limited thereto and may vary based on the thickness of the encapsulation layer 19.

[0216] The weir pattern portion 17, including the first weir pattern 17a and the second weir pattern 17b, can be surrounded by light-emitting devices (EDs) isolated by the device isolation portion 15. Furthermore, the light-emitting devices (EDs) surrounding the weir pattern portion 17 can be surrounded by common electrodes (CEs) isolated by the device isolation portion 15.

[0217] According to an embodiment of the present invention, the second weir pattern 17b may include a plurality of protruding patterns 17b1 and a closed-loop linear pattern 17b2.

[0218] Multiple protruding patterns 17b1 may be filled between the linear weir patterns 17a1 of the first weir pattern 17a. For example, multiple protruding patterns 17b1 may be filled into each of the multiple pattern break portions 17a2 of the first weir pattern 17a. Due to the protruding patterns 17b1 of the second weir pattern 17b, the first weir pattern 17a may have a closed-loop shape.

[0219] A closed-loop linear pattern 17b2 may be provided on a plurality of protruding patterns 17b1 and a linear weir pattern 17a1 of a first weir pattern 17a to have a closed-loop line shape. For example, each of the plurality of protruding patterns 17b1 may protrude from the closed-loop linear pattern 17b2 toward a plurality of pattern break portions 17a2 of the first weir pattern 17a.

[0220] According to an embodiment of the present invention, the weir pattern portion 17 may further include a third weir pattern 17c.

[0221] The third weir pattern 17c may be disposed on the second weir pattern 17b to have a closed-loop shape. The third weir pattern 17c may have a cross-sectional structure similar to that of the second weir pattern 17b. The third weir pattern 17c, together with the second weir pattern 17b, may prevent the diffusion or overflow of the encapsulation layer 19. For example, the third weir pattern 17c may be referred to by terms such as uppermost weir pattern (or upper weir pattern), auxiliary weir pattern, additional weir pattern, etc.

[0222] The third weir pattern 17c may include the same material as the dike portion 14, but embodiments of the invention are not limited thereto. For example, the third weir pattern 17c may be formed together with the dike portion 14. For example, the third weir pattern 17c may have a height (or thickness) greater than or equal to that of the dike portion 14. For example, the third weir pattern 17c may have a height (or thickness) equal to or different from that of the first weir pattern 17a and / or the second weir pattern 17b.

[0223] The weir pattern portion 17, including the first to third weir patterns 17a to 17c, can be surrounded by light-emitting devices (EDs) isolated by device isolation portion 15. Furthermore, the light-emitting devices (EDs) surrounding the weir pattern portion 17 can be surrounded by common electrodes (CEs) isolated by device isolation portion 15.

[0224] The encapsulation layer 19 can be disposed on the remaining portion of the substrate 10 except for the outermost edge portion including the pad portion PP, and can be implemented to cover the light-emitting device layer 13. For example, the encapsulation layer 19 can be implemented to surround the entire front surface and side surface of the light-emitting device layer 13. Furthermore, when the light-emitting device ED and the common electrode CE are isolated by the device isolation portion 15, the encapsulation layer 19 can surround the isolation surface (or separation surface) of the light-emitting device ED and the common electrode CE that are isolated by the device isolation portion 15. For example, the encapsulation layer 19 can fill (or embed) into the isolation space of the light-emitting device ED and the common electrode CE formed by the isolation structure (or undercut structure) of the device isolation portion 15 to seal or completely surround the device isolation portion 15, thereby completely surrounding or covering each of the isolated light-emitting device ED and the common electrode CE, thereby fundamentally (or completely) preventing the lateral penetration of moisture or humidity.

[0225] According to an embodiment of the present invention, the encapsulation layer 19 may include first to third encapsulation layers 19a to 19c.

[0226] The first encapsulation layer 19a can be implemented to prevent oxygen or moisture from penetrating into the light-emitting device layer 13. The first encapsulation layer 19a can be disposed on the common electrode CE and can surround the light-emitting device layer 13. Therefore, the entire front surface and side surface of the light-emitting device layer 13 can be surrounded by the first encapsulation layer 19a. The first encapsulation layer 19a can directly contact the top surface of the passivation layer 11d at the periphery of the weir pattern portion 17 and can cover the boundary portion (or interface) between the common electrode CE and the passivation layer 11d, thereby preventing or minimizing the lateral penetration of moisture or humidity. For example, the first encapsulation layer 19a can directly contact the top surface of the passivation layer 11d between the pad portion PP and the device isolation portion 15. According to an embodiment of the present invention, the first encapsulation layer 19a may include an inorganic material.

[0227] When the light-emitting device ED and the common electrode CE are separated by the device isolation portion 15, the first encapsulation layer 19a may surround the isolation surface (or separation surface) of the light-emitting device ED and the common electrode CE separated by the device isolation portion 15. For example, the first encapsulation layer 19a may fill (or embed) into the isolation space of the light-emitting device ED and the common electrode CE formed by the isolation structure (or undercut structure) of the device isolation portion 15 to seal or completely surround the device isolation portion 15, thereby completely surrounding or covering each of the isolated light-emitting device ED and the common electrode CE, thereby fundamentally (or completely) preventing lateral penetration of moisture or humidity.

[0228] The second encapsulation layer 19b may be implemented on the first encapsulation layer 19a, having a relatively thicker thickness than the first encapsulation layer 19a. The second encapsulation layer 19b may have a thickness that completely covers particles (or undesirable materials or undesirable structural elements) present or potentially present on the first encapsulation layer 19a. Due to its relatively thick thickness, the second encapsulation layer 19b may diffuse to the edge portion of the substrate 10, but the diffusion of the second encapsulation layer 19b may be blocked by the weir pattern portion 17. For example, the end of the second encapsulation layer 19b may directly contact the first encapsulation layer 19a on the weir pattern portion 17. Therefore, the second encapsulation layer 19b may be disposed only on the first encapsulation layer 19a in the inner region (or inner side region) surrounded by the weir pattern portion 17. For example, the second encapsulation layer 19b may be configured to cover the display area AA and the entire non-display area IA between the display area AA and the weir pattern portion 17. The second encapsulation layer 19b may be referred to as a particle cover layer. The second encapsulation layer 19b according to an embodiment of the present invention may comprise an organic material or a liquid organic material. For example, the second encapsulation layer 19b may include organic materials such as silicon carbide oxide (SiOCz), acrylic resin, epoxy resin, etc.

[0229] The third encapsulation layer 19c can be implemented to first prevent oxygen or moisture from penetrating into the light-emitting device layer 13. The third encapsulation layer 19c can be implemented to surround the entire second encapsulation layer 19b disposed inside the weir pattern portion 17 and the first encapsulation layer 19a disposed outside the weir pattern portion 17. For example, the third encapsulation layer 19c can directly contact the top surface of the passivation layer 11d at the periphery of the weir pattern portion 17 that is not covered by the first encapsulation layer 19a, and can cover the boundary portion (or interface) between the first encapsulation layer 19a and the passivation layer 11d, thereby additionally preventing or minimizing lateral penetration of moisture or humidity. For example, the third encapsulation layer 19c can directly contact the top surface of the passivation layer 11d between the pad portion PP and the device isolation portion 15. According to an embodiment of the present invention, the third encapsulation layer 19c may comprise the same or different inorganic material as the first encapsulation layer 19a.

[0230] Refer again Figure 1 and Figure 3 According to an embodiment of the present invention, the light-emitting display device may further include a wavelength conversion layer 21 disposed above the substrate 10.

[0231] The wavelength conversion layer 21 can convert the wavelength of light incident on each pixel region PA from the light-emitting area. For example, the wavelength conversion layer 21 can convert white light (or blue light) incident on it from the light-emitting area into colored light corresponding to the sub-pixel SP, or can only transmit the colored light corresponding to the sub-pixel SP. For example, the wavelength conversion layer 21 may include at least one of a wavelength conversion member and a color filter layer.

[0232] According to one embodiment, the wavelength conversion layer 21 may include a protective layer 21b and a plurality of wavelength conversion components 21a.

[0233] Multiple wavelength conversion components 21a may be disposed above the encapsulation layer 19 located in the light-emitting region EA of each of the multiple pixel regions PA. For example, each of the multiple wavelength conversion components 21a may be implemented with a size equal to or greater than the size of the light-emitting region EA of each sub-pixel region PA.

[0234] According to one embodiment, the plurality of wavelength conversion components 21a can be divided (or classified) into a red filter that converts white light to red light, a green filter that converts white light to green light, and a blue filter that converts white light to blue light. For example, a red filter (or a first filter) may be disposed above the encapsulation layer 19 in the light-emitting region EA of the red sub-pixel SP, a green filter (or a second filter) may be disposed above the encapsulation layer 19 in the light-emitting region EA of the green sub-pixel SP, and a blue filter (or a third filter) may be disposed above the encapsulation layer 19 in the light-emitting region EA of the blue sub-pixel SP.

[0235] According to another embodiment, a plurality of wavelength conversion members 21a may be disposed above the encapsulation layer 19 of each sub-pixel region SPA. For example, each of the plurality of wavelength conversion members 21a may be disposed above the encapsulation layer 19 to overlap the entire corresponding sub-pixel region SPA.

[0236] According to another embodiment, multiple wavelength conversion members 21a can be implemented by overlapping each other at an encapsulation layer 19 that overlaps with the circuit region CA (or non-light-emitting region) of each sub-pixel region SPA, excluding the light-emitting region EA. For example, two or more wavelength conversion members 21a of different colors are disposed at the encapsulation layer 19 that overlaps with the circuit region CA (or non-light-emitting region) of each sub-pixel region SPA. The two or more wavelength conversion members 21a disposed at the encapsulation layer 19 that overlaps with the circuit region CA (or non-light-emitting region) can function to prevent the appearance of light-blocking patterns of color mixing between adjacent sub-pixels SP or between adjacent pixels P.

[0237] The protective layer 21b may be configured to cover the wavelength conversion member 21a and provide a flat surface over the wavelength conversion member 21a. The protective layer 21b may be configured to cover the wavelength conversion member 21a and an encapsulation layer 19 in which the wavelength conversion member 21a is not disposed. According to one embodiment, the protective layer 21b may include an organic material. Alternatively, the protective layer 21b may further include a getter material for absorbing moisture and / or oxygen.

[0238] Alternatively, the wavelength conversion layer 21 according to another embodiment may include two or more layers of wavelength conversion members 21a disposed above the encapsulation layer 19 overlapping the circuit region CA (or non-light-emitting region) in each sub-pixel region SPA, excluding the light-emitting region EA. The two or more layers of wavelength conversion members 21a may function as a light-shielding pattern.

[0239] Alternatively, the wavelength conversion layer 21 can be a wavelength conversion sheet in sheet form and can be disposed on the encapsulation layer 19. In this case, the wavelength conversion sheet (or quantum dot sheet) may include a wavelength conversion member 21a disposed between a pair of films. For example, when the wavelength conversion layer 21 includes quantum dots for re-emitting colored light set in the sub-pixel, the light-emitting device layer 13 of the sub-pixel can be implemented to emit white light or blue light.

[0240] According to an embodiment of the present invention, the light-emitting display device may further include a functional film 23 disposed above the substrate 10.

[0241] The functional film 23 may be disposed above the wavelength conversion layer 21. For example, the functional film 23 may be bonded to the wavelength conversion layer 21 by a transparent adhesive member.

[0242] According to one embodiment, the functional film 23 may include an anti-reflective layer (or anti-reflective film) for preventing the reflection of external light, thereby improving outdoor visibility and contrast relative to the image displayed by the display panel. For example, the anti-reflective layer may include a circularly polarizing layer (or circularly polarizing film) to prevent external light reflected by the TFTs and / or pixel drive lines disposed on the substrate 10 from propagating to the outside.

[0243] According to one embodiment, the functional membrane 23 may further include a barrier layer (or barrier membrane) for firstly preventing the penetration of moisture or humidity or oxygen, the barrier layer may include a material with low water permeability (e.g., a polymer material).

[0244] According to one embodiment, the functional film 23 may further include an optical path control layer (or optical path control film) for controlling the path of light output from each pixel P to the outside. The optical path control layer may include a stacked structure in which high refractive index layers and low refractive index layers are stacked alternately and can change the path of light incident from each pixel P to reduce or minimize color shift based on viewing angle.

[0245] The light-emitting display device according to an embodiment of the present invention may further include a side sealing member 25 disposed on a substrate 10.

[0246] Side sealing member 25 may be formed between substrate 10 and functional film 23 and may cover all side surfaces of circuit layer 11 and wavelength conversion layer 21. For example, side sealing member 25 may cover all side surfaces of each of circuit layer 11 and wavelength conversion layer 21 located between functional film 23 and substrate 10 that are exposed to the outside of the light-emitting display device. In addition, side sealing member 25 may cover a portion of flexible circuit film 31 attached to each of a plurality of pad portions PP at an edge portion of substrate 10. Side sealing member 25 may prevent lateral light leakage caused by light emitted from light-emitting device ED of each sub-pixel SP that propagates to the outer surface of wavelength conversion layer 21. In particular, side sealing member 25 overlapping with pad portions PP of substrate 10 may prevent, reduce or minimize light reflection caused by pad electrodes PPe provided in pad portions PP.

[0247] Alternatively, the side sealing member 25 may further include an absorbent material for absorbing moisture and / or oxygen.

[0248] As described above, in the light-emitting display device according to an embodiment of the present invention, when forming (or manufacturing) the device isolation portion 15, the loss (or removal) of the metal pattern layer MPL of the roof structure due to the flow (or movement) of the patterning material can be prevented, reduced, or minimized by realizing the pattern break portion 17a2 in the first weir pattern 17a of the weir pattern portion 17, thereby allowing the device isolation portion 15 for isolating the light-emitting device ED to be formed normally. For example, in the light-emitting display device according to an embodiment of the present invention, since the flow (or movement) of the patterning material is smoothly carried out when forming (or manufacturing) the device isolation portion 15 based on the structural change of the weir pattern portion 17, over-etching of the first trench structure TS1 of the device isolation portion 15 can be prevented, thereby preventing, reducing, or minimizing the loss (or removal) of the metal pattern layer MPL of the roof structure, thus allowing the device isolation portion 15 to be formed normally. Therefore, in the light-emitting display device according to an embodiment of the present invention, the decrease in reliability of the light-emitting device ED caused by lateral penetration of moisture or humidity due to the loss or failure to form the device isolation portion 15 can be prevented, reduced, or minimized.

[0249] Figure 7 It is along Figure 1 Another cross-sectional view taken by line I-I' shown. Figure 8 It is along Figure 1 Another cross-sectional view taken from line II-II' shown. Figure 7 and Figure 8 The diagram illustrates the modification... Figures 1 to 6 The implementation method is based on the structure of the weir pattern shown in the diagram. Therefore, in the description Figure 7 and Figure 8 At that time, and Figures 1 to 6 Elements that are identical or corresponding to each other are referred to by similar reference numerals, and therefore their repeated descriptions will be omitted or briefly given below.

[0250] Reference Figure 7 and Figure 8 According to another embodiment of the present invention, the weir pattern portion 17 may include a first weir pattern 17a and a second weir pattern 17b'.

[0251] The first weir pattern 17a may include the same material as the planarization layer 12. The first weir pattern 17a may include a plurality of linear weir patterns 17a1 and a plurality of pattern break portions 17a2. The first weir pattern 17a may include a structure (or pattern break portion 17a2) for preventing loss (or removal) of the metal pattern layer of the eaves structure during the formation (or manufacture) of the device isolation portion 15, and may be referenced above. Figure 3 , Figure 4 and Figure 6 The first weir pattern 17a is described as being largely the same, so similar reference numerals refer to similar elements and their repeated descriptions are omitted.

[0252] The second weir pattern 17b' may be disposed on the first weir pattern 17a, having a closed-loop shape. The second weir pattern 17b' may comprise the same material as the dike portion 14. The second weir pattern 17b' may comprise a plurality of protruding patterns 17b1 and a closed-loop linear pattern 17b2. Except that the second weir pattern 17b' is formed together with the dike portion 14 from the same material as the dike portion 14, the second weir pattern 17b' may be associated with the above-mentioned reference. Figure 3 , Figure 4 and Figure 6 The second weir pattern 17b is substantially the same as the first weir pattern 17a, so similar reference numerals refer to similar elements and their repeated descriptions are omitted. Therefore, the second weir pattern 17b' may include a different material than the first weir pattern 17a, thus clearly distinguishing the boundary portion between the first weir pattern 17a and the second weir pattern 17b'.

[0253] According to another embodiment of the invention, the weir pattern portion 17 may further include a third weir pattern 17c.

[0254] The third weir pattern 17c can be set on the second weir pattern 17b' to have a closed loop shape. The third weir pattern 17c can be formed together with the embankment 14 from the same material as the embankment 14 and can be referenced above. Figure 3 , Figure 4 and Figure 6 The third weir pattern 17c is described as being largely the same, so similar reference numerals refer to similar elements and their repeated descriptions are omitted.

[0255] As described above, except that the first weir pattern 17a and the second weir pattern 17b' are made of different materials, the weir pattern portion 17 according to another embodiment of the present invention can be the same as that referred to above. Figure 3 , Figure 4 and Figure 6 The described weir pattern portion 17 is substantially the same, and thus similar to the weir pattern portion 17 described above, the loss (or removal) of the metal pattern layer MPL of the eaves structure can be prevented, reduced or minimized when forming (or manufacturing) the device isolation portion 15, thereby allowing the device isolation portion 15 to be formed (or manufactured) normally.

[0256] Figure 9 It is along Figure 1 Another cross-sectional view taken by line I-I' shown. Figure 10 It is along Figure 1 Another cross-sectional view taken from line II-II' shown. Figure 9 and Figure 10 The diagram illustrates the modification... Figures 1 to 6 The implementation method is based on the structure of the weir pattern shown in the diagram. Therefore, in the description Figure 9 and Figure 10 At that time, and Figures 1 to 6 Elements that are identical or corresponding to each other are referred to by similar reference numerals, and therefore their repeated descriptions will be omitted or briefly given below.

[0257] Reference Figure 9 and Figure 10 According to another embodiment of the present invention, the weir pattern portion 17 may include a first weir pattern 17a and a second weir pattern 17b'.

[0258] The first weir pattern 17a may include the same material as the planarization layer 12. The first weir pattern 17a may include a plurality of linear weir patterns 17a1 and a plurality of pattern break portions 17a2. The first weir pattern 17a may include a structure (or pattern break portion 17a2) for preventing loss (or removal) of the metal pattern layer of the eaves structure during the formation (or manufacture) of the device isolation portion 15, and may be referenced above. Figure 3 , Figure 4 and Figure 6 The first weir pattern 17a is described as being largely the same, so similar reference numerals refer to similar elements and their repeated descriptions are omitted.

[0259] The second weir pattern 17b' may be disposed on the first weir pattern 17a, having a closed-loop shape. The second weir pattern 17b' may comprise the same material as the dike portion 14. The second weir pattern 17b' may comprise a plurality of protruding patterns 17b1 and a closed-loop linear pattern 17b2. Except that the second weir pattern 17b' is formed together with the dike portion 14 from the same material as the dike portion 14, the second weir pattern 17b' may be associated with the above-mentioned reference. Figure 3 , Figure 4 and Figure 6 The second weir pattern 17b is substantially the same as the first weir pattern 17a, so similar reference numerals refer to similar elements and their repeated descriptions are omitted. Therefore, the second weir pattern 17b' may include a different material than the first weir pattern 17a, thus clearly distinguishing the boundary portion between the first weir pattern 17a and the second weir pattern 17b'.

[0260] According to another embodiment of the invention, the weir pattern portion 17 may further include a third weir pattern 17c'.

[0261] The third weir pattern 17c' may be disposed on the second weir pattern 17b' to have a closed-loop shape. According to an embodiment of the present invention, the third weir pattern 17c' may comprise the same material as the planarization layer 12. The third weir pattern 17c' may comprise a different material from the second weir pattern 17b', thus clearly distinguishing the boundary portion between the second weir pattern 17' and the third weir pattern 17c'. Except that the third weir pattern 17c' is formed on the second weir pattern 17b' using the same material as the planarization layer 12 after the process of forming (or manufacturing) the dike portion 14, the third weir pattern 17c' may be disposed on the second weir pattern 17b' using the same material as the planarization layer 12, as shown above. Figure 3 , Figure 4 and Figure 6 The third weir pattern 17c is described in a similar manner, so its repeated description is omitted.

[0262] As described above, except that the first weir pattern 17a and the second weir pattern 17b' are made of different materials and the second weir pattern 17b' and the third weir pattern 17c' are made of different materials, the weir pattern portion 17 according to another embodiment of the present invention may be the same as that referred to above. Figure 3 , Figure 4 and Figure 6 The described weir pattern portion 17 is substantially the same, and thus similar to the weir pattern portion 17 described above, the loss (or removal) of the metal pattern layer MPL of the eaves structure can be prevented, reduced or minimized when forming (or manufacturing) the device isolation portion 15, thereby allowing the device isolation portion 15 to be formed (or manufactured) normally.

[0263] Figure 11 It is along Figure 1 Another cross-sectional view taken by line I-I' shown. Figure 12 It is along Figure 1 Another cross-sectional view taken from line II-II' shown. Figure 11 and Figure 12 The diagram illustrates the modification... Figures 1 to 6 The implementation method is based on the structure of the weir pattern shown in the diagram. Therefore, in the description Figure 11 and Figure 12 At that time, and Figures 1 to 6Elements that are identical or corresponding to each other are referred to by similar reference numerals, and therefore their repeated descriptions will be omitted or briefly given below.

[0264] Reference Figure 11 and Figure 12 According to another embodiment of the present invention, the weir pattern portion 17 may include a first weir pattern 17a' and a second weir pattern 17b.

[0265] The first weir pattern 17a' may include a material containing a color filter (or wavelength conversion member) disposed in the wavelength conversion layer 21. For example, the first weir pattern 17a' may be formed as a single-layer or multi-layer structure including at least one wavelength conversion member or color filter layer disposed in the wavelength conversion layer 21. For example, the first weir pattern 17a' may include at least one of a red color filter, a green color filter, and a blue color filter.

[0266] The first weir pattern 17a' may include multiple linear weir patterns 17a1 and multiple pattern break portions 17a2. Except for the first weir pattern 17a' including structures (or pattern break portions 17a2) used to prevent loss (or removal) of the metal pattern layer of the eaves structure during the formation (or manufacture) of the device isolation portion 15 and including material containing a color filter (or wavelength conversion component), the first weir pattern 17a' may be related to the above-mentioned... Figure 3 , Figure 4 and Figure 6 The first weir pattern 17a is described in a similar manner, so its repeated description is omitted.

[0267] The second weir pattern 17b may be disposed on the first weir pattern 17a' to have a closed-loop shape. The second weir pattern 17b may include a plurality of protruding patterns 17b1 and a closed-loop linear pattern 17b2. Except that the second weir pattern 17b is formed together with the planarization layer 12 using the same material as the planarization layer 12, the second weir pattern 17b may be related to the above-mentioned... Figure 3 , Figure 4 and Figure 6 The second weir pattern 17b is substantially the same as the first weir pattern 17a', so similar reference numerals refer to similar elements and their repeated descriptions are omitted. Therefore, the second weir pattern 17b may include a different material than the first weir pattern 17a', thus clearly distinguishing the boundary portion between the first weir pattern 17a' and the second weir pattern 17b.

[0268] According to another embodiment of the invention, the weir pattern portion 17 may further include a third weir pattern 17c.

[0269] The third weir pattern 17c can be set on the second weir pattern 17b to have a closed loop shape. The third weir pattern 17c can be formed together with the embankment 14 using the same material as the embankment 14 and can be referenced above. Figure 3 , Figure 4 and Figure 6 The third weir pattern 17c is described as being largely the same, so similar reference numerals refer to similar elements and their repeated descriptions are omitted.

[0270] As described above, except that the first weir pattern 17a' includes a material containing a color filter (or wavelength conversion component), the weir pattern portion 17 according to another embodiment of the present invention may be the same as that referred to above. Figure 3 , Figure 4 and Figure 6 The described weir pattern portion 17 is substantially the same, and thus similar to the weir pattern portion 17 described above, the loss (or removal) of the metal pattern layer MPL of the eaves structure can be prevented, reduced or minimized when forming (or manufacturing) the device isolation portion 15, thereby allowing the device isolation portion 15 to be formed (or manufactured) normally.

[0271] Alternatively, in the weir pattern portion 17 according to another embodiment of the invention, the first weir pattern 17a' may be made of the same material as the planarization layer 12, the second weir pattern 17b may be made of a material containing a color filter (or wavelength conversion member), and the third weir pattern 17c may be made of the same material as the planarization layer 12. Even in this case, except that the second weir pattern 17b includes a material containing a color filter (or wavelength conversion member) and the third weir pattern 17c includes a material the same as the planarization layer 12, the weir pattern portion 17 according to another embodiment of the invention may be the same as the one referred to above. Figure 3 , Figure 4 and Figure 6 The described weir pattern portion 17 is substantially the same, and thus similar to the weir pattern portion 17 described above, the loss (or removal) of the metal pattern layer MPL of the eaves structure can be prevented, reduced or minimized when forming (or manufacturing) the device isolation portion 15, thereby allowing the device isolation portion 15 to be formed (or manufactured) normally.

[0272] Alternatively, in the weir pattern portion 17 according to another embodiment of the invention, the first weir pattern 17a' may be made of the same material as the planarization layer 12, the second weir pattern 17b may be made of a material containing a color filter (or wavelength conversion member), and the third weir pattern 17c may be made of the same material as the dike portion 14. Even in this case, except that the second weir pattern 17b includes a material containing a color filter (or wavelength conversion member) and the third weir pattern 17c includes a material the same as the dike portion 14, the weir pattern portion 17 according to another embodiment of the invention may be the same as the one referred to above. Figure 3 , Figure 4 and Figure 6The described weir pattern portion 17 is substantially the same, and thus similar to the weir pattern portion 17 described above, the loss (or removal) of the metal pattern layer MPL of the eaves structure can be prevented, reduced or minimized when forming (or manufacturing) the device isolation portion 15, thereby allowing the device isolation portion 15 to be formed (or manufactured) normally.

[0273] Figure 13 It is along Figure 1 Another cross-sectional view taken by line I-I' shown. Figure 14 It is along Figure 1 Another cross-sectional view taken from line II-II' shown. Figure 13 and Figure 14 The diagram illustrates the modification... Figures 1 to 6 The implementation method is based on the structure of the weir pattern shown in the diagram. Therefore, in the description Figure 13 and Figure 14 At that time, and Figures 1 to 6 Elements that are identical or corresponding to each other are referred to by similar reference numerals, and therefore their repeated descriptions will be omitted or briefly given below.

[0274] Reference Figure 13 and Figure 14 According to another embodiment of the present invention, the weir pattern portion 17 may include a first weir pattern 17a, a metal weir pattern 17m, and a second weir pattern 17b.

[0275] The first weir pattern 17a may include the same material as the planarization layer 12. The first weir pattern 17a may include a plurality of linear weir patterns 17a1 and a plurality of pattern break portions 17a2. The first weir pattern 17a may include a structure (or pattern break portion 17a2) for preventing loss (or removal) of the metal pattern layer of the eaves structure during the formation (or manufacture) of the device isolation portion 15, and may be referenced above. Figure 3 , Figure 4 and Figure 6 The first weir pattern 17a is described in a similar manner, so its repeated description is omitted.

[0276] A metal weir pattern 17m may be provided on the first weir pattern 17a. According to one embodiment of the invention, the metal weir pattern 17m may be provided only on each of the plurality of linear weir patterns 17a1 of the first weir pattern 17a. For example, the metal weir pattern 17m may not be provided in each of the plurality of pattern break portions 17a2 of the first weir pattern 17a. Therefore, the metal weir pattern 17m may be referred to by terms such as intermediate weir pattern, intermediate metal weir pattern, discontinuous metal weir pattern, intermittent metal weir pattern, dotted line metal weir pattern, etc.

[0277] The metal weir pattern 17m may include one or more metal layers. For example, the metal weir pattern 17m may be formed together with the pixel electrode PE using the same material as the pixel electrode PE.

[0278] According to an embodiment of the present invention, the metal weir pattern 17m may include a first weir metal layer 17m1 that directly contacts the first weir pattern 17a and a second weir metal layer 17m2 disposed on the first weir metal layer 17m1.

[0279] The first weir metal layer 17m1 and the second weir metal layer 17m2 may be formed together with the pixel electrode PE using the same material as the pixel electrode PE disposed in the display area AA. For example, the first weir metal layer 17m1 may include the same material as the first pixel electrode layer of the pixel electrode PE. The second weir metal layer 17m2 may include the same material as the second pixel electrode layer of the pixel electrode PE. For example, the first weir metal layer 17m1 and the second weir metal layer 17m2 may be formed together with a pixel electrode layer comprising a metallic material capable of absorbing hydrogen, one of a plurality of pixel electrode layers constituting the pixel electrode PE. For example, the metal weir pattern 17m may include a metal layer comprising titanium (Ti) or a metal layer comprising a molybdenum-titanium alloy (MoTi).

[0280] The second weir pattern 17b may be disposed on the first weir pattern 17a to have a closed-loop linear shape. The second weir pattern 17b is formed of the same material as the planarization layer 12. The second weir pattern 17b may include a plurality of protruding patterns 17b1 and a closed-loop linear pattern 17b2. Except that the second weir pattern 17b fills (or embeds) between the linear weir patterns 17a1 of the first weir pattern 17a and is disposed on the metal weir pattern 17m, the second weir pattern 17b may be associated with the above-mentioned reference. Figure 3 , Figure 4 and Figure 6 The second weir pattern 17b is substantially the same as described, so its repeated description is omitted. Therefore, the metal weir pattern 17m can be disposed between the first weir pattern 17a and the second weir pattern 17b, which include the same material, so that the boundary portion between the first weir pattern 17a and the second weir pattern 17b can be clearly distinguished.

[0281] According to another embodiment of the invention, the weir pattern portion 17 may further include a third weir pattern 17c.

[0282] The third weir pattern 17c can be set on the second weir pattern 17b to have a closed loop shape. The third weir pattern 17c can be formed together with the embankment 14 using the same material as the embankment 14 and can be referenced above. Figure 3 , Figure 4 and Figure 6 The third weir pattern 17c is described as being largely the same, so similar reference numerals refer to similar elements and their repeated descriptions are omitted.

[0283] As described above, except that the metal weir pattern 17m is disposed between the first weir pattern 17a and the second weir pattern 17b, the weir pattern portion 17 according to another embodiment of the present invention may be the same as the one referred to above. Figure 3 , Figure 4 and Figure 6 The described weir pattern portion 17 is substantially the same, and thus, similar to the weir pattern portion 17 described above, it can prevent, reduce, or minimize the loss (or removal) of the metal pattern layer MPL of the roof structure during the formation (or manufacturing) of the device isolation portion 15, thereby allowing the device isolation portion 15 to be formed (or manufactured) normally. Furthermore, in the weir pattern portion 17 according to another embodiment of the present invention, since the height (or thickness) based on the metal weir pattern 17m is increased, the diffusion or overflow of the encapsulation layer 19 can be effectively prevented. Furthermore, the weir pattern portion 17 according to another embodiment of the present invention may further include a metal weir pattern 17m comprising a metal material capable of absorbing hydrogen, thereby preventing, reducing, or minimizing characteristic changes of the TFT and / or light-emitting device due to hydrogen.

[0284] Figure 15 This is a plan view illustrating a light-emitting display device according to another embodiment of the present invention. Figure 16 This is a schematic side view illustrating a light-emitting display device according to another embodiment of the present invention. Figure 17 yes Figure 15 An enlarged view of region "B3" shown. Figure 18 yes Figure 15 Another enlarged view of area "B3" shown.

[0285] Reference Figures 15 to 18 According to another embodiment of the present invention, a light-emitting display device (or light-emitting display panel) may include a first substrate 100, the first substrate 100 including a display area AA and a plurality of pixels P arranged in the display area AA of the first substrate 100 at a first interval D1.

[0286] The first substrate 100 may include a first surface 100a, a second surface 100b, and an outer surface OS. The first surface 100a of the first substrate 100 may be defined as a front surface, top surface, or upper surface facing the front (or forward) direction of the light-emitting display device. The second surface 100b of the first substrate 100 may be defined as a back surface, rear surface, bottom surface, or lower surface facing the back (or rearward) direction of the light-emitting display device. The outer surface OS of the first substrate 100 may be defined as a side surface, side surface, or sidewall extending along the periphery between the first surface 100a and the second surface 100b, facing the light-emitting display device, and exposed to air. For example, when the first substrate 100 has a hexahedral structure, the outer surface OS of the first substrate 100 may include a hexahedral side surface.

[0287] The outer surface OS of the first substrate 100 may be formed parallel to the thickness direction Z of the light-emitting display device. For example, the outer surface OS of the first substrate 100 may include: a first outer surface parallel to the first direction X, a second outer surface parallel to the first outer surface, a third outer surface parallel to the second direction Y intersecting the first direction X and connecting one end of the first outer surface and one end of the second outer surface, and a fourth outer surface parallel to the third outer surface and connecting the other end of the first outer surface and the other end of the second outer surface. The first direction X may be a first length direction (e.g., a transverse direction) of the first substrate 100 or the light-emitting display device, and the second direction Y may be a second length direction (e.g., a longitudinal direction) of the first substrate 100 or the light-emitting display device.

[0288] The display area AA of the first substrate 100 can be an area for displaying an image and can be referred to as a display portion or an active portion. The size of the display area AA can be the same as or substantially the same as the first substrate 100 (or the light-emitting display device). For example, the size of the display area AA can be the same as the total size of the first surface 100a of the first substrate 100. Therefore, the display area AA can be implemented (or disposed) on the entire front surface of the first substrate 100, and thus the first substrate 100 may not include an opaque non-display area disposed along the edge portion of the first surface 100a to surround the entire display area AA. Therefore, the entire front surface of the light-emitting display device can realize the display area AA.

[0289] The end (or outermost portion) AAa of the display area AA may overlap with or be substantially aligned with the outer surface OS of the first substrate 100. For example, the lateral surface AAa of the display portion AA may be substantially coplanar with the outer surface OS of the first substrate 100. In other words, the lateral surface of the display portion AA and the outer surface OS of the first substrate 100 may be substantially aligned at the same position. The lateral surface AAa of the display portion AA may not be surrounded by a separate mechanism, but may be surrounded only by air. As another example, the lateral surface of the display portion AA may overlap with or be substantially aligned with the outer surface OS of the first substrate 100. Therefore, the outer surface OS of the first substrate 100 corresponding to the end AAa of the display area AA may be in direct contact with air without being surrounded by a separate mechanism, or may be surrounded by air. Thus, the light-emitting display device according to the present invention may have an air-bezel structure or a frameless structure, wherein the end AAa of the display area AA (or the lateral surface of the display portion AA) is surrounded by air rather than by an opaque non-display area.

[0290] According to one embodiment, the display area (or display portion) AA may include multiple pixel areas PA.

[0291] According to one embodiment, a plurality of pixel regions PA can be arranged (or configured) with a first interval D1 in the display area AA of the first substrate 100. Two pixel regions PA that are adjacent to each other along the first direction X and the second direction Y of the first substrate 100 can have the same first interval D1 without manufacturing process error range. The first interval D1 can be the pitch (or pixel spacing) between two adjacent pixel regions PA. For example, the first interval D1 can be the shortest distance (or shortest length) between the center portions of two adjacent pixel regions PA. Alternatively, the pixel spacing can be the dimension between one end of a pixel region PA parallel to the first direction X and the other end. Furthermore, as another example, the pixel spacing can be referred to as the dimension between one end of a pixel region PA parallel to the second direction Y and the other end.

[0292] Each of the plurality of pixel regions PA may have a first length L1 parallel to a first direction X and a second length L2 parallel to a second direction Y. Each of the first length L1 and the second length L2 may be the same as the first spacing D1. For example, the first length L1 may be referred to as a first width, a horizontal length, or a horizontal width. The second length L2 may be referred to as a second width, a vertical length, or a vertical width. The first length L1 or the second length L2 of the pixel region PA may be referred to as the pixel pitch.

[0293] The second interval D2 between the outermost pixel region PAo of the plurality of pixel regions PA and the outer surface OS of the first substrate 100 may be half or less than the first interval D1, such that the entire front surface of the first substrate 100 (or the entire front surface of the light-emitting display device) is referred to as the display area AA. For example, the second interval D2 may be the shortest distance (or shortest length) between the central portion of the outermost pixel region PAo and the outer surface OS of the first substrate 100.

[0294] When the second interval D2 is greater than half of the first interval D1, the first substrate 100 can have a larger size than the display area AA due to the area between the end of the outermost pixel area PAo (or the end AAa of the display area AA) and the outer surface OS of the first substrate 100. Therefore, the area between the end of the outermost pixel area PAo and the outer surface OS of the first substrate 100 can be set as a non-display area surrounding the entire display area AA. Thus, the first substrate 100 will necessarily include a border area based on the non-display area surrounding the entire display area AA. On the other hand, when the second interval D2 is half or less of the first interval D1, the end of the outermost pixel area PAo (or the end AAa of the display area AA) can overlap with the outer surface OS of the first substrate 100, or can be disposed in the space outside the outer surface OS of the first substrate 100. Therefore, the display area AA can be realized (or disposed) on the entire front surface of the first substrate 100.

[0295] According to one embodiment, the display area (or display portion) may include an outermost pixel area PAo and an inner pixel area (or inner pixel area) PAi.

[0296] Among the multiple pixel regions PA, the outermost pixel region PAo can be disposed along the edge (or peripheral portion) of the first substrate 100. For example, the outermost pixel region PAo can be referred to as the first pixel region PA1.

[0297] The inner pixel region PAI can be any pixel region other than the outermost pixel region PAo among multiple pixel regions PA, or it can be surrounded by the outermost pixel region PAo. The inner pixel region PAI can be referred to as the second pixel region PA2.

[0298] Each of the plurality of pixels P may be disposed in a corresponding pixel region PA among a plurality of pixel regions PA defined on a first surface 100a of the first substrate 100. For example, the display region AA may be a pixel array including a plurality of pixels P disposed on the first substrate 100. The pixels P of the pixel array may be adjacent to each other along a first direction X and a second direction Y. For example, the pixels P of the pixel array may be adjacent to each other along the first direction X and the second direction Y without separation space (or partition space). As another example, the ends of a plurality of outermost pixels Po in the pixel array may be aligned to overlap each other at the outer surface OS of the first substrate 100, or may be aligned on the same plane at the outer surface OS of the first substrate 100. For example, each pixel P of the pixel array may be disposed on the first substrate 100 to have a pixel pitch D1 along the first direction X and the second direction Y, and the interval D2 between the center portion of each outermost pixel Po and the outer surface OS of the first substrate 100 may be half or less of the pixel pitch D1.

[0299] According to one embodiment, the display area (or display portion) AA may include the outermost pixel Po and the inner pixel (or inner side pixel) Pi.

[0300] Among the multiple pixel regions PA, the outermost pixel Po may be located at the edge (or peripheral) portion of the first substrate 100. For example, the outermost pixel Po may be referred to as the first pixel P1 located in the outermost pixel region PAo.

[0301] An inner pixel Pi can be a pixel other than the outermost pixel Po among a plurality of pixels P, or it can be configured to be surrounded by the outermost pixel Po. For example, an inner pixel Pi can be referred to as a second pixel P2. An inner pixel Pi (or a second pixel P2) can be implemented to have a different construction or structure than the outermost pixel Po (or the first pixel P1).

[0302] The second interval D2 between each outermost pixel Po of the plurality of pixels P and the outer surface OS of the first substrate 100 may be half or less than the first interval D1, such that the entire front surface of the first substrate (or the entire front surface of the light-emitting display device) is referred to as the display area AA. The first interval D1 may be the shortest distance (or shortest length) between the center portions of two adjacent pixels P. The second interval D2 may be the shortest distance (or shortest length) between the center portion of the outermost pixel Po and the outer surface OS of the first substrate 100.

[0303] Reference Figure 17 and Figure 18 According to another embodiment, each of the plurality of pixels P may include first to fourth sub-pixels SP1 to SP4.

[0304] A first sub-pixel SP1 can be disposed in the first sub-pixel region of pixel region PA, a second sub-pixel SP2 can be disposed in the second sub-pixel region of pixel region PA, a third sub-pixel SP3 can be disposed in the third sub-pixel region of pixel region PA, and a fourth sub-pixel SP4 can be disposed in the fourth sub-pixel region of pixel region PA. As one implementation, the first sub-pixel SP1 can be configured to emit light of a first color, the second sub-pixel SP2 can be configured to emit light of a second color, the third sub-pixel SP3 can be configured to emit light of a third color, and the fourth sub-pixel SP4 can be configured to emit light of a fourth color. For example, each of the first to fourth colors can be different. For example, the first color can be red, the second color can be blue, the third color can be white, and the fourth color can be green. As another implementation, some of the first to fourth colors can be the same. For example, the first color can be red, the second color can be first green, the third color can be second green, and the fourth color can be blue.

[0305] The first to fourth sub-pixels SP1 to SP4 may each include multiple light-emitting areas EA1 to EA4 and multiple circuit areas CA1 to CA4.

[0306] The light-emitting areas EA1 to EA4 (or the light-emitting parts) can be set within the sub-pixel area as the central part CP close to pixel P.

[0307] According to one embodiment, the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 can be implemented within the corresponding pixel P or pixel region PA to have the same size (or the same area), such as Figure 17As shown in the diagram. For example, the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a uniform square structure or a non-uniform strip structure. For example, each of the light-emitting regions EA1 to EA4 having a uniform square structure or a non-uniform strip structure may be positioned close to the central portion CP of pixel P, thereby having a smaller size than each of the four equally divided regions of pixel P.

[0308] According to another embodiment, the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 can be implemented to have different sizes within the corresponding pixel P or pixel region PA, such as Figure 18 As shown in the figure. For example, the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform square structure or a non-uniform strip structure.

[0309] In each of the first to fourth sub-pixels SP1 to SP4, which have a non-uniform square structure (or a non-uniform strip structure), the size of each of the light-emitting regions EA1 to EA4 can be set based on resolution, luminous efficiency, or image quality. As one embodiment, when the light-emitting regions EA1 to EA4 have a non-uniform square structure (or a non-uniform strip structure), among the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the light-emitting region EA4 of the fourth sub-pixel SP4 may have the smallest size, and the light-emitting region EA3 of the third sub-pixel SP3 may have the largest size.

[0310] In the first to fourth sub-pixels SP1 to SP4, each of the light-emitting regions EA1 to EA4 can be separated from each other along the first direction X and the second direction Y. However, the embodiments of the present invention are not limited to this, and they can be adjacent to each other without separation space (or separation space).

[0311] The circuit regions CA1 to CA4 of each of the first to fourth sub-pixels SP1 to SP4 may be disposed around (or near) the corresponding light-emitting region among the light-emitting regions EA1 to EA4. Each of the circuit regions CA1 to CA4 may include pixel circuitry, signal lines, and power lines for emitting light from the corresponding sub-pixel among the first to fourth sub-pixels SP1 to SP4. For example, the circuit regions CA1 to CA4 may be referred to as non-light-emitting regions or peripheral portions.

[0312] Alternatively, in order to increase the aperture ratio of sub-pixels SP1 to SP4 corresponding to the dimensions of the light-emitting regions EA1 to EA4, or to reduce the pixel pitch D1 as the resolution of pixel P increases, the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may extend into the circuit regions CA1 to CA4 to overlap with some or all of the circuit regions CA1 to CA4. For example, each of the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may be implemented on the first substrate 100 to overlap with the corresponding circuit region in the circuit regions CA1 to CA4. In this case, the light-emitting regions EA1 to EA4 may have dimensions equal to or larger than those of the circuit regions CA1 to CA4.

[0313] Alternatively, each of the plurality of pixels P according to another embodiment of the present invention may include first to third sub-pixels SP1 to SP3.

[0314] The light-emitting areas EA1 to EA3 of the first to third sub-pixels SP1 to SP3 can each have a rectangular shape including a short side parallel to the first direction X and a long side parallel to the second direction Y. For example, they can be set in a 1×3 form or a 1×3 stripe form. For example, the first sub-pixel can be a red sub-pixel, the second sub-pixel can be a blue sub-pixel, and the third sub-pixel can be a green sub-pixel, but the embodiments of the present invention are not limited thereto.

[0315] According to another embodiment of the present invention, the light-emitting display device may further include a pad portion 110, which includes a plurality of pads disposed in the display area AA of the first substrate 100 and selectively connected to a plurality of pixels P. For example, the pad portion 110 may be a first pad portion or a front pad portion.

[0316] The pad portion 110 may be included in the outermost pixel Po at a first edge portion parallel to the first direction X disposed in the first surface of the first substrate 100. That is, the outermost pixel Po disposed at the first edge portion of the first substrate 100 may include at least one or more of a plurality of pads. Therefore, the plurality of pads may be disposed or included within the display area AA, so that no non-display area (or border area) based on the pad portion 110 is formed or there is no such area on the first substrate 100. Therefore, the outermost pixel Po (or the first pixel P1) may include the pad portion 110, and thus may be implemented to have a different structure or configuration than the inner pixel Pi (or the second pixel P2) that does not include the pad portion 110.

[0317] According to one embodiment, when the pad portion 110 is not disposed within the outermost pixel Po but between the outermost pixel Po and the outer surface OS of the first substrate 100, the first substrate 100 may include a non-display area corresponding to the area where the pad portion 110 is disposed. Due to this non-display area, the second interval D2 between the outermost pixel Po and the outer surface OS of the first substrate 100 will be greater than half of the first interval D1. The first substrate 100 will not be entirely implemented as a display area AA, and a separate border (or separate structure) will be needed to cover this non-display area. On the other hand, according to one embodiment of the present invention, the pad portion 110 may be disposed between the center portion of the outermost pixel Po and the outer surface OS of the first substrate 100 and may be included inside (or within) the outermost pixel Po. Therefore, no non-display area (or border area) based on the pad portion 110 is formed or exists between the outermost pixel Po and the outer surface OS of the first substrate 100.

[0318] Therefore, the light-emitting display device according to another embodiment of the present invention may have an air bezel structure, wherein the entire first substrate 100 of the pad portion 110 is implemented as a display area AA, so that all outer surfaces (or outer surfaces of the display panel) OS of the first substrate 100 aligned with the end of the display area AA are surrounded only by air, without having a separate mechanism surrounding them.

[0319] Figure 19 It is a diagram Figure 15 The front perspective view of the light-emitting display device shown. Figure 20 It is a diagram Figure 15 A diagram showing the rear surface of the light-emitting display device.

[0320] Reference Figure 19 and Figure 20 According to another embodiment of the present invention, the light-emitting display device 101 may include a first substrate 100, a second substrate 200, a bonding member 300 and a wiring portion 400.

[0321] The first substrate 100 may be referred to as a display substrate, pixel array substrate, upper substrate, front substrate, or base substrate. The first substrate 100 may be a glass substrate, or a bendable or flexible thin glass substrate or plastic substrate.

[0322] According to one embodiment, a first substrate 100 may include a plurality of pixel driving lines and a plurality of pixels P.

[0323] Pixel driving lines may be disposed above the first surface 100a of the first substrate 100 and may transmit signals required for driving (emitting light) each of a plurality of pixels P. For example, pixel driving lines may include a plurality of data lines DL, a plurality of gate lines GL, a plurality of pixel driving power lines (or first power lines) PL, a plurality of pixel common voltage lines (or second power lines) CVL, and a plurality of pixel reference voltage lines (or sensing lines) RL.

[0324] According to one embodiment, each of the multiple data lines DL, multiple gate lines GL, multiple pixel drive power lines PL, multiple pixel common voltage lines CVL, and multiple pixel reference voltage lines RL can be directly connected to each pad of the first pad portion 110 disposed at the first edge portion in the first surface 100a of the first substrate 100, or can be connected via pad connection lines (or pad wires).

[0325] The first pad portion 110 may be included within a plurality of outermost pixels Po located at a first edge portion of the first substrate 100 parallel to the first direction X. Here, the first edge portion of the first surface 100a of the first substrate 100 may include a first outer surface (or a side surface) OS1a of the outer surface OS of the first substrate 100.

[0326] The first pad portion 110 may include a plurality of first pads, which are disposed parallel to each other along a first direction on a passivation layer 11d at a first edge portion exposed on the first surface 100a of the first substrate 100.

[0327] Multiple pixels P can be respectively disposed in multiple pixel regions PA arranged along a first direction X and a second direction Y at a first interval (or first spacing) D1. Each of the multiple pixels P may include a light-emitting device (or light-emitting element) and pixel circuitry. The light-emitting device emits light based on a top-emitting type according to a signal provided through a corresponding pixel driving line adjacent to it and illuminates a portion above a first surface 100a of the first substrate 100. The pixel circuitry is connected to the adjacent pixel driving line to cause the light-emitting device to emit light. For example, the pixel circuitry may include a driving thin-film transistor (TFT) that provides a data current to the light-emitting device corresponding to a data signal provided through a data line DL.

[0328] The distance between the outermost pixel of the plurality of pixels P and the outer surface OS of the first substrate 100 can be half or less than the first interval D1. The second interval D2 between the center portion of the outermost pixel and the outer surface OS of the first substrate 100 can be half or less than the first interval D1, thus the entire front surface of the first substrate 100 (or the entire front surface of the light-emitting display device) can be implemented as the display area AA. Therefore, the light-emitting display device according to another embodiment of the present invention can have an air bezel structure in which the display area AA is surrounded by air.

[0329] According to one embodiment, the first substrate 100 may further include a gate driving circuit 150 disposed in the display area AA.

[0330] According to one embodiment, the gate drive circuit 150 can be implemented using a shift register, which includes multiple stages of circuitry 1501 to 150m (m is an integer of 2 or greater). For example, a light-emitting display device according to another embodiment of the present invention may include a shift register disposed in the display area AA of the first substrate 100 to provide a scan signal to the pixel P.

[0331] Each of the plurality of stage circuit portions 1501 to 150m may include a plurality of branch circuits 1511 to 151n (where n is an integer of 2 or greater) arranged spaced apart from each other in each horizontal row along the first direction X of the first substrate 100. The plurality of branch circuits 1511 to 151n may include at least one or more TFTs (or branch TFTs) and may be arranged between at least one or more pixels P (or pixel regions PA) within a horizontal row along the first direction X. For example, branch circuits 1511 to 151n may be arranged sequentially between two adjacent pixels P (or pixel regions PA) within a horizontal row along the first direction X. Each of the plurality of stage circuit portions 1501 to 150m may generate scan signals in a predetermined or selected order in response to a gate control signal provided through the first pad portion 110, and may provide the scan signals to the gate line GL. For example, the gate control signal may include a start signal, a plurality of shift clocks, at least one gate drive voltage, and at least one gate common voltage.

[0332] The first substrate 100 may further include a plurality of gate control line groups GCLs connected to the gate drive circuit 150. Each gate control line group GCL may be selectively connected to a plurality of branch circuits 1511 to 151n respectively disposed in a plurality of stage circuit sections 1501 to 150m.

[0333] According to one embodiment, the gate control line group (GCL) may include a start signal line, multiple shift clock lines, at least one gate drive voltage line, and at least one gate common voltage line. According to one embodiment, the multiple shift clock lines may be divided (or classified) into multiple scan clock lines and multiple carry clock lines. Here, the multiple carry clock lines may be omitted.

[0334] The first pad portion 110 may further include a first gate pad portion, which includes a plurality of first gate pads connected to the gate control line group GCL.

[0335] The second substrate 200 may be referred to as a wiring substrate, link substrate, lower substrate, rear substrate, or link glass. The second substrate 200 may be a glass substrate, or a bendable or flexible thin glass substrate or plastic substrate. The second substrate 200 may comprise the same material as the first substrate 100. For example, the dimensions of the second substrate 200 and the first substrate 100 may be the same or substantially the same.

[0336] The second substrate 200 can be joined (or connected) to the second surface of the first substrate 100 via a joining member 300. The second substrate 200 may include: a front surface facing the second surface of the first substrate 100 or joined to the joining member 300; a rear surface (or back surface) opposite to the front surface; and an outer surface OS between the front surface and the rear surface. The second substrate 200 can transmit signals to pixel drive lines and can increase the rigidity of the first substrate 100.

[0337] According to another embodiment of the present invention, the light-emitting display device may further include a second pad portion 210 disposed on the second substrate 200.

[0338] The second pad portion 210 may be disposed at a first edge portion in the rear surface 200b of the second substrate 200 that overlaps with the first pad portion 110 disposed on the first substrate 100. The first edge portion of the rear surface 200b of the second substrate 200 may include a first outer surface (or a surface) OS1b in the outer surface OS of the second substrate 200.

[0339] The second pad portion 210 may include a plurality of second pads, which are arranged at certain intervals along the first direction X, thereby overlapping with the pads of the first pad portion 110 respectively.

[0340] According to another embodiment of the present invention, the light-emitting display device may further include a third pad portion (or input pad portion) 230 and a wiring portion 250 disposed on the second substrate 200.

[0341] The third pad portion 230 may be disposed on the rear surface 200b of the second substrate 200. For example, the third pad portion 230 may be disposed in the central portion of the rear surface 200b of the second substrate 200 adjacent to the first edge portion. According to one embodiment, the third pad portion 230 may include a plurality of third pads (or input pads) spaced apart from each other.

[0342] The interconnect portion 250 may be disposed between the second pad portion 210 and the third pad portion 230. For example, the interconnect portion 250 may include multiple interconnects that individually (or in a one-to-one relationship) connect the second pad of the second pad portion 210 to the third pad of the third pad portion 230.

[0343] A bonding member 300 may be disposed between the first substrate 100 and the second substrate 200. The first substrate 100 and the second substrate 200 may be bonded to each other via the bonding member 300. For example, the second surface 100b of the first substrate 100 (see...) Figure 24 The first substrate 100 and the second substrate 200, which are joined (or bonded) to each other by the joining members 300, can be bonded to one surface of the joining member 300, and the front surface of the second substrate 200 can be bonded to the other surface of the joining member 300. Therefore, the first substrate 100 and the second substrate 200, which are joined (or bonded) to each other by the joining members 300, can be referred to as a light-emitting display panel.

[0344] The routing portion 400 may be referred to as a side routing portion or a printed line portion. The routing portion 400 may be configured to surround the outer surface OS of the first substrate 100 and the outer surface OS of the second substrate 200. According to one embodiment, the routing portion 400 may include a plurality of wirings 410, 430, 450, 470 and 490, which are disposed on each of the first outer surface (or a surface) OS1a of the outer surface OS of the first substrate 100 and the first outer surface (or a surface) OS1b of the outer surface OS of the second substrate 200.

[0345] Each of the plurality of wirings 410, 430, 450, 470, and 490 may be formed to surround each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200. As one embodiment, the plurality of wirings 410, 430, 450, 470, and 490 may be individually (or in a one-to-one relationship) connected between the pads of the first pad portion 110 and the pads of the second pad portion 210.

[0346] Alternatively, the second substrate 200 may be omitted. In this case, the second pad portion 210, the third pad portion (or input pad portion) 230, and the interconnect portion 250 may be directly disposed on the rear surface of the first substrate 100. Furthermore, the wiring portion 400 may include multiple wirings 410, 430, 450, 470, and 490 disposed around the outer surface OS of the first substrate 100.

[0347] The light-emitting display device 101 according to an embodiment of the present invention may further include a driving circuit unit 500.

[0348] The driving circuit unit 500 can drive (or illuminate) the pixels P disposed on the first substrate 100 based on digital video data and timing synchronization signals provided from the display driving system, so that the display area AA displays an image corresponding to the image data. The driving circuit unit 500 can be connected to a third pad portion 230 disposed on the rear surface 200b of the second substrate 200 and can output data signals, gate control signals, and driving power to the third pad portion 230 for driving (or illuminating) the pixels P disposed on the first substrate 100. For example, the driving circuit unit 500 can have a size smaller than the second substrate 200, so it can be covered by the second substrate 200 and is not exposed on the outer surface of the second substrate 200 or the outer surface of the first substrate 100.

[0349] According to one embodiment, the drive circuit unit 500 may include a flexible circuit film 510, a driver integrated circuit (IC) 530, a printed circuit board (PCB) 550, a timing controller 570, and a power supply circuit unit 590. The drive circuit unit 500 having this configuration can be used with... Figure 1 The drive circuit unit 30 shown is substantially the same, so its repeated description can be omitted or simplified.

[0350] The flexible circuit film 510 can be connected to the third pad portion 230 disposed on the rear surface 200b of the second substrate 200.

[0351] The driver IC 530 can be mounted on the flexible circuit film 510. The driver IC 530 can be connected to multiple data lines DL, multiple pixel drive power lines PL, multiple pixel common voltage lines CVL, and multiple reference voltage lines RL via the flexible circuit film 510, the third pad portion 230, the interconnect portion 250, the second pad portion 210, the wiring portion 400, and the first pad portion 110. The driver IC 530 can receive sub-pixel data and data control signals provided from the timing controller 570, and convert the sub-pixel data into analog data signals based on the data control signals to provide the analog data signals to the corresponding data lines DL. Furthermore, the driver IC 530 can generate reference voltages, pixel drive voltages, and pixel common voltages, and can provide these reference voltages, pixel drive voltages, and pixel common voltages to the corresponding voltage lines RL, power lines PL, and common voltage lines CVL.

[0352] The driver IC 530 can sense the characteristic value of the driving TFT disposed in the pixel P through multiple reference voltage lines RL disposed on the first substrate 100, generate sensing raw data corresponding to the sensing value, and provide the sensing raw data to the timing controller 570.

[0353] PCB 550 can be connected to another edge portion of flexible circuit film 510. PCB 550 can transmit signals and power between components of drive circuit unit 500.

[0354] The timing controller 570 can be mounted on PCB 550 and can receive digital video data and timing synchronization signals from the display driver system via a user connector located on PCB 550.

[0355] The timing controller 570 can arrange digital video data based on timing synchronization signals to generate pixel data that matches the pixel arrangement structure set in the display area AA and can provide the generated pixel data to the driver IC 530.

[0356] The timing controller 570 can generate each of a data control signal and a gate control signal based on a timing synchronization signal, control the driving timing of the driver IC 530 based on the data control signal, and control the driving timing of the gate drive circuit 150 based on the gate control signal. For example, the timing synchronization signal may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a master clock (or dot clock).

[0357] The timing controller 570 can drive each of the gate drive circuit 150 and the driver IC 530 based on an external sensing mode during a predetermined or selected external sensing period, generate compensation data for compensating for characteristic variations of the drive TFT of each pixel P based on the raw sensing data provided from the driver IC 530, and modulate pixel data based on the generated compensation data. For example, the timing controller 570 can drive each of the gate drive circuit 150 and the driver IC 530 based on an external sensing mode during each external sensing period corresponding to the blanking period (or vertical blanking period) of the vertical synchronization signal.

[0358] The power supply circuit unit 590 can be mounted on the PCB 550 and can use externally supplied input power to generate various source voltages required for displaying images on the pixel P, and provide the generated source voltages to the corresponding circuits.

[0359] Figure 21 yes Figure 19 An enlarged view of area "B4" shown. Figure 22 It is a diagram Figure 15 and Figure 19 The circuit diagram for one pixel is shown. Figure 21 and Figure 22 It is a diagram illustrating multiple pixels disposed on a first substrate.

[0360] Reference Figure 19 , Figure 21 and Figure 22 According to an embodiment of the present invention, the first substrate 100 may include multiple data lines DL, multiple gate lines GL, multiple pixel driving power lines PL, multiple pixel common voltage lines CVL, multiple pixels P, common electrode CE, multiple common electrode contact portions CECP, a first pad portion 110, a device isolation portion 15, and a weir pattern portion 17.

[0361] Multiple data lines DL can extend along a second direction Y and are arranged in the display area AA of the first substrate 100, separated from each other by a predetermined or selected interval along a first direction X. For example, among the multiple data lines DL, odd-numbered data lines DLo can be arranged along the second direction Y at the first edge portion of each of the multiple pixel areas PA arranged on the first substrate 100, and even-numbered data lines DLe can be arranged along the second direction Y at the second edge portion of each of the multiple pixel areas PA arranged on the first substrate 100.

[0362] Multiple gate lines GL can extend along a first direction X and are disposed in the display area AA of the first substrate 100, spaced apart from each other by a predetermined or selected interval along a second direction Y. For example, the odd-numbered gate lines GLo among the multiple gate lines GL can be disposed along the first direction X at the third edge portion of each of the multiple pixel areas PA disposed on the first substrate 100. The even-numbered gate lines GLe among the multiple gate lines GL can be disposed along the first direction X at the fourth edge portion of each of the multiple pixel areas PA disposed on the first substrate 100.

[0363] Multiple pixel driving power lines PL can extend along the second direction Y and are disposed in the display area AA of the first substrate 100, separated from each other by a predetermined or selected interval along the first direction X. For example, among the multiple pixel driving power lines PL, the odd-numbered pixel driving power lines PL can be disposed at the first edge portion of the odd-numbered pixel area PA relative to the first direction X, and the even-numbered pixel driving power lines PL can be disposed at the second edge portion of the even-numbered pixel area PA relative to the first direction X.

[0364] Two adjacent pixel driving power lines PL can be connected to multiple power sharing lines PSL disposed in each pixel region PA arranged along the second direction Y. For example, the multiple pixel driving power lines PL can be electrically connected to each other through multiple power sharing lines PSL, thus having a ladder structure or a mesh structure. The multiple pixel driving power lines PL can have a ladder structure or a mesh structure, thus preventing, reducing or minimizing the voltage drop (or IR drop) of the pixel driving power caused by the line resistance of each of the multiple pixel driving power lines PL. Therefore, the light-emitting display device according to the present invention can prevent, reduce or minimize the degradation of image quality caused by the deviation of the pixel driving power supplied to each pixel P.

[0365] Each of the multiple power sharing lines PSL can branch from the adjacent pixel drive power line PL parallel to the first direction X and can be set in the middle region of each pixel region PA.

[0366] Multiple pixel common voltage lines (CVLs) can extend along the second direction Y and are disposed in the display area AA of the first substrate 100, separated from each other by a predetermined or selected interval along the first direction X. For example, each of the multiple pixel common voltage lines (CVLs) can be disposed at the first edge portion of the even-numbered pixel area PA relative to the first direction X.

[0367] Multiple reference voltage lines RL can extend along a second direction Y and are arranged in the display area AA of the first substrate 100, separated from each other by a predetermined or selected interval along a first direction X. Each of the multiple reference voltage lines RL can be arranged in the central region of each pixel area PA arranged along the second direction Y.

[0368] Each of the multiple reference voltage lines RL can be shared by two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) in each pixel region PA along the first direction X. Therefore, each of the multiple reference voltage lines RL may include a reference branch line RDL. The reference branch line RDL may branch (or protrude) to two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) in each pixel region PA along the first direction X and may be electrically connected to the two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)).

[0369] Multiple pixels P can be respectively disposed in multiple pixel areas PA of equal size in the display area AA of the first substrate 100.

[0370] Each of the plurality of pixels P may include at least three sub-pixels. For example, each of the plurality of pixels P may include first to fourth sub-pixels SP1 to SP4.

[0371] Each of the first to fourth sub-pixels SP1 to SP4 may include a pixel circuit PC and a light-emitting device ED.

[0372] According to one embodiment, a pixel circuit PC can be disposed in the circuit region of pixel region PA and can be connected to adjacent gate lines GLo and GLe, adjacent data lines DLo and DLe, and pixel drive power line PL. For example, the pixel circuit PC disposed in the first sub-pixel SP1 can be connected to the odd number of data lines DLo and the odd number of gate lines GLo, the pixel circuit PC disposed in the second sub-pixel SP2 can be connected to the even number of data lines DLe and the odd number of gate lines GLo, the pixel circuit PC disposed in the third sub-pixel SP3 can be connected to the odd number of data lines DLo and the even number of gate lines GLe, and the pixel circuit PC disposed in the fourth sub-pixel SP4 can be connected to the even number of data lines DLe and the even number of gate lines GLe.

[0373] The pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can sample data signals provided from the corresponding data lines DLo and DLe in response to the scan signals provided from the corresponding gate lines GLo and GLe, and can control the current flowing from the pixel drive power line PL to the light-emitting device ED based on the sampled data signals.

[0374] According to one embodiment, the pixel circuit PC can be... Figure 2The three TFTs Tsw1, Tsw2, and Tdr, along with a capacitor Cst, are shown to sample data signals, and the current flowing into the light-emitting device (ED) can be controlled based on the sampled data signals. Except for the first switch TFT Tsw1 and the second switch TFT Tsw2 in the pixel circuit PC, which simultaneously turn on or off in response to a scan signal provided from their respective gate lines GLo and GLe, the pixel circuit PC can be connected to the above-mentioned reference... Figure 2 The pixel circuits PC described are largely the same, so their repeated descriptions can be omitted or simplified.

[0375] According to another embodiment, the pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can be implemented as a pixel driver chip using a semiconductor manufacturing process. It is disposed in the circuit region of the corresponding pixel region PA and connected to adjacent gate lines GLo and GLe, adjacent data lines DLo and DLe, and a pixel driver power line PL. For example, the pixel driver chip can be a minimum-unit microchip or a chipset, and can be a semiconductor packaged device with a small size, including two or more transistors and one or more capacitors. Such a pixel driver chip can sample data signals provided from the corresponding data lines DLo and DLe in response to scan signals provided from the corresponding gate lines GLo and GLe, and can control the current flowing from the pixel driver power line PL to the light-emitting device ED based on the sampled data signals.

[0376] The light-emitting device (ED) can be disposed in the light-emitting region EA of the pixel region PA, electrically connected to the pixel circuit PC and electrically connected to the common electrode CE. The ED emits light using the current flowing from the pixel circuit PC to the common electrode CE. The ED can be... Figure 2 The light-emitting devices (EDs) shown are largely the same, so their repeated descriptions can be omitted or simplified.

[0377] A common electrode CE may be disposed in the display area AA of the first substrate 100 and electrically connected to the light-emitting device ED of each of the plurality of pixels P. For example, the common electrode CE may be disposed in the display area AA of the first substrate 100, excluding the first pad portion 110 disposed in the first substrate 100.

[0378] Each of the plurality of common electrode contact portions CECP can electrically connect the common electrode CE to a corresponding pixel common voltage line CVL among the plurality of pixels P that overlap with each of the plurality of pixel common voltage lines CVL. Relative to the second direction Y, each of the plurality of common electrode contact portions CECP according to one embodiment can be electrically connected to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL at a portion between the plurality of pixels P or at a boundary portion between the plurality of pixels P, and can be electrically connected to a portion of the common electrode CE, thus electrically connecting the common electrode CE to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL.

[0379] Each of the plurality of common electrode contact portions CECP can be disposed between at least two adjacent pixels P among the plurality of pixels P, so as to electrically connect the common electrode CE to each of the plurality of pixel common voltage lines CVL, thereby preventing, reducing or minimizing the voltage drop (IR drop) of the pixel common power caused by the surface resistance of the common electrode CE. Therefore, the light-emitting display device according to the present invention can prevent, reduce or minimize the degradation of image quality caused by the deviation of the pixel driving power supplied to each pixel P arranged in the display area AA.

[0380] According to one embodiment, each of the plurality of common electrode contact portions (CECPs) can be formed together with a pixel electrode (PE) having a double-layer structure, thereby electrically connecting to each of the plurality of pixel common voltage lines (CVLs). Each of the plurality of common electrode contact portions (CECPs) can be connected to the common electrode (CE) via a side contact structure having a "(" shaped cross-section or a "<" shaped cross-section. For example, when each of the plurality of common electrode contact portions (CECPs) is formed of a first metal layer and a second metal layer, each of the plurality of common electrode contact portions (CECPs) can include a side contact structure corresponding to an undercut structure or a conical structure formed on the lateral surface of the first metal layer due to the etching rate difference between the first metal layer and the second metal layer. For example, when each of the plurality of common electrode contact portions (CECPs) is formed of a first to a third metal layer, each of the plurality of common electrode contact portions (CECPs) can include a side contact structure corresponding to an undercut structure or a conical structure formed on the lateral surface of the second metal layer due to the etching rate difference between the second metal layer and the third metal layer.

[0381] The first pad portion 110 may be disposed at a first edge portion parallel to the first direction X in the first surface of the first substrate 100. The first pad portion 110 may be disposed at the third edge portion of each outermost pixel region PAo located at the first edge portion of the first substrate 100. With respect to the second direction Y, the end of the first pad portion 110 may overlap or align with the end of each outermost pixel region PAo. Therefore, the first pad portion 110 may be included (or disposed) in each outermost pixel region PAo located at the first edge portion of the first substrate 100, so that no non-display area (or border area) based on the first pad portion 110 is formed or exists in the first substrate 100.

[0382] The first pad portion 110 may include a plurality of first pads, which are disposed parallel to each other along a first direction X at a first edge portion of the first substrate 100.

[0383] According to one embodiment, the first pad portion 110 may include a plurality of pad groups PG. Two or more of the plurality of pad groups PG may include at least one data pad DP and at least one gate pad GP. For example, according to one embodiment, the first pad portion 110 may include a plurality of pad groups PG arranged along a first direction X in the following order: pixel drive voltage pad PVP, data pad DP, reference voltage pad RVP, data pad DP, gate pad GP, pixel common voltage pad CVP, data pad DP, reference voltage pad RVP, data pad DP, and pixel drive voltage pad PVP.

[0384] Each of a plurality of pad groups PG can be connected to two adjacent pixels P disposed along a first direction X. For example, the plurality of pad groups PG may include a first pad group PG1 and a second pad group PG2. The first pad group PG1 includes a pixel drive voltage pad PVP, a data pad DP, a reference voltage pad RVP, a data pad DP, and a gate pad GP, which are continuously disposed along the first direction X in an odd-numbered pixel region PA. The second pad group PG2 includes a pixel common voltage pad CVP, a data pad DP, a reference voltage pad RVP, a data pad DP, and a pixel drive voltage pad PVP, which are continuously disposed along the first direction X in an even-numbered pixel region PA.

[0385] The first substrate 100 according to the present invention may further include multiple auxiliary power lines SPL and multiple auxiliary power contact portions SPCP.

[0386] Each of the plurality of auxiliary power lines SPL can extend along the second direction Y and can be disposed adjacent to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL. Each of the plurality of auxiliary power lines SPL can be electrically connected to the adjacent pixel common voltage line CVL but not electrically connected to the pixel common voltage pad CVP, and can be provided with pixel common power through the adjacent pixel common voltage line CVL. For this purpose, the first substrate 100 according to the invention may further include a plurality of line connection patterns LCP, which electrically connect adjacent pixel common voltage lines CVL and auxiliary power lines SPL.

[0387] Each of the plurality of line connection patterns LCP can be disposed on the first substrate 100 to intersect with adjacent pixel common voltage lines (CVL) and auxiliary power lines (SPL), and adjacent pixel common voltage lines (CVL) and auxiliary power lines (SPL) can be electrically connected by using a jumper structure. For example, one side of each of the plurality of line connection patterns LCP can be electrically connected to a portion of the auxiliary power line SPL through a first line contact hole formed in an insulating layer on the auxiliary power line SPL, and the other side of each of the plurality of line connection patterns LCP can be electrically connected to a portion of the pixel common voltage line CVL through a second line contact hole formed in an insulating layer on the pixel common voltage line CVL.

[0388] Each of the plurality of auxiliary power contact portions SPCP can electrically connect a common electrode CE between a plurality of pixels P overlapping with a plurality of auxiliary power lines SPL. Relative to the second direction Y, each of the plurality of auxiliary power contact portions SPCP according to one embodiment can be electrically connected to a plurality of auxiliary power lines SPL at a portion between a plurality of pixels P or at a boundary portion between a plurality of pixels P, and can be electrically connected to a portion of the common electrode CE, thus electrically connecting the common electrode CE to each of the plurality of auxiliary power lines SPL. Therefore, the common electrode CE can be additionally connected to each of the plurality of auxiliary power lines SPL via the auxiliary power contact portions SPCP. Therefore, the light-emitting display device according to an embodiment of the present invention can prevent, reduce, or minimize image quality degradation caused by deviations in the pixel common power supplied to each pixel P arranged in the display area AA. Furthermore, in the light-emitting display device according to the present invention, although no additional pixel common voltage pad CVP is provided (or formed) connected to each of the plurality of auxiliary power lines SPL, pixel common power can be provided to the common electrode CE in each of the plurality of pixel areas PA. Similar to each of the multiple common electrode contact portions CECP, each of the multiple auxiliary power contact portions SPCP can electrically connect one of the multiple auxiliary power lines SPL to the common electrode CE through a side contact structure having a "(" shaped cross-section structure or a "<" shaped cross-section structure.

[0389] The device isolation portion 15 may be disposed in a second region surrounding the first region of the first substrate 100. For example, the second region of the first substrate 100 may be an edge portion of the first substrate 100 or an edge portion of the outermost pixel Po. The first region of the first substrate 100 may be any region other than the second region. The device isolation portion 15 may be implemented to prevent lateral penetration of moisture or humidity in the lateral direction of the light-emitting display panel, thereby preventing, reducing, or minimizing degradation of the light-emitting device ED due to lateral moisture penetration. The device isolation portion 15 may be disposed inside the outermost pixel Po disposed along an edge portion of the first substrate 100. For example, the device isolation portion 15 may include at least two isolation patterns disposed between the outer surface OS of the first substrate 100 and the light-emitting region of the outermost pixel Po. Except for the device isolation portion 15 being configured to be disposed inside the outermost pixel Po disposed along an edge portion of the substrate 100, the device isolation portion 15 may be disposed with... Figures 1 to 14 The device isolation portions 15 shown are substantially the same, so similar reference numerals refer to similar elements, and their repeated descriptions are omitted or will be briefly given.

[0390] The weir pattern portion 17 may be disposed within the device isolation portion 15. For example, the weir pattern portion 17 may be disposed between two adjacent isolation patterns among at least two or more device isolation patterns 15a, 15b, 15c, and 15d. For example, the weir pattern portion 17 may be implemented as a closed loop surrounding the first device isolation pattern 15a, and may be implemented as being surrounded by the second to fourth device isolation patterns 15b, 15c, and 15d. For example, the weir pattern portion 17 may be disposed between the first device isolation pattern 15a and the second device isolation pattern 15b in the device isolation portion 15.

[0391] The weir pattern portion 17 may include a structure (or structural element) that prevents the loss (or removal) of the metal pattern layer of the eaves structure during the formation (or fabrication) of the device isolation portion 15. Except that the weir pattern portion 17 is configured to be disposed within the outermost pixel Po along an edge portion of the first substrate 100, the weir pattern portion 17 may be associated with… Figures 1 to 14 The weir pattern portions 17 shown are substantially the same, so similar reference numerals refer to similar elements, and their repeated descriptions are omitted or will be given briefly.

[0392] Figure 23 It is a diagram Figure 19 and Figure 21 The diagram shows the gate drive circuitry set in the display area shown.

[0393] Reference Figure 19 , Figure 21 and Figure 23 According to an embodiment of the present invention, the gate driving circuit 150 may be disposed in the display area AA of the first substrate 100 and may be connected to the gate control line group GCL disposed in the display area AA of the first substrate 100.

[0394] First, the gate control line group (GCL) may include multiple gate control lines connected to the gate drive circuit 150 in the display area AA of the first substrate 100. According to one embodiment, the gate control line group (GCL) may include a start signal line, multiple shift clock lines, at least one gate drive voltage line, and at least one gate common voltage line. Each line of the gate control line group (GCL) may extend along a second direction Y and may be disposed in the display area AA of the first substrate 100 at predetermined or selected intervals separated from each other along a first direction X. For example, each line of the gate control line group (GCL) may be disposed between at least one or more pixels P along the first direction X.

[0395] According to one embodiment, the gate drive circuit 150 can be implemented using a shift register, which includes multiple stages of circuitry 1501 to 150m.

[0396] Each of the plurality of stage circuit portions 1501 to 150m may be individually disposed in each horizontal row of the first surface 100a of the first substrate 100 along the first direction X, and may be associatedly connected to each other along the second direction Y. Each of the plurality of stage circuit portions 1501 to 150m may generate a scan signal in a predetermined or selected sequence in response to a gate control signal provided through the first pad portion 110 and the gate control line group GCL, and may provide the scan signal to the corresponding gate line GL.

[0397] Each of the plurality of stage circuit portions 1501 to 150m according to one embodiment may include a plurality of branch circuits 1511 to 151n and a branch network 153.

[0398] Each of the plurality of branch circuits 1511 to 151n can be selectively connected to a line of the gate control line group GCL via branch network 153 and can be electrically connected to each other via branch network 153. Each of the plurality of branch circuits 1511 to 151n can generate a scan signal based on a gate control signal provided through each line of the gate control line group GCL, and can provide the scan signal to the corresponding gate line GL.

[0399] Each of the plurality of branch circuits 1511 to 151n may include at least one of the plurality of TFTs constituting each of the stage circuit portions 1501 to 150m. Any one of the plurality of branch circuits 1511 to 151n may include a pull-up TFT connected to the gate line GL. Another of the plurality of branch circuits 1511 to 151n may include a pull-down TFT connected to the gate line GL.

[0400] Each of the plurality of branch circuits 1511 to 151n according to one embodiment may be disposed in a circuit region between two adjacent pixels P in each horizontal row of the first substrate 100, but the embodiments of the present invention are not limited thereto. For example, based on the number of TFTs constituting a stage circuit portion and the number of pixels P disposed in a horizontal row, each of the plurality of branch circuits 1511 to 151n may be disposed in a circuit region between at least one or more adjacent pixels P.

[0401] Branch network 153 may be disposed in each horizontal row of the first substrate 100 and may electrically connect a plurality of branch circuits 1511 to 151n. According to one embodiment, branch network 153 may include network lines and a plurality of control nodes.

[0402] Multiple control nodes may be disposed in each horizontal row of the first substrate 100 and may be selectively connected to multiple branch circuits 1511 to 151n in a horizontal row. For example, multiple control nodes may be disposed in the upper edge region (or lower edge region) of the pixel region arranged in each horizontal row of the first substrate 100.

[0403] The network lines can be selectively connected to the lines of the gate control line group GCL disposed in the first substrate 100 and can be selectively connected to a plurality of branch circuits 1511 to 151n. For example, the network lines can transmit gate control signals provided by the lines of the gate control line group GCL to the corresponding branch circuits 1511 to 151n and can transmit signals between the plurality of branch circuits 1511 to 151n.

[0404] As described above, according to an embodiment of the present invention, because the gate driving circuit 150 is disposed in the display area AA of the first substrate 100, the second interval D2 between the center portion of the outermost pixel area PAo and each outer surface OS of the first substrate can be equal to or less than half of the first interval (or pixel pitch) D1 between adjacent pixel areas PA. For example, when... Figure 1 When the gate driving circuit 150 shown is not disposed in the display area AA of the substrate 10 but is disposed at the edge portion of the first substrate 100, the second interval D2 will not be equal to or less than half of the first interval D1. Therefore, in a light-emitting display device according to another embodiment of the present invention, the gate driving circuit 150 may be disposed in the display area AA of the first substrate 100, and thus the second interval D2 may be implemented to be equal to or less than half of the first interval D1.

[0405] Figure 24 It is along Figure 19 The cross-sectional view taken by line III-III' shown in the figure. Figure 25 yes Figure 24 An enlarged view of area "B5" shown. In the description Figure 24 and Figure 25 At that time, and Figure 19 Elements that are identical or corresponding to each other are referred to by similar reference numerals, and their repeated descriptions are omitted or will be given briefly.

[0406] Reference Figure 19 , Figure 24 and Figure 25 A light-emitting display device according to another embodiment of the present invention may include a first substrate 100 and a second substrate 200 joined (or bonded) to each other by a bonding member 300. In describing the first substrate 100 and the second substrate 200, [the following is a more detailed description:] ... Figure 19 Elements that are identical or corresponding to each other are referred to by similar reference numerals, and their repeated descriptions are omitted or will be given briefly.

[0407] According to one embodiment, a first substrate 100 may include a display portion AA.

[0408] The display portion AA may include a circuit layer 11, a planarization layer 12, a light-emitting device layer 13, a dam 14, a device isolation portion 15, a weir pattern portion 17, an encapsulation layer 19, a wavelength conversion layer 21, a functional film 23, and a side sealing member 25. Except for the arrangement structure of the pixel circuit PC and light-emitting device ED of pixel P, and the device isolation portion 15 and weir pattern portion 17 disposed inside (or within) the outermost pixel Po of the first substrate 100, the components disposed in the display portion AA are... Figures 3 to 14 The components shown on the substrate 10 are substantially the same. Therefore, in the following description, similar reference numerals refer to similar components and their repeated descriptions will be omitted or briefly given.

[0409] The circuit layer 11 may be disposed on the first surface 100a of the first substrate 100. The circuit layer 11 may be referred to as a pixel array layer or a TFT array layer. According to one embodiment, the circuit layer 11 may include a lower metal layer BML, a buffer layer 11a, and a circuit array layer 11b.

[0410] The lower metal layer BML can be used as a pixel driving line disposed on the first surface 100a of the first substrate 100 along the second direction Y. For example, the lower metal layer BML can be formed on the first surface 100a of the first substrate 100, and then patterned by a patterning process into multiple data lines DL, multiple pixel driving power lines PL, multiple pixel common voltage lines CVL, multiple reference voltage lines RL, light-shielding pattern LSP, and gate control line group GCL.

[0411] A buffer layer 11a may be disposed on a first surface 100a of the first substrate 100 to cover the lower metal layer BML. The buffer layer 11a may include a first buffer layer BL1 covering the lower metal layer BML and a second buffer layer BL2 covering the first buffer layer BL1.

[0412] The circuit array layer 11b may include a pixel circuit PC, which includes a driving TFT Tdr in each of a plurality of pixel regions PA disposed above the buffer layer 11a.

[0413] The driving TFT Tdr disposed in each of the multiple pixel regions PA may include an active layer ACT, a gate insulating layer GI, a gate electrode GE, an interlayer insulating layer 11c, a first electrode (source / drain) SD1, a second electrode (drain / source) SD2, and a passivation layer 11d. Each of the first switching TFT Tsw1 and the second switching TFT Tsw2 constituting the pixel circuit PC may be formed together with the driving TFT Tdr, and therefore their detailed description may be omitted or simplified.

[0414] The source / drain metal layers that form the source / drain electrodes SD1 and SD2 can be used as pixel driving lines disposed along the first direction X. For example, the source / drain metal layers can be formed over the first surface 100a of the first substrate 100 and then patterned by a patterning process into gate lines GL, network lines of branch network 153 and multiple control nodes, multiple power sharing lines PSL, multiple line connection patterns LCP, and reference branch lines RDL.

[0415] The light-emitting device layer 13 can be disposed above the planarization layer 12 and can emit light towards the upper side of the first surface 100a of the first substrate 100 based on the top light-emitting pattern.

[0416] According to one embodiment, the light-emitting device layer 13 may include a pixel electrode PE, a light-emitting device ED, and a common electrode CE.

[0417] A pixel electrode PE can be disposed above a planarization layer 12 overlapping with the light-emitting region EA of each of the multiple pixel regions PA. The pixel electrode PE can be patterned and disposed in an island shape in each pixel region PA and can be electrically connected to the first electrode (source / drain) SD1 of the driving TFT Tdr of the corresponding pixel circuit PC. One side of the pixel electrode PE can extend to the first electrode (source / drain) SD1 of the driving TFT Tdr in the circuit region CA of the pixel region PA, and can be electrically connected to the first electrode (source / drain) SD1 of the driving TFT Tdr through an electrode contact hole ECH disposed in the planarization layer 12.

[0418] The metal layer (or pixel electrode layer) that realizes the pixel electrode PE can be used as the pads PVP, DP, RVP, DP, GP and CVP of the first pad portion 110. For example, the metal layer that realizes the pixel electrode PE can be formed above the first surface 100a of the first substrate 100, and then patterned into the pads PVP, DP, RVP, DP, GP and CVP of the first pad portion 110 by a patterning process.

[0419] The light-emitting device (ED) can be formed above and in direct contact with the pixel electrode (PE). The ED can be a common layer formed in each of multiple sub-pixels (SPs) without differentiation on a per-sub-pixel-SP basis. The ED can respond to current flowing between the pixel electrode (PE) and the common electrode (CE), thereby emitting white light (or blue light).

[0420] The common electrode CE can be formed above the light-emitting device ED and can directly contact the light-emitting device ED or can electrically contact the light-emitting device ED directly. The common electrode CE may include a transparent conductive material that transmits light emitted from the light-emitting device ED.

[0421] The dam 14 may be disposed above the planarization layer 12 to cover the edge portion of the pixel electrode PE. The dam 14 may define the light-emitting region EA (or opening portion) of the sub-pixel SP and electrically isolate the pixel electrodes PE disposed in adjacent sub-pixels SP. The dam 14 may be formed to cover the electrode contact hole ECH disposed in the sub-pixel SP. The dam 14 may be covered by the light-emitting device ED.

[0422] According to one embodiment, the first substrate 100 may further include a first margin area MA1, a second margin area MA2, and a weir pattern area DPA. For example, the first margin area MA1, the second margin area MA2, and the weir pattern area DPA may be a second area of ​​the first substrate 100 surrounding the first area.

[0423] The first margin region MA1 can be set between the light-emitting area EA of the outermost pixel Po and the weir pattern area DPA. Based on the shadow area (or tail) of the light-emitting device ED that inevitably occurs in the process of forming the light-emitting device ED, the first margin region MA1 can have a first width between the end of the light-emitting area EA (or dam 14) of the outermost pixel Po and the weir pattern area DPA.

[0424] A second margin region MA2 may be disposed between the outer surface OS of the first substrate 100 and the weir pattern region DPA. Based on the reliability margin of the light-emitting device ED in resisting moisture, the second margin region MA2 may have a second width between the outer surface OS of the first substrate 100 and the weir pattern region DPA. According to one embodiment, the second margin region MA2 may include a pad margin region overlapping with a first pad portion 110 disposed at a first edge portion in the first surface 100a of the first substrate 100.

[0425] The weir pattern region DPA can be set between the first margin region MA1 and the second margin region MA2. The weir pattern region DPA can have a third width corresponding to the width between the first margin region MA1 and the second margin region MA2.

[0426] The width of each of the first margin region MA1, the second margin region MA2, and the weir pattern region DPA can be implemented such that, relative to the first direction X, the second interval D2 between the center portion of the outermost pixel Po and the outer surface OS of the first substrate 100 is half or less than the first interval (or pixel pitch) D1 between two adjacent pixel regions PA.

[0427] Device isolation portion 15 may be disposed in each of the first margin region MA1 and the second margin region MA2 defined in the outermost pixel Po. According to one embodiment, device isolation portion 15 may include at least one device isolation pattern 15a disposed in the first margin region MA1 and at least one device isolation pattern 15b, 15c, and 15d disposed in the second margin region MA2. For example, according to one embodiment, device isolation portion 15 includes a first device isolation pattern 15a disposed in the first margin region MA1 and second to fourth device isolation patterns 15b, 15c, and 15d disposed in the second margin region MA2. In addition to being implemented in each of the first margin region MA1 and the second margin region MA2 defined in the outermost pixel Po, device isolation portion 15 and... Figures 1 to 14 The device isolation portions 15 shown are generally the same, so similar reference numerals refer to similar elements and their repeated descriptions are omitted or will be briefly given.

[0428] The weir pattern portion 17 can be configured in a closed-loop shape within the weir pattern region DPA between the first margin region MA1 and the second margin region MA2. The weir pattern portion 17 can be implemented with a first width separating the first margin region MA1 from the end of the light-emitting region EA relative to the first direction X. Furthermore, the weir pattern portion 17 can be implemented with a second width separating the second margin region MA2 from the outer surface OS of the first substrate 100 relative to the first direction X. The weir pattern portion 17 may include a structure (or structural element) to prevent the loss (or removal) of the metal pattern layer of the eaves structure during the formation (or fabrication) of the device isolation portion 15. Except for the weir pattern portion 17 being configured to be disposed within the outermost pixel Po along one edge portion of the first substrate 100, the weir pattern portion 17 can be... Figures 1 to 14 The weir pattern portion 17 shown is substantially the same, so similar reference numerals refer to similar elements and their repeated descriptions are omitted or will be briefly given.

[0429] An encapsulation layer 19 may be disposed over the portion of the first surface 100a of the first substrate 100, excluding the outermost edge portion, to cover the light-emitting device layer 13. For example, the encapsulation layer 19 may be implemented to surround the entire front and side surfaces of the light-emitting device layer 13. According to one embodiment, the encapsulation layer 19 may include first to third encapsulation layers 19a, 19b, and 19c. The first to third encapsulation layers 19a, 19b, and 19c may be... Figures 3 to 14 The first to third encapsulation layers 19a, 19b and 19c shown are substantially the same, so similar reference numerals refer to similar elements and their repeated descriptions are omitted or will be briefly given.

[0430] The wavelength conversion layer 21 can convert the wavelength of light incident from the light-emitting region EA of the sub-pixel SP. For example, the wavelength conversion layer 21 can convert white light (or blue light) incident from the light-emitting region EA into colored light corresponding to the corresponding sub-pixel SP. According to one embodiment, the wavelength conversion layer 21 may include a protective layer 21b and a plurality of wavelength conversion members 21a. The wavelength conversion layer 21 can be coupled with... Figures 3 to 14 The wavelength conversion layers 21 shown are substantially the same, so similar reference numerals refer to similar elements and their repeated descriptions will be omitted or briefly given.

[0431] The functional film 23 may be disposed above the wavelength conversion layer 21. For example, the functional film 23 may be bonded to the wavelength conversion layer 21 by a transparent adhesive member. According to one embodiment, the functional film 23 may further include at least one or more of the following: an anti-reflection layer (or anti-reflection film), a blocking layer (or blocking film), and an optical path control layer (or optical path control film) as described above.

[0432] The side sealing member 25 may be formed between the first substrate 100 and the functional film 23 and may cover all side (or lateral) surfaces of each of the circuit layer 11 and the wavelength conversion layer 21. For example, the side sealing member 25 may cover all side surfaces of each of the circuit layer 11 and the wavelength conversion layer 21 between the functional film 23 and the first substrate 100 that are exposed to the outside of the light-emitting display device. In addition, the side sealing member 25 may cover the first chamfer 100c formed (or provided) by a chamfering process at the corner between the first surface 100a and the outer surface OS of the first substrate 100. For example, each of the outermost outer surface of the first substrate 100, the outer surface of the side sealing member 25, and the outer surface of the functional film 23 may be positioned (or aligned) on the same vertical line VL.

[0433] Reference Figure 20 , Figure 24 and Figure 26 According to one embodiment, the second substrate 200 may include a metal pattern layer connected to the wiring portion 400 and an insulating layer that insulates the metal pattern layer.

[0434] The metal patterned layer (or conductive patterned layer) may include multiple metal layers. According to one embodiment, the metal patterned layer may include a first metal layer 201, a second metal layer 203, and a third metal layer 205. The insulating layer may include multiple insulating layers. For example, the insulating layer may include a first insulating layer 202, a second insulating layer 204, and a third insulating layer 206. The insulating layer may be referred to as a back insulating layer or a patterned insulating layer.

[0435] The first metal layer 201, the second metal layer 203, and the third metal layer 205 can be used as pads for the second pad portion 210, the third pad portion 230, and the interconnects for the interconnect portion 250 disposed on the rear surface 200b of the second substrate 200. For example, the first metal layer 201 can be used as some of the interconnects, and the third metal layer 205 can be used as pads and other interconnects. The second metal layer 203 can be used as a jumper wire (or bridging wire) to electrically connect interconnects disposed on different layers.

[0436] A first insulating layer 202 may be disposed above the rear surface 200b of the second substrate 200 to cover the first metal layer 201. A second insulating layer 204 may be disposed above the first insulating layer 202 to cover the second metal layer 203. A third insulating layer 206 may be disposed above the second insulating layer 204 to cover the third metal layer 205.

[0437] A bonding member 300 may be disposed between the first substrate 100 and the second substrate 200. Therefore, the first substrate 100 and the second substrate 200 can be bonded to each other via the bonding member 300. According to one embodiment, the bonding member 300 may be a transparent adhesive member comprising OCA or OCR, or a double-sided tape. According to another embodiment, the bonding member 300 may comprise fiberglass.

[0438] According to one embodiment, the bonding member 300 may be disposed in the entire space between the first substrate 100 and the second substrate 200. For example, the entire second surface 100b of the first substrate 100 may be bonded to the entire surface of the bonding member 300, and the entire front surface 200a of the second substrate 200 may be bonded to the entire other surface of the bonding member 300.

[0439] According to another embodiment, the bonding member 300 may be disposed in a patterned structure between the first substrate 100 and the second substrate 200. For example, the bonding member 300 may have a line pattern structure or a mesh pattern structure. The mesh pattern structure may further include a bending portion that discharges air bubbles that appear between the first substrate 100 and the second substrate 200 during the process of bonding the first substrate 100 to the second substrate 200 to the outside.

[0440] Figure 26 It is along Figure 19 The cross-sectional view shown by line IV-IV' is a diagram illustrating the cross-sectional structure of the first pad portion, the second pad portion, and the wiring portion of a light-emitting display device according to another embodiment of the present invention. In the description... Figure 26 At that time, and Figure 19 Elements that are identical or corresponding to each other are referred to by similar reference numerals, and their repeated descriptions are omitted or will be briefly given below.

[0441] Reference Figures 19 to 21 and Figure 26 In a light-emitting display device according to another embodiment of the present invention, the first pad portion 110 may include a plurality of pads PVP, DP, RVP, GP, and CVP disposed at a first edge portion in the first surface 100a of the first substrate 100. For example, each of the pads PVP, DP, RVP, GP, and CVP of the first pad portion 110 may be electrically connected to a corresponding line through a pad contact hole. For example, each of the plurality of pixel common voltage pads CVP disposed in the first pad portion 110 may be individually connected to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL through a pad contact hole.

[0442] In a light-emitting display device according to another embodiment of the present invention, the second pad portion 210 may include a plurality of second pads 211 disposed in the rear surface 200b of the second substrate 200 at a first edge portion overlapping with the first pad portion 110.

[0443] Each of the plurality of second pads 211 can be electrically connected to a corresponding wiring line through pad contact holes provided in the first insulating layer 202 and / or the second insulating layer 204 on the rear surface 200b of the second substrate 200. In addition, the plurality of second pads 211 can be individually connected to the pads PVP, DP, RVP, GP and CVP of the first pad section 110 through the wiring portion 400, respectively.

[0444] The wiring portion 400 may be configured to surround the outer surface OS of the first substrate 100 and the outer surface OS of the second substrate 200. For example, the wiring portion 400 may be disposed on each of the first outer surface (or a surface) OS1a of the outer surface OS of the first substrate 100 and the first outer surface (or a surface) OS1b of the outer surface OS of the second substrate 200.

[0445] According to one embodiment, the wiring portion 400 may include a plurality of wirings 411 disposed on each of a first outer surface (or a surface) OS1a disposed in the outer surface OS of the first substrate 100 and a first outer surface (or a surface) OS1b disposed in the outer surface OS of the second substrate 200.

[0446] Each of the plurality of wirings 411 may be formed around each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200. For example, each of the plurality of wirings 411 may be formed by a printing process using conductive paste. For example, the conductive paste may include Ag paste, but embodiments of the invention are not limited thereto.

[0447] In each of the multiple wirings 411, one end may surround each of the pads PVP, DP, RVP, GP and CVP of the first pad portion 110 provided at the first edge portion of the first substrate 100 and the first chamfer 100c, and the other end may surround the second pad 211 of the second pad portion 210 provided at the first edge portion of the second substrate 200 and the second chamfer 200c, and the central portion between this one end and the other end may surround each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200.

[0448] The wiring portion 400 according to an embodiment of the present invention may further include an edge coating 413.

[0449] The edge coating 413 can be implemented to cover multiple wirings 411. According to one embodiment, the edge coating 413 can be implemented to cover not only the multiple wirings 411, but also the first outer surface OS1a and first edge portion of the first substrate 100, and the first outer surface OS1b and first edge portion of the second substrate 200. The edge coating 413 can prevent corrosion of each of the multiple wirings 411, including metallic material, or electrical short circuits between the multiple wirings 411. Furthermore, the edge coating 413 can prevent, reduce, or minimize the reflection of external light caused by the multiple wirings 411 and the pads of the first pad portion 110. According to one embodiment, the edge coating 413 may include a light-shielding material containing black ink.

[0450] The top surface of the edge coating 413 covering the first chamfer 100c of the first substrate 100 may be covered by the side sealing member 25.

[0451] The outer surface of the edge coating 413 can be the outermost outer surface of the first substrate 100. Therefore, each of the outermost outer surface of the first substrate 100, the outer surface of the side sealing member 25, and the outer surface of the functional film 23 can be positioned (or aligned) on the same vertical line VL.

[0452] As mentioned above, with Figures 1 to 14 Similar to the light-emitting display device shown, the light-emitting display device according to another embodiment of the present invention can prevent, reduce or minimize the decrease in reliability of the light-emitting device ED caused by the loss or absence of the device isolation portion 15 due to lateral penetration of moisture or humidity, and may have an air frame structure or a frameless structure, wherein the display portion AA is surrounded by air rather than by an opaque non-display area.

[0453] Figure 27 This is an illustration of a multi-screen display device according to an embodiment of the present invention. Figure 28 It is along Figure 27 The cross-sectional view shown is taken by line V-V'. Figure 27 and Figure 28 The diagram illustrates the process of laying... Figures 15 to 26 The multi-screen display device shown is implemented according to another embodiment of the light-emitting display device of the present invention.

[0454] Reference Figure 27 and Figure 28 According to an embodiment of the present invention, a multi-screen display device (or a deployed display device) may include a plurality of display devices DM1 to DM4.

[0455] Multiple display devices DM1 to DM4 can each display a separate image or can display a single image in a segmented manner. Each of the multiple display devices DM1 to DM4 may include Figures 15 to 26 The light-emitting display device shown in this invention is therefore omitted or will be briefly described again.

[0456] Multiple display devices DM1 to DM4 can be laid on a separate tiling frame so that they are in contact with each other at their side surfaces. For example, multiple display devices DM1 to DM4 can be laid in an N×M configuration to realize a multi-screen display device with a large screen. For example, N is a positive integer of 1 or greater, and M is a positive integer of 2 or greater, but the embodiments of the present invention are not limited to this. For example, N is a positive integer of 2 or greater, and M is a positive integer of 1 or greater.

[0457] Each of the plurality of display devices DM1 to DM4 may not include a border area (or non-display area) surrounding the entire display area AA of the displayed image, but may instead have an air border structure in which the display area AA is surrounded by air. For example, in each of the plurality of display devices DM1 to DM4, the entire first surface of the first substrate 100 may be implemented as the display area AA.

[0458] According to an embodiment of the present invention, in each of the plurality of display devices DM1 to DM4, the second interval D2 between the central portion CP of the outermost pixel Po and the outermost outer surface VL of the first substrate 100 can be implemented as half or less of the first interval D1 (or pixel interval) between adjacent pixels. Therefore, in two adjacent display devices DM1 to DM4 that are joined (or in contact) with each other at their side surfaces based on a lateral bonding method along the first direction X and the second direction Y, the interval “D2+D2” between adjacent outermost pixel regions PAo can be equal to or less than the first interval D1 between the two adjacent pixels. (Refer to...) Figure 28In the first display device DM1 and the third display device DM3, which are joined (or in contact) with each other on their side surfaces along the second direction Y, the interval “D2+D2” between the center portion CP of the outermost pixel Po of the first display device DM1 and the center portion CP of the outermost pixel Po of the third display device DM3 can be equal to or less than the first interval D1 (or pixel interval) between two adjacent pixels in each of the first display device DM1 and the third display device DM3.

[0459] Therefore, the interval "D2+D2" between the central portions CP of the outermost pixels Po of two adjacent display devices DM1 to DM4 that are joined (or in contact) with each other at the side surfaces along the first direction X and the second direction Y can be equal to or less than the first interval D1 between two adjacent pixels in each of the display devices DM1 to DM4. Thus, there can be no seam or boundary portion between two adjacent display devices DM1 to DM4, thereby eliminating dark areas caused by boundary portions between display devices DM1 to DM4. As a result, the image displayed on a multi-screen display device with multiple display devices DM1, DM2, DM3, and DM4 arranged in an N×M form can be displayed continuously without any sense of interruption (or discontinuity) at the boundary portions between the multiple display devices DM1, DM2, DM3, and DM4.

[0460] exist Figure 27 and Figure 28 The diagram shows multiple display devices DM1 to DM4 arranged in a 2×2 configuration. However, embodiments of the present invention are not limited to this; the multiple display devices DM1 to DM4 can be arranged in an x×1 configuration, a 1×y configuration, or an x×y configuration. For example, x and y can be natural numbers 2 or greater that are equal to or different from each other. For example, x can be a natural number 2 or greater or equal to y, and y can be a natural number 2 or greater, or y can be greater than or less than x.

[0461] As described above, when the display area AA of each of the multiple display devices DM1 to DM4 is a screen and displays an image, the multi-screen display device according to the present invention can display an image continuously without interruption at the boundary portion between the multiple display devices DM1 to DM4, thereby enhancing the immersive experience of the viewer watching the image displayed by the multi-screen display device.

[0462] The light-emitting display device according to the present invention will be described below.

[0463] A light-emitting display device according to some embodiments of the present invention includes: a substrate; a light-emitting device layer including light-emitting devices disposed on the substrate; a weir pattern portion disposed on an edge portion of the substrate; an encapsulation layer disposed on the light-emitting device layer and including an organic material disposed in an inner region surrounded by the weir pattern portion; and a device isolation portion disposed on an edge portion of the substrate to isolate the light-emitting devices, the weir pattern portion including a discontinuous weir pattern disposed along the edge portion of the substrate.

[0464] According to some embodiments of the present invention, the weir pattern portion may further include a continuous weir pattern disposed on the discontinuous weir pattern to have a closed loop shape.

[0465] According to some embodiments of the present invention, the discontinuous weir pattern may include: a plurality of linear weir patterns spaced apart from each other along the edge portion of the substrate; and a plurality of pattern break portions disposed between the plurality of linear weir patterns, wherein the continuous weir pattern may fill each of the plurality of pattern break portions and be disposed on the plurality of linear weir patterns.

[0466] According to some embodiments of the present invention, the discontinuous weir pattern and the continuous weir pattern may comprise the same material.

[0467] According to some embodiments of the present invention, the discontinuous weir pattern and the continuous weir pattern may include different materials.

[0468] According to some embodiments of the present invention, a light-emitting display device may further include: a planarization layer disposed below the light-emitting device layer; and a wavelength conversion layer, the wavelength conversion layer including a wavelength conversion member disposed on the encapsulation layer, wherein the discontinuous weir pattern may include the same material as the planarization layer or the wavelength conversion member.

[0469] According to some embodiments of the present invention, a light-emitting display device may further include: a planarization layer disposed below the light-emitting device layer; a wavelength conversion layer including a wavelength conversion member disposed on the encapsulation layer; and a dam pattern disposed on the planarization layer to define a pixel region in the substrate, the discontinuous dam pattern comprising the same material as any one of the planarization layer, the wavelength conversion member, and the dam pattern.

[0470] According to some embodiments of the present invention, the weir pattern portion may further include an auxiliary weir pattern disposed on the continuous weir pattern to have a closed-loop shape, and the auxiliary weir pattern may include the same material as the flattening layer or the embankment.

[0471] According to some embodiments of the present invention, the weir pattern portion may further include: a metal weir pattern disposed on the discontinuous weir pattern; and a continuous weir pattern disposed on the metal weir pattern having a closed loop shape.

[0472] According to some embodiments of the present invention, the discontinuous weir pattern may include: a plurality of linear weir patterns spaced apart from each other along the edge portion of the substrate; and a plurality of pattern break portions disposed between the plurality of linear weir patterns, wherein the metal weir pattern may be disposed on the plurality of linear weir patterns, and the continuous weir pattern may fill each of the plurality of pattern break portions and be disposed on the metal weir pattern.

[0473] According to some embodiments of the present invention, the device isolation portion may include: a first device isolation pattern surrounded by the weir pattern portion; and a second device isolation pattern surrounding the weir pattern portion.

[0474] A light-emitting display device according to some embodiments of the present invention may include: a substrate; a device isolation portion including a first device isolation pattern and a second device isolation pattern disposed on an edge portion of the substrate to have an eaves structure; a light-emitting device layer disposed on the substrate; a weir pattern portion disposed between the first device isolation pattern and the second device isolation pattern; and an encapsulation layer including an organic material disposed on the light-emitting device layer and disposed in an inner region surrounded by the weir pattern portion, the light-emitting device layer including a light-emitting device including an isolation region isolated by the device isolation portion, and the weir pattern portion including: a first weir pattern including a plurality of linear weir patterns spaced apart from each other; and a second weir pattern filling between and disposed on the plurality of linear weir patterns.

[0475] According to some embodiments of the present invention, the first weir pattern and the second weir pattern may comprise the same material.

[0476] According to some embodiments of the present invention, a light-emitting display device may further include a planarization layer disposed below the light-emitting device layer, wherein the first weir pattern and the second weir pattern may include the same material as the planarization layer.

[0477] According to some embodiments of the present invention, the weir pattern portion may further include a metal weir pattern disposed between the first weir pattern and the second weir pattern, wherein the second weir pattern may fill between the plurality of linear weir patterns and be disposed on the metal weir pattern.

[0478] According to some embodiments of the present invention, a light-emitting display device may further include a passivation layer disposed on the substrate to support the weir pattern portion, each of the first device isolation pattern and the second device isolation pattern may include: a first isolation structure implemented by the passivation layer; a metal pattern layer disposed on the first isolation structure, the metal pattern layer being wider than the top surface of the first isolation structure; and a second isolation structure formed on the metal pattern layer.

[0479] According to some embodiments of the present invention, the lateral surface of the first isolation structure may be configured to have an undercut structure relative to the metal pattern layer, and the light-emitting device may be isolated by the undercut structure.

[0480] According to some embodiments of the present invention, the encapsulation layer may include: a first encapsulation layer disposed on the light-emitting device layer and the device isolation portion; a second encapsulation layer, the second encapsulation layer including an organic material disposed in an inner region surrounded by the weir pattern portion; and a third encapsulation layer surrounding the second encapsulation layer disposed inside the weir pattern portion and the first encapsulation layer disposed outside the weir pattern portion.

[0481] According to some embodiments of the present invention, the substrate may include a display area, the display area including a plurality of pixels having the light-emitting device, and the size of the display area may be the same as the size of the substrate.

[0482] The multi-screen display device according to the present invention will now be described.

[0483] A multi-screen display device according to some embodiments of the present invention may include: a plurality of display devices disposed along at least one of a first direction and a second direction intersecting the first direction, each of the plurality of display devices including a light-emitting display device, the light-emitting display device including: a substrate; a light-emitting device layer including light-emitting devices disposed on the substrate; a weir pattern portion disposed on an edge portion of the substrate; an encapsulation layer disposed on the light-emitting device layer and including an organic material disposed in an inner region surrounded by the weir pattern portion; and a device isolation portion disposed on an edge portion of the substrate to isolate the light-emitting devices, the weir pattern portion including a discontinuous weir pattern disposed along an edge portion of the substrate.

[0484] A multi-screen display device according to some embodiments of the present invention may include: a plurality of display devices disposed along at least one of a first direction and a second direction intersecting the first direction, each of the plurality of display devices including a light-emitting display device, the light-emitting display device including: a substrate; a device isolation portion including a first device isolation pattern and a second device isolation pattern disposed on an edge portion of the substrate to have an eaves structure; a light-emitting device layer disposed on the substrate; a weir pattern portion disposed between the first device isolation pattern and the second device isolation pattern; and an encapsulation layer including an organic material disposed on the light-emitting device layer and disposed in an inner region surrounded by the weir pattern portion, the light-emitting device layer including a light-emitting device including an isolation region isolated by the device isolation portion, and the weir pattern portion including: a first weir pattern including a plurality of linear weir patterns spaced apart from each other; and a second weir pattern filling between the plurality of linear weir patterns and disposed on the plurality of linear weir patterns.

[0485] According to some embodiments of the present invention, the substrate of each of the plurality of display devices may include a display area, the display area including a plurality of pixels having the light-emitting device, and the size of the display area may be the same as the size of the substrate.

[0486] According to some embodiments of the present invention, the device isolation portion of each of the plurality of display devices may include: a first device isolation pattern surrounded by the weir pattern portion; and a second device isolation pattern surrounding the weir pattern portion.

[0487] According to some embodiments of the present invention, each of the plurality of display devices may include a passivation layer disposed on the substrate to support the weir pattern portion, and each of the first device isolation pattern and the second device isolation pattern may include: a first isolation structure implemented by the passivation layer; a metal pattern layer disposed on the first isolation structure, the metal pattern layer being wider than the top surface of the first isolation structure; and a second isolation structure formed on the metal pattern layer.

[0488] According to some embodiments of the present invention, the lateral surface of the first isolation structure may be configured to have an undercut structure relative to the metal pattern layer, and the light-emitting device may be isolated by the undercut structure.

[0489] According to some embodiments of the present invention, the encapsulation layer of each of the plurality of display devices may include: a first encapsulation layer disposed on the light-emitting device layer and the device isolation portion; a second encapsulation layer comprising an organic material disposed in an inner region surrounded by the weir pattern portion; and a third encapsulation layer surrounding the second encapsulation layer disposed inside the weir pattern portion and the first encapsulation layer disposed outside the weir pattern portion.

[0490] The light-emitting display device according to the present invention can be applied to all electronic devices including light-emitting display panels. For example, the light-emitting display device according to the present invention can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop personal computers (PCs), laptops, notebook computers, workstations, navigation devices, car navigation devices, car display devices, automotive equipment, theater equipment, theater display devices, TVs, wallpaper display devices, signage devices, game consoles, laptops, monitors, cameras, portable video cameras, home appliances, etc.

[0491] The aforementioned features, structures, and effects of the present invention are included in at least one embodiment of the present invention, but are not limited to one embodiment. Furthermore, those skilled in the art can achieve the features, structures, and effects described in at least one embodiment of the present invention through combinations or modifications of other embodiments. Therefore, anything related to combinations and modifications should be interpreted as being within the scope of the present invention.

[0492] Various modifications and variations may be made to this invention without departing from the spirit or scope thereof, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover any modifications and variations falling within the scope of the appended claims and their equivalents.

Claims

1. A light-emitting display device, comprising: substrate; A light-emitting device layer, wherein the light-emitting device layer includes light-emitting devices disposed on the substrate; A weir pattern portion disposed at the edge portion of the substrate; An encapsulation layer disposed on the light-emitting device layer and comprising organic material disposed in an inner region surrounded by the weir pattern portion; and A device isolation portion is disposed at the edge of the substrate to surround the outermost pixel in the display area of ​​the substrate, thereby isolating the light-emitting device. The weir pattern portion includes: A discontinuous weir pattern, the discontinuous weir pattern being disposed along an edge portion of the substrate and configured to include a plurality of linear weir patterns spaced apart from each other to have gap spaces; and A continuous weir pattern is set on the discontinuous weir pattern. The continuous weir pattern includes multiple protruding patterns that extend into the gaps between the multiple linear weir patterns. The device isolation portion includes two or more device isolation patterns, each of the two or more device isolation patterns including: First isolation structure; and A metal pattern layer is disposed on the first isolation structure to have an eaves structure relative to the first isolation structure. The light-emitting device on the isolated portion of the device is separated from the eaves structure, and The discontinuous weir pattern is discontinuous along the direction surrounding the display area of ​​the substrate.

2. The light-emitting display device according to claim 1, wherein the continuous weir pattern is configured to have a closed-loop shape.

3. The light-emitting display device according to claim 2, The discontinuous weir pattern further includes: The multiple pattern breaks corresponding to the gap spaces between the multiple linear weir patterns, and Each of the plurality of protruding patterns fills each of the plurality of pattern break portions.

4. The light-emitting display device according to claim 1, wherein the discontinuous weir pattern and the continuous weir pattern comprise the same material.

5. The light-emitting display device according to claim 1, wherein the discontinuous weir pattern and the continuous weir pattern comprise different materials.

6. The light-emitting display device according to claim 1, further comprising: A planarization layer disposed below the light-emitting device layer; and A wavelength conversion layer, the wavelength conversion layer including wavelength conversion components disposed on the encapsulation layer. The discontinuous weir pattern therein comprises the same material as the planarization layer or the wavelength conversion member.

7. The light-emitting display device according to claim 2, further comprising: A planarization layer disposed below the light-emitting device layer; A wavelength conversion layer, the wavelength conversion layer including a wavelength conversion component disposed on the encapsulation layer; and A dam portion disposed on the planarization layer, the dam portion dividing the boundaries of pixel regions in the substrate. The discontinuous weir pattern comprises the same material as any one of the planarization layer, the wavelength conversion member, and the embankment.

8. The light-emitting display device according to claim 7, wherein: The weir pattern section also includes an auxiliary weir pattern disposed on the continuous weir pattern, having a closed-loop shape, and The auxiliary weir pattern comprises the same material as the flattening layer or the embankment.

9. The light-emitting display device according to claim 1, wherein the weir pattern portion further comprises: The metal weir pattern between the discontinuous weir pattern and the continuous weir pattern, and The continuous weir pattern is configured to have a closed-loop shape.

10. The light-emitting display device according to claim 9, The discontinuous weir pattern further includes: The multiple pattern breaks corresponding to the gap spaces between the multiple linear weir patterns. The metal weir pattern is disposed on the plurality of linear weir patterns, and Each of the plurality of protruding patterns fills each of the plurality of pattern break portions.

11. The light-emitting display device according to claim 1, wherein the two or more device isolation patterns comprise: A first device isolation pattern surrounded by the weir pattern portion; and A second device isolation pattern surrounding the weir pattern portion.

12. The light-emitting display device according to claim 1, further comprising a passivation layer disposed on the substrate to support the weir pattern portion, The first isolation structure is implemented by the passivation layer.

13. The light-emitting display device according to claim 1, wherein the metal pattern layer is wider than the top surface of the first isolation structure.

14. The light-emitting display device of claim 1, wherein each of the two or more device isolation patterns further comprises a second isolation structure formed on the metal pattern layer.

15. The light-emitting display device according to claim 1, The lateral surface of the first isolation structure is configured to have an undercut structure relative to the metal pattern layer, and The light-emitting device is isolated by the undercut structure.

16. The light-emitting display device according to any one of claims 1 to 15, wherein the encapsulation layer comprises: A first encapsulation layer disposed on the light-emitting device layer and the device isolation portion; A second encapsulation layer, the second encapsulation layer comprising an organic material disposed in an inner region surrounded by the weir pattern portion; and A third encapsulation layer surrounds the second encapsulation layer and is disposed inside the weir pattern portion, while the first encapsulation layer is disposed outside the weir pattern portion.

17. The light-emitting display device according to any one of claims 1 to 15, wherein: The display area includes a plurality of pixels having the light-emitting device. The weir pattern portion and the device isolation portion are configured to be disposed inside the outermost pixel located along the edge portion of the substrate, and The size of the display area is the same as the size of the substrate.

18. A multi-screen display device, comprising: A plurality of display devices arranged along at least one of a first direction and a second direction intersecting the first direction. Each of the plurality of display devices includes a light-emitting display device according to any one of claims 1 to 17.

19. The multi-screen display device according to claim 18, wherein: Each of the plurality of display devices has a substrate including a display area, the display area including a plurality of pixels having the light-emitting device, and The size of the display area is the same as the size of the substrate.

20. The multi-screen display device according to claim 18, wherein the encapsulation layer comprises: A first encapsulation layer disposed on the light-emitting device layer and the device isolation portion; A second encapsulation layer, the second encapsulation layer comprising an organic material disposed in an inner region surrounded by the weir pattern portion; and A third encapsulation layer surrounds a second encapsulation layer disposed inside the weir pattern portion and a first encapsulation layer disposed outside the weir pattern portion.

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