A bridgeless power factor correction converter

Abstract

The present invention relates to a bridgeless power factor correction converter, which includes a main circuit and a power factor correction control circuit; the main circuit includes an input side power grid, a first inductor, a first diode, a second diode, and a second inductor; the anode of the first diode is connected to the first end of the first switching tube, the second end of the first switching tube is connected to the first end of the sampling resistor, and the second end of the sampling resistor is connected to the second end of the second switching tube; the power factor correction control circuit is used to respectively obtain the voltage signal of the sampling resistor, the voltage difference between the L line and the N line of the input side power grid, and the voltage of the second filter capacitor; the power factor correction control circuit controls the first switching tube and the second switching tube to be turned on and off based on the obtained data, so that the input current of the input side power grid is proportional to the input voltage of the input side power grid and is expressed as a sine wave. The present application has the advantages of less sampling signals, simple circuit implementation, and low control difficulty.

Description

Technical Field

[0001] The present invention relates to the technical field of circuits, and in particular to a bridgeless power factor correction converter. Background Art

[0002] Power factor refers to the ratio of effective power to apparent power. It's a parameter used to measure the efficiency of electrical equipment. The power factor measures how effectively electricity is being used; a higher power factor indicates higher power utilization. Therefore, power factor adjustment can be used to improve the efficiency of electrical equipment, known as power factor correction.

[0003] Currently, the frequent and extensive use of power electronic devices has caused serious harmonic pollution to the power grid. Therefore, PFC (power factor correction) circuits must be introduced to reduce harmonic pollution in the power grid.

[0004] To improve conversion efficiency, bridgeless PFC circuits have been designed and are becoming a hot topic of research. Compared to traditional PFC circuits, bridgeless PFC circuits omit the front-end rectifier bridge, reducing the conduction losses of the diodes and improving conversion efficiency. Figure 1 This is a schematic diagram of a bridgeless PFC circuit. It features two switching transistors and two freewheeling diodes. By controlling the inductor current, the input current waveform of the bridgeless PFC circuit follows the input voltage waveform, achieving power factor correction. However, this solution is complex in sampling and controlling the input current, often requiring sampling multiple current signals, such as RS1, RS2, and RS3, and then obtaining the control current signal through superposition operations, making implementation complex.

[0005] Therefore, there is an urgent need for a bridgeless power factor correction converter with fewer sampling signals, simple circuit implementation, and low control difficulty. Summary of the Invention

[0006] The object of the present invention is to provide a bridgeless power factor correction converter in view of the above problems existing in the prior art.

[0007] In order to achieve the above-mentioned object of the invention, the present invention adopts the following technical solution: a bridgeless power factor correction converter includes a main circuit and a power factor correction control circuit;

[0008] The main circuit includes an L line of an input side power grid, a first inductor, a first diode, a second diode, a second inductor, and an N line of the input side power grid connected in sequence; a first filter capacitor is connected in parallel to the input side power grid; an anode of the second diode is connected to a first end of a second switching tube, a second end of the second switching tube is connected to a negative electrode of the second filter capacitor, and a positive electrode of the second filter capacitor is connected to a cathode of the second diode; an anode of the first diode is connected to a first end of the first switching tube, a second end of the first switching tube is connected to a first end of a sampling resistor, and a second end of the sampling resistor is connected to a second end of the second switching tube;

[0009] The power factor correction control circuit is used to respectively obtain the voltage signal of the sampling resistor, the voltage difference between the L line and the N line of the input side power grid, and the voltage of the second filter capacitor; the power factor correction control circuit controls the first switching tube and the second switching tube to be turned on and off based on the obtained data, so that the input current of the input side power grid is proportional to the input voltage of the input side power grid and appears as a sine wave.

[0010] Working Principle and Beneficial Effects: 1. Compared with the prior art that requires collecting current signals or voltage signals from multiple sampling resistors, the main circuit of the present application can realize that the sampling resistor only samples the circuit current waveform during the conduction period of the first switching tube and the second switching tube, and the sampling resistor only samples the inductor current waveform, that is, the current waveforms of the first inductor and the second inductor. The current waveforms of the first inductor and the second inductor are consistent. The power factor correction control circuit only needs to mainly collect the voltage signal of the sampling resistor to realize the power factor correction function;

[0011] 2. Compared with the existing technology, this application significantly reduces the number of sampling resistors, which can significantly simplify the main circuit, thereby reducing costs and reducing circuit losses. The existing technology needs to calculate the signals of multiple sampling resistors and perform superposition calculations and other methods, so it is more complicated and difficult to implement.

[0012] Furthermore, the power factor correction control circuit includes an operational amplifier, a multiplier connected to the output of the operational amplifier, an absolute value circuit connected to the output of the multiplier, a subtractor connected to the output of the absolute value circuit, a second comparator connected to the output of the subtractor, an OR gate connected to the output of the second comparator, and an RS trigger connected to the output of the OR gate; the other input of the OR gate is connected to the output of the first comparator, the positive electrode of the first comparator and the negative electrode of the second comparator are both connected to the first end of the sampling resistor, and the negative electrode of the first comparator is connected to the output of the absolute value circuit; the negative electrode of the operational amplifier inputs the voltage signal of the second filter capacitor; the other input of the multiplier inputs the voltage difference between the L line and the N line of the input side power grid; the positive electrode of the first comparator and the negative electrode of the second comparator both input the voltage of the sampling resistor; the S terminal of the RS trigger inputs the ZCD signal, and the G terminal of the RS trigger is respectively connected to the first switching tube and the second switching tube.

[0013] Furthermore, the negative electrode of the operational amplifier is connected to the second filter capacitor via a first resistor.

[0014] Furthermore, a first capacitor is connected between the negative electrode and the output end of the operational amplifier.

[0015] Furthermore, when the voltage of the L line of the input side power grid is greater than the voltage of the N line; if the first switch tube and the second switch tube are turned on, the current flows from the L line through the first inductor, the first switch tube, the sampling resistor, the second switch tube and the second inductor in sequence and returns to the N line; if the first switch tube and the second switch tube are turned off, the current flows from the L line through the first inductor, the first diode, the second filter capacitor, the body diode of the second switch tube and the second inductor in sequence and returns to the N line.

[0016] Furthermore, when the voltage of the L line of the input-side power grid is lower than the voltage of the N line; if the first switch tube and the second switch tube are turned on, the current flows from the N line through the second inductor, the second switch tube, the sampling resistor, the first switch tube and the first inductor in sequence and returns to the L line; if the first switch tube and the second switch tube are turned off, the current flows from the N line through the second inductor, the second diode, the second capacitor, the sampling resistor, the body diode of the first switch tube and the first inductor in sequence and returns to the L line.

[0017] Furthermore, the multiplier multiplies the output signal V Comp The voltage difference between the L line and the N line of the input side grid is V LN Multiplied output signal V m .

[0018] Furthermore, the absolute value circuit takes the absolute value of the signal Vm and outputs a signal Vp , the signal V p is the signal V m The absolute value of the subtractor outputs a signal Vk, which is V k =-V p .

[0019] Furthermore, when the sampling resistor voltage V cS1 Greater than signal V p When the first comparator outputs a high level; when the sampling resistor voltage V cS1 Less than signal V k When the sampling resistor voltage V cS1 Greater than signal V p When or sampling resistor voltage V cS1 Less than signal V k When the inductor current is intermittent, the S of the RS trigger is set high, and the G end of the RS trigger outputs a high level, driving the first switch tube and the second switch tube to turn on.

[0020] Furthermore, the operational amplifier adopts negative feedback control. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of a bridgeless PFC circuit in the prior art;

[0022] Figure 2 is a circuit diagram of the present invention;

[0023] Figure 3 1 is a schematic diagram of a power factor correction circuit of the present invention;

[0024] Figure 4 It is a circuit waveform diagram of the present invention. DETAILED DESCRIPTION

[0025] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention are within the scope of protection of the present invention.

[0026] Those skilled in the art should understand that, in the disclosure of the present invention, the terms "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like to indicate orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms cannot be understood as limiting the present invention.

[0027] The bridgeless power factor correction converter includes a main circuit and a power factor correction control circuit. The entire circuit is equivalent to a Boost circuit. The improvement of the main circuit over the prior art is that the number of sampling resistors is significantly reduced by simplifying the circuit. Figure 1 The figure shows a bridgeless PFC circuit in the prior art, which needs to collect current or voltage signals from three sampling resistors, RS1, RS2, and RS3. Therefore, the power factor correction circuit must undergo complex superposition operations to achieve the power factor correction function, which greatly increases the difficulty of implementation and circuit cost, and also has high losses.

[0028] The scheme of this application is shown in Figure 2 The circuit mainly includes the input side grid L (live) and N (neutral), the first filter capacitor CX1 and the second filter capacitor Co, the first inductor L1 and the second inductor L2, the first diode D1 and the second diode D2, the first switch S1 and the second switch S2, the sampling resistor RcS1 and the power factor correction control circuit. This circuit operates in variable frequency mode and is a critical continuous mode (CRM). For the specific connection relationship, please refer to Figure 2 The main circuit consists of the input power grid (L (hot) and N (neutral),) first and second filter capacitors CX1 and Co, first and second inductors L1 and L2, first and second diodes D1 and D2, first and second switching transistors S1 and S2, and sampling resistor RcS1.

[0029] Among them, when the first switch tube S1 and the second switch tube S2 are turned on, the input side grid voltage excites the first inductor L1 and the second inductor L2, and the current of the first inductor L1 and the second inductor L2 increases linearly. When the first switch tube S1 and the second switch tube S2 are turned off, the current is freewheeling through the first diode D1 and the body diode of the second switch tube S2 or through the second diode D2 and the body diode of the first switch tube S1, and the output voltage V O Subtract the input voltage V LNThe difference between the first and second inductors L1 and L2 demagnetizes the first and second inductors L1 and L2, and the currents of the first and second inductors L1 and L2 decrease linearly. When the difference is positive, the first and second inductors L1 and L2 are positively excited, while when the difference is negative, the first and second inductors L1 and L2 are reversely excited, that is, demagnetized.

[0030] Therefore, through the structure setting of the main circuit, when the grid voltage is in the positive half cycle, that is, V L >V N When the first switch tube S1 and the second switch tube S2 are turned on, the current flows from the L terminal through the first inductor L1, the first switch tube S1, the sampling resistor RcS1, the second switch tube S2, the second inductor L2 and returns to the N terminal; wherein, V L is the voltage of the input side grid L line, V N is the voltage of the N line of the input side grid. V LN is the input side grid voltage difference, that is, V LN =V L -V N , is the real-time voltage of the power grid.

[0031] If the first and second switches S1 and S2 are turned off, current flows from the L terminal through the first inductor L1, the first diode D1, the second filter capacitor Co, the body diode of the second switch S2, and the second inductor L2 back to the N terminal. Therefore, the sampling resistor RcS1 only samples the circuit current waveform during the period when the first and second switches S1 and S2 are on.

[0032] When the grid voltage is in the negative half cycle, that is, V N >V L When the first switch tube S1 and the second switch tube S2 are turned on, the current flows from the N terminal through the second inductor L2, the second switch tube S2, the sampling resistor RcS1, the first switch tube S1, the first inductor L1 and returns to the L terminal; if the first switch tube S1 and the second switch tube S2 are turned off, the current flows from the N terminal through the second inductor L2, the second diode D2, the second filter capacitor Co, the sampling resistor RcS1, the body diode of the first switch tube S1, and the first inductor L1 and returns to the L terminal. It can be seen that the sampling resistor RcS1 samples the inductor current waveforms of the first inductor L1 and the second inductor L2. The circuit waveform is as follows Figure 4 As shown, Figure 4 The left figure shows that when the grid voltage is in the positive half cycle (V L >V N ), the current flows in the forward direction, and the sampled V Rcs1 Signal and control signal V P The comparison determines the shutdown time; the right figure shows that when the grid voltage is in the negative half cycle (V L <V N ), the current flows in the negative direction, and the sampled VRcs1 Signal and control signal V K Comparison determines the turn-off time; among them, I LP It is the inductor current.

[0033] See also Figure 3 The power factor correction control circuit of the present application includes a first resistor R fb , first comparator Comp1, second comparator Comp2, operational amplifier Op1, first capacitor C fb , multiplier, subtractor, absolute value circuit, RS flip-flop RS1 and OR gate OR1.

[0034] The positive input of the operational amplifier Op1 in the figure is a preset reference voltage V ref , the negative electrode is connected to the first resistor R fb , the first resistor R fb Connect the second filter capacitor Co, so that the Vo signal of the second filter capacitor Co can be obtained. The output end of the operational amplifier Op1 is connected to the multiplier. The operational amplifier Op1 adopts negative feedback control to obtain stable output voltage control. When the output voltage V Comp Below the set value (reference voltage V ref ), the output V Comp Increase, thereby increasing V m Signal amplitude, increase V cS1 The comparison benchmark value increases the peak value of the inductor current and thus increases the output voltage. Conversely, when the output voltage V Comp When the output voltage is higher than the set value, V Comp Reduce, thereby reducing V m signal amplitude, reducing V cS1 The comparison benchmark value of V m is the output signal of the multiplier, V cS1 is the voltage signal of the acquisition resistor RcS1. Reference voltage V ref Set according to needs.

[0035] The output of the multiplier is connected to the absolute value circuit, and the other input of the multiplier is used to connect the L line and the N line respectively to obtain V LN , so the multiplier can convert V LN With V Comp Multiply to get signal V m , the signal Vm is input to the input end of the absolute value circuit, so Vm outputs the signal V through the absolute value circuit p Its value is V m The absolute value of the signal, V p =|V m |. The mathematical relationship is that when V m>=0, V p =V m When V m <0, V p =-Vm. Subtractor output signal V k =-V p .

[0036] The negative electrode of the subtractor is connected to the output end of the absolute value circuit, and the positive electrode of the second comparator Comp2 is connected to the output end of the subtractor.

[0037] The positive electrode of the first comparator Comp1 is connected to the first end of the sampling resistor RcS1 , and the negative electrode of the first comparator Comp1 is connected to the output end of the absolute value circuit.

[0038] The cathode of the second comparator Comp2 is connected to the first end of the acquisition resistor RcS1 , and the output end of the second comparator Comp2 is connected to the input end of the OR gate OR1 .

[0039] Specifically, the in-phase terminal of the first comparator Comp1 and the inverting terminal of the second comparator Comp2 are connected to the VcS1 signal. The inverting signal of the first comparator Comp1 comes from V p signal, the in-phase signal of the second comparator Comp2 comes from V k signal. Therefore, V m The calculation formula is:

[0040] .

[0041] The output end of the OR gate OR1 is connected to the R end of the RS flip-flop RS1, and the other input end of the OR gate OR1 is connected to the output end of the first comparator Comp1.

[0042] The S-terminal of RS flip-flop RS1 inputs the ZCD (Zero Current Detection) signal, and the G-terminal of RS flip-flop RS1 is connected to the third terminals of the first and second switching transistors S1 and S2, respectively. The ZCD signal input to the S-terminal of RS flip-flop RS1 indicates discontinuous inductor current and can come from either the inductor current sensing circuit or the auxiliary winding sensing circuit. There are many implementation methods, which are not detailed here. The control logic of RS flip-flop RS1 is that when the inductor current is discontinuous, the ZCD output is high, the S-terminal of RS flip-flop RS1 is set high, and the G-terminal of RS flip-flop RS1 outputs a high level, turning on the first and second switching transistors S1 and S2.

[0043] When V cS1 >V p When V cS1 <V kWhen V cS1 <V k or V cS1 >V p When , the OR gate circuit OR1 outputs a high level, the G terminal of the reset RS trigger RS1 outputs a low level, and the first switch tube S1 and the second switch tube S2 are turned off.

[0044] When V L >V N When V m >0,V p =V m , V k =-V m Because V cS1 is always greater than 0, so the second comparator Comp2 always outputs a low level, V cS1 The peak value is equal to V p , that is, V m ;

[0045] When V L <V N When V m <0,V p =-V m , V k =V m Because V cS1 is always less than 0, so the first comparator Comp1 always outputs a low level, V cS1 The peak value is equal to V k , that is, V m .

[0046] Therefore, V cS1 Peak V cS1_pk =Vm, derive the peak value of the inductor current I LP The relationship is:

[0047] ;

[0048] Because the input current is equal to the average inductor current I L1_avg , which is the peak value of the inductor current I LP half of the input current, then the input current is:

[0049] ; In the above formula, V rms Refers to the effective value of the input voltage, sin(x) represents the power grid as a sine wave.

[0050] It can be seen that the input current is proportional to the input voltage, and it tracks the input voltage and appears as a sine wave, thereby achieving good power factor correction control.

[0051] In summary, compared with the prior art, the present application actually only requires one sampling resistor RcS1 to sample the voltage signal V cS1 Because existing power factor correction control circuits also require input voltage differences and other data, as well as voltage or current signals from multiple sampling resistors, the power factor correction control circuit of this application achieves power factor correction. This circuit is simple to implement, requires fewer components, and has low loss.

[0052] The parts not described in detail in the present invention are prior art, so the present invention does not describe them in detail.

[0053] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the elements may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0054] Although this document uses a lot of professional terms, it does not exclude the possibility of using other terms. These terms are used only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional limitations is contrary to the spirit of the present invention.

[0055] The present invention is not limited to the above-mentioned optimal implementation mode. Anyone can derive other forms of products under the inspiration of the present invention. However, no matter what changes are made in the shape or structure, any technical solution that is the same or similar to that of the present application falls within the scope of protection of the present invention.

Claims

1. A bridgeless power factor correction converter, characterized in that: Including main circuit and power factor correction control circuit; The main circuit includes an L line of an input side power grid, a first inductor, a first diode, a second diode, a second inductor, and an N line of the input side power grid connected in sequence; a first filter capacitor is connected in parallel to the input side power grid; an anode of the second diode is connected to a first end of a second switching tube, a second end of the second switching tube is connected to a negative electrode of the second filter capacitor, and a positive electrode of the second filter capacitor is connected to a cathode of the second diode; an anode of the first diode is connected to a first end of the first switching tube, a second end of the first switching tube is connected to a first end of a sampling resistor, and a second end of the sampling resistor is connected to a second end of the second switching tube; The power factor correction control circuit is used to respectively obtain the voltage signal of the sampling resistor, the voltage difference between the L line and the N line of the input side power grid, and the voltage of the second filter capacitor; the power factor correction control circuit controls the first switch tube and the second switch tube to be turned on and off according to the obtained data, so that the input current of the input side power grid is proportional to the input voltage of the input side power grid and appears as a sine wave; The power factor correction control circuit includes an operational amplifier, a multiplier connected to the output of the operational amplifier, an absolute value circuit connected to the output of the multiplier, a subtractor having a negative terminal connected to the output of the absolute value circuit, a second comparator having a positive terminal connected to the output of the subtractor, an OR gate connected to the output of the second comparator, and an RS trigger having an R terminal connected to the output of the OR gate. The negative electrode of the operational amplifier is connected to the second filter capacitor through a first resistor, and the positive electrode inputs a reference voltage; the other input end of the OR gate is connected to the output end of the first comparator, the positive electrode of the first comparator and the negative electrode of the second comparator are both connected to the first end of the sampling resistor, and the negative electrode of the first comparator is connected to the output end of the absolute value circuit; the negative electrode of the operational amplifier inputs the voltage signal of the second filter capacitor; the other input end of the multiplier inputs the voltage difference between the L line and the N line of the input side power grid; the positive electrode of the subtractor is grounded; the positive electrode of the first comparator and the negative electrode of the second comparator are both inputted with the voltage of the sampling resistor; the S end of the RS trigger inputs the ZCD signal, and the G end of the RS trigger is respectively connected to the first switch tube and the second switch tube.

2. The bridgeless power factor correction converter according to claim 1, characterized in that: A first capacitor is connected between the negative electrode and the output end of the operational amplifier.

3. The bridgeless power factor correction converter according to claim 1, characterized in that: When the L line voltage of the input side power grid is greater than the N line voltage; if the first switch tube and the second switch tube are turned on, the current flows from the L line through the first inductor, the first switch tube, the sampling resistor, the second switch tube and the second inductor in sequence and returns to the N line; if the first switch tube and the second switch tube are turned off, the current flows from the L line through the first inductor, the first diode, the second filter capacitor, the body diode of the second switch tube and the second inductor in sequence and returns to the N line.

4. The bridgeless power factor correction converter according to claim 3, characterized in that: When the L line voltage of the input side power grid is lower than the N line voltage; if the first switch tube and the second switch tube are turned on, the current flows from the N line through the second inductor, the second switch tube, the sampling resistor, the first switch tube and the first inductor in sequence and returns to the L line; if the first switch tube and the second switch tube are turned off, the current flows from the N line through the second inductor, the second diode, the second capacitor, the sampling resistor, the body diode of the first switch tube and the first inductor in sequence and returns to the L line.

5. The bridgeless power factor correction converter according to claim 1, characterized in that: The multiplier converts the output signal V Comp The voltage difference between the L line and the N line of the input side grid is V LN Multiplied output signal V m .

6. The bridgeless power factor correction converter according to claim 5, characterized in that: The absolute value circuit takes the signal V m Take the absolute value and output signal V p , the signal V p is the signal V m The absolute value of the subtractor output signal V k , the signal V k =-V p .

7. The bridgeless power factor correction converter according to claim 6, characterized in that: When the sampling resistor voltage V cS1 Greater than signal V p When the first comparator outputs a high level; when the sampling resistor voltage V cS1 Less than signal V k When the sampling resistor voltage V cS1 Greater than signal V p When or sampling resistor voltage V cS1 Less than signal V k When the inductor current is intermittent, the S of the RS trigger is set high, and the G end of the RS trigger outputs a high level, driving the first switch tube and the second switch tube to turn on.

8. The bridgeless power factor correction converter according to claim 7, characterized in that: The operational amplifier adopts negative feedback control.

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