Calibration device and method

Abstract

A correction device includes a signal generator and a processor. The signal generator is configured to provide an input signal to a filter circuit having an actual time constant and configured to receive the input signal to output an output signal. The processor is configured to calculate an actual gain based on the output signal and the input signal, compare the actual gain with a target gain to obtain a comparison result, and determine whether to adjust the actual time constant of the filter circuit based on the comparison result. A correction method is also provided.

Description

Technical Field

[0001] The present invention relates to a correction device and method, and more particularly to a correction device and method suitable for filter circuits. Background Art

[0002] Generally speaking, filters are an indispensable component of wireless communication systems. However, due to process variations, the filter's frequency response is likely to deviate from the originally designed setting, thereby affecting the quality of signal demodulation.

[0003] To solve the above problem, a correction circuit is traditionally provided, which has the same time constant as the filter circuit to be corrected. By adjusting the capacitance value of the capacitor in the correction circuit, the time constant of the correction circuit reaches the target value. Finally, the capacitance setting corresponding to the target value is provided to the filter circuit to complete the correction. However, the above method can only compensate for the deviation of capacitance or resistance caused by process changes, and cannot further compensate for the deviation of other components (e.g., operational amplifier) ​​caused by process changes. Therefore, it is necessary to improve the traditional correction method. Summary of the Invention

[0004] In one aspect, the present invention provides a calibration device. The calibration device includes a signal generator and a processor. The signal generator is configured to provide an input signal to a filter circuit, wherein the filter circuit has an actual time constant, and is configured to receive the input signal and output an output signal. The processor is configured to calculate an actual gain based on the output signal and the input signal, compare the actual gain with a target gain to obtain a comparison result, and determine whether to adjust the actual time constant of the filter circuit based on the comparison result. The present invention also provides a calibration method.

[0005] Another aspect of the present application provides a calibration method. The calibration method includes: providing an input signal to a filter circuit, wherein the filter circuit has an actual time constant; receiving an output signal from the filter circuit; calculating an actual gain based on the output signal and the input signal; comparing the actual gain with a target gain to obtain a comparison result; and determining whether to adjust the actual time constant of the filter circuit based on the comparison result.

[0006] In summary, the calibration device and method of the present invention directly compare the filter circuit's actual gain with its target gain and adjust the filter circuit to compensate for variations in the filter circuit's components (e.g., resistors, capacitors, or operational amplifiers) due to process variations. This allows the filter circuit to be calibrated back to its original design settings, facilitating signal demodulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG1 is a block diagram illustrating a calibration device according to some embodiments of the present invention.

[0008] Figure 2A FIG2 is a diagram illustrating a frequency response of a filter circuit affected by process variations according to some embodiments of the present application.

[0009] Figure 2B FIG2 is a diagram illustrating a frequency response of a filter circuit affected by process variations after correction according to some embodiments of the present application.

[0010] Figure 3 FIG2 is a frequency response diagram illustrating another filter circuit affected by process variation according to some embodiments of the present application.

[0011] Figure 4 The figure shows a circuit diagram of a filter circuit according to some embodiments of the present invention.

[0012] Figure 5 The figure is a flow chart illustrating a calibration method according to some embodiments of the present invention.

[0013] Explanation of symbols

[0014] 10: Filter circuit

[0015] 100: Calibration device

[0016] 102: Signal Generator

[0017] 104: Processor

[0018] VIN: input signal

[0019] VOUT: output signal

[0020] gmr: actual gain

[0021] gm0: target gain

[0022] f1: actual center frequency

[0023] f0: default center frequency

[0024] A: Amplifier

[0025] R: resistance

[0026] C: Capacitor

[0027] I in+ : First input signal

[0028] I in- : Second input signal

[0029] Q in+ : The third input signal

[0030] Q in- : The fourth input signal

[0031] I out+ : First output signal

[0032] I out- : Second output signal

[0033] Q out+ : The third output signal

[0034] Q out- : The fourth output signal

[0035] S210, S220, S230, S240, S250, S260: Steps DETAILED DESCRIPTION

[0036] The following is a detailed description with examples and accompanying drawings. However, the specific embodiments described are only used to explain the present invention and are not used to limit the present invention. The description of the structural operation is not used to limit the order of their execution. Any structure recombined by the components to produce a device with equal functionality is within the scope of the present application.

[0037] Unless otherwise specified, the terms used in this disclosure and claims generally have the meaning commonly used in this field, as well as the common meanings in the disclosed content and the specific content.

[0038] In addition, the terms “coupled” or “connected” used herein may refer to two or more components making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more components operating or moving with each other.

[0039] See also Figure 1 One embodiment of the present invention relates to a calibration device 100. The calibration device 100 includes a signal generator 102 and a processor 104, and is used to calibrate a filter circuit 10 affected by process variations.

[0040] In this embodiment, the filter circuit 10 may be a bandpass filter and is designed to have a default center frequency f0 and a preset time constant τ0 corresponding to the default center frequency f0. However, due to process variations, the time constant of the filter circuit 10 may differ from the originally designed value, thereby causing the bandwidth and center frequency of the filter circuit 10 to also differ from the originally designed values. For example, the filter circuit 10 affected by process variations may have an actual time constant τ1 that differs from the preset time constant τ0 and an actual center frequency f1 that differs from the default center frequency f0.

[0041] Structurally, the signal generator 102 is coupled to the filter circuit 10, and the processor 104 is coupled to the signal generator 102 and the filter circuit 10. In this embodiment, the signal generator 102 may include a crystal oscillator (not shown) and a low-pass filter (not shown), and the processor 104 may be a central processing unit or a computer chip.

[0042] In order to better understand the present invention, the operation of the calibration device 100 will be discussed in the following paragraphs with reference to the accompanying drawings. Figure 1 As shown, the signal generator 102 provides an input signal V according to an instruction from the processor 104 (not shown). IN To the filter circuit 10, where the input signal V IN The frequency is equal to the default center frequency f0 originally designed for the filter circuit 10 .

[0043] The filter circuit 10 receives the input signal V IN , to output the output signal V OUT To the processor 104. The processor 104 receives the output signal V OUT , and according to the output signal V OUT With the input signal V IN Calculate the actual gain gm r Specifically, the processor 104 outputs a signal V OUT Divide by the input signal V IN To generate a ratio, and the absolute value of the ratio is used as the actual gain gm r .

[0044] In this embodiment, the filter circuit 10 has a target gain gm0 at the originally designed default center frequency f0. It can be understood that the target gain gm0 is the maximum gain value that the filter circuit 10 should have at the originally designed default center frequency f0. For example, the filter circuit 10 is designed to have a gain value of 1.5 (i.e., the target gain gm0) at 300MHz (i.e., the default center frequency f0). That is, when the input signal V INWhen the frequency is 300MHz, the ideal output signal V OUT The strength of the input signal at 300MHz should be V IN 1.5 times of.

[0045] However, the filter circuit 10 affected by the process variation has an actual center frequency f1 that is different from the default center frequency f0. In other words, the maximum gain value of the filter circuit 10 is changed to occur at the actual center frequency f1. At this time, if the input signal V IN Input to the filter circuit 10, the actual gain gm calculated by the processor 104 r The maximum gain value of the filter circuit 10 will not be the value originally designed. OUT The intensity at 300MHz will not reach the input signal V IN 1.5 times, in other words, the actual gain gm r Less than 1.5 (i.e., target gain gm0).

[0046] In actual gain gm r After the calculation, the processor 104 can be used to compare the actual gain gm r and the target gain gm0 to obtain the comparison result. In an ideal situation, the processor 104 compares the actual gain gm r The actual gain gm at the default center frequency f0 is obtained by comparing it with the target gain gm0. r However, if the filter circuit 10 is affected by process variations, the processor 104 compares the actual gain gm r With the target gain gm0, the actual gain gm at the default center frequency f0 will be obtained r The result is not equal to the target gain gm0.

[0047] Accordingly, the processor 104 may be further configured to determine whether to adjust the time constant of the filter circuit 10 according to the comparison result, so as to calibrate the frequency response of the filter circuit 10 to the originally designed value.

[0048] Specifically, see Figure 2A In this embodiment, the frequency response of the filter circuit 10 (indicated by the dotted line) is affected by process variations, so that the actual center frequency f1 is smaller than the default center frequency f0. Figure 2A As shown, the processor 104 compares the actual gain gm r and the target gain gm0, and get the actual gain gm rThe result is less than the target gain gm0. Taking the above practical application example, the actual center frequency f1 may be 100MHz which is less than 300MHz, and the actual gain gm r It can be 0.75 which is less than 1.5. When the actual gain gm r When the gain gm0 is less than the target gain gm0, the processor 104 may be used to adjust the capacitance value of at least one capacitor (not shown) in the filter circuit 10 (or the resistance value of at least one resistor (not shown) in the filter circuit 10) to adjust the actual time constant τ1 of the filter circuit 10, thereby changing the actual center frequency f1 and the actual gain gm0 of the filter circuit 10. r .

[0049] After several comparisons and adjustments, the actual gain gm r The actual center frequency f1 and the actual gain gm0 of the filter circuit 10 will be closer and closer. For example, the processor 104 can digitally adjust the capacitance value of the at least one capacitor from 64 farad to 32 farad, 16 farad, 8 farad and 4 farad in sequence. As the capacitance value of the at least one capacitor gradually decreases, the actual center frequency f1 and the actual gain gm0 of the filter circuit 10 will be closer and closer. r Taking the above practical application example as an example, as the capacitance value of the at least one capacitor gradually decreases, the actual center frequency f1 can gradually increase from 100MHz to 300MHz, and the actual gain gm at the default center frequency f0 is r It can be gradually increased from 0.75 to 1.5.

[0050] Next, see Figure 2B When the processor 104 compares the actual gain gm r and the target gain gm0, and get the actual gain gm r When the result is equal to the target gain gm0, the processor 104 no longer adjusts the actual time constant τ1 of the filter circuit 10. At this time, the actual time constant τ1 and the actual center frequency f1 of the calibrated filter circuit 10 are exactly equal to the preset time constant τ0 and the default center frequency f0 in the original design. Taking the above practical application example, after the filter circuit 10 is calibrated, the actual center frequency f1 can be 300MHz, and the actual gain gm0 at the default center frequency f0 is r It should be noted that the capacitance value of the at least one capacitor is the required setting value of the filter circuit 10 that is affected by process variations.

[0051] See also Figure 3 In other embodiments, the frequency response of the filter circuit 10 (shown by the dotted line) is affected by process variations, making the actual center frequency f1 greater than the default center frequency f0. In this case, the processor 104 compares the actual gain gmr Compared with the target gain gm0, the actual gain gm is still obtained r The result is less than the target gain gm0. Taking the above practical application example, the actual center frequency f1 may be 500MHz, which is greater than 300MHz, and the actual gain gm r Similarly, the processor 104 can digitally adjust the capacitance value of the at least one capacitor gradually (for example, starting from 4 farads and adjusting to 8 farads, 16 farads, 32 farads and 64 farads in sequence), so that the actual center frequency f1 of the filter circuit 10 gradually decreases, and the actual gain gm of the filter circuit 10 gradually decreases. r Taking the above practical application example as an example, as the capacitance value of the at least one capacitor gradually increases, the actual center frequency f1 can gradually decrease from 500MHz to 300MHz, and the actual gain gm at the default center frequency f0 is r It can be gradually increased from 0.75 to 1.5. Then, when the processor 104 obtains the actual gain gm r The result is equal to the target gain gm0 (such as Figure 2B As shown in FIG, the processor 104 no longer adjusts the actual time constant τ1 of the filter circuit 10. In this case, the capacitance value of the at least one capacitor is the required setting value of the filter circuit 10 affected by the process variation.

[0052] In some other embodiments, the processor 104 may adjust the capacitance of the at least one capacitor using a digital algorithm (eg, a binary search algorithm).

[0053] See also Figure 4 In other embodiments, the filter circuit 10 may be a complex bandpass filter (Complex Bandpass Filter) including a plurality of amplifiers A, a plurality of resistors R, and a plurality of capacitors C. Figure 4 The filter circuit 10 shown in FIG. 1 is configured such that the input signal V generated by the signal generator 102 is IN Including a first differential input signal (including a first input signal I in + and the second input signal I in - ) and the second differential input signal (including the third input signal Q in + and the fourth input signal Q in - ), wherein the phase of the first differential input signal is 90 degrees different from the phase of the second differential input signal. In addition, the output signal V output by the filter circuit 10 OUT Including a first differential output signal (including a first output signal I out+ and the second output signal I out - ) and the second differential output signal (including the third output signal Q out + and the fourth output signal Q out - ). Wherein, the calibration device 100 calibrates as follows Figure 4 The description of the filter circuit 10 is similar to that of the above-mentioned embodiment, so it will not be repeated here.

[0054] See also Figure 5 , which depicts a flow chart of a calibration method 200 according to one embodiment of the present invention. The calibration method 200 may be performed as follows: Figure 1 The calibration is performed on the illustrated apparatus 100 .

[0055] In step S210, an input signal V is provided. IN To the filter circuit 10 affected by the process, wherein the filter circuit 10 has an actual time constant τ1. In step S220, the output signal V from the filter circuit 10 is received. OUT In step S230, according to the input signal V IN With the output signal V OUT Calculate the actual gain gm r .

[0056] In steps S240 to S260, the actual gain gm is compared. r The actual time constant τ1 of the filter circuit 10 is adjusted based on the comparison result. Specifically, in step S240, the actual gain gm0 is compared with the target gain gm0 (i.e., the maximum gain value of the filter circuit 10 at the originally designed default center frequency f0). r If the comparison result shows "no", the process proceeds to step S250 to adjust the actual time constant τ1 of the filter circuit 10.

[0057] After adjusting the actual time constant τ1 of the filter circuit 10, the process returns to step S210 to provide the input signal V IN To the adjusted filter circuit 10, steps S220 to S240 are executed again. In short, as long as the actual gain gm is obtained in step S240, r If the result is not equal to the target gain gm0, the process proceeds to step S250 to adjust the actual time constant τ1 of the filter circuit 10 and execute steps S210 to S240 again.

[0058] If the comparison result of step S240 is “yes”, the process proceeds to step S260 , without adjusting the actual time constant τ1 of the filter circuit 10 (the actual time constant τ1 at this time is equal to the default time constant τ0 originally designed for the filter circuit 10 ), and the calibration method 200 ends.

[0059] In summary, the calibration device 100 and the calibration method 200 of the present invention directly compare the actual gain gm of the filter circuit 10 with the actual gain gm of the filter circuit 10. r The filter circuit 10 is adjusted based on the target gain gm0 to compensate for variations in various components (e.g., resistors, capacitors, or operational amplifiers) within the filter circuit 10 due to process variations. In this way, the filter circuit 10 can be calibrated back to its originally designed settings (i.e., the default center frequency f0, the default time constant τ0, and the target gain gm0) to facilitate signal demodulation.

[0060] Although the content of the present invention application has been disclosed as above through specific implementation methods, these multiple embodiments are not intended to limit the content of the present invention application. Ordinary technicians in this field may modify or adjust the technical solution of the present invention application based on the explicit or implicit content of the present invention application without departing from the concept and scope of the content of the present invention application. All these changes may fall within the scope of patent protection sought by the present invention application. In other words, the scope of protection of the content of the present invention application should be based on the scope defined by the claims.

Claims

1. A calibration device, characterized in that: The correction device comprises: a signal generator for providing an input signal to a filter circuit, wherein the filter circuit has a practical time constant and is configured to receive the input signal and output an output signal; and a processor configured to calculate an actual gain based on a ratio of a voltage value of the output signal to a voltage value of the input signal, compare the actual gain with a target gain to obtain a comparison result, and determine whether to adjust the actual time constant of the filter circuit based on the comparison result; The processor is a central processing unit.

2. The calibration device according to claim 1, wherein: When the comparison result shows that the actual gain is not equal to the target gain, the processor adjusts the actual time constant of the filter circuit to adjust the actual gain.

3. The calibration device according to claim 2, wherein: The processor adjusts the capacitance value of at least one capacitor in the filter circuit or the resistance value of at least one resistor in the filter circuit through a digital algorithm to adjust the actual time constant of the filter circuit.

4. The calibration device according to claim 1, wherein: When the comparison result shows that the actual gain is equal to the target gain, the processor does not adjust the actual time constant of the filter circuit.

5. The calibration device according to claim 4, characterized in that The filter circuit is designed to have a preset time constant and a default center frequency, and has the target gain at the default center frequency; When the comparison result shows that the actual gain is equal to the target gain, the actual time constant of the filter circuit is equal to the preset time constant, and the frequency of the input signal is equal to the default center frequency of the filter circuit.

6. A calibration method, characterized in that: The correction method comprises: providing an input signal to a filter circuit, wherein the filter circuit has a practical time constant; A processor receives an output signal from the filter circuit; The processor calculates an actual gain according to a ratio of a voltage value of the output signal to a voltage value of the input signal; The processor compares the actual gain and the target gain to obtain a comparison result; and The processor determines whether to adjust the actual time constant of the filter circuit according to the comparison result; The processor is a central processing unit.

7. The calibration method according to claim 6, wherein: Determining whether to adjust the actual time constant of the filter circuit according to the comparison result includes: When the comparison result shows that the actual gain is not equal to the target gain, the actual time constant of the filter circuit is adjusted to adjust the actual gain.

8. The calibration method according to claim 7, wherein: Adjusting the actual time constant of the filter circuit includes: The capacitance value of at least one capacitor in the filter circuit or the resistance value of at least one resistor in the filter circuit is adjusted by a digital algorithm.

9. The calibration method according to claim 6, wherein: Determining whether to adjust the actual time constant of the filter circuit according to the comparison result includes: When the comparison result shows that the actual gain is equal to the target gain, the actual time constant of the filter circuit is not adjusted.

10. The calibration method according to claim 9, wherein: The filter circuit is designed to have a preset time constant and a default center frequency, and has the target gain at the default center frequency; When the comparison result shows that the actual gain is equal to the target gain, the actual time constant of the filter circuit is equal to the preset time constant, and the frequency of the input signal is equal to the default center frequency of the filter circuit.

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