Semiconductor device, logic system thereof and operating method

Abstract

Embodiments of the present invention provide a semiconductor device, a logic system thereof, and a method of operating the semiconductor device. The semiconductor device includes a first latch circuit and a second latch circuit connected to the first latch circuit. The second latch circuit includes a first feedback circuit configured to receive a first clock signal of a first phase and a second clock signal of a second phase, and a first transmission circuit configured to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present invention generally relate to the field of semiconductor, and more particularly, to a semiconductor device and its logic system and method of operation. BACKGROUND

[0002] The present disclosure generally relates to a semiconductor device and its method of operation.

[0003] A flip-flop is a device that can store a single bit of data, where one of two states represents a "1" and the other represents a "0". This data storage can be used for state storage, and such a circuit can be described as a sequential logic in electronics. D-type flip-flops are widely used as a basic building block for random access memory (RAM) and registers. A D-type flip-flop captures the D input value at a specified edge of a clock, i.e., either rising or falling. The captured value is available at the Q output after the clock rising / falling edge. In some approaches, flip-flop circuits are limited in terms of minimum operating voltage and energy dissipation during operation. If operated at a voltage lower than its minimum operating voltage, data can not be correctly stored in the flip-flop. SUMMARY

[0004] One aspect of the present invention provides a semiconductor device, comprising: a first latch circuit; and a second latch circuit connected to the first latch circuit and having a first feedback circuit and a first transmission circuit, wherein the first feedback circuit is configured to receive a first clock signal having a first phase and a second clock signal having a second phase, the first transmission circuit is configured to receive the second clock signal and a third clock signal having a third phase, and the first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

[0005] Another aspect of the present invention provides a logic system, comprising: N flip-flop devices, wherein a first flip-flop device of the N flip-flop devices comprises: a first latch circuit having a first feedback circuit and a first transmission circuit; and a second latch circuit having a second feedback circuit and a second transmission circuit, wherein the first feedback circuit is configured to receive a first clock signal having a first phase and a second clock signal having a second phase, and the second feedback circuit is configured to receive the second clock signal and a third clock signal having a third phase.

[0006] Yet another aspect of the present disclosure provides a method of operating a semiconductor device, comprising: providing a first clock signal and a second clock signal to a first feedback circuit of a first latch circuit; providing the second clock signal and a third clock signal to a first transmission circuit of the first latch circuit; providing the second clock signal and the third clock signal to a second feedback circuit of a second latch circuit; and providing the second clock signal and the third clock signal to a second transmission circuit of the second latch circuit. BRIEF DESCRIPTION OF DRAWINGS

[0007] Various aspects of the present disclosure can be best understood with reference to the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various concepts presented herein are not necessarily meant to be implemented or realized in the described order. In fact, various concepts can be implemented or realized in any order or in parallel. It should also be noted that, in accordance with standard practice, the various components are not drawn to scale. In fact, the dimensions of the various features can be arbitrarily increased or decreased for the sake of discussion.

[0008] Figure 1A is a schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure.

[0009] Figure 1A is a schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure.

[0010] Figure 1A is a schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure.

[0011] Figure 1A shows waveforms of clock signals in accordance with some embodiments of the present disclosure.

[0012] Figure 1A shows waveforms of clock signals in accordance with some embodiments of the present disclosure.

[0013] Figure 2A is a schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure.

[0014] Figure 2A is a schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure.

[0015] Figure 2A is a schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure.

[0016] Figure 3A is a schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure.

[0017] Figure 3A is a schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure.

[0018] Figure 3A is a schematic diagram of a semiconductor device in accordance with some embodiments of the present disclosure.

[0019] Figure 4A is a schematic diagram of a semiconductor device according to some embodiments of the disclosure.

[0020] Figure 4A is a schematic diagram of a semiconductor device according to some embodiments of the disclosure.

[0021] Figure 5 is a flowchart including operations for operating a semiconductor device according to some embodiments of the disclosure. DETAILED DESCRIPTION

[0022] The present application provides many different embodiments, or examples, for implementing different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present application. These are, of course, merely examples and are not intended to limit the application in any way. For example, the arrangements described can be implemented in any of an order different from the specific arrangements described herein, or using other arrangements, components or configurations. Additionally, the described features can be implemented in any of a number of different embodiments, or examples, of the application. For simplicity, a few embodiments are fully described below. Additional embodiments include any combination of the features described but are not limited to the combinations explicitly described. Further, the described embodiments are not limited to the specific arrangements described, but can be practiced with other arrangements, components, and configurations.

[0023] Also, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or component's or portion's relationship to another element, component or portion as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0024] As used herein, although terms such as "first", "second" and "third" describe various elements, components, regions, layers and / or portions, these elements, components, regions, layers and / or portions should not be limited by these clauses. These terms are only used to distinguish one element, component, region, layer or portion from another. Unless the context clearly indicates otherwise, the terms such as "first", "second" and "third" used herein do not imply order or sequence.

[0025] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, as used herein, the terms "substantially", "about", and "approximately" generally mean values within 10% of the value being discussed, or within 5% of the value being discussed, or within 1% of the value being discussed. Alternatively, the terms "substantially", "about", and "approximately" mean within an acceptable standard error of the mean when considered by one of ordinary skill in the art. Those of ordinary skill in the art will appreciate that the acceptable standard error of the mean will vary with different technologies. Unless otherwise indicated, all numerical ranges, quantities, values and percentages, such as those disclosing amounts of materials, time durations, temperatures, operating conditions, ratios of quantities, etc., disclosed herein are to be understood as being modified in all instances by the term "substantially", "about", or "approximately". Thus, unless it is otherwise indicated, the numerical parameters set forth in the specification and attached claims are approximations. At the very least, each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one endpoint to the other endpoint or between two endpoints. Unless otherwise indicated, all ranges disclosed herein are inclusive of the endpoints.

[0026] The technology disclosed in the present disclosure provides a variety of solutions that result in a flip-flop having fewer clock transistors, shorter circuit propagation delay, improved minimum operating voltage, and lower power consumption than flip-flops configured based on other methods.

[0027] Figure 1A A schematic diagram of a semiconductor device is shown in accordance with some embodiments of the present disclosure.

[0028] Figure 1A A device 100 is shown. The device 100 can be an electronic device. The device 100 can be a semiconductor device. The device 100 can be an integrated circuit (IC) system. The device 100 can be a flip-flop. The device 100 includes a multiplexing device 10, a master stage 100m, a slave stage 100s, and an output device 17. The multiplexing device 10 includes inputs for receiving signals SE, SI, and D. The master stage 100m can also be referred to as a latch circuit. The slave stage 100s can also be referred to as a latch circuit.

[0029] The multiplexing device 10 is configured to select between the signal SI and the signal D based on the signal SE. In some embodiments, the multiplexing device 10 is configured to select the signal SI if the signal SE has a logic high value (e.g., "1") and to select the signal D if the signal SE has a logic low value (e.g., "0").

[0030] The master stage 100m includes a transmission circuit 11, a phase shifting circuit 12, and a feedback circuit 13. The transmission circuit 11 is electrically connected to the phase shifting circuit 12 and the feedback circuit 13. The transmission circuit 11 is electrically connected to the phase shifting circuit 12 and the feedback circuit 13. An output terminal of the phase shifting circuit 12 is electrically connected to an input terminal of the feedback circuit 13. An output terminal of the feedback circuit 13 is electrically connected to an input terminal of the phase shifting circuit 12.

[0031] In the present disclosure, the term "electrically connected to" and the term "connected to" can refer to the same meaning and can be used interchangeably.

[0032] The transmission circuit 11 includes two input terminals for receiving clock signals Phase_1 and Phase_2. The feedback circuit 13 includes two input terminals for receiving clock signals Phase_1 and Phase_2. In some embodiments, the feedback circuit 13 is configured to be turned off by the clock signals Phase_1 and Phase_2 before the transmission circuit 11 is turned on, so that the signals received by the master stage 100m can be properly transmitted to the slave stage 100s.

[0033] If the feedback circuit 13 remains on at the same time when the transmission circuit 11 is turned on, the signals transmitted by the master stage 100m to the slave stage 100s can be adversely affected, and as a result, the device 100 can not function as expected. It is expected that the feedback circuit 13 is completely turned off when the transmission circuit 11 is turned on so as not to affect the operation of the device 100.

[0034] The slave stage 100s includes a transmission circuit 14, a phase shifting circuit 15, and a feedback circuit 16. The transmission circuit 14 is electrically connected to the phase shifting circuit 15 and the feedback circuit 16. An output terminal of the phase shifting circuit 15 is electrically connected to an input terminal of the feedback circuit 16. An output terminal of the feedback circuit 16 is electrically connected to an input terminal of the phase shifting circuit 15.

[0035] The transmission circuit 14 includes two input terminals for receiving clock signals Phase_1 and Phase_2. The feedback circuit 16 includes two input terminals for receiving clock signals Phase_0 and Phase_1. In some embodiments, the feedback circuit 16 is configured to be turned off by the clock signals Phase_0 and Phase_1 before the transmission circuit 14 is turned on by the clock signals Phase_1 and Phase_2, so that the signals received by the slave stage 100s can be properly transmitted to the output device 17.

[0036] If the feedback circuit 16 is turned on at the same time when the transmission circuit 14 is also turned on, the signals transmitted by the slave stage 100s to the output device 17 can be adversely affected, and as a result, the device 100 can not function as expected. It is expected that the feedback circuit 16 is completely turned off when the transmission circuit 14 is turned on so as not to affect the operation of the device 100. This can be achieved by the feedback circuit 16 being electrically connected to the transmission circuit 14, as shown in FIG. 1. Figure 1AThe configuration shown is implemented in which the feedback circuit 16 is controlled by a signal (e.g., Phase_0 and Phase_1) that is ahead in timing of the signal used to control the transmission circuit 14 (e.g., Phase_1 and Phase_2).

[0037] Reference Figure 1A The device 100 may further include phase shifting circuits 18a and 18b. Phase shifting circuit 18a is configured to receive clock signal Phase_0 and then provide clock signal Phase_1. Phase shifting circuit 18b is configured to receive clock signal Phase_1 and then provide clock signal Phase_2. A phase shift exists between clock signals Phase_1 and Phase_0. A phase shift exists between clock signals Phase_2 and Phase_1. In some embodiments, phase shifting circuit 18a is an inverter. In some embodiments, phase shifting circuit 18b is an inverter.

[0038] The transmission circuit 11 of the master stage 100m and the transmission circuit 14 of the slave stage 100s are controlled by the same clock signals (i.e., Phase_1 and Phase_2). The feedback circuit 13 of the master stage 100m and the feedback circuit 16 of the slave stage 100s are controlled by different clock signals. That is, although the clock signal Phase_1 is fed into both feedback circuits 13 and 16, the clock signal Phase_0 is used only to control the feedback circuit 16, while the clock signal Phase_2 is used only to control the feedback circuit 13.

[0039] By controlling the feedback circuit 16 with an appropriate clock signal, signal interference / jitter between the master stage 100m and the slave stage 100s can be prevented. Signal interference / jitter between the master stage 100m and the slave stage 100s can also be prevented by turning off the feedback circuit 16 before the transmission circuit 14 is turned on. As a result, compared to other methods, device 100 improves Vmin by approximately 25mV to 50mV. That is, device 100 can operate normally at lower voltages. The reduced Vmin allows device 100 to be widely used in common semiconductor systems.

[0040] Figure 1B A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0041] Figure 1B Device 100P is shown. Device 100P can be an electronic device. Device 100P can be a semiconductor device. Device 100P can be an integrated circuit (IC) system. Device 100P can be a flip-flop. Device 100P can be a rising-edge triggered flip-flop. Device 100P can be an embodiment corresponding to device 100.

[0042] Device 100P includes a multiplexer 10P, a master stage 100Pm, a slave stage 100Ps, and an output device 17P. The multiplexer 10P includes input terminals for receiving signals SE, SEN, SI, and D. The master stage 100Pm can also be called a latch circuit. The slave stage 100Ps can also be called a latch circuit.

[0043] The multiplexer 10P is configured to select between signal SI and signal D based on signals SE and SEN. In some embodiments, the multiplexer 10P is configured to select signal SI if signal SE has a logic high value (e.g., "1") and signal SEN has a logic low value (e.g., "0"), and select signal D if signal SE has a logic low value and signal SEN has a logic high value.

[0044] Device 100P may further include phase shift circuits 18Pa, 18Pb, and 18Pc. Phase shift circuit 18Pa is configured to receive clock signal CP and then provide clock signal clk1. Phase shift circuit 18Pb is configured to receive clock signal clk1 and then provide clock signal clk2. A phase shift exists between clock signals clk1 and CP. A phase shift exists between clock signals clk2 and clk1. In some embodiments, phase shift circuit 18Pa is an inverter. In some embodiments, phase shift circuit 18Pb is an inverter.

[0045] The phase shift circuit 18Pc is configured to receive the signal SE and then provide the signal SEN. A phase shift exists between signals SE and SEN. In some embodiments, the phase shift circuit 18Pc is an inverter. In some embodiments, the signal SEN corresponds to the inversion of the signal SE.

[0046] The main stage 100Pm includes a transmission circuit 11P, a phase-shifting circuit 12P, and a feedback circuit 13P. The transmission circuit 11P is electrically connected to the phase-shifting circuit 12P and the feedback circuit 13P. The output of the phase-shifting circuit 12P is electrically connected to the input of the feedback circuit 13P. The output of the feedback circuit 13P is electrically connected to the input of the phase-shifting circuit 12P.

[0047] The transmission circuit 11P includes two input terminals for receiving clock signals clk1 and clk2. The feedback circuit 13P includes two input terminals for receiving clock signals clk1 and clk2. In some embodiments, the feedback circuit 13P is configured to be turned off by clock signals clk1 and clk2 before the transmission circuit 11P is turned on, so that the signals received by the master stage 100Pm can be correctly transmitted to the slave stage 100Ps.

[0048] If the feedback circuit 13P remains on while the transmission circuit 11P is on, the signal transmitted from the master stage 100Pm to the slave stage 100Ps may be adversely affected, resulting in the device 100P potentially failing to operate as expected. When the transmission circuit 11P is on, it is expected that the feedback circuit 13P will be completely off to avoid affecting the operation of the device 100P.

[0049] The slave stage 100Ps includes a transmission circuit 14P, a phase shifting circuit 15P, and a feedback circuit 16P. The transmission circuit 14P is electrically connected to the phase shifting circuit 15P and the feedback circuit 16P. The output terminal of the phase shifting circuit 15P is electrically connected to the input terminal of the feedback circuit 16P. The output terminal of the feedback circuit 16P is electrically connected to the input terminal of the phase shifting circuit 15P.

[0050] The transmission circuit 14P includes two inputs for receiving clock signals clk1 and clk2. The feedback circuit 16P includes two inputs for receiving clock signals CP and clk1. In some embodiments, the feedback circuit 16P is configured to be turned off by clock signals CP and clk1 before the transmission circuit 14P is turned on by clock signals clk1 and clk2, so that the signal received from stage 100Ps can be correctly transmitted to the output device 17P.

[0051] If the feedback circuit 16P remains on while the transmission circuit 14P is on, the signal transmitted from stage 100Ps to output device 17P may be adversely affected, resulting in device 100P potentially failing to operate as expected. When the transmission circuit 14P is on, it is expected that the feedback circuit 16P will be completely off to avoid affecting the operation of device 100P. This can be achieved through... Figure 1B The configuration shown is implemented in which the feedback circuit 16P is controlled by a signal (e.g., CP and clk1) that is ahead in timing of the signals (e.g., clk1 and clk2) used to control the transmission circuit 14P.

[0052] By controlling the feedback circuit 16P with a suitable clock signal, signal interference / jitter between the master stage 100Pm and the slave stage 100Ps can be prevented. Signal interference / jitter between the master stage 100Pm and the slave stage 100Ps can also be prevented by turning off the feedback circuit 16P before the transmission circuit 14P is turned on. Therefore, compared to other methods, device 100P improves Vmin by approximately 25mV to 50mV. That is, device 100P can operate normally at lower voltages. The reduced Vmin allows device 100P to be widely used in common semiconductor systems.

[0053] Figure 1C A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0054] Figure 1CDevice 100N is shown. Device 100N can be an electronic device. Device 100N can be a semiconductor device. Device 100N can be an integrated circuit (IC) system. Device 100N can be a flip-flop. Device 100N can be a falling-edge triggered flip-flop. Device 100N can be an embodiment corresponding to device 100.

[0055] Device 100N includes multiplexer 10N, master stage 100Nm, slave stage 100Ns, and output device 17N. Multiplexer 10N corresponds to the above-mentioned... Figure 1B The multiplexing device discussed is a 10P. The master stage (100nm) can also be called a latch circuit. The slave stage (100nm) can also be called a latch circuit.

[0056] Device 100N may further include phase shift circuits 18Na, 18Nb, and 18Nc. Phase shift circuit 18Na is configured to receive clock signal CPN and then provide clock signal clk1. Phase shift circuit 18Nb is configured to receive clock signal clk1 and then provide clock signal clk2. A phase shift exists between clock signal clk1 and CPN. A phase shift exists between clock signal clk2 and clk1. In some embodiments, phase shift circuit 18Na is an inverter. In some embodiments, phase shift circuit 18Nb is an inverter.

[0057] Figure 1C The clock signal CPN shown can correspond to Figure 1B The clock signal CP shown is inverted. 1B. Figure 1C The clock signal CPN shown is Figure 1B There may be a phase shift between the clock signals CP shown.

[0058] In some embodiments, the phase shift circuit 18Nc is configured to receive the signal SE and then provide the signal SEN. A phase shift exists between signals SE and SEN. In some embodiments, the phase shift circuit 18Nc is an inverter. In some embodiments, the signal SEN corresponds to the inversion of the signal SE.

[0059] The main stage 100Nm includes a transmission circuit 11N, a phase-shifting circuit 12N, and a feedback circuit 13N. The transmission circuit 11N is electrically connected to the phase-shifting circuit 12N and the feedback circuit 13N. The output of the phase-shifting circuit 12N is electrically connected to the input of the feedback circuit 13N. The output of the feedback circuit 13N is electrically connected to the input of the phase-shifting circuit 12N.

[0060] The transmission circuit 11N includes two inputs for receiving clock signals clk1 and clk2. The feedback circuit 13N includes two inputs for receiving clock signals clk1 and clk2. In some embodiments, the feedback circuit 13N is configured to be turned off by clock signals clk1 and clk2 before the transmission circuit 11N is turned on, so that the signals received by the master stage 100Nm can be correctly transmitted to the slave stage 100Ns.

[0061] If the feedback circuit 13N remains on while the transmission circuit 11N is on, the signal transmitted from the master stage 100Nm to the slave stage 100Ns may be adversely affected, resulting in the device 100N potentially failing to operate as expected. When the transmission circuit 11N is on, it is expected that the feedback circuit 13N will be completely off to avoid affecting the operation of the device 100N.

[0062] The slave stage 100Ns includes a transmission circuit 14N, a phase shifting circuit 15N, and a feedback circuit 16N. The transmission circuit 14N is electrically connected to the phase shifting circuit 15N and the feedback circuit 16N. The output terminal of the phase shifting circuit 15N is electrically connected to the input terminal of the feedback circuit 16N. The output terminal of the feedback circuit 16N is electrically connected to the input terminal of the phase shifting circuit 15N.

[0063] The transmission circuit 14N includes two inputs for receiving clock signals clk1 and clk2. The feedback circuit 16N includes two inputs for receiving clock signals CPN and clk1. In some embodiments, the feedback circuit 16N is configured to be turned off by clock signals CPN and clk1 before the transmission circuit 14N is turned on by clock signals clk1 and clk2, so that the signals received from stage 100Ns can be correctly transmitted to the output device 17N.

[0064] If the feedback circuit 16N remains on while the transmission circuit 14N is on, the signal transmitted from stage 100Ns to output device 17N may be adversely affected, resulting in device 100N potentially failing to operate as expected. When the transmission circuit 14N is on, the feedback circuit 16N can be expected to be completely off to avoid affecting the operation of device 100N. This can be achieved through... Figure 1C The configuration shown is implemented in which the feedback circuit 16N is controlled by a signal (e.g., CPN and clk1) that is ahead in timing of the signals (e.g., clk1 and clk2) used to control the transmission circuit 14N.

[0065] By controlling the feedback circuit 16N with an appropriate clock signal, signal interference / jitter between the master stage 100Nm and the slave stage 100Ns can be prevented. Signal interference / jitter between the master stage 100Nm and the slave stage 100Ns can also be prevented by turning off the feedback circuit 16N before the transmission circuit 14N is turned on. Therefore, compared to other methods, device 100N improves Vmin by approximately 25mV to 50mV. That is, device 100N can operate normally at lower voltages. The reduced Vmin allows device 100N to be widely used in common semiconductor systems.

[0066] Figure 1D The waveform of a clock signal according to some embodiments of the present disclosure is shown. Figure 1D The waveforms of clock signals CP, clk1, and clk2 are shown. There is a phase shift of ps1 between clock signal CP and clock signal clk1. There is a phase shift of ps2 between clock signals clk1 and clk2. (See figure.) Figure 1D As shown, the waveform of clock signal CP includes a rising edge re1 and a falling edge fe1. The waveform of clock signal clk1 includes a rising edge re2 and a falling edge fe2. The waveform of clock signal clk2 includes a rising edge re3 and a falling edge fe3.

[0067] Figure 1E The waveform of a clock signal according to some embodiments of the present disclosure is shown.

[0068] Figure 1E The waveforms of clock signals CPN, clk1, and clk2 are shown. There is a phase shift of ns1 between clock signals CPN and clk1. There is a phase shift of ns2 between clock signals clk1 and clk2.

[0069] Figure 2A A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0070] Figure 2A Device 200 is shown. Device 200 can be an electronic device. Device 200 can be a semiconductor device. Device 200 can be an integrated circuit (IC) system. Device 200 can be a flip-flop. Device 200 includes a multiplexer 20, a master stage 200m, a slave stage 200s, and an output device 27. The multiplexer 20 includes inputs for receiving signals SE, SI, and D.

[0071] The master stage 200m includes a transmission circuit 21, a phase-shifting circuit 22, and a feedback circuit 23. The master stage 200m can also be called a latching circuit. The slave stage 200s includes a transmission circuit 24, a phase-shifting circuit 25, and a feedback circuit 26. The slave stage 200s can also be called a latching circuit. Device 200 may also include phase-shifting circuits 28a and 28b. Phase-shifting circuit 28a receives clock signal Phase_0 and then provides clock signal Phase_1. Phase-shifting circuit 28b receives clock signal Phase_1 and then provides clock signal Phase_2.

[0072] Figure 2A The main stage 200m transmission circuit 21, phase shifting circuit 22, and feedback circuit 23 are configured similarly to... Figure 1A The main stage 100m transmission circuit 11, phase shifting circuit 12 and feedback circuit 13 are different except that the input signal of feedback circuit 23 is different from the input signal of feedback circuit 13.

[0073] refer to Figure 2A Feedback circuit 23 is configured to receive clock signals Phase_0 and Phase_1, while Figure 1A The feedback circuit 13 is configured to receive clock signals Phase_1 and Phase_2.

[0074] In some embodiments, the feedback circuit 23 is configured to be turned off by clock signals Phase_0 and Phase_1 before the transmission circuit 21 is turned on by clock signals Phase_1 and Phase_2, so that the signal 200m received by the master can be correctly transmitted to the slave 200s.

[0075] If the feedback circuit 23 remains on while the transmission circuit 21 is on, the signal transmitted from the master stage 200m to the slave stage 200s may be adversely affected, resulting in the device 200 potentially failing to operate as expected. When the transmission circuit 21 is on, the feedback circuit 23 can be expected to be completely off to avoid affecting the operation of the device 200. This can be achieved through... Figure 2A The configuration shown is implemented in which the feedback circuit 23 is controlled by a signal (e.g., Phase_0 and Phase_1) that is earlier in timing than the signals used to control the transmission circuit 21 (e.g., Phase_1 and Phase_2).

[0076] Figure 2A The slave stage 200s consists of a transmission circuit 24, a phase-shifting circuit 25, and a feedback circuit 26. It is configured similarly to... Figure 1A The slave stage 100s includes a transmission circuit 14, a phase shifting circuit 15, and a feedback circuit 16.

[0077] In some embodiments, the feedback circuit 26 is configured to be turned off by clock signals Phase_0 and Phase_1 before the transmission circuit 24 is turned on by clock signals Phase_1 and Phase_2, so that the signal 200s received from the slave stage can be correctly transmitted to the output device 27.

[0078] If the feedback circuit 26 remains on while the transmission circuit 24 is on, the signal transmitted from stage 200s to output device 27 may be adversely affected, and device 200 may not operate as expected. When the transmission circuit 24 is on, it is expected that the feedback circuit 26 will be completely off so as not to affect the operation of device 200. This can be achieved by the configuration shown in Figure A2, where the feedback circuit 26 is controlled by signals (e.g., Phase 0 and Phase 1) that are timing-advanced compared to the signals used to control the transmission circuit 24 (e.g., Phase 1 and Phase 2).

[0079] By controlling feedback circuits 23 and 26 with an appropriate clock signal, signal interference / jitter between the master stage 200m and the slave stage 200s can be prevented. As a result, compared with other methods, device 200 improves Vmin by approximately 25mV to 50mV. That is, device 200 can operate normally at a lower voltage. The reduced Vmin allows device 200 to be widely used in common semiconductor systems.

[0080] Figure 2B A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0081] Figure 2B Device 200P is shown. Device 200P can be an electronic device. Device 200P can be a semiconductor device. Device 200P can be an integrated circuit (IC) system. Device 200P can be a flip-flop. Device 200P can be a rising-edge triggered flip-flop. Device 200P can be an embodiment corresponding to device 200.

[0082] Device 200P includes a multiplexer 20P, a master stage 200Pm, a slave stage 200Ps, and an output device 27P. The multiplexer 20P corresponds to the above-mentioned... Figure 1B The multiplexing device discussed is a 10P multiplexer. The master stage (200Pm) can also be called a latch circuit. The slave stage (200Ps) can also be called a latch circuit.

[0083] Device 200P may further include phase shift circuits 28Pa, 28Pb, and 28Pc. Phase shift circuit 28Pa is used to receive clock signal CP and then provide clock signal clk1. Phase shift circuit 28Pb is configured to receive clock signal clk1 and then provide clock signal clk2. A phase shift exists between clock signal clk1 and CP. A phase shift exists between clock signal clk2 and clk1. In some embodiments, phase shift circuit 28Pa is an inverter. In some embodiments, phase shift circuit 28Pb is an inverter.

[0084] The phase shift circuit 28Pc is configured to receive the signal SE and then provide the signal SEN. A phase shift exists between signals SE and SEN. In some embodiments, the phase shift circuit 28Pc is an inverter. In some embodiments, the signal SEN corresponds to the inversion of the signal SE.

[0085] The main stage 200Pm includes a transmission circuit 21P, a phase-shifting circuit 22P, and a feedback circuit 23P. The transmission circuit 21P is electrically connected to the phase-shifting circuit 22P and the feedback circuit 23P. The output of the phase-shifting circuit 22P is electrically connected to the input of the feedback circuit 23P. The output of the feedback circuit 23P is also electrically connected to the input of the phase-shifting circuit 22P.

[0086] The transmission circuit 21P includes two input terminals for receiving clock signals clk1 and clk2. The feedback circuit 23P includes two input terminals for receiving clock signals clk1 and CP. In some embodiments, the feedback circuit 23P is configured to be turned off by clock signals clk1 and CP before the transmission circuit 21P is turned on, so that the signals received by the master stage 200Pm can be correctly transmitted to the slave stage 200Ps.

[0087] If the feedback circuit 23P remains on while the transmission circuit 21P is on, the signal transmitted from the master stage 200Pm to the slave stage 200Ps may be adversely affected, resulting in the device 200P potentially failing to operate as expected. When the transmission circuit 21P is on, the feedback circuit 23P can be expected to be completely off to avoid affecting the operation of the device 200P.

[0088] The slave stage 200Ps includes a transmission circuit 24P, a phase shifting circuit 25P, and a feedback circuit 26P. The transmission circuit 24P is electrically connected to the phase shifting circuit 25P and the feedback circuit 26P. The output terminal of the phase shifting circuit 25P is electrically connected to the input terminal of the feedback circuit 26P. The output terminal of the feedback circuit 26P is electrically connected to the input terminal of the phase shifting circuit 25P.

[0089] The transmission circuit 24P includes two inputs for receiving clock signals clk1 and clk2. The feedback circuit 26P includes two inputs for receiving clock signals CP and clk1. In some embodiments, the feedback circuit 26P is configured to be turned off by clock signals CP and clk1 before the transmission circuit 24P is turned on by clock signals clk1 and clk2, so that the signal received from stage 200Ps can be correctly transmitted to the output device 27P.

[0090] If the feedback circuit 26P remains on while the transmission circuit 24P is on, the signal transmitted from stage 200Ps to output device 27P may be adversely affected, resulting in device 200P potentially failing to operate as expected. When the transmission circuit 24P is on, it is expected that the feedback circuit 26P will be completely off to avoid affecting the operation of device 200P. This can be achieved through... Figure 2B The configuration shown is implemented in which the feedback circuit 26P is controlled by a signal (e.g., CP and clk1) that is ahead in timing of the signals (e.g., clk1 and clk2) used to control the transmission circuit 24P.

[0091] By controlling feedback circuits 23P and 26P with an appropriate clock signal, signal interference / jitter between the master stage 200Pm and the slave stage 200Ps can be prevented. Therefore, compared to other methods, device 200P improves Vmin by 25mV to 50mV. That is, device 200P can operate normally at lower voltages. The reduced Vmin allows device 200P to be widely used in common semiconductor systems.

[0092] Figure 2C A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0093] Figure 2C Device 200N is shown. Device 200N can be an electronic device. Device 200N can be a semiconductor device. Device 200N can be an integrated circuit (IC) system. Device 200N can be a flip-flop. Device 200N can be a falling-edge triggered flip-flop. Device 200N can be an embodiment corresponding to device 200.

[0094] Device 200N includes multiplexing device 20N, master stage 200Nm, slave stage 200Ns, and output device 27N. Multiplexing device 20N corresponds to the above-mentioned... Figure 1B The multiplexing device discussed is a 10P. The master stage (200nm) can also be called a latch circuit. The slave stage (200nm) can also be called a latch circuit.

[0095] Device 200N may further include phase shift circuits 28Na, 28Nb, and 28Nc. Phase shift circuit 28Na is configured to receive clock signal CPN and then provide clock signal clk1. Phase shift circuit 28Nb is configured to receive clock signal clk1 and then provide clock signal clk2. A phase shift exists between clock signal clk1 and CPN. A phase shift exists between clock signal clk2 and clk1. In some embodiments, phase shift circuit 28Na is an inverter. In some embodiments, phase shift circuit 28Nb is an inverter.

[0096] Figure 2C The clock signal CP shown can correspond to Figure 2B The clock signal CP shown is inverted. Figure 2C The clock signal CPN shown is Figure 2B There may be a phase shift between the clock signals CP shown.

[0097] The phase shift circuit 28Nc is configured to receive the signal SE and then provide the signal SEN. A phase shift exists between signals SE and SEN. In some embodiments, the phase shift circuit 28Nc is an inverter. In some embodiments, the signal SEN corresponds to the inversion of the signal SE.

[0098] The main stage 200Nm includes a transmission circuit 21N, a phase shifting circuit 22N, and a feedback circuit 23N. The transmission circuit 21N is electrically connected to the phase shifting circuit 22N and the feedback circuit 23N. The output terminal of the phase shifting circuit 22N is electrically connected to the input terminal of the feedback circuit 23N. The output terminal of the feedback circuit 23N is electrically connected to the input terminal of the phase shifting circuit 22N.

[0099] The transmission circuit 21N includes two inputs for receiving clock signals clk1 and clk2. The feedback circuit 23N includes two inputs for receiving clock signals clk1 and CPN. In some embodiments, the feedback circuit 23N is configured to be turned off by the clock signals clk1 and CPN before the transmission circuit 21N is turned on, so that the signals received by the master stage 200Nm can be correctly transmitted to the slave stage 200Ns.

[0100] If the feedback circuit 23N remains on while the transmission circuit 21N is on, the signal transmitted from the master stage 200Nm to the slave stage 200Ns may be adversely affected, resulting in the device 200N potentially failing to operate as expected. When the transmission circuit 21N is on, the feedback circuit 23N can be expected to be completely off to avoid affecting the operation of the device 200N.

[0101] The slave stage 200Ns includes a transmission circuit 24N, a phase-shifting circuit 25N, and a feedback circuit 26N. The transmission circuit 24N is electrically connected to the phase-shifting circuit 25N and the feedback circuit 26N. The output terminal of the phase-shifting circuit 25N is electrically connected to the input terminal of the feedback circuit 26N. The output terminal of the feedback circuit 26N is electrically connected to the input terminal of the phase-shifting circuit 25N.

[0102] The transmission circuit 24N includes two inputs for receiving clock signals clk1 and clk2. The feedback circuit 26N includes two inputs for receiving clock signals CPN and clk1. In some embodiments, the feedback circuit 26N is configured to be turned off by clock signals CPN and clk1 before the transmission circuit 24N is turned on by clock signals clk1 and clk2, so that the signals received from stage 200Ns can be correctly transmitted to the output device 27N.

[0103] If the feedback circuit 26N remains on while the transmission circuit 24N is on, the signal transmitted from stage 200Ns to output device 27N may be adversely affected, resulting in device 200N potentially failing to operate as expected. When the transmission circuit 24N is on, it is expected that the feedback circuit 26N will be completely off to avoid affecting the operation of device 200N. This can be achieved through... Figure 2C The configuration shown is implemented in which the feedback circuit 26N is controlled by a signal (e.g., CPN and clk1) that is ahead in timing of the signals (e.g., clk1 and clk2) used to control the transmission circuit 24N.

[0104] By controlling the feedback circuits 23N and 26N with an appropriate clock signal, signal interference / jitter between the master stage 200Nm and the slave stage 200Ns can be prevented. As a result, device 200N improves Vmin by approximately 25mV to 50mV compared to other methods. That is, device 200N can operate normally at lower voltages. The reduced Vmin allows device 200N to be widely used in common semiconductor systems.

[0105] Figure 3A A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0106] Figure 3A Device 300 is shown. Device 300 can be an electronic device. Device 300 can be a semiconductor device. Device 300 can be an integrated circuit (IC) system. Device 300 can be a flip-flop. Device 300 includes a multiplexer 30, a master stage 300m, a slave stage 300s, and an output device 37. The multiplexer 30 includes inputs for receiving signals SE, SI, and D. The master stage 300m can also be referred to as a latch circuit. The slave stage 300s can also be referred to as a latch circuit.

[0107] The function of multiplexer 30 is similar to that of multiplexers 10 and 20, and will not be described in detail here.

[0108] The master stage 300m includes a transmission circuit 31, a phase-shifting circuit 32, and a feedback circuit 33. The slave stage 300s includes a transmission circuit 34, a phase-shifting circuit 35, and a feedback circuit 36.

[0109] The transmission circuit 31, phase shifting circuit 32, and feedback circuit 33 of the master stage 300m are configured similarly to the transmission circuit 11, phase shifting circuit 12, and feedback circuit 13 of the master stage 100m. The transmission circuit 34, phase shifting circuit 35, and feedback circuit 36 ​​of the slave stage 300s are configured similarly to the transmission circuit 14, phase shifting circuit 15, and feedback circuit 16 of the master stage 100m.

[0110] Figure 3A The device 300 shown is similar to Figure 1A The device 100 shown, except that device 300 includes a clocked device 39 shared by the master stage 300m and the slave stage 300s. By sharing the clocked device 39 between the master stage 300m and the slave stage 300s, the total number of clocked devices within device 300 can be reduced. The clocked device mentioned in this disclosure can refer to a device that receives a clock signal. The clocked device mentioned in this disclosure can refer to a device triggered by a clock signal. Clocked devices can dissipate power regularly during the operation of a flip-flop device. Therefore, reducing the total number of clocked devices within a flip-flop device can help reduce the power consumption of the flip-flop device.

[0111] In some embodiments, the feedback circuit 33 is configured to be turned off by clock signals Phase_1 and Phase_2 before the transmission circuit 31 is turned on by clock signals Phase_1 and Phase_2, so that the signal 300m received by the master stage can be correctly transmitted to the slave stage 300s. In some embodiments, the feedback circuit 36 ​​is configured to be turned off by clock signals Phase_0 and Phase_1 before the transmission circuit 34 is turned on by clock signals Phase_1 and Phase_2, so that the signal received by the slave stage 300s can be correctly transmitted to the output device 37.

[0112] If feedback circuit 36 ​​remains on while transmission circuit 34 is on, the signal transmitted from stage 300s to output device 37 may be adversely affected, resulting in device 300 potentially failing to operate as expected. When transmission circuit 34 is on, feedback circuit 36 ​​can be expected to be completely off to avoid affecting the operation of device 300. This can be achieved through... Figure 3A The configuration shown is implemented in which the feedback circuit 36 ​​is controlled by a signal (e.g., Phase_0 and Phase_1) that is more advanced in timing than the signals used to control the transmission circuit 34 (e.g., Phase_1 and Phase_2).

[0113] Device 300 may also include phase shifting circuits 38a and 38b. The functions of phase shifting circuits 38a and 38b are similar to those of phase shifting circuits 18a and 18b, and will not be described in detail here.

[0114] The transmission circuit 31 of the master stage 300m and the transmission circuit 34 of the slave stage 300s can be controlled by the same clock signal (e.g., Phase 1 and Phase 2). The feedback circuit 33 of the master stage 300m and the feedback circuit 36 ​​of the slave stage 300s can be controlled by different clock signals. By controlling the feedback circuit 36 ​​with a suitable clock signal, signal interference / jitter between the master stage 300m and the slave stage 300s can be prevented. As a result, compared to other methods, device 300 improves Vmin by approximately 25mV to 50mV. The reduced Vmin allows device 300 to be widely used in common semiconductor systems.

[0115] Figure 3B A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0116] Figure 3B Device 300P is shown. Device 300P can be an electronic device. Device 300P can be a semiconductor device. Device 300P can be an integrated circuit (IC) system. Device 300P can be a flip-flop. Device 300P can be a rising-edge triggered flip-flop. Device 300P can be an embodiment corresponding to device 300.

[0117] Device 300P includes a multiplexer 30P, a master stage 300Pm, a slave stage 300Ps, and an output device 37P. The multiplexer 30P includes input terminals for receiving signals SE, SEN, SI, and D. The master stage 300Pm can also be called a latch circuit. The slave stage 300Ps can also be called a latch circuit.

[0118] The function of the 30P multiplexer is similar to that of the 10P and 20P multiplexers, and will not be described in detail here.

[0119] Device 300P may also include phase shifting circuits 38Pa, 38Pb, and 38Pc. The functions of phase shifting circuits 38Pa, 38Pb, and 38Pc are similar to those of phase shifting circuits 18Pa, 18Pb, and 18Pc, and will not be described in detail here.

[0120] The main stage 300Pm includes a transmission circuit 31P, a phase-shifting circuit 32P, and a feedback circuit 33P. The transmission circuit 31P is electrically connected to the phase-shifting circuit 32P and the feedback circuit 33P. The output terminal of the phase-shifting circuit 32P is electrically connected to the input terminal of the feedback circuit 33P. The output terminal of the feedback circuit 33P is electrically connected to the input terminal of the phase-shifting circuit 32P.

[0121] In some embodiments, the phase-shifting circuit 32P includes two inverters connected in series. Figure 1B Compared to or with the phase-shifting circuit 12P shown Figure 2B Compared to the phase shift circuit 22P shown, the phase shift circuit 32P includes an additional inverter, which helps reduce current leakage of device 300P. In some embodiments, the feedback circuit 33P includes a transmission gate configured to receive clock signals clk1 and clk2.

[0122] The transmission circuit 31P includes two input terminals for receiving clock signals clk1 and clk2. (Reference) Figure 3B The transmission circuit 31P includes two transistors, one located at the master stage 300Pm and configured to receive clock signal clk2, and the other (i.e., clock device 39P) located at the slave stage 300Ps and configured to receive clock signal clk1.

[0123] Clock device 39P can be part of transmission circuit 31P or feedback circuit 36P. Clock device 39P can be shared by transmission circuit 31P and feedback circuit 36P. Clock device 39P can be shared by master stage 300Pm and slave stage 300Ps.

[0124] The feedback circuit 33P includes two inputs configured to receive clock signals clk1 and clk2.

[0125] In some embodiments, the feedback circuit 33P is configured to be turned off by clock signals clk1 and clk2 before the transmission circuit 31P is turned on, so that the signal received by the master stage 300Pm can be correctly transmitted to the slave stage 300Ps.

[0126] The slave stage 300Ps includes a transmission circuit 34P, a phase-shifting circuit 35P, and a feedback circuit 36P. The transmission circuit 34P is electrically connected to the phase-shifting circuit 35P and the feedback circuit 36P. The output terminal of the phase-shifting circuit 35P is electrically connected to the input terminal of the feedback circuit 36P. The output terminal of the feedback circuit 36P is electrically connected to the input terminal of the phase-shifting circuit 35P.

[0127] Transmission circuit 34P includes two input terminals for receiving clock signals clk1 and clk2. Feedback circuit 36P includes two input terminals for receiving clock signals CP and clk1. Clock device 39P corresponds to the transistor in feedback circuit 36P configured to receive clock signal clk1. Clock device 39P can be shared by transmission circuit 31P and feedback circuit 36P.

[0128] In some embodiments, the feedback circuit 36P is configured to be turned off by clock signals CP and clkl before the transmission circuit 34P is turned on by clock signals clkl and clk2, so that the signals 300Ps received from the slave stage can be correctly transmitted to the output device 37P.

[0129] If the feedback circuit 36P remains on while the transmission circuit 34P is on, the signal transmitted from stage 300Ps to output device 37P may be adversely affected, resulting in device 300P potentially failing to operate as expected. When the transmission circuit 34P is on, it is expected that the feedback circuit 36P will be completely off to avoid affecting the operation of device 300P. This can be achieved through... Figure 3B The configuration shown is implemented in which the feedback circuit 36P is controlled by a signal (e.g., CP and clk1) that is ahead in timing of the signals (e.g., clk1 and clk2) used to control the transmission circuit 34P.

[0130] By controlling the feedback circuit 36P with an appropriate clock signal, signal interference / jitter between the master stage 300Pm and the slave stage 300Ps can be prevented. As a result, device 300P improves Vmin by approximately 25mV to 50mV. The reduced Vmin allows device 300P to be widely used in common semiconductor systems.

[0131] Furthermore, compared to other methods, the advantages of device 300P include shorter circuit propagation delays (e.g., clock-to-Q delay). Reference Figure 3B Before the clock signal CP can provide the output signal Q, it only needs to pass through the phase shifting circuits 38Pa and 38Pb, the transmission circuit 34P, and the output device 37P.

[0132] Figure 3C A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown.

[0133] Figure 3C Device 300N is shown. Device 300N can be an electronic device. Device 300N can be a semiconductor device. Device 300N can be an integrated circuit (IC) system. Device 300N can be a flip-flop. Device 300N can be a falling-edge triggered flip-flop. Device 300N can be an embodiment corresponding to device 300.

[0134] Device 300N includes a multiplexer 30N, a master stage 300Nm, a slave stage 300Ns, and an output device 37N. The multiplexer 30N includes inputs for receiving signals SE, SEN, SI, and D. The master stage 300Nm can also be referred to as a latch circuit. The slave stage 300Ns can also be referred to as a latch circuit.

[0135] The function of the 30N multiplexer is similar to that of the 10N and 20N multiplexers, and will not be described in detail here.

[0136] Device 300N may also include phase shifting circuits 38Na, 38Nb, and 38Nc. The functions of phase shifting circuits 38Na, 38Nb, and 38Nc are similar to those of phase shifting circuits 18Na, 18Nb, and 18Nc, and will not be described in detail here.

[0137] The main stage 300Nm includes a transmission circuit 31N, a phase-shifting circuit 32N, and a feedback circuit 33N. The transmission circuit 31N is electrically connected to the phase-shifting circuit 32N and the feedback circuit 33N. The output terminal of the phase-shifting circuit 32N is electrically connected to the input terminal of the feedback circuit 33N. The output terminal of the feedback circuit 33N is electrically connected to the input terminal of the phase-shifting circuit 32N.

[0138] In some embodiments, the phase-shifting circuit 32N includes two inverters connected in series. Figure 1C Compared to or with the phase-shifting circuit 12N shown Figure 2C Compared to the phase shift circuit 22N shown, phase shift circuit 32N includes an additional inverter. The additional inverter in phase shift circuit 32N helps reduce leakage current in device 300N. In some embodiments, feedback circuit 33N includes a transmission gate configured to receive clock signals clk1 and clk2.

[0139] The transmission circuit 31N includes two inputs configured to receive clock signals clk1 and clk2. (Reference) Figure 3C The transmission circuit 31N includes two transistors, one in the master stage 300Nm and configured to receive clock signal clk2, and the other (i.e., clock device 39N) in the slave stage 300Ns and configured to receive clock signal clk1.

[0140] Clock device 39N can be part of transmission circuit 31N and also part of feedback circuit 36N. Clock device 39N can be shared by transmission circuit 31N and feedback circuit 36N. Clock device 39N can be shared by master stage 300Nm and slave stage 300Ns.

[0141] The feedback circuit 33N includes two inputs configured to receive clock signals clk1 and clk2.

[0142] In some embodiments, the feedback circuit 33N is configured to be turned off by clock signals clk1 and clk2 before the transmission circuit 31N is turned on, so that the signal received by the master stage 300Nm can be correctly transmitted to the slave stage 300Ns.

[0143] The slave stage 300Ns includes a transmission circuit 34N, a phase-shifting circuit 35N, and a feedback circuit 36N. The transmission circuit 34N is electrically connected to the phase-shifting circuit 35N and the feedback circuit 36N. The output terminal of the phase-shifting circuit 35N is electrically connected to the input terminal of the feedback circuit 36N. The output terminal of the feedback circuit 36N is electrically connected to the input terminal of the phase-shifting circuit 35N.

[0144] The transmission circuit 34N includes two inputs configured to receive clock signals clk1 and clk2. The feedback circuit 36N includes two inputs for receiving clock signals CPN and clk1. The clock device 39N corresponds to the transistor in the feedback circuit 36N configured to receive clock signal clk1. The clock device 39N can be shared by the transmission circuit 31N and the feedback circuit 36N.

[0145] In some embodiments, the feedback circuit 36N is configured to be turned off by the clock signals CPN and clkl before the transmission circuit 34N is turned on by the clock signals clkl and clk2, so that the signal 300Ns received from the slave stage can be correctly transmitted to the output device 37N.

[0146] If the feedback circuit 36N remains on while the transmission circuit 34N is on, the signal transmitted from stage 300Ns to output device 37N may be adversely affected, resulting in device 300N potentially failing to operate as expected. When the transmission circuit 34N is on, it is expected that the feedback circuit 36N will be completely off to avoid affecting the operation of device 300N. This can be achieved through... Figure 3C The configuration shown is implemented in which the feedback circuit 36N is controlled by a signal (e.g., CPN and clk1) that is ahead in timing of the signals (e.g., clk1 and clk2) used to control the transmission circuit 34N.

[0147] By controlling the feedback circuit 36N with an appropriate clock signal, signal interference / jitter between the master stage 300Nm and the slave stage 300Ns can be prevented. Therefore, compared to other methods, device 300N improves Vmin by approximately 25mV to 50mV. This reduced Vmin allows device 300N to be widely used in common semiconductor systems.

[0148] Furthermore, compared to other methods, the benefits of device 300N include shorter circuit propagation delays (e.g., clock-to-Q delay). Reference Figure 3C Before the clock signal CPN can provide the output signal Q, it only needs to pass through the phase shifting circuits 38Na and 38Nb, the transmission circuit 34N, and the output device 37N. Figure 4A A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown. Figure 4ADevice 400 is shown. Device 400 can be an electronic device. Device 400 can be a semiconductor device. Device 400 can be an integrated circuit (IC) system. Device 400 can be a logic system. Device 400 can be a multi-bit flip-flop. Device 400 can be a rising-edge triggered flip-flop.

[0149] Device 400 includes devices 400_1, 400_2, 400_3, ..., and 400_n. Devices 400_1, 400_2, 400_3, ..., and 400_n can be connected in series. Each of devices 400_1, 400_2, 400_3, ..., and 400_n can be a flip-flop. Each of devices 400_1, 400_2, 400_3, ..., and 400_n can be a single-bit flip-flop. Device 400 can be a multi-bit flip-flop. Device 400 can be an n-bit flip-flop.

[0150] Device 400_1 includes inputs for receiving signals SI, D1, SE, and SEN. Device 400_1 includes inputs for receiving clock signals CP, clk1, and clk2. Device 400_1 includes an output for providing an output signal Q1. The output signal Q1 can be received by device 400_2.

[0151] Device 400_2 includes inputs for receiving signals Q1, D2, SE, and SEN. Device 400_2 includes inputs for receiving clock signals CP, clk1, and clk2. Device 400_2 includes an output for providing an output signal Q2. The output signal Q2 can be received by device 400_3.

[0152] Device 400_3 includes inputs for receiving signals Q2, D3, SE, and SEN. Device 400_3 includes inputs for receiving clock signals CP, clk1, and clk2. Device 400_3 includes an output for providing output signal Q3. Output signal Q3 can be received by subsequent devices.

[0153] Device 400_n includes inputs for receiving signals Qn-1, Dn-1, SE, and SEN. Device 400_n includes inputs for receiving clock signals CP, clk1, and clk2. Device 400_n includes an output for providing an output signal Qn.

[0154] Device 400 also includes a set of phase-shifting circuits 48. This set of phase-shifting circuits 48 can be configured to provide signal SEN based on signal SE. This set of phase-shifting circuits 48 can also be configured to provide clock signals clk1 and clk2 based on clock signal CP.

[0155] Each of devices 400_1, 400_2, 400_3, ... and 400_n can be derived from... Figure 1B The device shown is 100P. Figure 2B The device shown is 200P or Figure 3B The illustrated device 300P is implemented. In some embodiments, each of devices 400_1, 400_2, 400_3, ..., and 400_n has the same internal structure. In some embodiments, each of devices 400_1, 400_2, 400_3, ..., and 400_n is implemented individually by device 100P, individually by device 200P, or individually by device 300P. In some embodiments, devices 400_1, 400_2, 400_3, ..., and 400_n have different internal structures. In some embodiments, devices 400_1, 400_2, 400_3, ..., and 400_n are implemented by a combination of devices 100P, 200P, or 300P.

[0156] Figure 4B A schematic diagram of a semiconductor device according to some embodiments of the present disclosure is shown. Figure 4B Device 500 is shown. Device 500 can be an electronic device. Device 500 can be a semiconductor device. Device 500 can be an integrated circuit (IC) system. Device 500 can be a logic system. Device 500 can be a multi-bit flip-flop. Device 500 can be a falling-edge triggered flip-flop.

[0157] Device 500 includes devices 500_1, 500_2, 500_3, ..., and 500_n. Devices 500_1, 500_2, 500_3, ..., and 500_n can be connected in series. Each of devices 500_1, 500_2, 500_3, ..., and 500_n can be a flip-flop. Each of devices 500_1, 500_2, 500_3, ..., and 500_n can be a single-bit flip-flop. Device 500 can be a multi-bit flip-flop. Device 500 can be an n-bit flip-flop.

[0158] Device 500_1 includes inputs for receiving signals SI, D1, SE, and SEN. Device 500_1 includes inputs for receiving clock signals CPN, clk1, and clk2. Device 500_1 includes an output for providing an output signal Q1. The output signal Q1 can be received by device 500_2.

[0159] Device 500_2 includes inputs for receiving signals Q1, D2, SE, and SEN. Device 500_2 includes inputs for receiving clock signals CPN, clk1, and clk2. Device 500_2 includes an output for providing an output signal Q2. The output signal Q2 can be received by device 500_3.

[0160] Device 500_3 includes inputs for receiving signals Q2, D3, SE, and SEN. Device 500_3 includes inputs for receiving clock signals CPN, clk1, and clk2. Device 500_3 includes an output for providing output signal Q3. Output signal Q3 can be received by subsequent devices.

[0161] Device 500_n includes input terminals for receiving signals Qn-1, Dn-1, SE, and SEN. Device 500_n includes input terminals for receiving clock signals CPN, clk1, and clk2. Device 500_n includes an output terminal for providing an output signal Qn.

[0162] Device 500 also includes a set of phase-shifting circuits 58. This set of phase-shifting circuits 58 can be configured to provide signal SEN based on signal SE. This set of phase-shifting circuits 58 can also be configured to provide clock signals clk1 and clk2 based on clock signal CPN.

[0163] Each of devices 500_1, 500_2, 500_3, ... and 500_n can be generated by... Figure 1C The device shown is 100N. Figure 2C The device shown is 200N, or Figure 3C The device 300N shown is used to implement this. In some embodiments, each of devices 500_1, 500_2, 500_3, ..., and 500_n has the same internal structure. In some embodiments, each of devices 500_1, 500_2, 500_3, ..., and 500_n is implemented individually by device 100N, individually by device 200N, or individually by device 300N. In some embodiments, devices 500_1, 500_2, 500_3, ..., and 500_n have different internal structures. In some embodiments, devices 500_1, 500_2, 500_3, ..., and 500_n are implemented by a combination of devices 100N, 200N, or 300N.

[0164] Figure 5 A flowchart illustrating the operation of a method 600 for operating a semiconductor device according to some embodiments of the present disclosure is shown.

[0165] Figure 5 This includes operations 602, 604, 606, and 608 that operate the semiconductor device. In operation 602, a first clock signal and a second clock signal are provided to a first feedback circuit of the first latch circuit. In some embodiments, operation 602... Figure 1A Device 100 Figure 1B 100P of the device Figure 1C 100N device Figure 3ADevice 100 Figure 3B Device 300P or Figure 3C The operation is performed on device 300N. Taking device 100 as an example, clock signals Phase_0 and Phase_1 can be provided to the feedback circuit 16 of slave 100s.

[0166] In operation 604, the second clock signal and the third clock signal are provided to the first transmission circuit of the first latch circuit. In some embodiments, operation 604... Figure 1A Device 100 Figure 1B 100P of the device Figure 1C 100N device Figure 3A Device 100 Figure 3B Device 300P or Figure 3C The operation is performed on device 300N. Taking device 100 as an example, clock signals Phase_1 and Phase_2 can be provided to the transmission circuit 14 of slave 100s.

[0167] In operation 606, the second clock signal and the third clock signal are provided to the second feedback circuit of the second latch circuit. In some embodiments, operation 606... Figure 1A Device 100 Figure 1B 100P of the device Figure 1C 100N device Figure 3A Device 100 Figure 3B Device 300P or Figure 3C This is implemented on device 300N. Taking device 100 as an example, clock signals Phase_1 and Phase_2 can be provided to the feedback circuit 13 of the main stage 100m.

[0168] In operation 608, the second clock signal and the third clock signal are provided to the second transmission circuit of the second latching circuit. In some embodiments, operation 608... Figure 1A Device 100 Figure 1B 100P of the device Figure 1C 100N device Figure 3A Device 100 Figure 3B Device 300P or Figure 3C Figure 1A Figure 1B Figure 1C Figure 3A Figure 3B Figure 3C This is implemented on device 300N. Taking device 100 as an example, clock signals Phase_1 and Phase_2 can be provided to the transmission circuit 11 of the main stage 100m.

[0169] Some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes a first latch circuit and a second latch circuit connected to the first latch circuit. The second latch circuit includes a first feedback circuit and a first transmission circuit. The first feedback circuit is used to receive a first clock signal of a first phase and a second clock signal of a second phase. The first transmission circuit is used to receive the second clock signal and a third clock signal of a third phase. The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

[0170] In some embodiments, the first latch circuit includes a second feedback circuit and a second transmission circuit, wherein the second feedback circuit is configured to receive the second clock signal and the third clock signal, the second transmission circuit is configured to receive the second clock signal and the third clock signal, and the second feedback circuit is configured to be turned off by the second clock signal and the third clock signal before the second transmission circuit is turned on by the second clock signal and the third clock signal.

[0171] In some embodiments, a first phase shift exists between the second clock signal and the first clock signal.

[0172] In some embodiments, a second phase shift exists between the third clock signal and the second clock signal.

[0173] In some embodiments, the first latch circuit includes a second feedback circuit and a second transmission circuit, wherein the second feedback circuit is configured to receive the first clock signal and the second clock signal, the second transmission circuit is configured to receive the second clock signal and the third clock signal, and the second feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the second transmission circuit is turned on by the second clock signal and the third clock signal.

[0174] In some embodiments, the semiconductor device further includes a clock device shared by the first latch circuit and the second latch circuit.

[0175] In some embodiments, the semiconductor device further includes a phase-shifting circuit electrically connected between the first transmission circuit and the second transmission circuit of the first latching circuit.

[0176] In some embodiments, the phase-shifting circuit includes a first inverter and a second inverter, and the first inverter and the second inverter are connected in series.

[0177] In some embodiments, the semiconductor device further includes a multiplexing device connected to the second latch circuit, wherein the clock device is electrically connected between the first feedback circuit and the multiplexing device and is configured to receive the second clock signal.

[0178] Some embodiments of this disclosure provide a logic system. The logic system includes N flip-flop devices. A first flip-flop device among the N flip-flop devices includes a first latch circuit having a first feedback circuit and a first transmission circuit. The first flip-flop device further includes a second latch circuit having a second feedback circuit and a second transmission circuit. The first feedback circuit is used to receive a first clock signal of a first phase and a second clock signal of a second phase. The second feedback circuit is used to receive the second clock signal and a third clock signal of a third phase.

[0179] In some embodiments, the first transmission circuit is configured to receive a clock signal different from the clock signal received by the first feedback circuit, and the second transmission circuit is configured to receive the same clock signal as the clock signal received by the second feedback circuit.

[0180] In some embodiments, the first transmission circuit is configured to receive the second clock signal and the third clock signal, and the second transmission circuit is configured to receive the second clock signal and the third clock signal.

[0181] In some embodiments, the first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

[0182] In some embodiments, the second feedback circuit is configured to be turned off by the second clock signal and the third clock signal before the second transmission circuit is turned on by the second clock signal and the third clock signal.

[0183] In some embodiments, the first trigger device further includes a clock device shared by the first latch circuit and the second latch circuit.

[0184] In some embodiments, the clock device is configured to receive a clock signal shared by the first feedback circuit and the second transmission circuit.

[0185] In some embodiments, the clock device is configured to receive a second clock signal configured to control the first feedback circuit and the second transmission circuit.

[0186] Some embodiments of this disclosure provide a method for operating a semiconductor device. The method includes providing a first clock signal and a second clock signal to a first feedback circuit of a first latch circuit. The method also includes providing a second clock signal and a third clock signal to a first transmission circuit of the first latch circuit. Furthermore, the method includes providing the second clock signal and the third clock signal to a second feedback circuit of a second latch circuit. Finally, the method further includes providing the second clock signal and the third clock signal to a second transmission circuit of the second latch circuit.

[0187] In some embodiments, there is a first phase shift between the second clock signal and the first clock signal, and there is a second phase shift between the third clock signal and the second clock signal.

[0188] In some embodiments, the second clock signal is provided to the first feedback circuit and the second transmission circuit via a clock device shared by the first latch circuit and the second latch circuit.

[0189] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can be modified, substituted, and altered in various ways without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: First latch circuit; as well as A second latch circuit is connected to the first latch circuit and has a first feedback circuit and a first transmission circuit, wherein... The first feedback circuit includes an inverter configured to receive a first clock signal having a first phase and a second clock signal having a second phase. The first transmission circuit is configured to receive the second clock signal and a third clock signal having a third phase, and The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

2. The semiconductor device according to claim 1, wherein, The first latch circuit includes a second feedback circuit and a second transmission circuit, wherein The second feedback circuit is configured to receive the second clock signal and the third clock signal. The second transmission circuit is configured to receive the second clock signal and the third clock signal, and The second feedback circuit is configured to be turned off by the second clock signal and the third clock signal before the second transmission circuit is turned on by the second clock signal and the third clock signal.

3. The semiconductor device according to claim 1, wherein, There is a first phase shift between the second clock signal and the first clock signal.

4. The semiconductor device according to claim 1, wherein, There is a second phase shift between the third clock signal and the second clock signal.

5. The semiconductor device according to claim 1, wherein, The first latch circuit includes a second feedback circuit and a second transmission circuit, wherein The second feedback circuit is configured to receive the first clock signal and the second clock signal. The second transmission circuit is configured to receive the second clock signal and the third clock signal, and The second feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the second transmission circuit is turned on by the second clock signal and the third clock signal.

6. The semiconductor device according to claim 1, further comprising: The clock device is shared by the first latch circuit and the second latch circuit.

7. The semiconductor device according to claim 6, further comprising: The phase-shifting circuit is electrically connected between the first transmission circuit and the second transmission circuit of the first latch circuit.

8. The semiconductor device according to claim 7, wherein, The phase-shifting circuit includes a first inverter and a second inverter, and the first inverter and the second inverter are connected in series.

9. The semiconductor device according to claim 6, further comprising: A multiplexing device is connected to the second latch circuit, wherein the clock device is electrically connected between the first feedback circuit and the multiplexing device and is configured to receive the second clock signal.

10. A logic system for a semiconductor device, comprising: There are N trigger devices, wherein the first trigger device among the N trigger devices includes: The first latching circuit includes a first feedback circuit and a first transmission circuit; and The second latch circuit has a second feedback circuit and a second transmission circuit, wherein... The first feedback circuit includes an inverter configured to receive a first clock signal having a first phase and a second clock signal having a second phase. The second feedback circuit is configured to receive the second clock signal and a third clock signal having a third phase, and The first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

11. The logic system according to claim 10, wherein, The first transmission circuit is configured to receive a clock signal that is different from the clock signal received by the first feedback circuit, and the second transmission circuit is configured to receive a clock signal that is the same as the clock signal received by the second feedback circuit.

12. The logic system according to claim 10, wherein, The first transmission circuit is configured to receive the second clock signal and the third clock signal, and The second transmission circuit is configured to receive the second clock signal and the third clock signal.

13. The logic system according to claim 10, wherein, There is a phase shift between the second clock signal and the first clock signal.

14. The logic system according to claim 12, wherein, The second feedback circuit is configured to be turned off by the second clock signal and the third clock signal before the second transmission circuit is turned on by the second clock signal and the third clock signal.

15. The logic system according to claim 10, wherein, The first trigger device also includes a clock device shared by the first latch circuit and the second latch circuit.

16. The logic system according to claim 15, wherein, The clock device is configured to receive a clock signal shared by the first feedback circuit and the second transmission circuit.

17. The logic system according to claim 15, wherein, The clock device is configured to receive a second clock signal configured to control the first feedback circuit and the second transmission circuit.

18. A method of operating a semiconductor device, comprising: An inverter in a first feedback circuit provides a first clock signal and a second clock signal with a phase different from the first clock signal to a first latch circuit; The first transmission circuit of the first latch circuit provides the second clock signal and a third clock signal with a phase different from the first clock signal and the second clock signal; A second feedback circuit provides the second clock signal and the third clock signal to the second latch circuit; and A second transmission circuit provides the second clock signal and the third clock signal to the second latch circuit, wherein the first feedback circuit is configured to be turned off by the first clock signal and the second clock signal before the first transmission circuit is turned on by the second clock signal and the third clock signal.

19. The method according to claim 18, wherein, There is a first phase shift between the second clock signal and the first clock signal, and there is a second phase shift between the third clock signal and the second clock signal.

20. The method according to claim 18, wherein, The second clock signal is provided to the first feedback circuit and the second transmission circuit through a clock device shared by the first latch circuit and the second latch circuit.

Images