Redundant data protection for nand memory using self-authentication by internal firmware

Abstract

The present disclosure provides a method for data protection for a NAND memory. The method includes programming a first page and a second page of a NAND flash device in accordance with program data such that data stored in the first and second pages is redundant. The programming of the first and second pages includes a plurality of program operations using a plurality of program voltages and a plurality of verify operations to determine whether a programmed storage cell of the first page has a threshold voltage level in accordance with the program data. The method further includes determining completion of the programming of the first and second pages based on a pass result returned by each of the plurality of verify operations. The method further includes, after the determining, performing, by the NAND flash device, a read operation on the second page to self-verify data stored in the second page.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of semiconductor technology, and more specifically, the present disclosure relates to a method for debugging double program errors in NAND memory. BACKGROUND

[0002] As memory devices continue to shrink to smaller die sizes to reduce manufacturing costs and increase storage density, scaling of planar memory cells faces challenges due to process technology limitations and reliability issues. Three-dimensional (3D) memory architectures can address the density and performance limitations in planar memory cells.

[0003] In 3D NAND flash memory, multiple layers of memory cells can be stacked vertically, which can greatly increase the storage density per unit area. The vertically stacked memory cells can form a memory string in which the channels of the memory cells are connected in each memory string. Each memory cell can be addressed by a word line and a bit line. Data (i.e., logical states) of memory cells in an entire memory page sharing the same word line can be read or programmed simultaneously. However, as scaling is aggressively pursued, reliability can be an issue for 3D NAND flash memory. SUMMARY

[0004] Embodiments of methods and systems for data protection in memory devices are described in the present disclosure.

[0005] In some embodiments, a method can provide a redundant backup method using NAND self-verification. The method can include programming a first page and a second page of a NAND flash memory device according to program data such that data stored in the first page and the second page is redundant. Each of the first page and the second page includes a plurality of memory cells corresponding to a first word line or a second word line. The programming of the first page and the second page can include a plurality of program operations using a plurality of program voltages and a plurality of verify operations. Some of the plurality of verify operations can be performed after corresponding ones of the plurality of program operations to determine whether a programmed memory cell of the first page has a threshold voltage level according to the program data. The method can further include determining completion of the programming of the first page and the second page based on a pass result returned by each of the plurality of verify operations. The method can further include, after the determining, performing, by the NAND flash memory device, a read operation on the second page to self-verify data stored in the second page according to the program data.

[0006] In some embodiments, the first page can be configured for single level cell flash (SLC) programming. The second page can be configured for multi-level cell flash (MLC) programming, triple level cell flash (TLC) programming, or quad level cell flash (QLC) programming.

[0007] In some embodiments, the performing of the read operation can include reducing a time of completion of the method compared to performing the read operation by the one or more host computing devices to externally verify data stored at the second page according to the program data.

[0008] In some embodiments, the method can further include releasing the first page to receive new data for storage.

[0009] In some embodiments, the performing of the read operation can include comparing stored data determined from the read operation and the program data. The performing of the read operation can further include determining a pass result if a failed bit count is below a threshold, or determining a fail result if the failed bit count is above a threshold.

[0010] In some embodiments, the method can further include receiving an input by the NAND flash device to adjust the performing of the read operation.

[0011] In some embodiments, the method can further include limiting the performing of the read operation to one or more regions in the NAND flash device specified by the input. The one or more specified regions include at least one of: a region for single level cell flash (SLC); a region for multi-level cell flash (MLC); a region for triple level cell flash (TLC); a region for quad level cell flash (QLC); a page; a block; and a slice.

[0012] In some embodiments, the method can further include delaying caching of future program data until after the performing of the read operation.

[0013] In some embodiments, the method can further include detecting usage of the cache, wherein the delaying is based on the detecting of the usage of the cache.

[0014] In some embodiments, a NAND flash device can use NAND self-verification to provide redundant data backup. The NAND flash device can include a memory array. The memory array can include a first page and a second page, each of the first and second pages including a plurality of memory cells corresponding to a first word line or a second word line. The NAND flash device can also include a peripheral circuit coupled to the first and second pages via the first and second word lines. The peripheral circuit can program the first and second pages according to the program data such that data stored in the first and second pages is redundant. The programming of the first and second pages can include a plurality of program operations using a plurality of program voltages and a plurality of verify operations. Some of the plurality of verify operations can be performed after corresponding ones of the plurality of program operations to determine whether a programmed memory cell of the first page has a threshold voltage level according to the program data. The peripheral circuit can also determine completion of the programming of the first and second pages based on a pass result returned by each of the plurality of verify operations. The peripheral circuit can also perform, after the determining, a read operation of the second page by the NAND flash device to self-verify storage of data at the second page according to the program data.

[0015] In some embodiments of the NAND flash device, the first page can be configured for single-level cell flash (SLC) programming. The second page can be configured for multi-level cell flash (MLC) programming, triple-level cell flash (TLC) programming, or quad-level cell flash (QLC) programming.

[0016] In some embodiments of the NAND flash device, the performing of the read operation can include reducing a time to include completion of a redundant data storage process of the programming of the first and second pages compared to performing the read operation by one or more host computing devices to externally verify data stored at the second page according to the program data.

[0017] In some embodiments of the NAND flash device, the NAND flash device can release the first page to receive new data for storage.

[0018] In some embodiments of the NAND flash device, the performing of the read operation can include comparing stored data determined from the read operation and the program data. The performing of the read operation can also include determining a pass result if a failed bit count is below a threshold or a fail result if the failed bit count is above a threshold.

[0019] In some embodiments of the NAND flash device, the NAND flash device can receive an input to adjust the performance of the read operation.

[0020] In some embodiments of the NAND flash device, the NAND flash device can further limit the performance of the read operation to one or more regions in the NAND memory specified by the input. The one or more specified regions include at least one of: a region for single level cell flash (SLC); a region for multi-level cell flash (MLC); a region for triple level cell flash (TLC); a region for quad level cell flash (QLC); a page; a block; and a chip region.

[0021] In some embodiments of the NAND flash device, the NAND flash device can delay caching of future program data until after the performance of the read operation.

[0022] In some embodiments of the NAND flash device, the NAND flash device can further detect usage of the cache, wherein the delay is based on the detection of the usage of the cache.

[0023] In some embodiments, a memory system can provide a redundant backup method using NAND self-verification. The memory system can include a NAND flash device that can store data. The NAND flash device can include a memory array. The memory array can include a first page and a second page, each of the first and second pages including a plurality of memory cells corresponding to a first word line or a second word line. The NAND flash device can further include a peripheral circuit coupled to the first and second pages via the first and second word lines. The peripheral circuit can program the first and second pages according to the program data such that the data stored in the first and second pages are redundant. The programming of the first and second pages can include a plurality of program operations using a plurality of program voltages and a plurality of verify operations. Some of the plurality of verify operations can be performed after corresponding ones of the plurality of program operations to determine whether a programmed memory cell of the first page has a threshold voltage level according to the program data. The peripheral circuit can further determine completion of the programming of the first and second pages based on a pass result returned by each of the plurality of verify operations. The peripheral circuit can further perform, after the determining, a read operation of the second page by the NAND flash device to self-verify storage of data at the second page according to the program data.

[0024] In some embodiments of the memory system, the first page can be configured for single level cell flash (SLC) programming. The second page can be configured for multi-level cell flash (MLC) programming, triple level cell flash (TLC) programming, or quad level cell flash (QLC) programming.

[0025] In some embodiments of the memory system, the execution of the read operation can include reducing a time to complete a redundant data storage process including the programming of the first and second pages compared to performing one or more host computing devices' read operations to externally verify data stored in the second page according to the programmed data.

[0026] In some embodiments of the memory system, the NAND flash device can further release the first page to receive new data for storage.

[0027] In some embodiments of the memory system, the execution of the read operation can include comparing stored data determined from the read operation and the programmed data. The execution of the read operation can further include determining a pass result if a failed bit count is below a threshold, or a fail result if the failed bit count is above a threshold.

[0028] In some embodiments of the memory system, the NAND flash device can further receive an input to adjust the execution of the read operation.

[0029] In some embodiments of the memory system, the NAND flash device can further limit the execution of the read operation to one or more regions in the NAND flash device specified by the input. The one or more specified regions include at least one of: a region for single level cell flash (SLC); a region for multi-level cell flash (MLC); a region for triple level cell flash (TLC); a region for quad level cell flash (QLC); a page; a block; and a chip storage area.

[0030] In some embodiments of the memory system, the NAND flash device can further delay caching of future programmed data until after the execution of the read operation.

[0031] In some embodiments of the memory system, the NAND flash device can further detect usage of the cache, wherein the delay is based on the detection of the usage of the cache.

[0032] Other aspects of the disclosure will become apparent to those skilled in the art from the following description, which is given by way of example only, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the relevant art to make and use the disclosure.

[0034] Figure 1 and Figures 2A-2B A storage system with one or more memory chips is shown in accordance with some embodiments.

[0035] Figure 3 A schematic diagram of a memory die is shown in accordance with some embodiments.

[0036] Figure 4 A schematic diagram of a three-dimensional (3D) memory die is shown in accordance with some embodiments.

[0037] Figure 5 A perspective view of a portion of a 3D memory structure is shown in accordance with some embodiments.

[0038] Figure 6 A threshold voltage V th distribution of a NAND flash is shown in accordance with some embodiments.

[0039] Figure 7 A method of programming a memory cell is shown in accordance with some embodiments.

[0040] Figure 8A A method of storing data in a NAND memory and self-verification of data is shown in accordance with some embodiments.

[0041] Figure 8B A timeline using the method described in Figure 8A is shown in accordance with some embodiments.

[0042] Figure 9 A timeline for comparing adjustments performed using NAND firmware is shown.

[0043] Figure 10 A snapshot of a portion of a NAND memory in which a double program event occurs is shown in accordance with some embodiments.

[0044] Figure 11 A process flow including a double program event is shown in accordance with some embodiments.

[0045] Figure 12 A timeline of debugging a double program event is shown in accordance with some embodiments.

[0046] Figure 13 A method for performing SLC backup is shown in accordance with some embodiments.

[0047] Figure 14 A method for identifying unreliable areas in NAND memory is shown in accordance with some embodiments.

[0048] Figure 15 and Figure 16 A method for implementing NAND self-verification in SLC backup is shown in accordance with some embodiments.

[0049] The features and advantages of embodiments of the present application will become more apparent from the detailed description in conjunction with the accompanying drawings upon reading and understanding the detailed description. In the drawings, like reference numerals are used to identify like elements throughout the several views, although like reference numerals do not necessarily refer to the same element in all views. Wherever appropriate, similar reference numerals can be used throughout the drawings to refer to similar elements. Elements first introduced in a figure are designated with a first digit of the reference numeral that is equal to the number of the figure in which the element is introduced.

[0050] Embodiments of the present application will be described with reference to the accompanying drawings. DETAILED DESCRIPTION

[0051] While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Persons skilled in the relevant art will recognize that other configurations and arrangements can be employed without departing from the spirit and scope of the description. It will be apparent to those skilled in the relevant art that the description can also be employed in various other applications.

[0052] It should be noted that references to "one embodiment," "an embodiment,” "example embodiments,” "some embodiments,” etc., indicate that the described embodiments can include a particular feature, structure, or characteristic, but every embodiment can not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of those skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

[0053] In general, the terminology or nomenclature used herein is understood to be used in a descriptive sense and not a prescriptive sense unless otherwise indicated. For example, the term "one or more," as used herein, can be used in a descriptive sense to describe any feature, structure, or characteristic in a singular sense or in a plural sense, depending on the context in which it is used. Similarly, terms such as "a," "an," or "the," as used herein, can be understood to convey a singular usage or a plural usage, depending on the context in which it is used. Further, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, but instead can allow for existence of other factors not necessarily expressly described.

[0054] It should be readily understood that the meaning of "on," "over," and "above" in the present disclosure should be construed in the broadest possible way, such that "on" means not only "directly on" but also "on with intervening features or layers therebetween." Furthermore, "over" or "above" means not only "over" or "above" but also can include the meaning of "over" or "above" without intervening features or layers therebetween (i.e., directly over).

[0055] Furthermore, spatially relative terms, such as "beneath", "below", "lower", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or in process step, in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0056] As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where the semiconductor device is formed, and thus, unless otherwise noted, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite the top surface, and thus the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added to the top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0057] As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. A layer has a top side and a bottom side, where the bottom side of the layer is relatively close to a substrate and the top side is relatively far from the substrate. A layer can extend over an entire underlying or overlying structure, or can have a range that is less than a range of the underlying or overlying structure. Further, a layer can be a region of a uniform or non-uniform continuous structure that has a thickness that is less than a thickness of the continuous structure. For example, a layer can be between any set of horizontal planes between or at top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a taper. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above and / or below. A layer can comprise multiple layers. For example, an interconnect layer can include one or more conductive and contact layers in which contacts, interconnect lines, and / or vertical interconnect accesses (VIA) are formed, as well as one or more dielectric layers.

[0058] In the present disclosure, for ease of description, "layer" is used to refer to an element that has substantially the same height along a vertical direction. For example, a word line and an underlying gate dielectric layer can be referred to as "a layer", a word line and an underlying insulating layer can be referred to together as "a layer", word lines of substantially the same height can be referred to as "a layer of word lines" or similar wording, and so on.

[0059] As used herein, the term "nominal / nominally" refers to a desired or target value of a feature or parameter of a component or process step, as well as a range of values above and / or below the desired value, set during a design phase of a product or process. The range of values can be due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" denotes a value of a given quantity that can vary based on a particular technology node associated with a subject semiconductor device. Based on a particular technology node, the term "about" can denote a value of a given quantity that varies within, for example, 10-30% of the value (e.g., ±10%, ±20%, or ±30% of the value).

[0060] In the present disclosure, the term "horizontal / horizontally / lateral / laterally" refers to nominally parallel to a side surface of a substrate, while the term "vertical" or "vertically" refers to nominally perpendicular to the side surface of the substrate.

[0061] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having vertically oriented strings (referred to herein as "memory strings", e.g., NAND strings) of memory cell transistors in a lateral orientation on a substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0062] Figure 1A block diagram of a system S1 having a storage system 10 is shown in accordance with some embodiments. In some embodiments, the system S1 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage therein. The storage system 10 (e.g., a NAND storage system) can include a memory controller 20 and one or more semiconductor memory chips 25-1, 25-2, 25-3,..., 25-n. Each semiconductor memory chip 25 (hereinafter simply referred to as “memory chip”) can be a NAND chip (e.g., “flash,” “NAND flash,” or “NAND”). The storage system 10 can communicate with a host 15 through the memory controller 20, where the memory controller 20 can be connected to the one or more memory chips 25-1, 25-2, 25-3,..., 25-n via one or more memory channels 30-1, 30-2, 30-3,..., 30-n. In some embodiments, each memory chip 25 can be managed by the memory controller 20 via the one or more memory channels 30-1, 30-2, 30-3,..., 30-n.

[0063] In some embodiments, the host 15 can include a processor of an electronic device, such as a central processing unit (CPU) or a system on a chip (SoC), such as an application processor (AP). The host 15 can send data to be stored in the storage system 10 and / or can retrieve data from the storage system 10.

[0064] In some embodiments, memory controller 20 can process I / O requests received from host 15, ensure data integrity and efficient storage, and manage memory chips 25. To perform these tasks, memory controller 20 can run firmware 21, which can be executed by one or more processors 22 (e.g., microcontroller units, CPUs) of memory controller 20. For example, memory controller 20 can run firmware 21 to map logical addresses (e.g., addresses used by the host associated with host data) to physical addresses (e.g., the actual location where the data is stored) in memory chip 25. Controller 20 also runs firmware 21 to manage defective blocks of memory in memory chip 25, where firmware 21 can remap logical addresses to different physical addresses, i.e., move data to different physical addresses. Controller 20 may also include one or more memories 23 (e.g., DRAM, SRAM, EPROM, etc.) that can be used to store various metadata used by firmware 21. In some embodiments, memory controller 20 can also perform error recovery via error correction code (ECC) engine 29. ECC is used to detect and correct raw bit errors occurring within each memory chip 25.

[0065] In some embodiments, the memory channel 30 can provide data and control communication between the memory controller 20 and each memory chip 25 via a data bus. The memory controller 20 can select one of the memory chips 25 based on a chip enable signal.

[0066] In some embodiments, Figure 1 Each memory chip 25 may include one or more memory dies 100, wherein each memory die may be a 3D NAND memory.

[0067] In some embodiments, the memory controller 20 and one or more memory chips 25 can be integrated into various types of storage devices, for example, included in the same package, such as a Universal Flash Memory (UFS) package or an eMMC package. That is, the storage system 10 can be implemented and packaged into different types of end electronic products. Figure 2A In one example shown, the memory controller 20 and a single memory chip 25 can be integrated into a memory card 26. The memory card 26 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 26 may also include a connector for connecting the memory card 26 to a host computer (e.g., ...). Figure 1 The host 15) is coupled to the memory card connector 24. Figure 2BIn another example shown, the memory controller 20 and multiple memory chips 25 can be integrated into a solid-state drive (SSD) 27. The SSD 27 may also include a connection between the SSD 27 and a host computer (e.g., Figure 1 The host 15) is coupled to the SSD connector 28.

[0068] Figure 3 A top view of a memory die 100 according to some embodiments is shown. Figure 3 The example configurations shown are given as non-limiting examples, and it should be understood that the memory is scalable. In some embodiments, the memory die 100 may include one or more memory surfaces 101, each of which may include multiple memory blocks 103. The same and concurrent operations may be performed at each memory surface 101. A memory block 103 (the size of which may be megabytes (MB)) is the minimum size for performing an erase operation. The memory die 100 may include, for example, four memory surfaces 101. Each memory surface 101 may include, for example, six memory blocks 103. Each memory block 103 may include multiple memory cells, wherein each memory cell can be addressed via interconnects such as bit lines and word lines. Bit lines and word lines may be arranged vertically (e.g., in rows and columns, respectively), thereby forming an array of metal lines. Figure 3 In this disclosure, the directions of the bit lines and word lines are marked as "BL" and "WL". The memory block 103 is also referred to as a "memory array" or "array". A memory array is the core area in a memory device that performs memory functions.

[0069] In some embodiments, the memory die 100 may further include a peripheral region 105, a region surrounding the memory surface 101. The peripheral region 105 may include a variety of digital, analog, and / or mixed-signal circuitry to support the functionality of the memory array, such as page buffers, row and column decoders, and sense amplifiers. The peripheral circuitry uses active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as will be apparent to those skilled in the art.

[0070] In some embodiments, Figure 3 The arrangement of the memory surface 101 in the memory die 100 shown and the arrangement of the memory block 103 in each memory surface 101 are merely examples and do not limit the scope of this disclosure.

[0071] Figure 4A schematic diagram of a memory die 100 is shown in accordance with some embodiments. In some embodiments, the memory die 100 can include one or more memory blocks 103 (e.g., 103-1, 103-2, 103-3). Each memory block 103 can include a plurality of memory strings 212. Each memory string 212 includes a plurality of memory cells 340. Memory cells 340 sharing a same word line form a memory page 432. The memory string 212 can also include at least one field effect transistor (e.g., MOSFET) at each end, controlled by a lower select gate (LSG) 332 and an upper select gate (TSG) 334, respectively. A drain terminal of the top select transistor 334-T can be connected to a bit line 341, while a source terminal of the lower select transistor 332-T can be connected to an array common source (ACS) 430. The ACS 430 can be shared by the memory strings 212 in the entire memory block and is also referred to as a common source line.

[0072] In some embodiments, the memory die 100 can also include peripheral circuitry, which can include a number of digital, analog, and / or mixed-signal circuits to support the functionality of the memory blocks 103, such as page buffers / sense amplifiers 50, row decoders / word line drivers 40, column decoders / bit line drivers 52, control circuitry 70, voltage generators 65, and input / output buffers 55. These circuits can include active and / or passive semiconductor devices, such as transistors, diodes, capacitors, resistors, etc., as would be apparent to one of ordinary skill in the art.

[0073] In some embodiments, the memory block 103 can be coupled with the row decoder / word line driver 40 via a word line (“WL”) 333, a lower select gate (“LSG”) 332, and a top select gate (“TSG”) 334. The memory block 103 can be coupled with the page buffer / sense amplifier 50 via a bit line (“BL”) 341. The row decoder / word line driver 40 can select one of the memory blocks 103 on the memory die 100 in response to X-path control signals provided by the control circuitry 70. The row decoder / word line driver 40 can transfer voltages provided from the voltage generators 65 to the word lines according to the X-path control signals. During a read operation and a program operation, the row decoder / word line driver 40 can transfer a read voltage V read and a program voltage V pgm to the selected word line, and transfer a pass voltage V pass to the unselected word line.

[0074] In some embodiments, the column decoder / bit line driver 52 can transfer an inhibit voltage V inhibitTransfers to unselected bit lines and connects the selected bit line to ground. In other words, the column decoder / bit line driver 52 can be configured to select or deselect one or more memory strings 212 according to Y-path control signals from the control circuit 70. The page buffer / sense amplifier 50 can be configured to read data from and program (write) data to the memory block 103 according to control signals from the control circuit 70. For example, the page buffer / sense amplifier 50 can store a page of data to be programmed into one of the memory pages 432. In another example, the page buffer / sense amplifier 50 can perform a verify operation to ensure that the data has been properly programmed into each memory cell 340. In yet another example, during a read operation, the page buffer / sense amplifier 50 can sense a current flowing through the bit line 341 that reflects the logic state (i.e., data) of the memory cell 340 and amplify the small signal to a measurable amplification.

[0075] In some embodiments, the input / output buffer 55 can transfer I / O data from / to the page buffer / sense amplifier 50, as well as addresses ADDR or commands CMD to the control circuit 70. In some embodiments, the input / output buffer 55 can serve as an interface between the memory controller 20 (in Figure 1 ) and the memory die 100 on the memory chip 25.

[0076] In some embodiments, the control circuit 70 can control the page buffer / sense amplifier 50 and the row decoder / word line driver 40 in response to the commands CMD transferred by the input / output buffer 55. During a program operation, the control circuit 70 can control the row decoder / word line driver 40 and the page buffer / sense amplifier 50 to program the selected memory cells. During a read operation, the control circuit 70 can control the row decoder / word line driver 40 and the page buffer / sense amplifier 50 to read the selected memory cells. The X-path control signals and the Y-path control signals include a row address X-ADDR and a column address Y-ADDR that can be used to locate the selected memory cells in the memory block 103. The row address X-ADDR can include a page index PD, a block index BD, and a plane index PL to identify the memory page 432, the memory block 103, and the memory plane 101 (in Figure 3 ), respectively. The column address Y-ADDR can identify a byte or a word in the data of the memory page 432.

[0077] In some embodiments, the voltage generator 65 can generate voltages to be provided to the word lines and the bit lines under the control of the control circuit 70. The voltages generated by the voltage generator 65 include a read voltage V read , a program voltage V pgm, by voltage V pass , inhibit voltage V inhibit , etc.

[0078] Note that, Figure 1 , Figures 2A-2B and Figures 3-4 The arrangement of electronic components in the memory system 10 and the memory die 100 in Figure 4 The components on the memory die 100 shown in Figure 4 The components on the memory die 100 shown in

[0079] Figure 5 A perspective view of a 3D memory structure 500 is shown, in accordance with some embodiments. In some embodiments, the memory die 100 can be a 3D NAND memory, and the 3D memory structure 500 can be a portion of the memory die 100, for example in the region 108 in Figure 3 The 3D memory structure 500 can include a staircase region 210 and a channel structure region 211. The channel structure region 211 can include a plurality of memory strings 212, each of which includes a plurality of stacked memory cells 340. The staircase region 210 can include a staircase structure.

[0080] In some embodiments, the 3D memory structure 500 can include a substrate 330, an insulating film 331 above the substrate 330, a layer of lower select gates (LSG) 332 above the insulating film 331, and a plurality of layers of control gates 333 (also referred to as “word lines (WL)”), which are stacked on top of the LSG 332 to form a film stack 335 composed of alternating conductive and dielectric layers. For clarity, the dielectric layers adjacent to the control gate layers are not shown in Figure 5

[0081] ​In some embodiments, the control gates of each layer are separated by the slit structures 216-1 and 216-2 through the film stack 335. The 3D memory structure 500 can also include a layer of top select gates (TSG) 334 on the stack of control gates 333. The stack of TSG 334, control gates 333, and LSG 332 can also be referred to as "gate electrodes." The 3D memory structure 500 can also include doped source line regions 344 in some portions of the substrate 330 between adjacent LSGs 332. Each memory string 212 of the 3D memory structure 500 can include a channel hole 336 extending through the insulating film 331 and the film stack 335 of alternating conductive and dielectric layers. The memory string 212 can also include a memory film 337 on the sidewalls of the channel hole 336, a channel layer 338 above the memory film 337, and a core fill film 339 surrounded by the channel layer 338. Memory cells 340 (e.g., 340-1, 340-2, 340-3) can be formed at the intersection of the control gates 333 (e.g., 333-1, 333-2, 333-3) and the memory string 212. A portion of the channel layer 338 can be responsive to the corresponding control gate and is also referred to as the channel 338 of the memory cell. The 3D memory structure 500 also includes a plurality of bit lines (BL) 341 connected to the memory strings 212 above the TSG 334. The 3D memory structure 500 can also include a plurality of metal interconnect lines 343 connected to the gate electrodes through the plurality of contact structures 214. The edges of the film stack 335 are configured to be stepped to allow electrical connection to each layer of the gate electrodes.

[0082] In Figure 5 , three layers of control gates 333-1, 333-2, and 333-3 and one layer of TSG 334 and one layer of LSG 332 are shown for illustration purposes. In this example, each memory string 212 can include three memory cells 340-1, 340-2, and 340-3 corresponding to the control gates 333-1, 333-2, and 333-3, respectively. In some embodiments, the number of control gates and the number of memory cells can be greater than three to increase storage capacity. The 3D memory structure 500 can also include other structures, such as TSG cutouts, common source contacts (i.e., array common source), and dummy memory strings. For simplicity, these structures are not shown in Figure 5 . It is noted that, Figure 5 The 3D memory structure 500 shown is by way of example only and does not limit the scope of the application, and any other suitable 3D memory structure can also be employed.

[0083] Referring back to Figure 4In some embodiments, the storage blocks 103 can be formed based on floating gate technology. In some embodiments, the storage blocks 103 can be formed based on charge trapping technology. Charge trapping based NAND flash memory can provide high storage density and high intrinsic reliability. The stored data in the form of logical states (“states,” e.g., threshold voltages V th of the storage cells 340) depends on the number of charge carriers trapped in the storage film 337 of the storage cells 340.

[0084] In some embodiments, in NAND flash memory, read operations and write operations (also referred to as program operations) can be performed for a storage page 432, and erase operations can be performed for a storage block 103.

[0085] In some embodiments, in NAND memory, the storage cells 340 can be in an erase state ER or a program state PI. Initially, the storage cells 340 in a storage block 103 can be reset to the erase state ER as a logical “1” by enabling a negative voltage difference between the control gate 333 and the channel 338 such that the trapped charge carriers in the storage film of the storage cells 340 can be removed. For example, the negative voltage difference can be induced by setting the control gate 333 of the storage cells 340 to ground and applying a high positive voltage (erase voltage V erase ) to the ACS 430. In the erase state ER (“state ER”), the threshold voltage V th of the storage cells 340 can be reset to a lowest value.

[0086] In some embodiments, during programming (i.e., writing), a positive voltage difference between the control gate 333 and the channel 338 can be established by, for example, applying a program voltage V pgm (e.g., a positive voltage pulse between 10 V and 20 V) on the control gate 333 and grounding the corresponding bit line 341. As a result, charge carriers (e.g., electrons) can be injected into the storage film of the storage cells 340, thereby increasing the threshold voltage V th of the storage cells 340. Thus, the storage cells 340 can be programmed to the program state PI (“state PI” or logical “0”).

[0087] In some embodiments, the state (e.g., state ER or state PI) of a storage cell can be determined by measuring or sensing the threshold voltage V th of the storage cell. During a read operation, a read voltage V read may be applied on the control gate 333 of the storage cell, and a current flowing through the storage cell can be measured at the bit line 341. A pass voltage V pass may be applied on unselected word lines to turn on the unselected storage cells.

[0088] In some embodiments, the NAND flash memory can be configured to operate in a single-level cell flash (SLC) mode. To increase storage capacity, the NAND flash memory can also be configured to operate in a multi-level cell flash (MLC) mode, a triple-level cell flash (TLC) mode, a quad-level cell flash (QLC) mode, or a combination of any of these modes. In the SLC mode, a storage cell stores 1 bit and has two logic states ("states"), logic {1 and 0}, i.e., states ER and PI. In the MLC mode, a storage cell stores 2 bits and has four logic states, logic {11, 10, 01, and 00}, i.e., states ER, PI, P2, and P3. In the TLC mode, a storage cell stores 3 bits and has eight logic states, logic {111, 110, 101, 100, 011, 010, 001, 000}, i.e., states ER and states PI-P7. In the QLC mode, a storage cell stores 4 bits and has sixteen logic states. The memory controller 20 of the storage system 10 (see Figure 1 ) can convert data received from the host 15 into corresponding logic states of the storage cells on the memory die 100, and vice versa.

[0089] Figure 6 Fig. 1 shows threshold voltage V th distributions of a NAND flash memory programmed in a triple-level cell flash (TLC) mode, according to some embodiments. th In some embodiments, each state of a storage cell can correspond to a particular range of threshold voltage V th distribution of threshold voltage V pgm may be incrementally increased by adding a step-up pulse V step . Thus, the eight TLC states can be programmed from state PI with a lower threshold voltage to state P7 with a highest threshold voltage.

[0090] In some embodiments, after programming, the eight TLC states ER and PI-P7 can be verified in a verification process by using one or more read reference voltages V R1 -V R7 . By applying one or more of the read reference voltages V R1 -V R7 to the control gate of a target storage cell, a range of threshold voltage V th of the storage cell can be determined. For example, to verify whether a storage cell is in state ER, a read reference voltage V R1If the target storage cell is in state ER, the threshold voltage V th is lower than the read reference voltage V R1 . The target storage cell can be turned on and form a conductive path in the channel. If the target storage cell is in any of the states P1-P7, the threshold voltage V th is higher than the read reference voltage V R1 . The target storage cell is thereby turned off. By measuring or sensing the current through the target storage cell on the corresponding bit line via the page buffer / sense amplifier 50, the threshold voltage V th or the state of the target storage cell can be verified.

[0091] In some embodiments, as mentioned above, for determining the two states ER and P1 stored in SLC mode, it is sufficient to rely on the read reference voltage V R1 only. For determining the four states ER and P1-P3 in MLC mode, the read reference voltages V R1 , V R2 , and V R3 may be used. For determining the eight states ER and P1-P7 in TLC mode, the read reference voltages V R1 -V R7 may be used. For example, in TLC mode, the threshold voltage of state ER is lower than V R1 , while the threshold voltage of state P7 is higher than V R7 , with the threshold voltage of state P1 being between V R1 and V R2 . States P2-P6 can be determined similarly.

[0092] Figure 7 A process flow 700 for programming a storage cell to a target logical state (e.g., state P1) is shown in accordance with some embodiments. It should be appreciated that the process flow 700 is not exhaustive and that other operational steps can also be performed before, after, or between any of the illustrated operational steps. In some embodiments, some operational steps of the process flow 700 can be omitted or include other operational steps, which are not described herein for the sake of simplicity. In some embodiments, the operational steps of the process flow 700 can be performed in a different order and / or variations.

[0093] In some embodiments, at operational step S705, a program loop count (PLC) can be reset, e.g., PLC = 0. Operational step S705 can be started when the memory controller 20( Figure 1 ) sends a command to the memory die 100 for programming a storage cell on the memory die 100.

[0094] At operation step S710, the storage cell is programmed by applying a programming voltage V pgm to the word line of the storage cell. And the PLC can be incremented by 1 at operation step S715, i.e. PLC = PLC + 1. The programming voltage V pgm may be selected according to the target logic state of the storage cell, wherein the target logic state depends on the programming data sent by the memory controller 20.

[0095] At operation step S720, the threshold voltage V th of the storage cell can be determined by applying a first read reference voltage on the word line of the storage cell and measuring the current flowing through the storage cell at the corresponding bit line. th The threshold voltage V R1 of the storage cell is compared with the first read reference voltage (also referred to as program verify level). For example, if the storage cell is to be programmed to the target logic state P1, the first read reference voltage V R1 (see Figure 6 ) can be used, because for state P1, the condition is that the threshold voltage of the storage cell is between the read reference voltage V R1 and V R2 .

[0096] At operation step S725, it is determined whether the threshold voltage V th of the storage cell is higher or lower than the first read reference voltage V R1 . As mentioned before, if the threshold voltage V th of the storage cell is lower than the first read reference voltage V R1 , the storage cell can be turned on, thereby forming a conductive path in the channel. The current measured at the corresponding bit line by the page buffer / sense amplifier 50 (in Figure 4 ) is relatively high. If the threshold voltage V th of the storage cell is higher than the first read reference voltage V R1 , the storage cell is turned off and the current measured at the corresponding bit line by the page buffer / sense amplifier 50 is relatively low.

[0097] If the threshold voltage V th of the storage cell is determined to be lower than the first read reference voltage V R1 , the process flow 700 proceeds to operation step S730, in which it is checked whether the PLC is smaller than a maximum value PLC max .

[0098] In some embodiments, the maximum value PLC max may be a predetermined value, e.g. PLC max = 25. In some embodiments, the maximum value PLC maxThe PLC can be determined from a set of memory cells selected across different memory dies during a pre-screening program test.

[0099] If the PLC is less than the PLC max , then at operation step S735, the program voltage V pgm can be increased by an amount AV such that the program voltage V pgm = V pgm + AV. And at operation step S710, the memory cell can be reprogrammed again with the increased program voltage V pgm .

[0100] Operation steps S710-S735 can be repeated until a desired target threshold voltage V th is reached for the memory cell. However, if at operation step S730, the PLC max has been reached but the memory cell is still not programmed to the target logic state, then at step S740, the memory cell program failure can be identified.

[0101] If at operation step S725, the threshold voltage V th of the memory cell is determined to be higher than the first read reference voltage V R1 , then at operation step S745, the threshold voltage Vth of the memory cell can be compared to a second read reference voltage. If the memory cell is to be programmed to the target logic state PI, then the second read reference voltage V R2 (see Figure 6 ) can be used. If at operation step S750, the threshold voltage V th of the memory cell is determined to be lower than the second read reference voltage V R2 , then at operation step S755, the memory cell can be identified as a program pass (i.e., programmed to the target logic state). In SLC mode with only states ER and PI, the second reference voltage can be omitted.

[0102] However, if at operation step S750, the threshold voltage V th of the memory cell is determined to be higher than the second read reference voltage V R2 , then at step S740, the memory cell program failure can be identified because during programming, the threshold voltage of the memory cell can be increased by applying a program voltage V pgm on the memory cell control gate (i.e., the corresponding word line), but cannot be decreased. In 3D NAND memory, after the memory cell is erased and reset to state ER, the memory cell can be reprogrammed to a logic state with a lower threshold voltage. The erase operation resets all memory cells in a memory block to state ER because the memory cells in the same memory block share the same array common source 430.

[0103] Referring back Figure 4 In some embodiments, while a storage block (e.g., storage block 103) is the smallest erasable unit in a 3D NAND memory, a storage page (e.g., storage page 432) is the smallest addressable unit for read and program operations. During read and program operations, data (i.e., logical states) in a selected storage page of a storage block can be read or programmed according to a page index PD and a block index BD contained in an address ADDR received by control circuit 70. Data in a selected storage page can be read or programmed by applying a pass voltage V inhibit A storage cell that has reached a target logical state (i.e., a target threshold voltage) can be inhibited from further programming.

[0104] The above has described embodiments regarding the structure of a 3D NAND memory and the functioning of a 3D NAND memory. In some embodiments, it is desirable to provide reliable storage cells for programming and subsequent erasing and reprogramming. Referring to Figure 7 The method of FIG. 7 shows an example of how to verify a storage cell after a program operation. At the end of process flow 700, a storage cell can pass or fail the verification process. Those skilled in the art will appreciate that once the program and verify operations on a storage cell have ended (either passed or failed), the program and verify operations can move to the next storage cell (i.e., process flow 700 can restart at the next storage cell). In some embodiments, moving to the next storage cell can include “masking” the completed storage cell so that the algorithm iteration of process flow 700 does not erroneously repeat on the same storage cell. Masking a storage cell (or masking a storage memory bit) can be described as temporarily or permanently marking or identifying a storage cell so that future operations can be adjusted (e.g., skipped) based on the marking. In one example, a bit can be permanently masked when an uncorrectable fault is found. A NAND controller can inhibit further use of a defective storage cell. One example of masking is described above with reference to Figure 4 inhibit .

[0105] In some embodiments, process flow 700 can be sufficient for storage cells that are to receive programming (i.e., an operation that changes the state of a storage cell from ER to a higher state (e.g., PI)). According to process flow 700, the verify process starting at S720 can follow the programming step at S710 (e.g., program a storage cell with a program voltage and then verify correctness). But what about storage cells that are to remain in the ER state? In an example scenario, an 8-bit string is sought to be written to a storage page 432 Figure 4 ​) one of the eight bit strings can include bits corresponding to the electronic state {P1 ER ER P1 ER P1 ER ER}. It can be appreciated that a memory cell that receives a P1 state will go through step S710 and subsequently be verified by step S720 and the steps thereafter. However, a cell that remains in the ER state will not go through steps S710 and S720. It is common practice to erase a memory block prior to writing new data to the block (e.g., typically, all memory cells in a block start in the ER state prior to programming commencing). Thus, in order to write the ER state of the programmed data to the memory cell, the NAND does not perform any operation on the memory cell (i.e., the memory cell is skipped, which relies on the assumption that the memory cell is already in the ER state).

[0106] It is reiterated that in some embodiments, programming a page does not equate to programming every memory cell in the page. Some cells can skip receiving the program operation. Thus, programming a page can include programming only one or more of the memory cells in the page. Verification is performed when a memory cell is programmed (e.g., ER→P1 can trigger a verify operation), but not when a memory cell remains in ER (e.g., ER→ER memory cells are not programmed and thus can skip verification). Problems can arise where verification is skipped. This can be a problem if the existing state in the skipped memory cell is not the expected ER (e.g., the memory cell has a persistent P1 state). In this case, a write operation will assume that the memory cell is in the ER state, which is not the case. Conversely, the memory controller will assume that the “write” operation ER→ER has been successfully performed (due to lack of verification), but what actually happened is that the P1 state persisted (P1→P1). When data is later read from this memory cell, the data will be found to be corrupted. Thus, there is a need for a method and system to provide data protection before uncorrectable error correction code (UECC) occurs, so that the chance of data loss can be minimized.

[0107] To mitigate errors as described above, operations can be introduced to make the processing such as processing flow 700 more robust.

[0108] Figure 8 illustrates a processing flow 800 for storing data in a NAND memory and self-verification of the data, in accordance with some embodiments. In some embodiments, the functions described in the method steps can be performed by circuitry on the NAND memory device itself (e.g., one or more processors 22( Figure 1 ), control circuitry in the memory chip 25( Figure 10to be programmed in the page). The page of the NAND memory can include memory cells (e.g., page 432 Figure 4 )) corresponding to the word line. The programming of the selected page can include a plurality of program operations (step S810) using a plurality of program voltages. The programming of the selected page can also include a plurality of verify operations (step S820). Some of the plurality of verify operations can be performed after corresponding ones of the plurality of program operations to determine from the program data whether a programmed memory cell of the plurality of memory cells has a threshold voltage level. At step S820, a verification of the programming of the memory cells can be performed to determine whether the programming was performed correctly or whether step S810 should be performed again (see, e.g., step S735 Figure 7 )) (see, e.g., S720 Figure 7 ))).

[0109] In some embodiments, at step S860, the programmed memory cell among the memory cells can be masked after the verification of step S820 (e.g., if the result is pass, the memory cell is masked for the remainder of the data storage process; if the result is fail, restart at S810). At step S865, a check can be performed to determine whether a target number of bits in the page have been programmed from the program data (e.g., a check to see whether the storage of the program data is complete or incomplete). In other words, a decision step is performed to determine whether the final bit from the program data has been programmed in the page (e.g., the final bit can be the last non-ER state programmed in the page from the program data). If the storage has not ended, the process can return to step S810 and continue to move to subsequent memory cells for the remainder of the programming. It should be appreciated that the process flow 800 can include determining completion of the programming of the selected page based on a return of a pass result for each of the plurality of verify operations. Another condition to determine completion of the programming can be to consider the n bits of the memory cell storing the program data, where n is an integer greater than 1. The determination can be based on programming the n-th bit of the program data in the page.

[0110] In some embodiments, at step 870, another verification operation can be performed by performing a read operation on the page and comparing data determined from the self- verifying read operation to the programmed data used to initiate the process flow 800. The steps of Figure 8 can be implemented as a firmware method in a NAND controller (e.g., controller 20 Figure 1 )).

[0111] In some embodiments, at step S875, the process flow 800 of storing data in a NAND page is ended. The ending can be marked by a pass or fail determination from the additional verification step S870. The pass / fail determination can be based on an exact match between the stored data determined by the read operation on the page and the programmed data used to initiate the process flow 800. In some embodiments, the pass / fail determination can be based on a fail count threshold. For example, if the fail bit count is below a given threshold, the NAND firmware can determine a pass result. It should be appreciated that the term "below threshold" is also intended to include the range of "below or equal to threshold" as the difference between the two terms is merely a shift in the threshold (e.g., below 10 and below or equal to 9 are the same). Similar logic applies to the terms "above threshold" and "above or equal to threshold". The threshold can be adjusted based on the needs or preferences of the environment in which the NAND memory is to be implemented. For example, a data storage center with multiple redundant backup mechanisms can use a different threshold than a user on a personal computer.

[0112] In some embodiments, the timeline shown in Figure 8 illustrates an example of the processes described thus far. For example, there can be multiple loops of steps S810 and S820 to program and verify multiple storage cells in a page of NAND memory (other steps are not shown on the timeline for clarity, but should be understood to be present). At the end of the loops (i.e., when the programmed data has been fully transferred to the page), step S870 is performed to verify the stored data using the internal read capability of the NAND memory. The programming of the page of NAND storage is then ended at step S875.

[0113] As mentioned previously, in some embodiments, the process flow 800 can be used to increase the robustness of the NAND memory in cases where the process flow 700 Figure 7 ) is not performed, for example, when the data to be written is in the ER state, but the actual state present in the corresponding storage cell is PI, etc. This example can occur when, for example, a first program stores data on a page but a subsequent second program stores the data of the second program on the same page (e.g., over-programming of the memory). The over-programming error can be caused by a poor encoding. Whether or not step S820 (or Figure 7the self-verification of step 870 can read the entire page, detecting any errors that step S820 can have missed. In this way, data corruption can be prevented. For example, if a fail result is issued at step S875, the firmware in the memory controller can select a different page to store the programming data. If the read operation at step S870 returns a fail result (e.g., masking a region of the NAND memory), the NAND memory can also prevent further use of one or more faulty regions of the NAND memory. Moreover, step S870 can be a single instance at the end of the data storage process, which can result in a much smaller time burden than, for example, performing read verification after each loop.

[0114] In some embodiments, the NAND firmware implementation of step S870 allows for additional verification to be performed quickly at an early stage of the data storage operation. Since the read of the page is performed by the hardware on the NAND memory itself, the read operation can also be referred to as an internal read, or self-verification. In contrast, if the external host computer were to perform step S870, the resulting additional time burden can be high enough to discourage performing step S870.

[0115] In some embodiments, the additional verification of step S870 can come with certain drawbacks. For example, even though the internal firmware implementation is faster than the host firmware implementation, the verification step S870 can still add time to the read operation to a degree that can not be desirable for a consumer of the NAND memory. After all, step S870 is an additional read step, and can add, for example, tens of microseconds to the data storage process. Accordingly, the NAND memory firmware can be implemented with features that allow for adjusting how the NAND firmware performs step S870. That is, in some embodiments, the method can include receiving input at the NAND memory to adjust the verification performed on the storage of data in the page.

[0116] In some embodiments, the input can allow, disable, time-shift, etc. which areas of the NAND memory will receive the read operation of step S870 and limit the read operation of step S870 from being performed. Certain areas of the NAND memory can be more reliable than others. Thus, the input can be used to specify one or more areas of the NAND memory to allow or disable the read operation of step S870 from being performed. The one or more specified areas can include, for example, at least one of an area for SLC, an area for MLC, an area for TLC, an area for QLC, a page, a block, or a plane, to name a few non-limiting examples. As an example, the input can include instructions to perform self-verification for a first SLC portion, a first TLC portion, and a second TLC portion, and a particular page. As another example, the input can include instructions to perform self-verification for a particular QLC portion. Terms such as "at least one of element 1, element 2, and element 3" can refer to permutations such as one or more of element 1; one or more of element 2; one or more of element 1 and one or more of element 2; one or more of element 1 and one or more of element 3; one or more of element 2 and one or more of element 3; or one or more of element 1, one or more of element 2, and one or more of element 3. Corresponding permutations for groups with fewer or more elements are envisioned.

[0117] In some embodiments, the input can be implemented as a prefix to a command provided by a user for performing a data storage operation. There can be one or two bits to specify the SLC / MLC / TLC / QLC mode. For example, there can be three bits to specify any one of an upper page, a middle page, or a lower page of a TLC page.

[0118] In some embodiments, the NAND firmware can determine when and where to implement self-verification in an automated manner (without user input). For example, the NAND memory can implement a record of which storage cells or groups of storage cells are defective or otherwise at risk. Based on the record, the NAND firmware can implement self-verification when data is stored in a storage cell known to have an associated risk.

[0119] In some embodiments, the input can also adjust how certain data is handled during the data storage process (e.g., delay clearing cached data).

[0120] Figure 9Time lines 900 and 902 for adjusting operations performed using NAND firmware are shown in accordance with some embodiments. In some embodiments, a NAND memory product can have a cache system implementation. The cache system can conflict with a NAND firmware self-verification feature (e.g., the read operation of step S870 in FIG. 8). Thus, it is contemplated that the NAND firmware can adjust operations depending on whether a cache is implemented in the NAND memory. The adjustment of NAND operations can be controlled by user input or by an automatic process in the NAND firmware.

[0121] In some embodiments, time line 900 shows the creation of a cache data transfer A 904 in a cache area of the NAND memory. The cache data transfer A is then used by a program A, which is represented in time line 900 as program busy A 906. For example, program busy A 906 can be an operation to program memory cells of a page in the NAND memory (e.g., according to process flow 800 (FIG. 8)). During program busy A 906, another cache data transfer 908 can be prepared for a future execution of program B, which is represented in time line 900 as program busy B 910. Once program busy A 906 ends, the preparation of cache data transfer B 908 allows program B to be executed immediately. One problem is that the creation of cache data transfer B 908 overwrites the existing cache data transfer A 904. After all, the cache storage is designed to be small for fast and temporary storage. Then, it can be that program busy A 906 attempts to perform self-verification step S870 (FIG. 8) only to find that the cache has been claimed by program B. Note that the data of the cache can be used as a basis for comparison when performing a page read at step S870 (FIG. 8).

[0122] Thus, in some embodiments, when the NAND memory employs a cache, the NAND firmware can adjust operations to operate as shown in time line 902. Time lines 900 and 902 are similar in terms of the processes performed, however, time line 902 moves the creation of cache data transfer B 908 to a timing after program busy A 906. Notably, this is a tradeoff in which the time savings of the cache are abandoned to allow for the use of NAND firmware self-verification. By arranging the timing of cache data transfer B 908 in this way, program busy 906 can freely include step S870 (FIG. 8) without the risk of finding a cache that has been overwritten. In some embodiments, the NAND firmware can adjust the timing. For example, the NAND firmware can be configured to detect the use of a cache and then perform a delay of the creation of cache data transfer B 908 based on the detection.

[0123] As previously mentioned, in some embodiments, the NAND firmware implementation of step S870 (Figure 8) allows for fast execution of self-verification at an early stage of the data storage operation. This functionality can be used to improve the debugging process, for example, to fix issues related to double programming.

[0124] Figure 10 A process flow 1000 for programming a page of NAND memory is shown, in accordance with some embodiments. In particular, Figure 10 Three snapshots of a portion of a NAND memory in which a double programming event occurs are shown. Figure 10 The example scenario of Figure 10 should be understood as non-limiting (e.g., more or less than 6 pages of NAND memory can be written to by the program, there can be other ways to cause a double programming error, etc.). At step S1002, a first set of instructions can be executed by one or more computing devices (e.g., host computer 15 Figure 1 The first set of instructions can include instructions for storing data to a page of NAND memory according to first program data. In Figure 10 In the example shown, the first set of instructions has caused the memory controller 20 Figure 1 to store data in PgO-Pg6 (denoted as PgO pgm-Pg6 pgm) according to the first program data. Also shown at step S1002 is the address at which the next storage event begins. It is represented by the next program pointer 1008, which points to Pg7 (pages Pg7 and beyond are in an erased state (“ers”) and ready to receive program data).

[0125] In some embodiments, at step S1004, a second set of instructions can be executed by one or more computing devices. The second set of instructions can include instructions for storing data to a page of NAND memory according to second program data. However, due to an error in the encoding of the data storage operation, the program pointer is misaddressed to Pg4, which stores data corresponding to the first program data. This event can be referred to as a double programming event. The misaddressing is represented by the erroneous program pointer 1008’ and the corresponding overwritten page is denoted as Pg4 double program 1010.

[0126] In some embodiments, the data stored in Pg4 is not used by the one or more computing devices until a later time (e.g., minutes later, days later, etc.). At step S1006, the one or more computing devices perform an operation to read back the data from Pg4 of the NAND memory. The read fails due to the uncorrectable error correction code in Pg4. There is a high likelihood that the data at Pg4 has been corrupted at this time, neither representing the first programmed data nor the second programmed data. This occurs because, as described above, the storage cells that receive the ER state are skipped. For example, a storage cell that has a state {ER P1 ER P1} that is incorrectly overwritten by the second programmed data {P1 ER P1ER} can result in the storage cell actually storing {P1 P1 P1 P1}. The skipping of the ER state results in a combination of P1 states of the first and second programmed data, resulting in corrupted stored data (garbage data that does not represent either the first programmed data or the second programmed data).

[0127] In some embodiments, to correct the misaddressed error, e.g., the error described with reference to Figure 10 the developer can implement debugging measures to determine the cause of the error. Once the cause of the error is determined, the instruction code can be corrected as appropriate. Again, the data stored in Pg4 can not be read for days. This presents a significant obstacle to debugging efforts, as the discovery of the misaddressed error can occur much later. Many operations can occur in the time between the dual programming event and the subsequent read failure. Since the developer is not benefited by hindsight, the developer has no choice but to suspect that all operations can be at issue. The developer can then set up tests for each operation to rule out the operation that nominally worked. It should be appreciated that this can be a tedious process if the number of tests to be performed is in the hundreds or thousands. To reduce this burden, the debugging process can be enhanced by implementing the NAND self-verification embodiments disclosed herein.

[0128] Figure 11Processing flows 1100, 1102, and 1104 are shown that include a double program event, according to some embodiments. By comparing the differences of each processing flow, it is apparent that the NAND self-verification method in the embodiments herein can significantly enhance the debugging process by detecting the error immediately after it occurs. In some embodiments, a program executed by one or more computing devices encounters a UECC memory. The source of the error is unknown, for example, it can be a defect in the code while reading data from the NAND of the executed program, a defect in the logic of the one or more computing devices, an error in the NAND memory, a defect in the NAND firmware code, etc. To determine the cause of the UECC, a developer can prepare a test case (e.g., a simulation). The test case can include execution of the program that encountered the UECC, but subject to specific constraints (e.g., test case parameters) imposed by the developer.

[0129] In some embodiments, flow 1100 can include steps S1106, S1108, S1112, and S1114. At step 1106, a test case is executed. At step S1108, the test case can interact with end-user firmware (e.g., firmware intended for consumer use) in order to store data in the NAND memory, for example, using processing flow 700( Figure 7 ). The end-user firmware can include, for example, firmware in the host 15( Figure 1 ) and / or firmware in the NAND memory. In the context of processing flow 1100, it should be appreciated that the NAND firmware does not implement NAND self-verification (e.g., it is disabled or not present). At step S1112, a double program write occurs in a page of the NAND memory (e.g., Pg4 double program 1010( Figure 10 )). At step S1114 (which can be minutes later, days later, or more), a UECC read is encountered as a result of the double program. In this case, the developer of the program has little additional information about how the UECC occurred, except that the test constraints were able to produce the UECC read at step S1114. The possible suspect of the error can be any operation performed by the program and firmware between steps S1106 to S1114. The developer is unaware of the double program event at step S1112, and it is the goal of the present disclosure to discover it.

[0130] In some embodiments, a developer can implement a processing flow 1102 that has some enhancements to the processing flow 1100. The processing flow 1102 can include steps S1106, S1110, S1112, and S1116. Step 1106 can be as previously described. The difference now is that at step 1110, the test case is allowed to interact with debug firmware (e.g., provided by the developer). The debug firmware is a workaround that attempts to stop the computer operation closer to whatever caused the UECC read. The debug firmware can include, for example, instructions that read certain outputs of the process in the test case and then stop the running of the test case when an anomaly is found in one of the outputs. However, at step S1112, a double programming error occurs, but the verification of the written data has not been performed for some time. At step S1116, the debug process detects the anomaly and returns a failure result, stopping the test case. In this case, the debug process implemented by the developer is better designed to rule out possible error causes by detecting the anomaly before the UECC read event in step S1114 of the processing flow 1100. However, the debug process can be further enhanced by implementing the NAND self-verification embodiments disclosed herein, as in processing flow 1104.

[0131] In some embodiments, another problem with using debug firmware is that it can add a significant amount of runtime and overhead. For example, the debug firmware can be set to introduce a redundant next program pointer that is used to track the next program pointer 1008( Figure 10 ). The redundant program pointer can be set to point to a dummy layer or a deep layer. The redundant program pointer and the next program pointer 1008 can be compared to determine a match or whether a data corruption has occurred. This process can add a significant amount of debug code and take a significant amount of time to reach the point of failure. This can result in high overhead because there is more firmware code to check the logic to see if the NAND sequence is failing. This solution can change a large portion of the firmware. The firmware can be thought of as a pipeline. Each time the comparison of the redundant program pointer is performed, the pipeline is paused, which adds a significant amount of time.

[0132] In some embodiments, the process flow 1104 can include steps S1106, S1110, S1112', and S1116. Steps 1106 and S1110 can be as previously described. The process flow 1104 differs in that self-verification via the NAND firmware is enabled (e.g., the read step of S870 (FIG. 8) is enabled). In some embodiments, step S870 (FIG. 8) can be in a disabled state to improve system performance, but can be enabled when needed. For example, the debug firmware can include instructions that cause the NAND firmware to turn on the NAND self-verification feature. At step S1112', a double program error occurs. In contrast to the previously presented process flows, the process flow 1104 can detect the double programmed page at the read back step. The read back fails, and the NAND self-verification process issues a failure indication that the data in the particular page of the NAND memory is in error. This indication can be used to stop the test scenario and the debug process at a point in time close to the double program event. This information is valuable to quickly identify which part of the code is the cause of the double program error. That is, debugging can be performed based on the timing of the program stop. Moreover, in contrast to the redundant program pointer scenario described above (which adds a significant amount of time and overhead), using step S870 (FIG. 8) does not implement such a wide-ranging change to the firmware operation, and the timing impact is less severe. Step S870 is a fast page read using an internal capability of the NAND memory.

[0133] A double program event and subsequent detection method can be described in the following manner. In some embodiments, a selected page of a NAND flash device can be programmed according to first program data. The selected page can then be programmed according to second program data. The selected page can include memory cells corresponding to a word line (e.g., page 432 Figure 4 ). The programming of the selected page can include a plurality of program operations using a plurality of program voltages (e.g., steps S710 Figure 7 ) or S820 (FIG. 8)). The programming of the selected page can also include a plurality of verify operations. Some of the plurality of verify operations can be performed after a corresponding some of the plurality of program operations to determine whether a programmed memory cell of the plurality of memory cells has a threshold voltage level according to the first program data or the second program data (e.g., steps S720 Figure 7 ).

[0134] Then, in some embodiments, the selected page can be subjected to a self- verification using firmware associated with the NAND memory to determine whether the stored first data was overwritten (or whether the second data was overwritten if the instructions were executed in a different order). The method can include issuing a failure indication upon determining that the data stored at the selected page was overwritten. The self-verification can include performing an internal read operation by the NAND flash device of the selected page (e.g., step S870 (FIG. 8)) to determine the data stored at the selected page.

[0135] It should be appreciated that, in some embodiments, the features described with reference to Figure 11 the other figures can also incorporate the features described. For example, input for adjusting the performance of read operations (e.g., enabling step S870 (FIG. 8)) can be provided for the debug firmware and / or the NAND firmware. In another example, if the NAND memory has a cache system, the NAND self-verification can be configured to interact with the cache features described with reference to Figure 9 the other figures. In yet another example, input can also be used to limit the areas in the NAND memory for which the NAND self-verification is used, as described with reference to FIG. 8.

[0136] Figure 12 A timeline 1200 of a debug double program event is shown, in accordance with some embodiments. In some embodiments, the upper side of the timeline 1200 represents events related to the debug firmware. The lower side of the timeline 1200 represents events related to a test case of a program. The debug firmware and the test case can implement one or more of the features described with reference to Figure 11 the other figures.

[0137] In some embodiments, the debug firmware begins at time 1202. At time 1204, the debug firmware sends input to the firmware of the NAND memory to enable NAND self- verification, as described with reference to FIG. 8, Figure 9 and / or Figure 11 the other figures. At time 1206, a test case of a program can be run. Based on the requirements of the test case, it is contemplated that the test case is started at this point in time, or that the test case was previously started and continues to run at time 1206. At time 1208, the NAND self-verification feature determines a failure due to a double program event. At time 1210, the debug firmware and / or the NAND firmware are instructed to stop. At time 1212, the test case is stopped. At time 1214, debugging begins. Because the test case and the firmware were stopped immediately after the double program event, the debugging step can be significantly simplified, as it is easier to identify the section of code that caused the double program event to occur.

[0138] In some embodiments, debugging can be performed by one or more computing devices (e.g., host 15 Figure 1 )).

[0139] In some embodiments, the NAND self-verification features disclosed herein can be implemented in a method involving data backup for protection against data corruption. One example of a data backup scheme can include a RAID arrangement of storage drives (e.g., using physical drives, logical drives, or a combination thereof). The storage drives can include one or more NAND memory devices. The RAID arrangement can rely on so-called parity bits at the end of each block for protection. Typically, the RAID arrangement relies on controller hardware support to instruct the linked storage drives to operate in a redundant arrangement. The additional controller hardware support results in additional RAM and die size costs. Furthermore, the amount of protection provided by each parity group can be limited (e.g., one data error per parity group).

[0140] In some embodiments, an alternative to a RAID arrangement for protecting data in NAND memory can be to implement so-called SLC backup.

[0141] Figure 13 A process flow 1300 for performing SLC backup is shown in accordance with some embodiments. In some embodiments, standard MLC programming, TLC programming, or QLC programming will be performed on the NAND memory. It is suspected that in some portions of the NAND memory, certain memory cells used for MLC programming, TLC programming, or QLC programming have an inherently associated risk (e.g., one or more memory cells can not properly receive programming). Since SLC programming is more reliable than MLC programming, TLC programming, or QLC programming, redundant SLC programming will be performed along with the original MLC programming, TLC programming, or QLC programming.

[0142] In some embodiments, programming data is provided for storage in the NAND memory. At step S1302, a page of the NAND memory is programmed using MLC programming, TLC programming, or QLC programming in accordance with the programming data (e.g., using steps in process flow 700( Figure 7 ). At step S1304, the MLC programmed, TLC programmed, or QLC programmed page is read back from the NAND memory using one or more computing devices (e.g., host computer 15( Figure 1 )). Note that the host firmware can issue instructions to read from the NAND memory, rather than from the firmware 21( Figure 1) to initiate a page read instruction. At step S1306, MLC programming, TLC programming, or QLC programming can also be programmed in a suitable number of SLC pages in the NAND memory (e.g., TLC programming data can be written to three SLC pages). The programmed data saved to the SLC region of the NAND memory can provide a reliable backup for data in the less reliable MLC region, TLC region, or QLC region of the NAND memory. However, the time burden associated with the process flow 1300 can be undesirable, especially the time spent performing read-back using the host firmware.

[0143] The NAND self-verification methods disclosed herein can be used to modify the SLC backup scheme and shorten the time burden of performing data backup, thereby improving the performance of data protection methods in NAND memory systems. However, before describing the backup operation using the NAND self-verification methods, it is instructive to first describe a method for identifying unreliable regions in a NAND memory.

[0144] Figure 14 A process flow 1400 for identifying unreliable regions in a NAND memory is shown, in accordance with some embodiments. In some embodiments, it should be appreciated that an unreliable region can refer to a region in the NAND memory where there is a risk of being unable to correctly program data (e.g., the unreliable region has an associated data programming failure probability). In one non-limiting example, the risk can be quantified as a threshold probability. A low failure probability (e.g., below the threshold) can be considered reliable, and vice versa. The threshold probability can be determined based on the needs of a user or developer of the NAND firmware, for example.

[0145] In some embodiments, at step S1402, a data storage test can be performed on the NAND memory. The data storage test can include, for example, storing data in a page of the NAND memory (e.g., using the process flow 700( Figure 7 ))). The data storage test can also include reading back the stored data from the page of the NAND memory. At step S1404, an analysis can be performed on the data read back in step S1402. The analysis can include determining read failure regions in the NAND memory. The analysis can include generating a list of one or more reliable and / or unreliable regions. The reliability and / or unreliability can be quantified as described above (e.g., based on a failure probability). At step S1406, the determined reliability / unreliability regions can be stored and / or sent to the NAND firmware to inform subsequent SLC backup procedures.

[0146] Figure 15A process flow 1500 for implementing NAND self-verification in an SLC backup process is shown in accordance with some embodiments. In some embodiments, program data is provided for storage in a NAND memory using MLC programming, TLC programming, or QLC programming. However, in contrast to process flow 1300( Figure 13 ), the area of the NAND memory that is identified as unreliable can follow process flow 1500. The unreliable area can be determined using, for example, process flow 1400( Figure 14 ). The data provided is stored in pages of the NAND memory in accordance with the program data.

[0147] In some embodiments, at step S1502, the memory cells of a first page of the NAND memory can be programmed in accordance with the program data (e.g., using step S710( Figure 7 ) or S810 (FIG. 8)). The programming of the memory cells of the first page of the NAND memory can be performed using SLC programming, which is more reliable than MLC programming, TLC programming, or QLC programming.

[0148] In some embodiments, at step S1504, a verification can be performed to determine whether the programming of the memory cells of the first page was performed correctly (e.g., using step S720( Figure 7 ) or S820 (FIG. 8)). Note that the program data was originally provided for MLC programming, TLC programming, or QLC programming. Thus, the above-described data storage operations can be performed using SLC programming for an appropriate number of additional pages (e.g., QLC programming data can be written to four SLC pages).

[0149] In some embodiments, at step S1506, the memory cells of a second page of the NAND memory can be programmed in accordance with the program data (e.g., using step S710( Figure 7 ) or S810 (FIG. 8)). The programming of the memory cells of the second page of the NAND memory can be performed using MLC programming, TLC programming, or QLC programming. At step S1502, the data stored in the MLC area, TLC area, or QLC area of the NAND memory matches the data stored in the SLC area of the NAND memory.

[0150] In some embodiments, at step S1508, a verification can be performed to determine whether the programming of the memory cells of the second page was performed correctly (e.g., using step S720( Figure 7 ) or S820 (FIG. 8)).

[0151] In some embodiments, at step S1510, a read operation can be performed on the second page using firmware associated with the NAND memory to verify storage of data in the second page (e.g., NAND self-verification, similar to step S870 (FIG. 8)). Using the NAND internal firmware to verify the programmed second page (i.e., MLC page, TLC page, or QLC page) can perform the program verification faster than performing the verification using host firmware (as done in step S1304 Figure 13 ) of the SLC backup method includes not performing a read operation on the second page using firmware associated with one or more host computing devices configured to perform the SLC backup method, the one or more host computing devices being a host of the NAND memory. In other words, performing the read operation on the second page using firmware associated with the NAND memory further includes reducing the time required for completion of the backup method as compared to performing the read operation on the second page using firmware associated with the one or more host computing devices. In some examples, the completion speed can be improved by 5% or more, 10% or more, or 15% or more as compared to performing the read operation on the second page using firmware associated with the one or more host computing devices.

[0152] In some embodiments, at step S1512, the first page (SLC region) can be released in preparation for receiving new data (i.e., the data stored in the first page can be invalidated and / or erased).

[0153] Described with reference to FIG. 8 is that, in some embodiments, the input can be used to adjust the performance of the read operation using NAND firmware 21 Figure 1 ). Further, described with reference to Figure 14 is that one or more reliability / unreliability regions can be determined, stored, and / or sent to the NAND firmware to inform a subsequent SLC backup process. Figure 16 Additional details relating to these aspects of FIG. 8 and Figure 14 are shown, examples are provided with non-limiting capabilities. That is, it should be appreciated that additional features not explicitly shown in FIG. 8, Figure 14 or Figure 16 are still contemplated based on the embodiments described with reference to the other figures.

[0154] Figure 16 A process flow 1600 for implementing NAND self-verification in an SLC backup process is shown, in accordance with some embodiments. In some embodiments, at step S1602, one or more firmware can be initiated. The one or more firmware can include, for example, firmware 21 Figure 1The firmware of one or more computing devices, which provide enabled communication between the NAND memory and one or more host computing devices. At startup, at step S1604, the NAND self-verification feature in the NAND firmware can be enabled and configured (e.g., enabling execution step S870 (Figure 8)). Enabling the NAND self-verification feature can be achieved using inputs (e.g., reference time 1204 (…)). Figure 12 (as described in the original text). This input may also include information about unreliable areas of the NAND memory (e.g., as described in the reference). Figure 14 (As described).

[0155] In some embodiments, one or more regions of the NAND memory can be selected by using firmware associated with the NAND memory to enable read operations. NAND self-verification can be performed on the selected regions. Input can be used to specify one or more selected regions (e.g., unreliable regions). This can significantly improve the speed of the SLC backup process by not performing NAND self-verification on regions determined to be reliable (e.g., as referenced). Figure 14 (As described).

[0156] As previously described, in some embodiments, the input can be implemented as a prefix of a user-provided command for performing data storage operations. At step S1604, with the NAND self-verification feature enabled, various configurations can be made. For example, step S1604 may include configuring a word line bitmap (for selecting a word line or page), configuring a string bitmap (for selecting a string), configuring a page type bitmap (for selecting a specific page, such as an upper page, middle page, or lower page), and configuring a memory level type (for selecting MLC, TLC, or QLC). The selection of a specific location in the NAND memory was previously illustrated with reference to Figure 8.

[0157] In some embodiments, at step S1606, an SLC backup process can be performed on the selected region of the NAND memory specified in step S1604. Step S1606 can be performed by executing process flow 1500 (…). Figure 5 This can be achieved using steps S1502 and S1504. Figure 15 This is used to write to the SLC region of the NAND memory. Steps S1506 and S1508 can be used to write to the MLC, TLC, or QLC regions of the NAND memory. Figure 15 Performing NAND self-verification can be done using step S1510 (). Figure 15 This can be achieved using step S870 (Figure 8). Unnecessary SLC regions can be invalidated using step S1512.

[0158] The method steps in the embodiments disclosed herein can be performed in any conceivable order, and not all steps need to be performed.

[0159] In summary, the present disclosure provides a redundant backup method using NAND self-verification. The method can include programming a first page and a second page of a NAND flash device according to program data such that data stored in the first and second pages is redundant. Each of the first and second pages includes a plurality of memory cells corresponding to a first word line or a second word line. The programming of the first and second pages can include a plurality of program operations using a plurality of program voltages and a plurality of verify operations. Some of the plurality of verify operations can be performed after corresponding ones of the plurality of program operations to determine whether a programmed memory cell of the first page has a threshold voltage level according to the program data. The method can further include determining completion of the programming of the first and second pages based on a pass result returned by each of the plurality of verify operations. The method can further include, after the determining, performing a read operation of the second page by the NAND flash device to self-verify data stored at the second page according to the program data.

[0160] The present disclosure also provides a NAND flash device that can provide redundant data backup using NAND self-verification. The NAND flash device can include a memory array. The memory array can include a first page and a second page, each of the first and second pages including a plurality of memory cells corresponding to a first word line or a second word line. The NAND flash device can further include a peripheral circuit coupled to the first page and the second page via the first word line and the second word line. The peripheral circuit can program the first and second pages according to program data such that data stored in the first and second pages is redundant. The programming of the first and second pages can include a plurality of program operations using a plurality of program voltages and a plurality of verify operations. Some of the plurality of verify operations can be performed after corresponding ones of the plurality of program operations to determine whether a programmed memory cell of the first page has a threshold voltage level according to the program data. The peripheral circuit can further determine completion of the programming of the first and second pages based on a pass result returned by each of the plurality of verify operations. The peripheral circuit can further, after the determining, perform a read operation of the second page by the NAND flash device to self-verify storage of data at the second page according to the program data.

[0161] The present disclosure also provides a memory system for a redundant backup method using NAND self-verification. The system can include a NAND flash device that can store data. The NAND flash device can include a memory array. The memory array can include a first page and a second page, each of the first and second pages including a plurality of memory cells corresponding to a first word line or a second word line. The NAND flash device can also include a peripheral circuit coupled to the first and second pages via the first and second word lines. The peripheral circuit can program the first and second pages according to the program data such that the data stored in the first and second pages are redundant. The programming of the first and second pages can include a plurality of program operations using a plurality of program voltages and a plurality of verify operations. Some of the plurality of verify operations can be performed after corresponding ones of the plurality of program operations to determine whether a programmed memory cell of the first page has a threshold voltage level according to the program data. The peripheral circuit can also determine completion of the programming of the first and second pages based on a pass result returned by each of the plurality of verify operations. The peripheral circuit can also perform, after the determining, a read operation of the second page by the NAND flash device to self-verify storage of data at the second page according to the program data.

[0162] The foregoing description of the specific embodiments will so fully reveal the general nature of the present disclosure that others can easily utilize the disclosure for realizing various applications without undue experimentation. Consequently, the particular embodiments are presented for the purpose of illustration and disclosure and not limitation. It will be understood by those skilled in the art that various modifications can be made of the specific embodiments described without departing from the scope of the present disclosure. Accordingly, the disclosure is intended to embrace all such alterations, modifications, and variations caused by those skilled in the art based on the teachings presented herein. It is intended that the description contained hereinadequately describes and enables those skilled in the art to make and use the claimed subject matter.

[0163] The embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of the functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

[0164] The Summary and Abstract sections can set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventors, and thus, are not intended to limit the present disclosure and the appended claims in any way.

[0165] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A programming method for a NAND flash device, comprising: programming programming data to a first region or a second region of the NAND flash device, wherein the first region has a probability of programming failure that is higher than a threshold probability, wherein programming the programming data to the first region comprises: programming a first page of the first region according to the programming data using single-level cell flash (SLC) programming and programming a second page of the first region according to the programming data using multi-level cell flash (MLC) programming, triple-level cell flash (TLC) programming, or quad-level cell flash (QLC) programming, wherein data stored in the first page and the second page is redundant, wherein each of the first page and the second page includes a plurality of memory cells corresponding to a first word line or a second word line, and wherein programming the first page and the second page comprises: a plurality of programming operations using a plurality of programming voltages; and a plurality of verify operations, wherein some of the plurality of verify operations are performed after corresponding ones of the plurality of programming operations to determine whether programmed memory cells of the first page have a threshold voltage level according to the programming data; determining completion of programming the first page and the second page based on a pass result returned by each of the plurality of verify operations; and after the determining, performing a read operation by the NAND flash device of the second page to self-verify data stored at the second page according to the programming data, and wherein programming the programming data to the second region comprises programming the second region without using SLC programming.

2. The programming method of claim 1, further comprising: not performing a read operation of the second page by one or more host computing devices, wherein the read operation of the second page by the one or more host computing devices is to externally verify data stored at the second page according to the programming data.

3. The programming method of claim 1, further comprising: releasing the first page to receive new data for storage.

4. The programming method of claim 1, wherein, the performing of the read operation comprises: comparing data stored at the second page determined from the read operation and the programming data; and determining a pass result if a failed bit count is below a threshold or a fail result if the failed bit count is above a threshold.

5. The programming method of claim 1, further comprising: receiving an input by the NAND flash device to adjust the performing of the read operation.

6. The programming method of claim 5, further comprising: limiting the performing of the read operation to one or more regions in the NAND flash device specified by the input, wherein the one or more regions comprise at least one of: a region for single-level cell flash (SLC); a region for multi-level cell flash (MLC); a region for triple-level cell flash (TLC); a region for quad-level cell flash (QLC); a page; a block; and a slice storage area.

7. The programming method of claim 1, further comprising: delaying a cache of future programming data until after the performing of the read operation.

8. The programming method of claim 7, further comprising: detecting usage of the cache, wherein the delaying is based on the detection of usage of the cache.

9. A NAND flash device, comprising: a memory array including a first page and a second page, each of the first page and the second page including a plurality of memory cells corresponding to a first word line or a second word line; and a peripheral circuit coupled to the first page and the second page via the first word line and the second word line and configured to: program program data to a first region or a second region of the NAND flash device, wherein the first region has a probability of program failure that is higher than a threshold probability, wherein programming the program data to the first region includes: programming the first page of the first region according to the program data using single-level cell flash (SLC) programming and programming the second page of the first region according to the program data using multi-level cell flash (MLC) programming, triple-level cell flash (TLC) programming, or quad-level cell flash (QLC) programming, wherein data stored in the first page and the second page is redundant, wherein programming the first page and the second page includes: a plurality of program operations using a plurality of program voltages; and a plurality of verify operations, wherein some of the plurality of verify operations are performed after corresponding ones of the plurality of program operations to determine whether programmed memory cells of the first page have a threshold voltage level according to the program data; determining completion of programming the first page and the second page based on a pass result returned by each of the plurality of verify operations; and after the determining, performing a read operation by the NAND flash device of the second page to self-verify data stored at the second page according to the program data, and wherein programming the program data to the second region includes programming the second region without using SLC programming.

10. The NAND flash memory device of claim 9, further comprising: a read operation by one or more host computing devices of the second page is not performed, wherein the read operation by the one or more host computing devices of the second page is to externally verify data stored at the second page according to the program data.

11. The NAND flash memory device of claim 9, wherein, the NAND flash device is configured to release the first page to receive new data for storage.

12. The NAND flash memory device of claim 9, wherein, the performing of the read operation includes: comparing data stored at the second page determined from the read operation and the program data; and determining a pass result if a failed bit count is below a threshold or a fail result if the failed bit count is above a threshold.

13. The NAND flash memory device of claim 9, wherein, the NAND flash device is configured to receive an input to adjust the performing of the read operation.

14. The NAND flash memory device of claim 13, wherein, the NAND flash device is further configured to limit the performing of the read operation to one or more regions in the NAND flash device specified by the input, wherein the one or more regions include at least one of: a region for single-level cell flash (SLC); a region for multi-level cell flash (MLC); a region for triple-level cell flash (TLC); and a region for quad-level cell flash (QLC). Regions for quad-level cell (QLC) four-tiered unit flash memory; Pages; Blocks; and Slice storage areas.

15. The NAND flash memory device of claim 9, wherein, The NAND flash memory device is configured to delay caching of future program data until after execution of the read operation.

16. The NAND flash memory device of claim 15, wherein, The NAND flash memory device is further configured to detect usage of the cache, wherein the delaying is based on the detection of usage of the cache.

17. A memory system, comprising: a NAND flash memory device configured for storing data, the NAND flash memory device comprising: a memory array comprising a first page and a second page, each of the first page and the second page comprising a plurality of storage units corresponding to a first word line or a second word line; and a peripheral circuit coupled to the first page and the second page via the first word line and the second word line, and configured to: program program data to a first region or a second region of the NAND flash memory device, wherein the first region has a probability of program failure that is higher than a threshold probability, wherein programming the program data to the first region comprises: programming the first page of the first region from the program data using single-level cell (SLC) programming, and programming the second page of the first region from the program data using multi-level cell (MLC) programming, triple-level cell (TLC) programming, or quad-level cell (QLC) programming, wherein data stored in the first page and the second page is redundant, wherein programming the first page and the second page comprises: a plurality of program operations using a plurality of program voltages; and a plurality of verify operations, wherein some of the plurality of verify operations are performed after corresponding ones of the plurality of program operations to determine whether programmed storage units of the first page have a threshold voltage level from the program data; determining completion of programming the first page and the second page based on a pass result returned by each of the plurality of verify operations; and after the determining, performing a read operation by the NAND flash memory device of the second page to self-verify data stored at the second page from the program data, and wherein programming the program data to the second region comprises programming the second region without using SLC programming.

18. The memory system of claim 17, further comprising: a read operation of the second page by one or more host computing devices is not performed, wherein the read operation of the second page by the one or more host computing devices is to externally verify data stored at the second page from the program data.

19. The memory system of claim 17, wherein, The NAND flash memory device is further configured to release the first page to receive new data for storage.

20. The memory system of claim 17, wherein, The execution of the read operation comprises: comparing data stored at the second page determined from the read operation and the program data; and determining a pass result if a failed bit count is below a threshold, or determining a fail result if the failed bit count is above a threshold.

21. The memory system of claim 17, wherein, The NAND flash device is further configured to receive an input to adjust the performance of the read operation.

22. The memory system of claim 21, wherein, The NAND flash device is further configured to limit the performance of the read operation to one or more regions in the NAND flash device specified by the input, wherein the one or more regions include at least one of: a region for single layer cell flash (SLC); a region for multi layer cell flash (MLC); a region for triple layer cell flash (TLC); a region for quad layer cell flash (QLC); a page; a block; and a die storage area.

23. The memory system of claim 17, wherein, The NAND flash device is further configured to delay caching of future program data until after the performance of the read operation.

24. The memory system of claim 23, wherein, The NAND flash device is further configured to detect usage of the cache, wherein the delay is based on the detection of usage of the cache.

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