A safety chip fault detection circuit and terminal device
Through the combined circuit of the phase difference alarm module, the false alarm filtering module and the latch output module, the reliability problem of the safety chip fault detection is solved, and more accurate fault detection is achieved without increasing the circuit area.
Patent Information
- Application Number
- CN202011300168.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-11-19
- Publication Date
- 2025-09-05
- Estimated Expiration
- 2040-11-19
AI Technical Summary
The reliability of fault detection in existing security chips is low, and the glitch detector has a limited detection range and is difficult to cover the entire chip, resulting in an increase in chip area and a decrease in performance.
The combined circuit of phase difference alarm module, false alarm filtering module and latch output module is adopted to improve the accuracy and reliability of detection through phase detection, filtering processing and latching alarm signals.
The reliability of safety chip fault detection is improved, false alarms are reduced, and the detection range is expanded without increasing the circuit area.
Smart Images
Figure CN114518528B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of clock fault detection, and in particular to a security chip fault detection circuit and terminal equipment. Background Art
[0002] Side-channel attacks on security chips primarily extract cryptographic parameters such as keys, thereby depriving the chips of their confidentiality. Attacking security chips by creating clock faults is a type of side-channel attack. Conventional technology typically employs glitch detectors to detect abnormal changes in clock signals and generate alarms when glitches occur, thereby protecting against clock signal fault injection attacks. However, due to the limited detection range of glitch detectors, multiple glitch detectors must be placed within the chip to achieve full-chip detection, significantly increasing the chip area and reducing performance. Furthermore, the unique structure of the memory cells within security chips makes it difficult to integrate glitch sensors. This creates blind spots in the chip's detection range, making it impossible to fully protect against clock attacks. Consequently, the reliability of current security chip fault detection is low. Summary of the Invention
[0003] Embodiments of the present invention provide a security chip fault detection circuit and a terminal device to solve the problem of low reliability of security chip fault detection.
[0004] In a first aspect, an embodiment of the present invention provides a safety chip fault detection circuit, which includes a phase difference alarm module, a false alarm filtering module, and a latch output module, wherein:
[0005] The phase difference alarm module is configured to receive a clock to be detected and a reference clock, and perform phase detection on the clock to be detected and the reference clock to obtain a first pulse;
[0006] The false alarm filtering module, wherein the input end of the false alarm filtering module is connected to the output end of the phase difference alarm module, is used to filter the first pulse to obtain an alarm signal;
[0007] The latch output module has an input end connected to the output end of the false alarm filtering module and is used to latch the alarm signal.
[0008] In a second aspect, an embodiment of the present invention provides a terminal device, which includes the above-mentioned security chip fault detection circuit.
[0009] In an embodiment of the present invention, a phase difference alarm module receives a clock to be detected and a reference clock, and performs phase detection on the clock to be detected and the reference clock. When a phase difference exists between the clock to be detected and the reference clock, the phase difference alarm module outputs a first pulse. Furthermore, a false alarm filtering module filters the first pulse to obtain an alarm signal. Further, a latch output module latches the alarm signal and outputs the alarm signal. The phase difference alarm module of the present invention can detect the phase difference between the clock to be detected and the reference clock, and the false alarm filtering module can filter the inherent phase difference in the actual chip design. The obtained alarm signal is more accurate, thereby improving the reliability of safety chip fault detection. BRIEF DESCRIPTION OF THE DRAWINGS
[0010] Figure 1 This is one of the structural diagrams of a safety chip fault detection circuit provided by an embodiment of the present invention;
[0011] Figure 2 This is one of the principle diagrams of a safety chip fault detection circuit provided by an embodiment of the present invention;
[0012] Figure 3 This is the second schematic diagram of a safety chip fault detection circuit provided by an embodiment of the present invention;
[0013] Figure 4 This is the second structural diagram of a safety chip fault detection circuit provided by an embodiment of the present invention;
[0014] Figure 5 This is the third structural diagram of a safety chip fault detection circuit provided by an embodiment of the present invention;
[0015] Figure 6 This is the fourth structural diagram of a safety chip fault detection circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0016] The following will be combined with the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0017] The terms "first," "second," and the like in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of this application can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "first" and "second" generally distinguish objects of the same type, and do not limit the number of objects. For example, the first object may be one or more.
[0018] See Figure 1 , Figure 1 This is one of the structural diagrams of a safety chip fault detection circuit provided by an embodiment of the present invention, such as Figure 1 As shown, the safety chip fault detection circuit includes a phase difference alarm module 101, a false alarm filtering module 102 and a latch output module 103, wherein:
[0019] The phase difference alarm module 101 is used to receive the clock to be detected and the reference clock, and perform phase detection on the clock to be detected and the reference clock to obtain a first pulse;
[0020] A false alarm filtering module 102, the input end of which is connected to the output end of the phase difference alarm module, for filtering the first pulse to obtain an alarm signal;
[0021] The latch output module 103 has an input terminal connected to the output terminal of the false alarm filtering module and is used to latch the alarm signal.
[0022] It should be noted that in the actual design of security chips, due to clock jitter and wiring parasitics, the input clock signal has inherent phase differences, and the phase difference alarm module 101 generates a false alarm signal with a fixed width. The input signal to be detected may contain both alarm signals corresponding to clock failures and false alarm signals. It is necessary to filter out the false alarm signals to ultimately obtain an alarm signal, and then issue an alarm based on the alarm signal.
[0023] The phase difference alarm module 101 performs phase detection on the input clock signal, detecting changes in the clock signal's edges. It offers high-speed response and easily generates a fault alarm within a single clock cycle. The input clock signal includes the clock to be detected and a reference clock. If a phase difference exists between the clock to be detected and the reference clock, the phase difference alarm module outputs a first low-level pulse. This first pulse may include both an alarm signal corresponding to a clock fault and a false alarm signal.
[0024] In addition, the alarm filtering module 102 is used to filter the first pulse to filter out the false alarm signal in the first pulse and obtain the alarm signal corresponding to the clock failure.
[0025] Since the duration of the alarm signal may be very short, such as only 1 nanosecond, the generated alarm time is too short and the alarm effect is not obvious. Therefore, it is necessary to latch the received alarm signal through the latch output module 103, so that the alarm signal can be continuously output to achieve the ideal alarm effect.
[0026] In an embodiment of the present invention, a phase difference alarm module receives a clock to be detected and a reference clock, and performs phase detection on the clock to be detected and the reference clock. When a phase difference exists between the clock to be detected and the reference clock, the phase difference alarm module outputs a first pulse. Furthermore, a false alarm filtering module filters the first pulse to obtain an alarm signal. Further, a latch output module latches the alarm signal and outputs the alarm signal. The phase difference alarm module of the present invention can detect the phase difference between the clock to be detected and the reference clock, and the false alarm filtering module can filter the inherent phase difference in the actual chip design. The obtained alarm signal is more accurate, thereby improving the reliability of safety chip fault detection.
[0027] like Figure 2 As shown, the principle of implementing fault detection and alarm in an embodiment of the present invention is as follows: a clock to be detected and a reference clock are input, phase detection is performed on the clock to be detected and the reference clock, and if a phase difference exists between the clock to be detected and the reference clock, a phase difference alarm signal is obtained. This phase difference alarm signal generally includes an alarm signal and a false alarm signal. Furthermore, the phase difference alarm signal is transmitted to the next circuit module for false alarm filtering, and the false alarm signal is filtered out, while the alarm signal is retained. Furthermore, the retained alarm signal is latched and output as an alarm.
[0028] like Figure 3 As shown, when a fault is injected, the edge of the clock signal to be detected may be advanced, and there is a phase difference between the clock to be detected and the reference clock, which will generate a low-level "0" alarm signal. The alarm signal can last for a period of time under the action of the latch output module, and can be cleared when a reset signal is received; based on the same principle, when a fault is injected, the edge of the clock signal to be detected may lag behind the reference clock, and there is a phase difference between the clock to be detected and the reference clock, which will generate a low-level "0" alarm signal. The alarm signal can last for a period of time under the action of the latch output module, and can be cleared when a reset signal is received.
[0029] As an optional implementation, Figure 4 As shown, the phase difference alarm module 101 includes:
[0030] XOR gate;
[0031] The first pin of the XNOR gate is used to input a clock to be detected, the second pin of the XNOR gate is used to input a reference clock, and the third pin of the XNOR gate is used to output a first pulse;
[0032] The third pin of the XOR gate is connected to the false alarm filtering module.
[0033] It's important to note that the XOR gate is a logic gate that implements the logical exclusive OR in digital logic. If the two input levels are different, the output is a high level "1"; if the two input levels are the same, the output is a low level "0." The XOR-NOR gate is an inversion of the XOR gate. This means it first performs an XOR operation on the two input levels and then negates the XOR result. If the two input levels are different, the output is a low level "0"; if the two input levels are the same, the output is a high level "1."
[0034] The first pin of the XNOR gate inputs the clock to be tested, and the second pin of the XNOR gate inputs the reference clock. If the levels of the clock to be tested and the reference clock are the same, it indicates that there are no alarm signals or false alarm signals corresponding to clock failure, and a high-level "1" pulse is output. If the levels of the clock to be tested and the reference clock are different, it indicates that there may be an alarm signal or false alarm signal corresponding to clock failure, and a low-level "0" pulse is output. This pulse is the first pulse.
[0035] At the same time, the third pin of the XOR gate is connected to the false alarm filtering module, and transmits the first pulse of the low level to the false alarm filtering module.
[0036] In this implementation, the phase difference between the clock to be detected and the reference clock is detected by an XOR gate, the circuit area is small, and the integration difficulty is low, so it can be applied to various digital circuit design processes.
[0037] Optional, such as Figure 4 As shown, the false alarm filtering module 102 includes:
[0038] Delay and OR gate;
[0039] The first pin of the delayer is connected to the phase difference alarm module, and the second pin of the delayer is connected to the second pin of the OR gate;
[0040] The first pin of the OR gate is connected to the phase difference alarm module, and the third pin of the OR gate is connected to the latch output module.
[0041] It should be noted that the OR gate has multiple input terminals and one output terminal. As long as one of the inputs is a high level "1", the output is a high level "1"; only when all the inputs are low level "0", the output is a low level.
[0042] A delayer is a circuit that delays a pulse signal for a certain period of time. If the width of the first pulse received by the XOR gate is less than the inherent delay time of the delayer, the delayer can delay the pulse signal. Within the inherent delay time, if the first pin of the OR gate receives a low-level "0" pulse and the second pin of the OR gate does not receive a low-level "0" pulse, the third pin of the OR gate will output a high-level "1" signal. If the inherent delay time has expired and the second pin of the OR gate receives a low-level "0" pulse and the first pin of the OR gate does not receive a low-level "0" pulse, the third pin of the OR gate will still output a high-level "1" signal. When the level width of the first pulse obtained by the XOR gate is greater than the inherent delay time of the delayer, since the delayer can delay the pulse signal, within the inherent delay time, the first pin of the OR gate inputs the first pulse of low level "0", and the second pin of the OR gate does not input the first pulse of low level "0", then the third pin of the OR gate outputs a high level "1" signal; because the level width of the first pulse is greater than the inherent delay time of the delayer, the inherent delay time has passed, the second pin of the OR gate inputs the first pulse of low level "0", and the first pin of the OR gate inputs the first pulse of low level "0", then the third pin of the OR gate still outputs a low level "0" signal, and this low level "0" signal is an alarm signal.
[0043] The operating principles of digital systems indicate that after the system clock is physically implemented on the board, inherent clock edge deviation exists on each branch of the clock tree structure due to varying parasitic parameters on each branch. The filtering function implemented by the delayer and OR gate can filter out false alarm signals caused by inherent clock edge deviation between the clock under test and the reference clock, thus avoiding false alarms. Furthermore, fault injection increases inherent clock edge deviation. The inherent delay time of the delayer can be adjusted according to the actual application scenario to filter out the increased inherent clock edge deviation.
[0044] In addition, the third pin of the OR gate is connected to the latch output module, and the alarm signal can be transmitted to the latch output module.
[0045] In this implementation, the delay device and the OR gate can filter out false alarm signals, thereby achieving filtering processing of the alarm signal, thereby improving the reliability of safety chip fault detection.
[0046] Optional, such as Figure 5 As shown, the delay device includes a plurality of delay units;
[0047] Multiple delay units are connected in series;
[0048] The first pin of the target delay unit is connected to the second pin of the OR gate, the first pin of the target delay unit is also connected to the third pin of the delayer, and the target delay unit is any delay unit among the multiple delay units;
[0049] The third pin of the delay device is used for receiving a trim selection signal.
[0050] It should be noted that the delay device includes multiple delay units, which can be composed of any logic gate circuit. For example, the delay unit can be an inverter or a buffer with different delay characteristics. The type of delay unit does not affect the functional implementation of the present invention. In this embodiment, the type of delay unit is not limited.
[0051] The delayer consists of a series of delay units (Delay Unit 1, Delay Unit 2, Delay Unit 3, ..., Delay Unit n). When the first pulse is input to the first pin of the delayer, the input signal at the delayer input changes from a high-level "1" to a low-level "0." Within the preset delay time, the edge of the low-level "0" signal is delayed. After the preset delay time, the low-level "0" signal reaches the delayer output. The third pin of the delayer is used to receive a trim selection signal. The length of the preset delay time is determined by a selection switch controlled by the trim selection signal. Only one selection switch is turned on at a time. Generally speaking, the more delay units the input signal at the delayer input passes through, the longer the preset delay time.
[0052] Depending on the actual application scenario, the number of delay units can be adjusted before the delayer is used by configuring a trim selection signal to adjust the desired preset delay time and eliminate the inherent clock phase difference generated during system design. This adjustment can be performed at any stage of chip testing or chip application. Configuring the trim selection signal does not affect the functional implementation of the present invention. Furthermore, the configured trim value can be stored in on-chip memory or off-chip memory, and the storage location of the configured trim value does not affect the functional implementation of the present invention.
[0053] In this embodiment, since the delay device includes multiple delay units, the adjustment selection signal can adjust the delay time of the delay device according to the requirements of different application scenarios, thereby expanding the application scope of safety chip fault detection and improving the accuracy of filtering false alarm signals.
[0054] Optionally, the latch output module 103 includes a register;
[0055] The first pin of the register is connected to the third pin of the false alarm filtering module or gate;
[0056] The second pin of the register transmits the alarm signal to the third pin of the register;
[0057] The third pin of the register outputs an alarm signal;
[0058] The fourth pin of the register receives a reset signal.
[0059] The first pin of the register, also known as the register's clock terminal, is connected to the third pin of the false alarm filtering module's OR gate and can be used to receive alarm signals. When the output signal of the false alarm filtering module's OR gate changes from a high-level "1" to a low-level "0," a falling edge occurs on the register's clock terminal, triggering the register to take action. At this point, the second pin of the register immediately transmits the low-level "0" signal received by the first pin to the third pin of the register, maintaining the low-level "0" fault detection alarm signal. The second pin of the register serves as the register's input, while the third pin of the register serves as the register's output.
[0060] The fourth pin of the register is used to receive a reset input signal. When a reset operation is required, the fourth pin of the register receives the reset input signal, the register is reset, and the alarm signal at the output end of the register changes from a low level "0" to a high level "1", and the fault alarm is cleared.
[0061] In this implementation, since the fault detection alarm signal can be continuously generated through the register, the fault alarm is cleared when the reset input signal is received, thereby achieving a better alarm effect.
[0062] Optional, such as Figure 6 As shown, the phase difference alarm module 101 includes a plurality of XOR gates and AND gates;
[0063] A first pin of a first XNOR gate among the multiple XNOR gates is connected to a first clock pin to be detected of the first pin of the phase difference alarm module, and a second pin of a first XNOR gate among the multiple XNOR gates is connected to a second pin of the phase difference alarm module;
[0064] A first pin of a second XNOR gate among the multiple XNOR gates is connected to a second clock pin to be detected of the first pin of the phase difference alarm module, and a second pin of the second XNOR gate among the multiple XNOR gates is connected to a second pin of the phase difference alarm module;
[0065] The third pin of the first XNOR gate is connected to the first pin of the AND gate, and the third pin of the second XNOR gate is connected to the second pin of the AND gate;
[0066] The third pin of the AND gate is connected to the false alarm filtering module.
[0067] It should be noted that the AND gate is a basic logic gate circuit that performs the "AND" operation. It has multiple input terminals and one output terminal. When all inputs are high level "1" at the same time, the output is high level "1", otherwise the output is low level "0".
[0068] The phase difference alarm module may include a plurality of XNOR gates, and two adjacent XNOR gates are connected to the same AND gate.
[0069] At the same time, the first pin of the first XNOR gate is used to input the first clock to be detected, and the second pin of the first XNOR gate is used to input the reference clock. The first pin of the second XNOR gate is used to input the second clock to be detected, and the second pin of the second XNOR gate is used to input the reference clock. According to the basic principle of the AND gate, if it is detected that there is no phase difference between the first clock to be detected and the reference clock, the first XNOR gate outputs a first pulse of a high level "1". At the same time, if it is detected that there is no phase difference between the second clock to be detected and the reference clock, the second XNOR gate outputs a first pulse of a high level "1". At this time, the AND gate outputs a high level "1" signal.
[0070] In other cases, the AND gate outputs a low-level "0" signal. The other cases here include: when a phase difference is detected between the first clock to be detected and the reference clock, the first XOR gate outputs a first pulse of a low level "0", and at the same time, it is detected that there is no phase difference between the second clock to be detected and the reference clock, the second XOR gate outputs a first pulse of a high level "1"; when it is detected that there is no phase difference between the first clock to be detected and the reference clock, the first XOR gate outputs a first pulse of a high level "1", and at the same time, it is detected that there is a phase difference between the second clock to be detected and the reference clock, the second XOR gate outputs a first pulse of a low level "0"; when a phase difference is detected between the first clock to be detected and the reference clock, the first XOR gate outputs a first pulse of a low level "0", and at the same time, it is detected that there is a phase difference between the second clock to be detected and the reference clock, the second XOR gate outputs a first pulse of a low level "0".
[0071] In this embodiment, since the phase difference alarm module includes a plurality of XOR gates, it is possible to detect multiple clock signals to be detected simultaneously.
[0072] The embodiment of the present invention also provides a terminal device, which can realize Figure 1 To avoid repetition, the technical effects in the method embodiments are not described here in detail.
[0073] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.
[0074] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above embodiment methods can be implemented by means of software plus the necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method.
[0075] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.
Claims
1. A safety chip fault detection circuit, characterized in that: It includes a phase difference alarm module, a false alarm filtering module and a latch output module, among which: The phase difference alarm module is configured to receive a clock to be detected and a reference clock, and perform phase detection on the clock to be detected and the reference clock to obtain a first pulse; The false alarm filtering module, wherein the input end of the false alarm filtering module is connected to the output end of the phase difference alarm module, is used to filter the first pulse to obtain an alarm signal; The latch output module, the input end of the latch output module is connected to the output end of the false alarm filtering module, and is used to latch the alarm signal; The false alarm filtering module includes: Delay and OR gate; The first pin of the delayer is connected to the phase difference alarm module, and the second pin of the delayer is connected to the second pin of the OR gate; The first pin of the OR gate is connected to the phase difference alarm module, and the third pin of the OR gate is connected to the latch output module; The delay device includes a plurality of delay units; The multiple delay units are connected in series; The first pin of the target delay unit is connected to the second pin of the OR gate, the first pin of the target delay unit is also connected to the third pin of the delayer, and the target delay unit is any delay unit among the multiple delay units; The third pin of the delay device is used to receive a trimming selection signal.
2. The safety chip fault detection circuit according to claim 1, wherein: The phase difference alarm module includes: XOR gate; The first pin of the XNOR gate is used to input the clock to be detected, the second pin of the XNOR gate is used to input the reference clock, and the third pin of the XNOR gate is used to output the first pulse; The third pin of the XOR gate is connected to the false alarm filtering module.
3. The safety chip fault detection circuit according to claim 1, wherein: The latch output module includes a register; The first pin of the register is connected to the third pin of the false alarm filtering module or gate; The second pin of the register transmits the alarm signal to the third pin of the register; The third pin of the register outputs the alarm signal; The fourth pin of the register receives a reset signal.
4. The safety chip fault detection circuit according to claim 1, wherein: The phase difference alarm module includes a plurality of XOR gates and AND gates; A first pin of a first XNOR gate among the multiple XNOR gates is connected to a first clock pin to be detected of the first pin of the phase difference alarm module, and a second pin of a first XNOR gate among the multiple XNOR gates is connected to a second pin of the phase difference alarm module; A first pin of a second XNOR gate among the multiple XNOR gates is connected to a second clock pin to be detected of the first pin of the phase difference alarm module, and a second pin of the second XNOR gate among the multiple XNOR gates is connected to a second pin of the phase difference alarm module; The third pin of the first XNOR gate is connected to the first pin of the AND gate, and the third pin of the second XNOR gate is connected to the second pin of the AND gate; The third pin of the AND gate is connected to the false alarm filtering module.
5. A terminal device, characterized in that: The terminal device comprises the security chip fault detection circuit according to any one of claims 1 to 4.
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