System and method for determining a change in a read threshold voltage

Abstract

A memory system includes a memory device and a controller. The controller determines whether a read threshold voltage other than a historical read threshold voltage used as a read threshold voltage in a previous successful read operation is to be used for a next read operation based on a failed bit count associated with the read operation, an error correction capability of a decoder, and a utilization of a queue in the decoder. When it is determined that the historical read threshold voltage is not used for the next read operation, the controller determines a failed bit count associated with a read operation of a memory cell of the memory device using a read threshold voltage. The controller determines an optimal read threshold voltage based on the failed bit count. The controller transmits a first command including a parameter associated with setting the optimal read threshold voltage to the memory device.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a scheme for determining whether to change a read threshold voltage in a memory system. BACKGROUND

[0002] A computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. Accordingly, the use of portable electronic devices such as mobile phones, digital cameras, notebook computers has rapidly increased. These portable electronic devices generally use a memory system having a memory device, i.e., a data storage device. The data storage device is used as a main memory device or an auxiliary memory device of the portable electronic devices.

[0003] Since memory systems using memory devices do not have moving parts, they provide excellent stability, durability, high information access speed, and low power consumption. Examples of memory systems having these advantages include universal serial bus (USB) memory devices, memory cards having various interfaces such as universal flash storage (UFS), and solid state drives (SSDs). The memory systems can perform a read operation using various read thresholds. SUMMARY

[0004] Aspects of the present invention include systems and methods for determining whether to change a read threshold voltage based on error information using deep learning.

[0005] In an aspect, a memory system includes a memory device including a plurality of memory cells and a controller including a decoder. The controller can determine whether a read threshold voltage other than a history read threshold voltage that is a read threshold voltage used in a previous successful read operation is to be used for a next read operation based on a failed bit count associated with read operations using the history read threshold voltage, an error correction capability of the decoder, and a utilization of a queue in the decoder. When it is determined that the history read threshold voltage is not used for the next read operation, the controller determines a failed bit count associated with read operations of the plurality of memory cells using a plurality of read threshold voltages. The controller determines an optimal read threshold voltage based on the failed bit count, the optimal read threshold voltage having a lowest failed bit count among the plurality of read retry threshold voltages. The controller transmits a first command including a parameter associated with setting the optimal read threshold voltage to the memory device.

[0006] In another aspect, a method for operating a memory system including a memory device and a controller coupled to the memory device and including a decoder, the method includes determining whether a read threshold voltage other than a history read threshold that was used as a read threshold voltage in a previous successful read operation is to be used for a next read operation based on a failed bit count associated with read operations using the history read threshold voltage, an error correction capability of the decoder, and a utilization of a queue in the decoder; when it is determined that the history read threshold voltage is not to be used for the next read operation, determining failed bit counts associated with read operations using a plurality of read threshold voltages to a plurality of memory cells of the memory device; determining a best read threshold voltage having a lowest failed bit count among the plurality of read threshold voltages based on the failed bit counts; and transmitting a first command including a parameter associated with setting the best read threshold voltage to the memory device.

[0007] Other aspects of the application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram illustrating a data processing system according to an embodiment of the present application.

[0009] Figure 2 is a block diagram illustrating a memory system according to an embodiment of the present application.

[0010] Figure 3 is a circuit diagram illustrating a memory block of a memory device according to an embodiment of the present application.

[0011] Figure 4 is a diagram illustrating a state distribution of different types of cells of a memory device.

[0012] Figure 5A is a diagram illustrating an example of Gray coding of a multi-level cell (MLC).

[0013] Figure 5B is a diagram illustrating a state distribution of a page of a multi-level cell (MLC).

[0014] Figure 6A is a diagram illustrating an example of Gray coding of a triple-level cell (TLC).

[0015] Figure 6B is a diagram illustrating a state distribution of a page of a triple-level cell (TLC).

[0016] Figure 7 An example of a deep neural network architecture for data storage performance optimization implemented based on some embodiments of the disclosed technology is shown.

[0017] Figure 8 An example configuration of a computational neural network including input neurons, hidden neurons, output neurons, and a layer of synapses is shown.

[0018] Figure 9 An example of a training method for a deep neural network for data storage optimization implemented based on some embodiments of the disclosed technology is shown.

[0019] Figure 10 An example of an inference method for a deep neural network for data storage optimization implemented based on some embodiments of the disclosed technology is shown.

[0020] Figure 11 An example of a deep neural network system for data storage optimization implemented based on some embodiments of the disclosed technology is shown.

[0021] Figures 12A to 12C An architecture of a deep neural network according to an embodiment of the present invention is shown.

[0022] Figure 13 is a diagram showing a flow of an error recovery algorithm in a memory system.

[0023] Figure 14 is a diagram showing a memory system including a deep neural network according to an embodiment of the present invention.

[0024] Figure 15 and Figure 16 is a diagram showing a read threshold variation determiner according to an embodiment of the present invention.

[0025] Figure 17 is a flowchart showing an operation of a memory system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] Various embodiments are described in more detail below. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the invention to those skilled in the art. Additionally, the reference to "an embodiment," "another embodiment," etc., in various places in the specification does not necessarily refer to the same embodiment, and such phrases do not necessarily refer to a single embodiment. The terms "example" and "exemplary" used throughout this disclosure should not be construed as applying to all embodiments. Throughout the disclosure, like- referenced numerals refer to parts of the same figures and embodiments of the present invention.

[0027] The present application can be implemented in numerous ways, including as a method; an apparatus; a system; a computer program product (which can be implemented on a computer-readable storage medium); and / or a processor, such as a processor configured to fetch and execute instructions stored in a memory coupled to the processor and / or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the application can take, can be referred to as techniques. Generally, the order of the steps of disclosed methods can be altered from that described in this specification without departing from the scope of the application. Unless otherwise specified, an component such as a processor or a memory described as being configured to perform a task can be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. As used herein, the term 'processor' or the like refers to one or more devices, circuits, and / or processing cores adapted to process data, such as computer program instructions.

[0028] A detailed description of embodiments of the application and examples of aspects of the application are provided below with reference to the accompanying drawings. The application is described in connection with these embodiments, but the application is not limited to any embodiment. The scope of the application is limited only by the claims. The application encompasses numerous alternatives, modifications and equivalents. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the application. These details are provided for the purpose of example; the application can be practiced without some or all of these specific details. For the purpose of clarity, technical material that is known in the technical fields related to the application has not been described in detail so that the application is not unnecessarily obscured.

[0029] Figure 1 is a block diagram illustrating a data processing system 2 according to an embodiment of the present application.

[0030] Referring to Figure 1 The data processing system 2 can include a host device 5 and a memory system 10. The memory system 10 can receive a request from the host device 5 and operate in response to the received request. For example, the memory system 10 can store data to be accessed by the host device 5.

[0031] The host device 5 can be implemented with any one of various electronic devices. In various embodiments, the host device 5 can include an electronic device such as a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and / or a digital video recorder and a digital video player. In various embodiments, the host device 5 can include a portable electronic device such as a mobile phone, a smart phone, an electronic book, an MP3 player, a portable multimedia player (PMP), and / or a portable game machine.

[0032] The memory system 10 can be implemented with any one of various storage devices such as a solid state drive (SSD) and a memory card. In various embodiments, the memory system 10 can be provided as one of various components in an electronic device such as a computer, an ultra mobile personal computer (PC) (UMPC), a workstation, a netbook PC, a personal digital assistant (PDA), a portable computer, a web tablet PC, a wireless phone, a mobile phone, a smart phone, an electronic book reader, a portable multimedia player (PMP), a portable game device, a navigation device, a black box, a digital camera, a digital multimedia broadcast (DMB) player, a three-dimensional television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device of a data center, a device capable of receiving and transmitting information in a wireless environment, a radio frequency identification (RFID) device, and one of various electronic devices of a home network, one of various electronic devices of a computer network, one of electronic devices of a telecommunication network, or one of various components of a computing system.

[0033] The memory system 10 can include a memory controller 100 and a semiconductor memory device 200. The memory controller 100 can control overall operations of the semiconductor memory device 200.

[0034] The semiconductor memory device 200 can perform one or more erase operations, program operations, and read operations under the control of the memory controller 100. The semiconductor memory device 200 can receive a command CMD, an address ADDR, and data DATA through input / output lines. The semiconductor memory device 200 can receive power PWR through a power supply line and a control signal CTRL through a control line. The control signal CTRL can include a command latch enable signal, an address latch enable signal, a chip enable signal, a write enable signal, a read enable signal, and other operation signals according to the design and configuration of the memory system 10.

[0035] The memory controller 100 and the semiconductor memory device 200 can be integrated in a single semiconductor device such as a solid state drive (SSD). The SSD can include a storage device for storing data. When the semiconductor memory system 10 is used in the SSD, the operating speed of a host device (e.g., the host device 5 of FIG. 1) coupled to the memory system 10 can be significantly improved. Figure 1

[0036] ​The memory controller 100 and the semiconductor memory device 200 can be integrated in a single semiconductor device such as a memory card. For example, the memory controller 100 and the semiconductor memory device 200 can be integrated as a Personal Computer (PC) card of Personal Computer Memory Card International Association (PCMCIA), a CompactFlash (CF) card, a Smart Media (SM) card, a Memory Stick, a MultiMediaCard (MMC), a Reduced Size MultiMediaCard (RS-MMC), a micro type of MMC (micro- MMC), a Secure Digital (SD) card, a mini Secure Digital (mini-SD) card, a micro Secure Digital (micro-SD) card, a Secure Digital High Capacity (SDHC), and / or a Universal Flash Storage (UFS).

[0037] Figure 2 is a block diagram illustrating a memory system according to an embodiment of the present application. For example, Figure 2 The memory system of Figure 1 The memory system 10 shown in

[0038] Referring to Figure 2 , the memory system 10 can include a memory controller 100 and a semiconductor memory device 200. The memory system 10 can operate in response to a request from a host device (e.g., the host device 5 of Figure 1 , and in particular, store data to be accessed by the host device.

[0039] The semiconductor memory device 200 can store data to be accessed by the host device.

[0040] The semiconductor memory device 200 can be implemented with a volatile memory device such as Dynamic Random Access Memory (DRAM) and / or Static Random Access Memory (SRAM), or a non-volatile memory device such as Read Only Memory (ROM), Mask ROM (MROM), Programmable ROM (PROM), Erasable Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), Ferroelectric Random Access Memory (FRAM), Phase-Change RAM (PRAM), Magnetic RAM (MRAM), and / or Resistive RAM (RRAM).

[0041] The memory controller 100 can control storage of data in the semiconductor memory device 200. For example, the memory controller 100 can control the semiconductor memory device 200 in response to a request from the host device. The memory controller 100 can provide data read from the semiconductor memory device 200 to the host device, and can store data provided from the host device into the semiconductor memory device 200.

[0042] The memory controller 100 can include a storage 110, a control component 120 (which can be implemented as a processor such as a central processing unit (CPU)), an error correction code (ECC) component 130, a host interface (I / F) 140, and a memory interface (I / F) 150 coupled through a bus 160.

[0043] The storage 110 can serve as a working memory of the memory system 10 and the memory controller 100, and store data used to drive the memory system 10 and the memory controller 100. When the memory controller 100 controls the operation of the semiconductor memory device 200, the storage 110 can store data used for operations such as a read operation, a write operation, a program operation, and an erase operation by the memory controller 100 and the semiconductor memory device 200.

[0044] The storage 110 can be implemented with a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). As described above, the storage 110 can store data used by the host device in the semiconductor memory device 200 for a read operation and a write operation. To store the data, the storage 110 can include a program memory, a data memory, a write buffer, a read buffer, a mapping buffer, etc.

[0045] The control component 120 can control the general operation of the memory system 10 and a write operation or a read operation with respect to the semiconductor memory device 200 in response to a write request or a read request from the host device. The control component 120 can drive firmware called a flash translation layer (FTL) to control the general operation of the memory system 10. For example, the FTL can perform operations such as logical-to-physical (L2P) mapping, wear leveling, garbage collection, and / or bad block handling. The L2P mapping is referred to as logical block addressing (LBA).

[0046] The ECC component 130 can detect and correct errors in data read from the semiconductor memory device 200 during a read operation. When the number of error bits is greater than or equal to a threshold number of correctable error bits, the ECC component 130 can not correct the error bits, but can output an error correction failure signal indicating a failure to correct the error bits.

[0047] In various embodiments, the ECC component 130 can perform error correction operations based on encoding modulation such as Low-Density Parity-Check (LDPC) code, Bose-Chaudhuri-Hocquenghem (BCH) code, turbo code, turbo product code (TPC), Reed-Solomon (RS) code, convolutional code, recursive systematic code (RSC), trellis coded modulation (TCM), or block coded modulation (BCM). However, error correction is not limited to these techniques. Thus, the ECC component 130 can include any and all circuitry, systems, or devices for suitable error correction operations.

[0048] The host interface 140 can communicate with a host device through one or more of various interface protocols such as Universal Serial Bus (USB), Multi-Media Card (MMC), Peripheral Component Interconnect Express (PCI-e or PCIe), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Enhanced Small Disk Interface (ESDI), and Electronic Integrated Drive (IDE).

[0049] The memory interface 150 can provide an interface between the memory controller 100 and the semiconductor memory device 200 to allow the memory controller 100 to control the semiconductor memory device 200 in response to a request from the host device. The memory interface 150 can generate a control signal for the semiconductor memory device 200 and process data under the control of the control component 120. When the semiconductor memory device 200 is a flash memory such as NAND flash memory, the memory interface 150 can generate a control signal for the memory and process data under the control of the control component 120.

[0050] The semiconductor memory device 200 can include a memory cell array 210, a control circuit 220, a voltage generating circuit 230, a row decoder 240, a page buffer array 250 (which can be in the form of a page buffer array), a column decoder 260, and an input and output (input / output) circuit 270. The memory cell array 210 can include a plurality of memory blocks 211 that can store data. The voltage generating circuit 230, the row decoder 240, the page buffer array 250, the column decoder 260, and the input / output circuit 270 can form a peripheral circuit of the memory cell array 210. The peripheral circuit can perform a program operation, a read operation, or an erase operation on the memory cell array 210. The control circuit 220 can control the peripheral circuit.

[0051] The voltage generation circuit 230 can generate operating voltages of various levels. For example, in an erase operation, the voltage generation circuit 230 can generate operating voltages of various levels, such as an erase voltage and a pass voltage.

[0052] The row decoder 240 can be in electrical communication with the voltage generation circuit 230 and the plurality of memory blocks 211. The row decoder 240 can select at least one memory block among the plurality of memory blocks 211 in response to a row address generated by the control circuit 220, and transmit an operating voltage provided from the voltage generation circuit 230 to the selected memory block.

[0053] The page buffer array 250 can be coupled with the memory cell array 210 through bit lines BL (as shown) in response to a page buffer control signal generated by the control circuit 220, pre-charge the bit lines BL with a positive voltage, transmit and receive data to and from the selected memory block in a program operation and a read operation, or temporarily store the transmitted data. Figure 3

[0054] The column decoder 260 can transmit and receive data to and from the page buffer array 250, or transmit and receive data to and from the input / output circuit 270.

[0055] The input / output circuit 270 can transmit a command and an address received from an external device (e.g., a memory controller 100) to the control circuit 220, transmit data from the external device to the column decoder 260, or output data from the column decoder 260 to the external device outside the device through the input / output circuit 270. Figure 1

[0056] The control circuit 220 can control the peripheral circuit in response to the command and the address.

[0057] Figure 3 is a circuit diagram illustrating a memory block of a semiconductor memory device according to an embodiment of the present application. For example, Figure 3 The memory block illustrated in Figure 2 may be any one of the memory blocks 211 of the memory cell array 210 illustrated in

[0058] Referring to Figure 3 , the exemplary memory block 211 can include a plurality of word lines WL0 to WLn-1 connected to the row decoder 240, a drain select line DSL, and a source select line SSL. These lines can be arranged in parallel with the plurality of word lines between the DSL and the SSL.

[0059] ​​The exemplary memory block 211 can further include a plurality of cell strings 221 coupled to bit lines BL0 to BLm-1, respectively. Each column of cell strings can include one or more drain select transistors DST and one or more source select transistors SST. In the illustrated embodiment, each cell string has one DST and one SST. In the cell string, a plurality of memory cells or memory cell transistors MC0 to MCn-1 can be coupled in series between the select transistors DST and SST. Each of the memory cells can be formed as a multi-layer cell. For example, each of the memory cells can be formed as a single-layer cell (SLC) storing 1 bit of data. Each of the memory cells can be formed as a multi-layer cell (MLC) storing 2 bits of data. Each of the memory cells can be formed as a three-layer cell (TLC) storing 3 bits of data. Each of the memory cells can be formed as a four-layer cell (QLC) storing 4 bits of data.

[0060] The source of the SST in each cell string can be coupled to a common source line CSL, and the drain of each DST can be coupled to a respective bit line. The gate of the SST in a cell string can be coupled to the SSL, and the gate of the DST in a cell string can be coupled to the DSL. The gates of the memory cells across a cell string can be coupled to a respective word line. That is, the gate of memory cell MC0 is connected to a respective word line WL0, the gate of memory cell MC1 is connected to a respective word line WL1, and so on. A group of memory cells coupled to a particular word line can be referred to as a physical page. Thus, the number of physical pages in the memory block 211 can correspond to the number of word lines.

[0061] The page buffer array 250 can include a plurality of page buffers 251 coupled to the bit lines BL0 to BLm-1. The page buffers 251 can operate in response to page buffer control signals. For example, the page buffers 251 can temporarily store data received through the bit lines BL0 to BLm-1 or sense voltages or currents of the bit lines during a read operation or a verify operation.

[0062] In some embodiments, the memory block 211 can include NAND-type flash memory cells. However, the memory block 211 is not limited to this type of cell, but can include NOR-type flash memory cells. The memory cell array 210 can be implemented as a hybrid flash memory that combines two or more types of memory cells, or a one-NAND flash memory in which a controller is embedded inside a memory chip.

[0063] Figure 4 is a graph showing a distribution of states or program voltage (PV) levels of different types of cells of a memory device.

[0064] Referring to Figure 4Each of the memory cells can be implemented with a particular type of cell, such as a single-level cell (SLC) that stores 1 bit of data, a multi-level cell (MLC) that stores 2 bits of data, a triple-level cell (TLC) that stores 3 bits of data, or a quad-level cell (QLC) that stores 4 bits of data. Typically, all of the memory cells in a particular memory device are of the same type, but this is not required.

[0065] SLC can include two states, P0 and PI. P0 can represent an erased state and PI can represent a programmed state. Since SLC can be set to one of two different states, each SLC can program or store 1 bit according to a set encoding method. MLC can include four states, P0, PI, P2, and P3. Of these states, P0 can represent an erased state and PI through P3 can represent programmed states. Since MLC can be set to one of four different states, each MLC can program or store 2 bits according to a set encoding method. TLC can include eight states, P0 through P7. Of these states, P0 can represent an erased state and PI through P7 can represent programmed states. Since TLC can be set to one of eight different states, each TLC can program or store 3 bits according to a set encoding method. QLC can include sixteen states, P0 through P15. Of these states, P0 can represent an erased state and PI through P15 can represent programmed states. Since QLC can be set to one of sixteen different states, each QLC can program or store 4 bits according to a set encoding method.

[0066] Referring back to Figure 2 and Figure 3 Semiconductor memory device 200 can include a plurality of memory cells (e.g., NAND flash memory cells). The memory cells are arranged in an array of rows and columns, as Figure 3The cells of each row are connected to a word line (e.g., WL0), while the cells of each column are connected to a bit line (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, the data to be written (“1” or “0”) is provided at the bit line while the word line is asserted. During a read operation, the word line is again asserted and the threshold voltage of each cell can be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., coupled to) the same word line. When the memory cells are implemented with MLC, the multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cells are implemented with TLC, the multiple pages include a MSB page, a center significant bit (CSB) page, and a LSB page. When the memory cells are implemented with QLC, the multiple pages include a MSB page, a center most significant bit (CMSB) page, a center least significant bit (CLSB) page, and a LSB page. The memory cells can be programmed using a coding scheme (e.g., Gray coding) to increase the capacity of the memory system 10, such as an SSD.

[0067] Figure 5A is a diagram illustrating an example of coding for multi-level cell (MLC).

[0068] Referring to Figure 5A The MLC can be programmed using a set coding. The MLC can have 4 program states, including an erase state E (or PV0) and a first program state PV1 to a third program state PV3. The erase state E (or PV0) can correspond to “11”. The first program state PV1 can correspond to “10”. The second program state PV2 can correspond to “00”. The third program state PV3 can correspond to “01”.

[0069] In the MLC, as Figure 5B illustrated, there are two types of pages, including a LSB page and a MSB page. One or two thresholds can be applied to retrieve data from the MLC. For the MSB page, a single threshold is VT1. VT1 distinguishes the first program state PV1 and the second program state PV2. For the LSB page, 2 thresholds include a threshold VT0 and a threshold VT2. VT0 distinguishes the erase state E and the first program state PV1. VT2 distinguishes the second program state PV2 and the third program state PV3.

[0070] Figure 6A is a diagram illustrating an example of Gray coding for triple level cell (TLC).

[0071] Referring to Figure 6AThe TLC can be programmed using Gray coding. The TLC can have 8 programmed states, including an erase state E (or PV0) and first through seventh program states PV1-PV7. The erase state E (or PV0) can correspond to “110”. The first program state PV1 can correspond to “011”. The second program state PV2 can correspond to “001”. The third program state PV3 can correspond to “000”. The fourth program state PV4 can correspond to “010”. The fifth program state PV5 can correspond to “110”. The sixth program state PV6 can correspond to “100”. The seventh program state PV7 can correspond to “101”.

[0072] In the TLC, as shown in Figure 6B , there are 3 types of pages, including LSB pages, CSB pages, and MSB pages. 2 or 3 thresholds can be applied to retrieve data from the TLC. For MSB pages, 2 thresholds include a threshold VT0 that distinguishes the erase state E and the first program state PV1, and a threshold VT4 that distinguishes the fourth program state PV4 and the fifth program state PV5. For CSB pages, 3 thresholds include VT1, VT3, and VT5. VT1 distinguishes the first program state PV1 and the second program state PV2. VT3 distinguishes the third program state PV3 and the fourth program state PV4. VT5 distinguishes the fifth program state PV5 and the sixth program state PV6. For LSB pages, 2 thresholds include VT2 and VT6. VT2 distinguishes the second program state PV2 and the third program state PV3. VT6 distinguishes the sixth program state PV6 and the seventh program state PV7.

[0073] After programming a memory array including a plurality of memory cells as shown in Figure 5A and 6A , when a read operation is performed on the memory array using a particular voltage reference value such as a read threshold (i.e., a read voltage level), the charge level of a memory cell (e.g., the threshold voltage level of a transistor of the memory cell) is compared to one or more voltage reference values (also referred to as “read voltage levels” or “read thresholds”) to determine the state of the individual memory cell. For example, when a particular read threshold is applied to the memory array, those memory cells whose threshold voltage levels are higher than the particular voltage reference value are turned on and detected as “on” cells, while those memory cells whose threshold voltage levels are lower than the particular voltage reference value are turned off and detected as “off” cells. Thus, each read threshold is arranged between adjacent threshold voltage distribution windows corresponding to different program states, such that each read threshold can distinguish between these program states by turning on or off the memory cell transistor.

[0074] When performing read operations on memory cells in a data storage device using MLC techniques, the threshold voltage levels of the memory cells are compared to a plurality of read threshold levels to determine the state of an individual memory cell. Read errors can be caused by distorted or overlapping threshold voltage distributions. Ideal memory cell threshold voltage distributions can be significantly distorted or overlap due to, for example, program and erase (P / E) cycles, inter-cell interference, and data retention errors. For example, as the number of program / erase cycles increases, the margin between adjacent threshold voltage distributions for different program states decreases, and eventually the distributions begin to overlap. As a result, memory cells with threshold voltages that fall within the overlapping range of adjacent distributions can be read as being programmed to a value different from the original target value, resulting in a read error. In most cases, such read errors can be managed by using error correction codes (ECC). When the number of error bits for a read operation exceeds the ECC error correction capability of the data storage, the read operation fails.

[0075] Certain conditions or operating conditions, such as charge leakage over time and device usage wear, can cause threshold voltage shifts. Such threshold voltage shifts can create read errors because several "off' cells can have threshold voltages above the read threshold due to threshold voltage shifts. Various conditions can cause threshold voltage shifts to create read errors. For example, a memory device with low endurance can create more read errors than a memory device with high endurance. Such threshold voltage shifts can be caused by operating conditions, such as an increase in the number of program / erase cycles for a memory array and an increase in the operating temperature of the data storage device. Read interference and the location of the memory chip or memory block can also be considered to determine whether threshold voltage shifts can occur.

[0076] Endurance of a flash memory can refer to the maximum number of program / erase operations that the flash memory can successfully perform. Each memory cell can only be programmed and erased a limited number of times before it can fail. In some embodiments of the disclosed technology, endurance of a flash memory refers to the maximum number of program / erase operations per set period (e.g., day). Endurance of a flash memory can be affected by structural issues (e.g., high memory density) and operating conditions (e.g., high program voltage).

[0077] Data retention can refer to operating conditions related to the time that a memory cell maintains a correctly programmed state. Data retention can vary depending on the operating temperature and the number of program / erase operations performed on the memory cell. Subjecting memory cells to high temperatures and a large number of program / erase operations tends to decrease their data retention.

[0078] Read disturb represents a phenomenon where reading data from a flash memory cell causes the threshold voltage of other un-read cells in the same block to shift to a different (e.g., higher) value. While the individual threshold voltage shifts are small, over time as read operations are performed, the threshold voltage shifts eventually become large enough to change the state of the memory cell.

[0079] The die, block, and word line indices can represent the physical location of the memory cell to be read. The data storage device can be composed of multiple memory chip dies, each including multiple memory blocks. Each memory block includes multiple memory cells, and each memory cell is selected by a word line coupled to each memory cell. The memory controller can be configured to track movement of data across multiple dies and multiple blocks. Based on the movement of data, the memory controller can determine how many program / erase operations have been performed on a certain memory die or a certain memory block. This information can be stored with reference to the die index, the block index, and the word line index to identify locations in the set of program / erase operations. When data is read from any of these locations, the likelihood of a read error is higher.

[0080] However, this read error can be minimized by modifying the read threshold. In some embodiments of the disclosed technology, a flash memory based data storage SSD device can modify the read threshold according to operating conditions of the read error. These operating conditions include, but are not limited to, the endurance of the memory device, the data retention, the read disturb, the age of the associated storage device, the operating temperature of the data storage device, and the location of the memory cell to be read (which can be indicated by the die index, the block index, and / or the word line index).

[0081] The performance (e.g., input / output operations per second and throughput) of a data storage device such as an SSD depends largely on the read threshold setting (i.e., read voltage setting) applied when the first read operation is performed. If the read threshold is not optimized, the performance can degrade because such an unoptimized read threshold voltage can cause a read error. The optimization of the read threshold voltage depends on certain operating conditions such as the physical location of the data, the device endurance, the data retention time, the operating temperature, the read disturb, and the age of the device. However, it is not practical to manually consider all possible combinations of different operating conditions to modify the read threshold. It would be even more difficult to obtain an optimized read threshold manually if the operating conditions change frequently. Therefore, there is a need to provide a system and method to optimize the read threshold using deep learning. One implementation of deep learning has a structure as shown in Figure 7 、 Figure 8 and Figure 9 performs as shown in Figure 10 and Figure 11The operations shown. Such a structure is described in U.S. Patent Application Serial No. 16 / 717,888, entitled “STORAGE DEVICE PERFORMANCE OPTIMIZATION USING DEEP LEARNING,” which is incorporated herein by reference.

[0082] In some embodiments of the disclosed technology, read errors can be minimized by using a deep neural network to identify specific effects of threshold voltage shifts that can occur in the memory cell array of a data storage device based on operating conditions discussed above. In some implementations of the disclosed technology, operating conditions that will cause threshold voltage shifts that can result in read errors are classified and quantified using a deep neural network. Some implementations of the disclosed technology include determining criteria that must be met for a read threshold to be set to a particular value. For example, when it is determined that the criteria for an optimal read threshold are not met (e.g., when the number of errors or error indications from the memory device are near an undesirably high value, temperature values are near lower or higher thresholds, etc.), the memory controller can use values generated by a deep learning neural network engine to obtain new values to modify the read threshold based on sensed operating conditions. Operating conditions, including physical location of the data, endurance of the data storage device, data retention, operating temperature, read disturbance, and age of the data storage device, can be used to estimate or predict threshold voltage shifts. The deep neural network can be trained based on input data collected from a large number of flash memory chip dies. For example, the deep neural network can be trained based on a limited combination of operating conditions. In an implementation, the optimized read threshold voltage is computed from the trained deep neural network engine. In another implementation, the values obtained by the trained neural network engine can be stored in a memory (e.g., a lookup table) of the data storage device, and a memory controller in the data storage device can modify the read threshold voltage based on the values.

[0083] In some embodiments of the disclosed technology, a deep neural network is used to predict optimal read thresholds from operating conditions of a storage device. In one example, a deep learning network can be used to interpolate optimal read thresholds associated with operating conditions that are not present in a training dataset obtained from offline memory device characterization. In some embodiments of the disclosed technology, a trained deep neural network for optimizing read threshold voltages can be obtained from an offline computation process based on a limited combination of operating conditions. Based on a larger set of operating conditions, optimal read thresholds for all possible combinations of operating conditions can be computed by a trained deep learning network, so that the optimization results can be used during actual read operations of a memory device.

[0084] Figure 7 An example of a deep neural network architecture for data storage performance optimization implemented based on some embodiments of the disclosed technology is shown. The deep neural network architecture for data storage performance optimization 700 includes a plurality of input nodes 710, first and second connection layers 720 and 760, a plurality of connection nodes 730 and 750, and a deep neural network 740, and a plurality of output nodes 770. Here, the first and second connection layers 720 and 760 can be fully connected layers. For example, the first connection layer 720 can be configured to connect all input nodes 710 to all connection nodes 730 of the deep neural network 740. Likewise, the second connection layer 760 can be configured to connect all output nodes 770 to all connection nodes 750 of the deep neural network 740. In some embodiments of the disclosed technology, the input nodes 710 and the output nodes 770 can be input neurons and output neurons, and the first connection layer 720 and the second connection layer 760 can be synapse layers, as will be discussed below.

[0085] The trained deep neural network 740 receives, through the plurality of input nodes 710, the first connection layer 720, and the first connection nodes 730, operating conditions that result in read errors, such as endurance, retention, read disturbance, die index, block index, word line index, age of the data storage drive, and / or temperature. The deep neural network 740 measures data in a memory device under a combination of operating conditions using a set of read thresholds. For example, the deep neural network 740 can read out data from a certain memory cell of a data storage device under an input combination of operating conditions, including endurance of the memory device to which the memory cell belongs, data retention of the memory device to which the memory cell belongs, expected read disturbance associated with the memory cell, age of the data storage device, operating temperature of the data storage device, and physical location of the memory cell (which can be determined based on die index, block index, and word line index). For operating conditions with continuous values, some implementation examples of the disclosed deep neural network only select or extract discrete values. In this way, the best read threshold can be derived from the trained deep neural network. In an implementation, the threshold voltage optimized corresponding to each combination of operating conditions can be stored in a memory (e.g., SRAM) of the storage device.

[0086] Figure 8 An example configuration of a computational neural network including input neurons 810, hidden neurons 820, output neurons 830, and synapse layers 840 and 850 is shown. For example, the synapse layer 840 can include a plurality of weights W 11 , W 12 , W 13 , W 14 , W 21 , W22 , W 23 , W 24 , W 31 , W 32 , W 33 and W 34 . Input neurons 810 receive some values and propagate them to the network's hidden neurons 820. The weighted sum from one or more layers of hidden neurons 820 is eventually propagated to the output neurons 830. Here, the output of a neuron is often referred to as activation, and the synapse is often referred to as a weight. An example of computation for each layer can be represented as:

[0087]

[0088] where Wji, Xi, and Yj are the weights, input activations, and output activations, respectively.

[0089] In some embodiments of the disclosed technology, input parameters such as endurance, retention, read disturb, die index, block index, word line index, age of the data storage drive, and temperature, etc. are fed into the first layer of a deep neural network, and the output of this layer can be interpreted as representing the presence of different features that cause threshold voltage shift. In subsequent layers, these features are then combined into a measure of the possible presence of higher level features, which are further combined to provide a probability that these high level features require read threshold modification.

[0090] In some embodiments of the disclosed technology, the neural network algorithm for data storage performance optimization includes determining the values of the weights (and biases) in the neural network, and is referred to as training the network. After training, the program can perform its task by computing the output of the neural network using the weights determined during training. Running the program using these weights is called inference. There are multiple ways to train the weights. Supervised learning is a method where all training samples are labeled. Unsupervised learning is another method where all training samples are unlabeled, and the goal is essentially to find the structure or clusters in the data. Semi-supervised learning is in between the two methods, where only a small portion of the training data is labeled.

[0091] Figure 9An example of a training method 900 for a deep neural network for data storage optimization implemented based on some embodiments of the disclosed technology is shown. First, in the case where the operating conditions have continuous values, discrete values are selected from the continuous values of the operating conditions that cause read errors in the data storage device. At step 910, data in the memory device is read out at certain combinations of operating conditions using a first set of read threshold voltages. For example, threshold voltages of memory cells of the memory device are measured at certain combinations of operating conditions using the first set of read threshold voltages. In an implementation, threshold voltages of memory cells are measured at certain combinations of discrete values of operating conditions using a set of read threshold voltages. At step 920, a suitable read threshold is found to produce a labeled training dataset. At step 930, based on the characteristics of the memory device, the number of layers and the size of each layer are determined to construct a deep neural network engine. For example, the number of layers and the size of each layer are determined as hyperparameters of the deep neural network engine. Some examples of the deep neural network engine can include at least two layers, N input nodes, and M output nodes. Here, N is the number of conditions considered and M is the number of different read threshold settings considered. The number of layers and the size of each layer depend on the characteristics of the memory cells. After the number of layers and the size of each layer are determined, the layers and input / output nodes of the deep neural network engine are configured. At step 940, the deep neural network engine is trained using the labeled training dataset corresponding to the best read threshold. At step 950, the trained deep neural network engine is used to compute read threshold voltage values at a larger set of operating conditions.

[0092] In some embodiments of the disclosed technology, the deep neural network engine for data storage performance optimization can be designed to help identify the most influential operating conditions in determining the threshold voltage offset amount to select an optimized read threshold for a given threshold voltage distribution window. Based on these features, machine learning techniques can be utilized to decide the optimized read threshold to minimize read errors. In an implementation, the optimized read threshold associated with the labeled training dataset can be stored in the memory (e.g., SRAM) of the storage device.

[0093] Figure 10 An example of an inference method 1000 for a deep neural network for data storage optimization implemented based on some embodiments of the disclosed technology is shown. At step 1010, the current operating conditions are fed to the input nodes of the trained deep neural network. At step 1020, the best read threshold is obtained from the output nodes of the trained deep neural network. At step 1030, the read threshold is modified to the best read threshold. At step 1040, data can be read out from the memory cells using the best read threshold.

[0094] Figure 11An example of a deep neural network 1100 for data storage optimization implemented based on some embodiments of the disclosed technology is shown. The deep neural network 1100 can include one or more processors 1110 and one or more memory devices 1120 operably coupled to the one or more processors 1110. The one or more processors 1110 are operable to receive a plurality of operating conditions that result in read errors in a data storage device. Some of the operating conditions that result in read errors in a data storage device include endurance, retention, read disturbance, die index, block index, word line index, age of the data storage drive, and operating temperature. The one or more processors 1110 are operable to predict an optimal read threshold value from the operating conditions of the storage device. For example, the one or more processors can interpolate an optimal read threshold value associated with operating conditions that are not present in a training dataset obtained from an offline memory device characterization using a deep learning algorithm.

[0095] In some embodiments of the disclosed technology, the one or more processors 1110 can be used to measure threshold voltages of memory cells at certain combinations of operating conditions. The one or more processors 1110 can be used to find an optimal read threshold value for each threshold voltage distribution, resulting in a labeled training dataset. In one example, the one or more processors 1110 can include a labeled training data preparation module 1112 configured to produce the labeled training dataset. The one or more processors 1110 can be used to configure input nodes 1130 for receiving and output nodes 1140. For example, the one or more processors 1110 can be used to configure N input nodes and M output nodes, where N is the number of operating conditions under consideration and M is the number of different read threshold settings under consideration. The one or more processors 1110 can be used to decide hyperparameters of the deep neural network. The one or more processors can be used to train based on the labeled training dataset. In one example, the one or more processors 1110 can include a training module 1114 configured to train based on the labeled training dataset. In some embodiments of the disclosed technology, the one or more memory devices 1120 can be configured to store a set of hyperparameters 1122 of the trained model and read thresholds 1124.

[0096] The one or more processors 1110 can be used to obtain an optimal read threshold value from the output nodes corresponding to a combination of operating conditions fed to the input nodes. The optimal read threshold value and its corresponding combination of operating conditions can be used to compute an optimal threshold voltage of a memory device in a data storage device. In implementations, the data storage device can be used to decide a read threshold value using the trained deep neural network engine.

[0097] As described above, to optimize read threshold voltage values, one embodiment of a deep learning framework has a structure as shown in Figure 7 Figure 7 The deep learning framework of Figures 12A to 12C uses features such as NAND conditions (i.e., endurance, retention, read disturb, age of the drive, temperature) and physical location of the data (i.e., die index, block index, WL index). Another embodiment of a deep learning framework has a structure as shown in Figure 7 Figures 12A to 12C In addition to the features of

[0098] Figures 12A to 12C An architecture of a deep neural network 1100 according to an embodiment of the application is shown.

[0099] Referring to Figures 12A to 12C , a deep neural network (DNN) 1100 can receive a plurality of operating conditions that cause read errors in a data storage device (e.g., a memory system of Figure 2 ). The operating conditions can include conditions of the associated memory device (i.e., NAND) such as endurance, retention, read disturb, age of the data storage device (or drive) and operating temperature, and physical location of the data to be read (e.g., die index, block index, and word line index), as shown in Figure 7 Further, the operating conditions can include a set of read threshold voltages and error information associated with data read from the memory device using the set of read threshold voltages. In the example shown in Figure 12A , the set of read threshold voltages can be [VT2, VT6] for the LSB page of TLC. In the example shown in Figure 12B , the set of read threshold voltages can be [VT0, VT4] for the MSB page of TLC. In the example shown in Figure 12C ​​In the example shown, for the CSB page of a TLC, the read threshold voltage set can be [VT1, VT3, VT5]. In some embodiments, the error information can be a failure bit count (FBC), which is obtained by decoding read data from the memory device using the read threshold voltage set provided to the DNN 1100. Therefore, the deep neural network 1100 can have a regression deep learning framework, which can be used to predict the optimal read threshold from operating conditions including the read threshold voltage set and error information, as well as other operating conditions, such as... Figure 7 As shown. For example, the deep neural network 1100 can use a deep learning algorithm to interpolate an optimal read threshold associated with operating conditions in a training dataset obtained from a feature description of an offline storage device, where the optimal read threshold does not exist in the training dataset.

[0100] Based on typical reading schemes, it can be configured to implement Figure 11 Deep neural network models Figure 2 The control component 120 can use a default read threshold voltage to control read operations on memory cells. When a read operation using the default read threshold voltage fails, the control component 120 can control... Figure 13 The error recovery algorithm 1300 is shown.

[0101] Reference Figure 13 The control component 120 may perform one or more read retry operations (1310) on memory cells using one or more read threshold voltages applied in a set order. For example, the read threshold voltages may include N (e.g., N is 50) read threshold voltages (or read voltage levels), including a first read threshold voltage to an Nth read threshold voltage. The first read threshold voltage may be a previously used read threshold voltage (i.e., a historical read threshold voltage). A historical read threshold voltage may be the read threshold voltage used in the last successful decoding, i.e., the read voltage used in a read operation that passed before the read retry operation. The control component 120 may perform read retry operations until a successful decoding associated with the corresponding read retry operation is determined.

[0102] When all read retry operations using the read threshold voltage fail, the control component 120 may perform additional recovery operations. For example, additional recovery operations may include optimal read threshold voltage search (1320), soft decoding using error correction codes (ECC) (1330), and independent disk redundant array (RAID) recovery (1340).

[0103] As described above, the error recovery algorithm 1300 records the last successful read threshold record and updates it as a history read threshold voltage. However, depending on the conditions of the page to be read, the history read threshold voltage can sometimes be far from the optimal read threshold voltage for the next read operation. When the gap (or difference) between the history read threshold voltage and the optimal read threshold is large, the error related to the decoding of the read data can be large and exceeds the error correction capability of the error correction code (ECC) scheme used in decoding the read data. Thus, what should be estimated and used for the next read operation is the optimal read threshold voltage, not the history read threshold voltage. Doing so can reduce the probability of decoding failure for the next read operation. However, the optimal read threshold voltage can frequently change depending on various factors including the conditions or states of the memory device 200. The frequent change of the read threshold voltage results in more set commands being transmitted from the memory controller 100 to inform the memory device 200 of the change of the read threshold. Transmitting the set commands can increase the overall read latency, thereby degrading the quality of service (QoS) of the read operation of the memory system. Accordingly, various embodiments provide a scheme for determining whether to use another read threshold voltage in the next read operation instead of the history read threshold voltage based on the error information (e.g., the failed bit count) and the utilization of the queue in the decoder. When certain conditions are satisfied, the embodiments can determine that another read threshold voltage, not the history read threshold voltage, is to be used for the next read operation, which is determined based on the error information and the utilization. Accordingly, the embodiments can reduce the frequency of the change of the read threshold voltage and the corresponding transmission from the controller to the memory device regarding such change, thereby improving the overall read latency and quality of service (QoS) of the read operation in the memory system.

[0104] Figure 14 is a diagram illustrating a memory system 10 including a deep neural network according to an embodiment of the present application.

[0105] Referring to Figure 14 , the memory system 10 can include a memory controller 100 and a memory device 200. The memory device 200 can include a plurality of memory cells (e.g., NAND flash memory cells) 2100 and a voltage generation circuit 230 configured to generate operation voltages for various operations on the memory cells 2100. The memory cells are arranged in an array of rows and columns, as Figure 3The cells in each row are connected to word lines (e.g., WL0), and the cells in each column are connected to bit lines (e.g., BL0). These word lines and bit lines are used for read and write operations. During a write operation, the data to be written ("1" or "0") is provided to the bit line while the word line is high. During a read operation, the word line is high again, and the threshold voltage for each cell can then be obtained from the bit line. Multiple pages can share memory cells belonging to (i.e., connected to) the same word line. When the memory cell is implemented using MLC, multiple pages include a most significant bit (MSB) page and a least significant bit (LSB) page. When the memory cell is implemented using TLC, multiple pages include an MSB page, a middle significant bit (CSB) page, and an LSB page. When the memory cell is implemented using QLC, multiple pages include an MSB page, a middle most significant bit (CMSB) page, a middle least significant bit (CLSB) page, and an LSB page. The memory cells can be programmed using an encoding scheme (e.g., Gray encoding) to increase the capacity of a memory system 10 such as an SSD.

[0106] The memory controller 100 may include a deep neural network (DNN) 1100, a decoder 1410, and a read threshold change determiner 1420. These components can utilize... Figure 2 The control component 120 is implemented using internal components (i.e., firmware (FW)). Although not shown in Figure 5, the memory controller 100 and the memory device 200 may include, for example, internal components (i.e., firmware (FW)). Figure 2 Various other components are shown.

[0107] exist Figure 11 In the illustrated embodiments, the deep neural network 1100 may include one or more processors 1110 and one or more memory devices 1120 operatively coupled to the one or more processors 1110. The deep neural network 1100 can control various operations, such as operations on memory cells 2100, and optimize read threshold voltage values ​​using features such as NAND conditions (i.e., endurance, retention, read interference, driver lifespan, temperature) and the physical location of data (i.e., die index, block index, WL index). In some embodiments, the deep neural network 1100 may include a read level table storing multiple read threshold voltages (or read voltage levels), and use a read threshold voltage selected from the read level table to control read operations on memory cells 2100.

[0108] The decoder 1410 can include a queue for storing data read from the memory cell 2100. The utilization of the queue can change according to the amount of data read from the memory cell 2100. The decoder 1410 can decode the data stored in the queue and generate error information (i.e., failed bit count (FBC)) corresponding to the decoding result. In some embodiments, the decoder 1410 can be implemented with a decoder using a low-density parity-check (LDPC) code as an error correction code (ECC), i.e., an LDPC decoder.

[0109] When it is determined that the initial read operation fails, the deep neural network 1100 can perform a read retry operation on the memory cell 2100 using the historical read threshold voltage. When it is determined that the read retry operation using the historical read threshold voltage fails, the deep neural network 1100 can perform one or more additional read retry operations on the memory cell 2100 using one or more other read threshold voltages. The plurality of read threshold voltage entries in the read threshold voltage table 1300 (e.g., Figure 13 The plurality of read threshold voltage entries in the read threshold voltage table 1300 (e.g.,

[0110] In some embodiments, the deep neural network 1100 can determine and maintain error information (i.e., failed bit count (FBC)) associated with the decoding results of the read operations on the plurality of memory cells using the plurality of read retry threshold voltages.

[0111] The read threshold change determiner 1420 can determine whether to change the historical read threshold voltage, i.e., to use another read threshold voltage. When it is determined that such a change is not needed, the historical read threshold voltage can be used for the next read operation. When it is determined that a read threshold voltage other than the historical read threshold voltage is to be used, the optimal read threshold voltage can be estimated and used for the next read operation.

[0112] The deep neural network 1100 can estimate the optimal read threshold voltage for the next read operation among the plurality of read threshold voltages based on the failed bit counts associated with the decoding of the data read from the memory cell 2100. For example, the optimal read threshold voltage can be the read threshold voltage among the plurality of read retry thresholds having the lowest failed bit count.

[0113] In some embodiments, the read threshold change determiner 1420 can determine whether to use a read threshold voltage other than the historical read threshold voltage based on the failed bit count, the error correction capability of the decoder, and the utilization of the queue in the decoder.

[0114] When it is determined that the historical read threshold voltage is not to be used for the next read operation, the deep neural network 1100 can transmit a command including parameters associated with setting the optimal read threshold to the memory device 200. When it is determined that the historical read threshold voltage is to be used for the next read operation, the deep neural network 1100 can transmit a command indicating no change to the historical read threshold voltage to the memory device 200. Alternatively, when it is determined that the historical read threshold voltage is to be used for the next read operation, the deep neural network 1100 can not transmit any command to the memory device 200.

[0115] Figure 15 and Figure 16 is a diagram illustrating a read threshold change determiner 1420 according to an embodiment of the present application.

[0116] Referring to Figure 15 , the read threshold change determiner 1420 can receive a failed bit count (FBC) from the deep neural network 1100 and a utilization of a queue from the decoder 1410. Further, the read threshold change determiner 1420 can receive a historical read (HR) threshold voltage from the deep neural network 1100 firmware and an error correction capability and a utilization threshold from the decoder 1410. Alternatively, the error correction capability and the utilization threshold can be provided to the read threshold change determiner 1420 in advance.

[0117] The read threshold change determiner 1420 can determine whether the historical read threshold voltage is to be used for the next read operation, i.e., whether the historical read threshold voltage is to be changed, based on the failed bit count (FBC), the error correction capability of the decoder 1410, and the utilization of the queue in the decoder 1410.

[0118] When it is determined that such a change is to be made, the read threshold change determiner 1420 can transmit a first command to the memory device 200. In some embodiments, the first command can indicate that the read threshold voltage to be used for the next read operation is changed from the historical read threshold voltage to the optimal read threshold voltage and include parameters set for using the optimal read threshold voltage. For example, the first command can be a set parameter command for updating, in the voltage generation circuit 230 of the memory device 200, that the optimal read threshold voltage is to be used for the next read operation, not the historical read threshold voltage.

[0119] When it is determined that the historical read threshold voltage is to be used in the next read operation, the read threshold change determiner 1420 can transmit a second command to the memory device 200. In some embodiments, the second command can indicate that the historical read threshold voltage is not to be changed, and thus no change operation is to be performed on the memory device 200. Alternatively, when it is determined that the historical read threshold voltage is to be used in the next read operation, the read threshold change determiner 1420 can not transmit any command to the memory device 200.

[0120] When the failed bit count corresponding to the historical read threshold voltage is less than a portion of the error correction capability of the decoder 1410, the read threshold change determiner 1420 can determine that the historical read threshold voltage is to be used in the next read operation. In some embodiments, the portion can be 75% of the code error correction capability. For example, for a code that can correct 200 bit errors, the portion is 150. In this case, the deep neural network 1100 can select the historical read threshold for the next read operation.

[0121] When the utilization of the queue is greater than a set utilization threshold or when the failed bit count corresponding to the historical read threshold voltage is greater than or equal to a portion of the decoder error correction capability, the read threshold change determiner 1420 can determine that the historical read threshold voltage is not to be used in the next read operation, i.e., the historical read threshold voltage is to be changed in the next read operation. In some embodiments, a percentage of the maximum queue size can be used as the utilization threshold, e.g., the utilization threshold is set to 80% of the maximum queue size. In these cases, the deep neural network 1100 can select the optimal read threshold for the next read operation.

[0122] Referring to Figure 16 , the read threshold change determiner 1420 can include a first comparator 1422, a second comparator 1424, and a command output component 1426. The first comparator 1422 can compare the utilization of the queue with a set utilization threshold. The second comparator 1424 can compare the failed bit count (i.e., FBCHR) corresponding to the historical read threshold with a small portion of the error correction capability. The command output component 1426 can select one of the first command and the second command based on the outputs, i.e., comparison results, of the first comparator 1422 and the second comparator 1424, and transmit the selected command to the memory device 200.

[0123] The command output component 1426 can include a logic gate 1426A and a selector 1426B. The logic gate 1426A can receive the comparison results of the first comparator 1422 and the second comparator 1424 and perform a logical operation on the comparison results. In some embodiments, the logic gate 1426A can be implemented with an OR gate. The selector 1426B can select one of the first command and the second command in response to the logical operation of the logic gate 1426A and transmit the selected command to the memory device 200.

[0124] In some embodiments, the first command can be a set parameter command associated with a parameter for the optimal read threshold setting, and the second command can indicate not to perform a change operation on the memory device 200.

[0125] As described above, the estimated fail bit count can be estimated for the current history read threshold voltage. When the estimated fail bit count is below a fraction of the decoder error correction capability, the setting of the history read threshold voltage can be kept and used. Otherwise, the optimal read threshold voltage with the lowest estimated fail bit count can be selected by a set parameter command and used to replace the history read threshold voltage. According to embodiments, the change from the history read threshold voltage to the optimal read threshold voltage occurs when it is determined that the history read threshold voltage is to be changed.

[0126] The read threshold change determiner 1420 can receive the estimated fail bit counts for all candidate read retry threshold (RRT) from the deep neural network 1100. The read threshold change determiner 1420 can also receive the current history read threshold voltage recorded by the firmware. This history read threshold voltage should be included in the candidate RRT. The read threshold change determiner 1420 can receive the correction capability of the decoder corresponding to the error correction code used to decode the relevant page. The read threshold change determiner 1420 can also receive the current utilization of the queue in the decoder. When the current utilization of the queue (as a percentage of its total utilization capacity) is large, selecting a read threshold voltage close to the optimal one by a set parameter command is beneficial to reduce the decoding latency of the next read. Thus, even though there is an increase in latency due to the set parameter command, the overall read latency can be smaller.

[0127] In some implementations, the utilization threshold can be dynamically modified by the firmware according to the current workload of the drive, the required read QoS, and the NAND conditions (e.g., reserved, completed program-erase cycles) through registers. In other implementations, the deep neural network 1100 can provide a confidence of the estimated fail bit count (FBC), and the confidence value is used to make better decisions in the read threshold change determiner 1420. In some variations, if the confidence of the FBC is below a certain threshold, the read threshold change determiner 1420 can decide to not change the read threshold voltage. optthe confidence is higher (or lower), the read threshold variation determiner 1420 can select (or not select) the set parameter command. In some variations, if the deep neural network 1100 selects the same read threshold voltage as the best read threshold voltage for more than a set portion of the physical pages (e.g., 2 pages), the read threshold variation determiner 1420 can select the set parameter command, where the read operation is suspended in the corresponding memory device (e.g., NAND flash die) for the set portion of the physical pages.

[0128] Figure 17 is a flowchart illustrating operations 1700 of a memory system according to an embodiment of the present application. The operations 1700 can be performed by firmware of a memory controller 100 including a deep neural network 1100 in the memory controller 100. Figure 14

[0129] Referring to FIG. 17, Figure 17 At operation 1710, the memory controller 100 can determine whether a read threshold voltage other than a history read threshold voltage is to be used for a next read operation based on a fail bit count associated with a read operation using the history read threshold voltage, an error correction capability of a decoder, and / or a utilization of a queue in the decoder. The history read threshold voltage can be a read threshold voltage used in a previous successful read operation.

[0130] At operation 1720, when it is determined that the history read threshold voltage is not to be used for the next read operation (i.e., the history read threshold voltage is to be changed), the memory controller 100 can determine fail bit counts associated with read operations using a plurality of read threshold voltages on a plurality of memory cells.

[0131] At operation 1730, the memory controller 100 can determine a best read threshold voltage having a lowest fail bit count among the plurality of read threshold voltages based on the fail bit counts.

[0132] At operation 1740, the memory controller 100 can transmit a first command to the memory device, the first command indicating a change from the history read threshold voltage to the best read threshold voltage and including a parameter set for the best read threshold.

[0133] In some embodiments, when it is determined that the history read threshold voltage is to be used for the next read operation, the memory controller 100 can transmit a second command to the memory device indicating not to change the history read threshold voltage and not to perform a corresponding change operation on the memory device.

[0134] ​In some embodiments, when the failed bit count corresponding to the historical read threshold voltage is less than a fraction (e.g., 75%) of the error correction capability of the decoder, the memory controller 100 can determine that the historical read threshold voltage is to be used for the next read operation.

[0135] In some embodiments, when the failed bit count corresponding to the historical read threshold voltage is greater than or equal to a fraction (e.g., 75%) of the error correction capability of the decoder, the memory controller 100 can determine that the historical read threshold voltage is not to be used for the next read operation.

[0136] In some embodiments, when the utilization of the queue is greater than a set utilization threshold, the memory controller 100 can determine that the historical read threshold voltage is not to be used for the next read operation.

[0137] As described above, embodiments provide a scheme for determining whether to change the historical read threshold voltage (i.e., whether the historical read threshold voltage is to be used for the next read operation) based on error information (e.g., failed bit count) and estimating the optimal read threshold voltage when it is determined that the historical read threshold voltage is not to be used for the next read operation. According to embodiments, the historical read threshold voltage is changed to the optimal read threshold voltage under certain conditions, i.e., when it is determined that such a change is to be made. Thus, embodiments can reduce the frequency of read threshold voltage changes and the corresponding transmission from the controller to the memory device regarding such changes, thereby improving the overall read latency and quality of service (QoS) of read operations in the memory system.

[0138] While some detailed descriptions and explanations of the foregoing embodiments have been provided for purposes of clarity and understanding, the present disclosure is not limited to the details provided. As will be appreciated by persons skilled in the art, there are many alternatives ways of implementing the present disclosure. Accordingly, the disclosed embodiments are illustrative and not restrictive. The present disclosure is intended to include all alternatives and equivalents of all elements thereof.

Claims

1. A memory system comprising: a memory device comprising a plurality of memory cells; and a controller comprising a decoder, and: determining whether a read threshold voltage other than a historical read threshold voltage used as a read threshold voltage in a previous successful read operation is to be used for a next read operation based on a failed bit count associated with read operations using the historical read threshold voltage, an error correction capability of the decoder, and a utilization of a queue in the decoder, wherein the utilization of the queue represents a percentage of a total utilization capacity of the queue; after determining that the historical read threshold voltage is not to be used for the next read operation, determining a failed bit count associated with read operations using a plurality of read threshold voltages on the plurality of memory cells; determining a best read threshold voltage having a lowest failed bit count among the plurality of read threshold voltages based on the failed bit count; and transmitting a first command comprising a parameter associated with setting the best read threshold voltage to the memory device, or when it is determined that the historical read threshold voltage is to be used for the next read operation, transmitting a second command indicating no change to the historical read threshold voltage to the memory device, wherein, in a first comparison, the utilization of the queue is compared to a set utilization threshold, in a second comparison, a failed bit count corresponding to the historical read threshold voltage is compared to a portion of the error correction capability, and an output of the first comparison and an output of the second comparison are used to select the first command or the second command transmitted to the memory device.

2. The memory system of claim 1, wherein when the failed bit count corresponding to the historical read threshold voltage is less than a portion of the error correction capability of the decoder, the controller determines that the historical read threshold voltage is to be used for a next read operation, and selects the historical read threshold voltage.

3. The memory system of claim 2, wherein when the failed bit count corresponding to the historical read threshold voltage is greater than or equal to a portion of the error correction capability of the decoder, the controller determines that the historical read threshold voltage is not to be used for a next read operation.

4. The memory system of claim 3, wherein when the utilization of the queue is greater than the set utilization threshold, the controller determines that the historical read threshold voltage is not to be used for a next read operation.

5. The memory system of claim 4, wherein the controller comprises: a first comparator to compare the utilization of the queue to the set utilization threshold; and a second comparator to compare the failed bit count corresponding to the historical read threshold voltage to a portion of the error correction capability.

6. The memory system of claim 5, wherein the controller further comprises: a command output component selects one of the first command and the second command based on outputs of the first comparator and the second comparator, and transmits the selected command to the memory device.

7. The memory system of claim 6, wherein the command output component comprises: a logic gate that receives outputs of the first comparator and the second comparator and outputs a logical operation of the comparison results; and a selector that selects one of the first command and the second command in response to the logical operation and transmits the selected command to the memory device.

8. The memory system of claim 7, wherein the logic gate comprises: an OR gate that receives outputs of the first comparator and the second comparator and performs an OR operation on the outputs.

9. A method of operating a memory system, the memory system comprising a memory device and a controller coupled to the memory device and comprising a decoder, the method comprising: determining whether a read threshold voltage other than a history read threshold voltage used as a read threshold voltage in a previous successful read operation is to be used for a next read operation based on a failed bit count associated with read operations using the history read threshold voltage, an error correction capability of the decoder, and a utilization of a queue in the decoder, wherein the utilization of the queue represents a percentage of a total utilization capacity of the queue; after determining that the history read threshold voltage is not to be used for the next read operation, determining failed bit counts associated with read operations of a plurality of memory cells of the memory device using a plurality of read threshold voltages; based on the failed bit counts, determining an optimal read threshold voltage having a lowest failed bit count among the plurality of read threshold voltages; and transmitting a first command comprising a parameter associated with setting the optimal read threshold voltage to the memory device, or when it is determined that the history read threshold voltage is to be used for the next read operation, transmitting a second command indicating no change to the history read threshold voltage to the memory device, wherein, in a first comparison, the utilization of the queue is compared to a set utilization threshold, in a second comparison, the failed bit count corresponding to the history read threshold voltage is compared to a portion of the error correction capability, and outputs of the first comparison and the second comparison are used to select the first command or the second command transmitted to the memory device.

10. The method of claim 9, wherein determining whether the history read threshold voltage is to be used comprises: when the failed bit count corresponding to the history read threshold voltage is less than the portion of the error correction capability of the decoder, determining that the history read threshold voltage is to be used for the next read operation.

11. The method of claim 10, wherein determining whether the history read threshold voltage is to be used comprises: when the failed bit count corresponding to the history read threshold voltage is greater than or equal to the portion of the error correction capability of the decoder, determining that the history read threshold voltage is not to be used for the next read operation.

12. The method of claim 11, wherein determining whether to use the historical read threshold voltage comprises: determining not to use the historical read threshold voltage when the utilization of the queue is greater than the set utilization threshold.

13. The method of claim 12, further comprising: comparing, by a first comparator, the utilization of the queue to the set utilization threshold; and comparing, by a second comparator, a failed bit count corresponding to the historical read threshold voltage to a portion of the error correction capability.

14. The method of claim 13, further comprising: selecting one of the first command and the second command based on outputs of the first comparator and the second comparator.

15. The method of claim 14, wherein the selecting one of the first command and the second command comprises: performing a logical operation on the comparison results; and selecting one of the first command and the second command in response to the logical operation.

16. The method of claim 15, wherein the logical operation comprises an OR operation.

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