A preparation method of a semiconductor test chip for fault analysis

Abstract

The present invention discloses a method for preparing a semiconductor test chip for fault analysis. By using an adhesive layer composed of an adhesive material that is non-volatile, non-liquid, has a high adhesion property to dielectric materials, and has a low adhesion property to metal contact materials, it is possible to selectively remove a partial thickness of the dielectric material with a large area and high uniformity, and completely retain the metal contact material, without generating a chemical reaction with the semiconductor sample or even damaging the structure to be analyzed. Moreover, by selecting different adhesive layer materials, the adhesion degree to the dielectric layer can be controlled, and thus the thickness of the removed dielectric layer can be controlled. Therefore, a semiconductor test chip for fault analysis applicable to size reduction can be provided.

Description

Technical Field

[0001] The present invention discloses a method for preparing a semiconductor test chip for failure analysis, and particularly relates to a method for preparing a semiconductor test chip for failure analysis by utilizing the difference in material adhesion. Background Art

[0002] It is known that the method for preparing a semiconductor test chip for failure analysis usually has to delayer layer by layer to provide a semiconductor test chip for failure analysis. As Figures 1A to 1B shown in a known method for preparing a semiconductor test chip for failure analysis, the steps include first providing a semiconductor sample 10 as Figure 1A shown. The aforementioned semiconductor sample 10 includes a semiconductor component 100, a metal contact layer 180 connecting the aforementioned semiconductor component 100, a first dielectric layer 170 covering the aforementioned semiconductor component 100 and the aforementioned metal contact layer 180, a wire layer 185 formed on the aforementioned first dielectric layer 170 and connecting the aforementioned metal contact layer 180 to electrically connect the aforementioned semiconductor component 100, and a second dielectric layer 200 covering the aforementioned wire layer 185. The aforementioned semiconductor component 100 includes, for example, a semiconductor substrate 110, a gate 120, a gate oxide layer 130, a source 140, and a drain 160. Then, as Figure 1B shown, the aforementioned second dielectric layer 200 and the aforementioned wire layer 185 are removed by using manual grinding and chemical etching solution to partially expose the metal contact layer 180 for facilitating the search for defect locations or subsequent failure analysis. As Figures 1A to 1B shown in a known method for preparing a semiconductor test chip for failure analysis, since the aforementioned second dielectric layer 200 and the aforementioned wire layer 185 are removed by using manual grinding and chemical etching solution, for a semiconductor sample with a larger size, due to the thicker dielectric layer, the semiconductor component 100 is less likely to be damaged during the process of removing the aforementioned second dielectric layer 200 by using manual grinding and chemical etching solution. However, as the semiconductor manufacturing process size gradually shrinks, the thickness of the dielectric layer becomes smaller and smaller. When using manual grinding and chemical etching solution for delayer treatment, the semiconductor component 100 in the semiconductor sample 10 may be damaged, as Figure 1B shown because the etching solution leaks through the failure point during the grinding process, resulting in defect channels 190, 195 where the first dielectric layer 170 is etched to expose the surface of the gate 120 or the surface of the drain 160, or the metal contact layer 180 is etched and damaged, leading to the inability to complete the preparation of the semiconductor test chip for failure analysis.

[0003] In view of this, a method for preparing a semiconductor test chip for failure analysis that does not damage the semiconductor component in the semiconductor sample is eagerly awaited in the current semiconductor industry. Summary of the Invention

[0004] The present invention discloses a method for preparing a semiconductor test piece for fault analysis, which is characterized by comprising the following steps: providing a semiconductor sample, wherein the semiconductor sample includes a semiconductor component, a metal contact layer, a first dielectric layer, a wire layer, and a second dielectric layer, wherein the metal contact layer is connected to the semiconductor component, the first dielectric layer covers the semiconductor component and the metal contact layer, the wire layer is formed on the first dielectric layer and electrically connects the semiconductor component by connecting the metal contact layer, and the second dielectric layer covers the wire layer; performing a grinding treatment on the semiconductor sample, with the interface between the metal contact layer and the wire layer as the grinding end point, and gradually grinding away the second dielectric layer and the wire layer; forming an adhesive layer on the surface of the ground semiconductor sample, wherein the adhesion of the adhesive layer to the first dielectric layer is greater than the adhesion of the adhesive layer to the metal contact layer; and after curing the adhesive layer, peeling off the adhesive layer, so that a part of the first dielectric layer is peeled off together with the adhesive layer, and a part of the metal contact layer is exposed.

[0005] The method for preparing a semiconductor test piece for fault analysis as described above, wherein the first and second dielectric layers are composed of the same or different dielectric materials.

[0006] The method for preparing a semiconductor test piece for fault analysis as described above, wherein the first and second dielectric layers are composed of the same dielectric material, and the dielectric material is mainly silicon oxide.

[0007] The method for preparing a semiconductor test piece for fault analysis as described above, wherein the grinding treatment step is manual grinding or mechanical grinding.

[0008] The method for preparing a semiconductor test piece for fault analysis as described above, wherein the adhesive layer is a glue layer, a tape, or a wax layer.

[0009] The method for preparing a semiconductor test piece for fault analysis as described above, wherein the glue layer or the tape contains a non-volatile and non-liquid adhesive material.

[0010] The method for preparing a semiconductor test piece for fault analysis as described above, wherein the non-volatile and non-liquid adhesive material is silicone.

[0011] The method for preparing a semiconductor test piece for fault analysis as described above, wherein the thickness of the adhesive layer is between 50 and 100 micrometers.

[0012] The method for preparing a semiconductor test piece for fault analysis as described above, wherein the curing step of the adhesive layer is room temperature curing, heat curing, or light curing. Description of the Drawings

[0013] Figures 1A to 1B The illustrated cross-sectional process schematic diagram is a known method for preparing a semiconductor sample for failure analysis.

[0014] Figures 2A to 2D The illustrated cross-sectional process schematic diagram is a method for preparing a semiconductor sample for failure analysis according to the embodiments disclosed in the present invention.

[0015] Among them, a brief description of the symbols in the drawings is as follows:

[0016] 10 Semiconductor sample

[0017] 10’ Ground semiconductor sample

[0018] 20 Semiconductor test wafer for failure analysis

[0019] 100 Semiconductor component

[0020] 110 Semiconductor substrate

[0021] 120 Gate

[0022] 130 Gate oxide layer

[0023] 140 Source

[0024] 160 Drain

[0025] 170 First dielectric layer

[0026] 180 Metal contact layer

[0027] 185 Conductive line layer

[0028] 190, 195 Defect channels

[0029] 200 Second dielectric layer

[0030] 250 Interface between the metal contact layer and the conductive line layer

[0031] 250’ Surface of the ground semiconductor sample 10’

[0032] 300 Adhesive layer Detailed implementation manners

[0033] In order to make the disclosure of the present invention more detailed and complete, the following provides an illustrative description of the implementation aspects and specific embodiments of the present invention; however, this is not the only form for implementing or applying the specific embodiments of the present invention. The following disclosed embodiments can be combined or replaced with each other under beneficial circumstances, or other embodiments can be added to one embodiment without further record or explanation.

[0034] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the embodiments below. However, embodiments of the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown schematically in the drawings for simplicity.

[0035] Embodiment

[0036] Please refer to Figures 2A to 2D , the cross-sectional process schematic diagram shown therein is a method for preparing a semiconductor sample for failure analysis disclosed according to an embodiment of the present invention.

[0037] First, as Figure 2A shown, a semiconductor sample is provided. The aforementioned semiconductor sample includes a semiconductor sample 10. The aforementioned semiconductor sample 10 includes a semiconductor component 100, a metal contact layer 180, a first dielectric layer 170, a wire layer 185, and a second dielectric layer 200. Among them, the aforementioned metal contact layer 180 is connected to the aforementioned semiconductor component 100. The aforementioned first dielectric layer 170 covers the aforementioned semiconductor component 100 and the aforementioned metal contact layer 180. The aforementioned wire layer 185 is formed on the aforementioned first dielectric layer 170 and electrically connects the aforementioned semiconductor component 100 by connecting the aforementioned metal contact layer 180. And the aforementioned second dielectric layer 200 covers the aforementioned wire layer 185. The aforementioned semiconductor component 100 includes, for example but not limited to, a semiconductor substrate 110, a gate 120, a gate oxide layer 130, a source 140, and a drain 160. Among them, in this embodiment according to the present invention, the aforementioned first and second dielectric layers 170 and 200 are composed of the same dielectric material, such as but not limited to silicon oxide, and other common semiconductor dielectric materials can also be used as the first and second dielectric layers 170 and 200. In addition, in other embodiments according to the present invention, the aforementioned first and second dielectric layers 170 and 200 may also be composed of other different dielectric materials.

[0038] Secondly, as Figure 2B shown, a grinding process is performed on the aforementioned semiconductor sample 10, with the interface 250 between the aforementioned metal contact layer 180 and the aforementioned wire layer 185 as the grinding end point, and the aforementioned second dielectric layer 200 and the aforementioned wire layer 185 are gradually ground away to form a surface 250' of a ground semiconductor sample 10'. According to an embodiment of the present invention, the aforementioned grinding process step can use manual grinding or mechanical grinding.

[0039] Next, as Figure 2CAs shown, an adhesive layer 300 is formed on the surface 250' of the polished semiconductor sample 10'. The adhesion of the adhesive layer 300 to the first dielectric layer 170 is greater than the adhesion of the adhesive layer 300 to the metal contact layer 180. According to an embodiment of the present invention, the adhesive layer 300 may be a glue layer, a tape, or a wax layer, and the glue layer or the tape contains a non-volatile and non-liquid adhesive material, such as, but not limited to, silicone. Other adhesive materials having the property that the adhesion to the first dielectric layer 170 is greater than the adhesion of the adhesive layer 300 to the metal contact layer 180 are also applicable to the present invention. In addition, according to an embodiment of the present invention, the thickness of the adhesive layer 300 is, for example but not limited to, between 50 and 100 microns.

[0040] Then, as Figure 2D shown, after curing the adhesive layer 300, the adhesive layer 300 is peeled off, so that a part of the first dielectric layer 170 is peeled off together with the adhesive layer 300, and a part of the metal contact layer 180 is partially exposed, thereby completing the preparation of a semiconductor test chip 20 for failure analysis. According to an embodiment of the present invention, the curing step may be room temperature curing, heat curing, or light curing.

[0041] In summary, according to the method for preparing a semiconductor test chip for failure analysis disclosed by the present invention, by using an adhesive layer composed of a non-volatile, non-liquid adhesive material having a high adhesion property to dielectric materials and a low adhesion property to wire materials, a part of the dielectric material with a large area and high uniformity can be selectively removed, and the metal contact material can be completely retained, without generating a chemical reaction with the surface of the semiconductor sample or even damaging the structure to be analyzed. Moreover, by selecting different adhesive layer materials, the adhesion to the dielectric layer can be controlled, and thus the thickness of the removed dielectric layer can be controlled. Therefore, a semiconductor test chip for failure analysis suitable for size reduction can be prepared.

[0042] Although the present invention has been disclosed as above with embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the appended claims.

Claims

1. A method for preparing a semiconductor test chip for fault analysis, characterized in that, Comprising the following steps: Providing a semiconductor sample, the semiconductor sample including a semiconductor component, a metal contact layer, a first dielectric layer, a wire layer, and a second dielectric layer, wherein the metal contact layer is connected to the semiconductor component, the first dielectric layer covers the semiconductor component and the metal contact layer, the wire layer is formed on the first dielectric layer and electrically connects the semiconductor component by connecting the metal contact layer, and the second dielectric layer covers the wire layer; Performing a grinding process on the semiconductor sample, with the interface between the metal contact layer and the wire layer as the grinding end point, gradually grinding and removing the second dielectric layer and the wire layer; Forming an adhesive layer on the surface of the ground semiconductor sample, the adhesion of the adhesive layer to the first dielectric layer being greater than the adhesion of the adhesive layer to the metal contact layer; And After curing the adhesive layer, peeling off the adhesive layer, so that a part of the first dielectric layer is peeled off together with the adhesive layer, and a part of the metal contact layer is exposed.

2. The method for preparing a semiconductor test chip for fault analysis according to claim 1, characterized in that, Wherein the first and second dielectric layers are composed of the same or different dielectric materials.

3. The method for preparing a semiconductor test chip for fault analysis according to claim 1, characterized in that, Wherein the first and second dielectric layers are composed of the same dielectric material, and the dielectric material is mainly silicon oxide.

4. The method for preparing a semiconductor test chip for fault analysis according to claim 1, wherein, Wherein the grinding process step is manual grinding or mechanical grinding.

5. The method for preparing a semiconductor test chip for fault analysis according to claim 1, characterized in that, Wherein the adhesive layer is a glue layer, a tape, or a wax layer.

6. The method for preparing a semiconductor test chip for fault analysis according to claim 5, characterized in that, Wherein the glue layer or the tape contains a non-volatile and non-liquid adhesive material.

7. The method for preparing a semiconductor test chip for fault analysis according to claim 6, wherein, Wherein the non-volatile and non-liquid adhesive material is silica gel.

8. The method for preparing a semiconductor test chip for fault analysis according to claim 1, characterized in that, Wherein the thickness of the adhesive layer is between 50 and 100 microns.

9. The method for preparing a semiconductor test chip for failure analysis according to claim 1, characterized in that, Wherein the curing step of the adhesive layer is room temperature curing, heat curing, or light curing.

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