reducing the spacing between conductive features by implantation

Abstract

This application relates to reducing spacing between conductive features by implantation. A method includes forming a first dielectric layer over a source / drain region, and forming a source / drain contact plug over the source / drain region and electrically connecting the source / drain contact plug to the source / drain region. A top of the source / drain contact plug has a first lateral dimension. An implantation process is performed to implant dopants into the first dielectric layer. The implantation process causes the source / drain contact plug to have a second lateral dimension that is less than the first lateral dimension. The method also includes forming a second dielectric layer over an etch stop layer, and forming a gate contact plug adjacent to the source / drain contact plug.

Description

Technical Field

[0001] This disclosure generally relates to reducing the spacing between conductive features by injection. Background Technology

[0002] In integrated circuit manufacturing, contact plugs are used for electrical coupling to the source and drain regions and gate of transistors. Source / drain contact plugs are typically connected to source / drain silicide regions, and their formation process includes: forming contact openings to expose the source / drain regions, depositing a metal layer, depositing a barrier layer on top of the metal layer, performing an annealing process to react the metal layer with the source / drain regions, filling the remaining contact openings with metal (e.g., tungsten or cobalt), and performing a chemical mechanical polishing (CMP) process to remove excess metal. More than one layer of contact plugs may be formed. Summary of the Invention

[0003] According to a first aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising: forming a first dielectric layer over a source / drain region; forming a source / drain contact plug over the source / drain region and electrically connecting the source / drain contact plug to the source / drain region, wherein the top of the source / drain contact plug has a first lateral dimension; performing an implantation process to implant a dopant into the first dielectric layer, wherein the implantation process causes the source / drain contact plug to have a second lateral dimension smaller than the first lateral dimension; forming a second dielectric layer over an etch stop layer; and forming a gate contact plug adjacent to the source / drain contact plug.

[0004] According to a second aspect of this disclosure, a semiconductor structure is provided, comprising: an interlayer dielectric; a source / drain contact plug in the interlayer dielectric, wherein an upper portion of the interlayer dielectric includes a dopant having a first dopant concentration, and a lower portion of the interlayer dielectric includes a dopant having a second dopant concentration, wherein the second dopant concentration is less than the first dopant concentration; a gate stack located on one side of the source / drain contact plug; and a gate contact plug on the gate stack and electrically coupled to the gate stack.

[0005] According to a third aspect of this disclosure, a semiconductor structure is provided, comprising: a source / drain region; a silicide region above and in contact with the source / drain region; a first interlayer dielectric; a first contact plug above and in contact with the silicide region, wherein the first contact plug extends into the first interlayer dielectric; an etch stop layer above and in contact with the first contact plug; a second interlayer dielectric above and in contact with the etch stop layer; a second contact plug extending into the second interlayer dielectric; and a dopant having a first dopant concentration at the top of the first interlayer dielectric and a second dopant concentration at the bottom of the first interlayer dielectric, wherein the first dopant concentration is at least two orders of magnitude higher than the second dopant concentration. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1-7 , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11 , Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 13-15 These are perspective and cross-sectional views of intermediate stages in the formation of transistors and corresponding contact plugs according to some embodiments.

[0008] Figure 16 and Figure 17 These are curves showing the injected material in the contact plug and interlayer dielectric, respectively, according to some embodiments.

[0009] Figure 18 The leakage current based on the overlay shift is shown according to some embodiments.

[0010] Figure 19 The process flow for forming a fin field-effect transistor (FinFET) and corresponding contact plugs according to some embodiments is shown. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] In addition, this document may use spatially relevant terms (e.g., "below," "below," "lower than," "above," "upper") to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially relevant terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein may be interpreted accordingly.

[0013] According to some embodiments, a contact plug and a method of forming the same are provided. The contact plug has a larger lateral dimension at its top than at its bottom. An implantation process is performed to dope a dopant into the top of a dielectric layer in which the contact plug is located, thereby reducing the lateral dimension of the top of the contact plug. This increases the spacing between the contact plug and its adjacent conductive features and reduces the leakage current between the contact plug and its adjacent conductive features. It should be understood that, although a FinFET is used as an example, other types of transistors (e.g., planar transistors, gate-all-around (GAA) transistors, etc.) may also employ embodiments of this disclosure. Furthermore, although a source / drain contact plug is used as an example, other conductive features (including but not limited to conductive lines, conductive plugs, conductive vias, etc.) may also employ embodiments of this disclosure to increase the spacing between them and their adjacent conductive features. The embodiments discussed herein provide examples of how the subject matter of this disclosure can be carried out or used, and modifications that can be made will be readily understood by those skilled in the art while remaining within the contemplated scope of the different embodiments. Throughout the various views and illustrative embodiments, the same reference numerals are used to indicate the same elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figure 1-7 , Figure 8A , Figure 8B , Figure 9A, Figure 9B , Figure 10A , Figure 10B , Figure 11 , Figure 12A , Figure 12B , Figure 12C , Figure 12D and Figure 13-15 Perspective and cross-sectional views are shown of intermediate stages in the formation of a fin field-effect transistor (FinFET) and corresponding contact plugs according to some embodiments of the present disclosure. The corresponding processes are also schematically reflected in… Figure 19 The process flow shown is 200.

[0015] Figure 1 A perspective view of the initial structure formed on wafer 10 is shown. Wafer 10 includes a substrate 20. Substrate 20 may be a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed of other semiconductor materials. Substrate 20 may be doped with p-type or n-type impurities. Isolation regions 22, such as shallow trench isolation (STI) regions, may be formed extending from the top surface of substrate 20 into substrate 20. Corresponding processes are performed in... Figure 19 The process flow 200 shown is referred to as process 202. A portion of the substrate 20 between adjacent STI regions 22 is referred to as a semiconductor strip 24. The top surface of the semiconductor strip 24 and the top surface of the STI region 22 may be substantially flush with each other. According to some embodiments of this disclosure, the semiconductor strip 24 is a portion of the original substrate 20, and therefore the material of the semiconductor strip 24 is the same as the material of the substrate 20. According to an alternative embodiment of this disclosure, the semiconductor strip 24 is an alternative strip formed by etching a portion of the substrate 20 between the STI regions 22 to form a trench, and performing an epitaxial process to grow another semiconductor material in the trench. Therefore, the semiconductor strip 24 is formed of a semiconductor material different from that of the substrate 20. According to some embodiments, the semiconductor strip 24 is formed of silicon germanium, silicon carbon, or a group III-V compound semiconductor material.

[0016] STI region 22 may include a liner oxide (not shown), which may be a thermal oxide layer formed by thermal oxidation of a surface layer of substrate 20. The liner oxide may also be a deposited silicon oxide layer formed using methods such as atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), etc. STI region 22 may also include a dielectric material on top of the liner oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc.

[0017] refer to Figure 2The STI region 22 is recessed, causing the top of the semiconductor strip 24 to protrude above the top surface 22A of the rest of the STI region 22, forming a protruding fin 24'. The corresponding process is... Figure 19 The process flow 200 shown is designated as process 204. Etching can be performed using a dry etching process, for example, using NF3 and NH3 as etching gases. According to an alternative embodiment of this disclosure, a wet etching process is used to perform the recessing of the STI region 22. Etching chemicals may include, for example, a diluted HF solution.

[0018] In the above embodiments, the fins can be patterned using any suitable method. For example, one or more photolithography processes (including dual-patterning or multi-patterning processes) can be used to pattern the fins. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins.

[0019] refer to Figure 3 A dummy gate stack 30 is formed on the top surface and sidewalls of the (protruding) fins 24'. The corresponding process is shown as process 206 in the process flow 200 shown in 19. The dummy gate stack 30 may include a dummy gate dielectric 32 and a dummy gate 34 on top of the corresponding dummy gate dielectric 32. The dummy gate electrode 34 may be formed, for example, using polysilicon, and may also use other materials. Each dummy gate stack 30 may also include one (or more) hard mask layers 36 on top of the dummy gate electrode 34. The hard mask layer 36 may be formed from silicon nitride, silicon oxide, silicon oxynitride, etc., multiple layers thereof. The dummy gate stack 30 may span one or more protruding fins 24' and / or STI regions 22. The dummy gate stack 30 also has a length direction perpendicular to the length direction of the protruding fins 24'.

[0020] Next, gate spacers 38 are formed on the sidewalls of the dummy gate stack 30. The corresponding process is as follows: Figure 19 The process flow 200 shown is also referred to as process 206. According to some embodiments of this disclosure, the gate spacer 38 is formed of one or more dielectric materials such as silicon nitride, silicon carbonitride, etc., and may have a single-layer structure or a multilayer structure including multiple dielectric layers.

[0021] Then, an etching process is performed to etch the portion of the protruding fin 24' not covered by the dummy gate stack 30 and the gate spacer 38, resulting in Figure 4 The structure shown. The corresponding process is... Figure 19 The process flow 200 is shown as process 208. This recess can be anisotropic, thus protecting the portion of the fin 24' directly beneath the dummy gate stack 30 and gate spacer 38 from etching. According to some embodiments, the top surface of the recessed semiconductor strip 24 can be lower than the top surface 22A of the STI region 22. The space left by the etched protruding fin 24' and semiconductor strip 24 is referred to as a recess 40. The recess 40 is located on opposite sides of the dummy gate stack 30.

[0022] Next, as Figure 5 As shown, epitaxial regions (source / drain regions) 42 are formed by selectively growing (by epitaxy) semiconductor material in the groove 40. The corresponding process is described in... Figure 19 The process flow 200 shown is referred to as process 210. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type impurities can be doped in situ as epitaxy proceeds. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), etc., can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphide (SiP), silicon carbon phosphide (SiCP), etc., can be grown. According to an alternative embodiment of this disclosure, the epitaxial region 42 includes a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof. After the trench 40 is filled with the epitaxial region 42, further epitaxial growth of the epitaxial region 42 causes the epitaxial region 42 to extend horizontally and can form a facet. Further growth of the epitaxial region 42 can also cause adjacent epitaxial regions 42 to merge with each other. Voids (air gaps) 44 may be generated. According to some embodiments of this disclosure, the formation of the epitaxial region 42 can be completed while the top surface of the epitaxial region 42 is still wavy, or while the top surface of the merged epitaxial region 42 has become flat. This is achieved by... Figure 6 This is achieved by further growth on the extended region 42 shown.

[0023] Following this epitaxial process, epitaxial region 42 may be further implanted with p-type or n-type impurities to form source and drain regions, which are also denoted by reference numeral 42. According to an alternative embodiment of this disclosure, when epitaxial region 42 is in-situ doped with p-type or n-type impurities during epitaxy, the implantation process is skipped.

[0024] Figure 7 A perspective view of the structure after the formation of the contact etch stop layer (CESL) 46 and the interlayer dielectric (ILD) 48 is shown. The corresponding process is described in... Figure 19The process flow 200 shown is designated as process 212. CESL 46 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 48 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition process. ILD 48 can be formed from an oxygen-containing dielectric material, which can be a silicon oxide-based dielectric material, such as silicon oxide (e.g., formed using tetraethyl orthosilicate (TEOS) as a process gas), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. According to some embodiments, ILD 48 includes hydrogen with an atomic percentage greater than about 3%. The hydrogen percentage can also be in the range between about 1% and about 10%. According to some embodiments, the hydrogen atomic percentage can be increased by optimizing the precursor concentration, flow rate, and / or partial pressure. Planarization processes such as chemical mechanical polishing (CMP) or mechanical grinding can be performed to make the top surfaces of ILD 48, dummy gate stack 30 and gate spacer 38 flush with each other.

[0025] Next, the dummy gate stack 30, including the hard mask layer 36, the dummy gate electrode 34, and the dummy gate dielectric 32, is replaced with an alternative gate stack 56, including the metal gate electrode 54 and the gate dielectric 52, as shown in FIG8. The corresponding process is described in... Figure 19 The process flow 200 shown is illustrated as process 214. When forming the replacement gate stack 56, it is first removed in one or more etching processes. Figure 7 The hard mask layer 36, dummy gate electrode 34, and dummy gate dielectric 32 shown form a trench / opening between the gate spacers 38. The top surface and sidewalls of the protruding semiconductor fins 24' are exposed to the resulting trench.

[0026] Next, as Figure 8A and Figure 8B As shown, perspective and cross-sectional views are presented respectively, forming a replacement gate dielectric layer 52 that extends into the trench between the gate spacers 38. Figure 8B It shows Figure 8AReference sections 8B-8B are shown in the figure. According to some embodiments of this disclosure, each gate dielectric layer 52 includes an interface layer (IL) as its lower portion, which contacts the exposed surface of the corresponding protruding fin 24'. The IL may include an oxide layer, such as a silicon oxide layer, formed by a thermal oxidation, chemical oxidation, or deposition process of the protruding fin 24'. The gate dielectric layer 52 may also include a high-k dielectric layer formed on the IL. The high-k dielectric layer may include a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, etc. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9 and may be greater than about 7.0. The high-k dielectric layer is formed as a conformal layer and extends on the sidewalls of the protruding fin 24' and the sidewalls of the gate spacer 38. According to some embodiments of this disclosure, the high-k dielectric layer is formed using ALD or CVD.

[0027] Further reference Figure 8A and Figure 8B A gate electrode 54 is formed on a gate dielectric 52. The gate electrode 54 includes a stacked conductive layer. This stacked conductive layer is not shown separately, but the stacked conductive layers are distinguishable from each other. The deposition of the stacked conductive layer can be performed using one or more conformal deposition methods such as ALD or CVD. The stacked conductive layer may include a diffusion barrier layer (sometimes also called a glue layer) and one or more work function layers above the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (or may not) be doped with silicon. The work function layer determines the work function of the gate and includes at least one layer, or multiple layers formed of different materials. The material of the work function layer is selected depending on whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer may include a TaN layer and a titanium aluminum (TiAl) layer above the TaN layer. When the FinFET is a p-type FinFET, the work function layer may include a TaN layer and a TiN layer above the TaN layer. After depositing one or more work function layers, a binder layer, which may be another TiN layer, is formed. This binder layer may or may not completely fill the trenches left by the removed dummy gate stack.

[0028] The deposited gate dielectric layer and conductive layer are formed as conformal layers extending into the trench and including portions above ILD 48. Next, if the adhesive layer does not completely fill the trench, a metal material is deposited to fill the remaining trench. This metal material can be formed, for example, from tungsten or cobalt. Subsequently, a planarization process, such as CMP or mechanical polishing, is performed to remove portions of the gate dielectric layer, stacked conductive layer, and metal material above ILD 48. As a result, gate electrode 54 and gate dielectric 52 are formed. Gate electrode 54 and gate dielectric 52 are collectively referred to as replacement gate stack 56. The top surfaces of replacement gate stack 56, gate spacer 38, CESL 46, and ILD 48 can now be substantially coplanar.

[0029] Figure 8A and Figure 8B The formation of a (self-aligned) hard mask 58 according to some embodiments is also shown. The corresponding process is... Figure 19 The process flow 200 shown is referred to as process 216. Forming the hard mask 58 may include performing an etching process to recess the gate stack 59, forming grooves between the gate spacers 38, filling these grooves with a dielectric material, and then performing a planarization process such as CMP or mechanical polishing to remove excess dielectric material. The hard mask 58 may be formed of silicon nitride, silicon oxynitride, silicon carbonitride, etc.

[0030] Figure 9A and Figure 9B Perspective and cross-sectional views of the formation of the source / drain contact opening 60 are shown, respectively. The corresponding process is described in... Figure 19 The process flow 200 is shown as process 218. Forming the contact opening 60 includes etching the ILD 48 to expose the lower portion of the CESL 46, and then etching the exposed portion of the CESL 46 to expose the epitaxial region 42. According to some embodiments of this disclosure, such as... Figure 9A As shown, the gate spacer 38 is spaced from the nearest contact opening 60 by some remaining portions of the ILD 48 and CESL 46. According to other embodiments, the sidewalls of the gate spacer 38 or CESL 46 are exposed to the contact opening 60.

[0031] According to some embodiments, such as Figure 9B As shown, the top lateral dimension (width) Wtl of the contact opening 60 is greater than the corresponding bottom dimension Wb1. The difference (Wt1-Wb1) can be greater than about 3 nm, and can be in the range of about 1 nm to about 5 nm. The sidewall 60S of the ILD48 (the sidewall facing the contact opening 60) can be substantially straight.

[0032] refer to Figure 10A and Figure 10BThis forms a silicide region 66 and a source / drain contact plug 70. According to some embodiments, a metal layer 62 (e.g., a titanium or cobalt layer) is deposited, for example, using physical vapor deposition (PVD) or a similar method. Figure 10B Metal layer 62 is a conformal layer and extends to the top surface of source / drain region 42 and the sidewalls of ILD 48. Then, a metal nitride layer (e.g., titanium nitride layer) 64 is deposited as a capping layer. An annealing process is then performed to form source / drain silicide regions 66, as shown. Figure 10A and Figure 10B As shown. The corresponding process is in Figure 19 The process flow 200 shown is designated as process 220. Next, a metallic material 68, such as cobalt or tungsten, is filled into the remainder of the contact opening. Then, a planarization process, such as CMP or mechanical polishing, is performed to remove excess metal layer 62 and metallic material 68, leaving contact plug 70. The corresponding process is described in... Figure 19 The process flow 200 shown is also referred to as process 220. This forms FinFET 100. The contact plug 70 has sidewalls 70S, which can be straight and angled, for example, having an angle α1 of less than 90 degrees.

[0033] refer to Figure 11 Deposit and etch stop layer 72. The corresponding process is in... Figure 19 The process flow 200 shown is referred to as process 222. The etch stop layer 72 may be formed from silicon-containing materials such as SiN, SiCN, SiC, SiOCN, etc., or from other non-silicon dielectric materials. Formation methods may include PECVD, ALD, CVD, etc.

[0034] refer to Figure 12A , Figure 12B or Figure 12C Execute injection process 74. The corresponding process is in... Figure 19 The process flow 200 is shown as process 224. In implantation process 74, dopants are implanted to cause the volume of ILD 48, CESL 46, and gate spacer 38 to expand, thereby squeezing the contact plug 70 and reducing their lateral dimensions, as will be discussed in detail later. According to some embodiments, the dopants include Ge, Xe, Ar, Si, or combinations thereof.

[0035] Figure 12DA cross-sectional view of the contact plug 70 after implantation process 74 is shown. To illustrate the result of the implantation process, the top sidewall 70S of the contact plug 70 before implantation process 74 is shown in dashed lines, and the top sidewall 70S' of the contact plug 70 after implantation process 74 is shown in solid lines. According to some embodiments, the top of the contact plug 70 shrinks in the width direction due to the implantation process. This shrinkage of the top of the contact plug 70 may be due to the implantation of dopants into dielectric layers (e.g., ILD 48, CESL 46, and gate spacer 38), causing these dielectric layers to expand in volume and compress the contact plug 70, reducing the lateral dimension of the top of the contact plug 70 from Wt1 to Wt1'. According to some embodiments, the difference (Wt1-Wt1') is greater than about 1 nm and can be in the range between about 1 nm and about 5 nm. On the other hand, the amount of dopants reaching the lower part of ILD 48 (if present) is very small and does not change the bottom lateral dimension Wb1.

[0036] In addition, refer to Figure 10A The top length Ltl of the contact plug 70 can be greater than the top width Wtl. When compressed, the contact plug 70 is more difficult to shrink in the length direction than in the width direction. The larger the top length Lt1, the smaller the shrinkage value (Lt1-Lt1'), where Lt1' is the top length after the injection process 74. Therefore, the shrinkage value (Lt1-Lt1') is less than (Wt1-Wt1'). According to some embodiments, the shrinkage value (Lt1-Lt1') is less than about 0.5 nm, less than about 0.2 nm, or less than about 0.1 nm.

[0037] Return to reference Figure 12D Due to the implantation process, the contact plug 70 can be made taller because the overall volume of the contact plug 70 remains essentially unchanged. The increase in height ΔH can be greater than about 3 nm, and can be in the range of about 1 nm to about 10 nm. The top surface 70T of the contact plug 70 can be circular, and the circular portion can protrude above the top surface of ILD 48. The dashed line 70T shows a possible outline of the circular top surface of the contact plug 70.

[0038] Furthermore, due to the injection process 74, the position of the top sidewall of the contact plug 70 changes, wherein the top sidewall portion before the injection process is shown as 70S, and the top sidewall portion after the injection process is shown as 70S'. According to some embodiments, the straight sidewall 70S (before the injection process 74) may have a tilt angle α1 of less than 90 degrees. The tilt angle α1 may also be less than about 70 degrees, and may be in the range between about 60 degrees and about 85 degrees. The straight sidewall portion 70S' of the top of the contact plug 70 (after the injection process 74) may have a tilt angle α2 greater than the tilt angle α1. The tilt angle α2 may be greater than about 85 degrees, and may be in the range between about 70 degrees and about 100 degrees. The difference (α2-α1) may be in the range between about 1 degree and about 15 degrees.

[0039] According to some embodiments, the top of the contact plug (which is laterally contracted by the injection process) has a height H1, which can be in the range of about 3 nm to about 10 nm. Furthermore, the ratio H1 / H2 (where H2 is the total height of the contact plug 70) can be greater than about 0.15, and can be in the range of about 0.15 to about 0.5.

[0040] To achieve lateral contraction at the top of the contact plug 70, the implanted energy is selected to be within a range that is neither too high nor too low. If the implanted energy is too high, the dopant may penetrate the etch stop layer 72, ILD 48, and CESL 46 and reach the source / drain region 42. This could adversely alter the characteristics of the resulting FinFET in an uncontrollable manner. If the implanted energy is too low, the dopant cannot extend deep enough into ILD 48, thus limiting the height H1 of the contraction portion. Figure 12D The dose is too low. According to some embodiments, the implantation process 74 can be performed using energy in the range of about 2 keV to about 50 keV. The dopant dose is also selected such that it is not too high, which would excessively alter the characteristics of the etch stop layer 72, the implanted ILD 48, and CESL46, nor too low, which would sufficiently reduce the width of the top of the contact plug. According to some embodiments, the dose is about 1E14 / cm². 2 and 1E16 / cm 2 Within the range between. Energy and dose can be selected in combination to reduce the size of the top 1 / 3 portion of each contact plug 70 by 1 nm or more.

[0041] Furthermore, to increase the magnitude of shrinkage, implanted dielectric layers such as ILD 48 can have an increased percentage of hydrogen atoms. Experimental results show that the shrinkage of contact plug 70 is more significant when there is more hydrogen in the implanted dielectric material adjacent to contact plug 70. This is likely due to the effect of breaking bonds in the dielectric material. For example, Si-O bonds in the dielectric material may break due to the implantation process. The increase in hydrogen content (as described previously in ILD 48) makes more hydrogen atoms available and able to connect to the broken bonds, thus increasing the volume of the implanted dielectric material compared to the volume before the implantation process.

[0042] The implantation process 74 can be performed vertically or at an angle of less than about 60 degrees. During the implantation process 74, wafer 10 can be cooled or heated, or it can be at room temperature. For example, the temperature of wafer 10 during implantation can be in the range of about -100°C to about 500°C.

[0043] refer to Figure 12A , Figure 12B and Figure 12C As a result of implantation process 74, doped regions 76A are formed in the corresponding overlying portions of the contact plug 70 and etch stop layer 72, and doped regions 76B are formed in the corresponding overlying portions of the dielectric layer (e.g., ILD 48, gate spacer 38, hard mask 58) and etch stop layer 72. Since the contact plug 70 (particularly the metal region 68) is formed of metal and is therefore dense, dopant is more likely to accumulate at the top surface of the metal region 68. Doped regions 76A therefore extend only into the shallow surface portion of the contact plug 70, and the dopant concentration is significantly lower in the lower portion than in the corresponding upper portion. The doped regions 68A and 68B shown may represent regions with relatively high concentrations, for example, whose concentration is less than two orders of magnitude (or possibly three orders of magnitude) below the corresponding peak concentration values. Doped regions with lower concentrations are not shown as portions of doped regions 68A and 68B. Because the metal region 68 is relatively dense and the dielectric layer is relatively porous, the depth D1 of the doped region 76A in the dielectric layer is less than the depth D2 of the doped region 76B. According to some embodiments, the depth D1 is less than the height H1. Furthermore, the depth D2 is less than the total thickness T1 of CESL 46 and ILD 48, so that the bottom of the contact plug 70 does not laterally contract. Otherwise, the resistance of the contact plug 70 would be unfavorably increased. For example, the ratio D2 / T1 can be in the range of about 0.3 to about 1. Furthermore, the ratio D1 / D2 can be in the range of about 0.05 to about 0.5. According to some embodiments, the depth D1 is in the range of about 1 nm to about 5 nm, and the depth D2 is in the range of about 5 nm to about 20 nm.

[0044] According to some embodiments, such as Figure 12A As shown, implantation process 74 is performed on wafer 10 without any implantation mask and is performed by etching stop layer 72. Because there is no implantation mask, the entire wafer 10 is implanted, and all surface features of wafer 10 receive dopant. According to an alternative embodiment, such as... Figure 12B As shown, implantation is performed without forming the etch stop layer 72. It is understood that implantation with or without the etch stop layer 72 can have different effects. For example, the implanted dopant may have a distribution (sometimes Gaussian) where the peak concentration of the dopant is located at the surface of the implanted feature or at a certain depth below the top surface of the implanted feature, depending on the dopant type, implantation energy, etc. Implantation with or without the etch stop layer provides a means to adjust the peak concentration position / level to obtain the maximum result. For example, without the etch stop layer, the peak concentration can be at a deeper level, while with the etch stop layer, the peak concentration can be at a shallower level.

[0045] According to other alternative embodiments, such as Figure 12C As shown, the implantation is performed with an implantation mask 75 formed to shield the area that will not be implanted. For example, the implantation mask 75 can be formed in a region far from the contact plug 70 because the expansion of the distant region will not cause compression of the contact plug 70. Implantation with an implantation mask can confine the implantation area to the desired region without affecting other areas. For example, when implanting Si or Ge, and when the dopant concentration is high, the leakage current between adjacent conductive features (e.g., adjacent contact plugs 70) may increase due to the high concentration of Si or Ge in the dielectric layer. Since Si / Ge will not be doped into the continuous region connecting two adjacent conductive features, the implantation mask can prevent this increase in leakage current. On the other hand, in some cases, such as when there is no leakage problem (when implanting Xe and / or Ar, or when the dopant concentration is low), the cost of the implantation mask can be saved by not forming it. It should be understood that in Figure 12C In the diagram, the etch stop layer 72 is shown as a dashed line to indicate whether or not the etch stop layer 72 may be formed during the implantation process 74.

[0046] Because the metal region 68 is relatively dense, the dopant accumulates around the top surface of the metal region 68 (both above and below the top surface). Furthermore, the dopant may have portions located directly above the metal region 68, and portions extending into at least the lower portion of the etch stop layer 72. This causes the doped region 76A to extend into at least the lower portion of the etch stop layer 72, and possibly into the entire etch stop layer 72. Figure 16 The vertical distribution curves of dopants in the metal region 68 and etch stop layer 72 according to some embodiments are shown. These distribution curves were measured on a sample wafer using secondary ion mass spectrometry (SIMS). The X-axis shows the distribution from the top surface of the etch stop layer 72 and along... Figure 12A The depth is measured in the direction marked by arrow 77A. The Y-axis shows the normalized dopant concentration. A peak dopant concentration is observed at the interface between the etch stop layer 72 and the metal region 68, indicating dopant accumulation at this interface. Furthermore, a high dopant concentration is present in the etch stop layer 72, likely due to backscattering from the metal region 68. Therefore, as... Figure 12A As shown, the doped region 76A extends into the etch stop layer 72. According to some embodiments, the dopant concentration in the metal region 68 and the etch stop layer 72 is approximately 1E17 / cm². 3 And approximately 1E22 / cm 3 The peak dopant concentration PC1 in the metal region 68 and the etch stop layer 72 can be within the range of approximately 1E20 / cm². 3 And approximately 1E22 / cm 3 Within the range between.

[0047] Figure 17 The distribution curves of dopants in ILD 48 and etch stop layer 72 according to some embodiments are shown. These distribution curves were also measured from the same wafer using SIMS. The X-axis shows the distribution from the top surface of etch stop layer 72 and along... Figure 12A The direction marked by arrow 77B indicates the depth measured. The Y-axis shows the normalized dopant concentration. Due to the lower density value of the dielectric layer, the peak concentration of doped region 76B is inside ILD 48, not at the interface between etch stop layer 72 and ILD 48. The dopant in ILD 48 extends deeper than in doped region 76A, but has a lower density than... Figure 16 This results in a less steep change. According to some embodiments, the dopant concentration in the etch stop layer 72 and ILD 48 is approximately 1E17 / cm³. 3 And approximately 1E22 / cm 3 Within the range between [specific values]. The peak dopant concentration PC2 in etch stop layer 72 and ILD 48 can be approximately 1E17 / cm². 3 And approximately 1E22 / cm 3 Within the range between [a certain range]. The peak dopant concentration PC2 can be lower than the peak dopant concentration PC1 ([a certain range]). Figure 16 ).

[0048] Refer again Figure 12A , Figure 12B or Figure 12CAccording to some embodiments, the dopant concentration (of the implanted dopant) at the bottom of metal region 68 is at least three orders of magnitude (1 / 1000th) lower than the peak dopant concentration at the interface between metal region 68 and etch stop layer 72. According to some embodiments, the bottom of metal region 68 may be free of implanted dopant. According to some embodiments, the dopant concentration (of the implanted dopant) at the bottom of metal ILD 48 and the lower part of CESL 46 is at least three orders of magnitude (1 / 1000th) or four orders of magnitude lower than the peak dopant concentration in ILD 48. According to some embodiments, the bottom of ILD 48 may be free of implanted dopant.

[0049] refer to Figure 13 ILD 78 is formed on top of etch stop layer 72. The corresponding process is as follows: Figure 19 The process flow 200 shown is designated as process 226. The materials and formation methods of ILD 78 can be selected from the same candidate materials and formation methods used to form ILD 48. For example, ILD 78 can include silicon oxide, PSG, BSG, BPSG, etc., which include silicon. According to some embodiments, ILD 78 is formed using PECVD, FCVD, spin coating, etc.

[0050] Figure 14 The etching of ILD 78 to form source / drain contact openings 80 is shown. The corresponding process is described in... Figure 19 The process flow 200 shown is designated as process 228. According to some embodiments, the ILD 78 is etched using process gases comprising: C2F6; CF4; SO2; a mixture of HBr, Cl2, and O2; or a mixture of HBr, Cl2, O2, and CF2, etc. This etching process is anisotropic.

[0051] Next, as Figure 14 As shown, the etch stop layer 72 is etched in an anisotropic process. The corresponding process is... Figure 19 The process flow 200 shown is also referred to as process 228. The source / drain contact plug 70 is thus exposed to the gate opening 80. The etch stop layer 72 can be etched using a fluorine-containing gas such as: a mixture of CF4, O2, and N2; a mixture of NF3 and O2; SF6; or a mixture of SF6 and O2. The etching can be anisotropic or isotropic.

[0052] Figure 14 Further illustration shows the formation of a gate contact opening 84 according to some embodiments, which is formed by etching ILD 78, etch stop layer 72, and hard mask 58. The corresponding process is described in... Figure 19The process flow 200 shown is referred to as process 230. In the following discussion, as... Figure 16 and Figure 17 In the example embodiment shown, a common metal-filling process is shared to form the gate contact plug 88 and the source / drain contact plug 86. It should be understood that the gate contact plug 88 may also be formed before or after the source / drain contact plug 86.

[0053] Figure 15 The diagram shows source / drain contact plugs 86 and gate contact plugs 88 formed in openings 80 and 84, respectively. The corresponding process is described in... Figure 19 The process flow 200 shown is illustrated as process 232. According to some embodiments, this forming process includes: depositing one or more metal materials, which may be deposited using PVD, CVD, electroplating, combinations thereof, etc., followed by a planarization process to remove excess portions of the metal material(s). The deposited metal material(s) may include tungsten, cobalt, molybdenum, copper, or alloys thereof. The metal material may be the same as or different from the material of metal region 68. For example, when metal region 68 is formed of or includes cobalt, the metal material may be formed of or include tungsten or cobalt. According to some embodiments, the source / drain contact plug 86 and the gate contact plug 88 are glue-less, wherein each of the source / drain contact plug 86 and the gate contact plug 88 is integrally formed of a homogeneous material without a glue layer. According to an alternative embodiment, each of the source / drain contact plug 86 and the gate contact plug 88 includes a glue layer, which may be formed of titanium, titanium nitride, tantalum, tantalum nitride, etc. The deposited metallic material (e.g., tungsten, cobalt, etc.) is thus deposited on top of the adhesive layer. Therefore, dashed lines are illustrated to show the possible boundary between the adhesive layer and the overlying metallic material.

[0054] like Figure 15As shown, the spacing S1 between the contact plug 70 and its adjacent conductive feature (e.g., gate contact plug 88) may be small. The leakage current between the contact plug 70 and its adjacent conductive feature is related to the spacing S1, and the larger the spacing S1, the smaller the leakage current. To reduce the leakage current, the spacing between the contact plug 70 and its adjacent conductive feature can be increased, or the spacing can be not increased, and the contact plug 70 can be formed narrower. Both methods have disadvantages. The adverse effect of increasing the spacing is that it increases the size of the FinFET 100, while making the contact plug 70 narrower results in higher resistance. According to embodiments of this disclosure, a contact plug such as the contact plug 70 may have an upper portion that is wider than the corresponding lower portion, and this upper portion is the main source of leakage. Therefore, by shrinking the upper portion, making the upper portion (rather than the lower portion) smaller, the main part of the leakage current is reduced. Since the wider upper portion of the contact plug 70 is not the main contributor to the resistance, this does not significantly increase the resistance of the contact plug 70.

[0055] According to some embodiments, an additional implantation process 90 is performed to laterally shrink the tops 86T and 88T of the source / drain contact plug 86 and the gate contact plug 88, respectively. The corresponding process is described in... Figure 19 The process flow 200 shown is designated as process 234. Injection process 90 can be combined with injection process 74 ( Figure 12A , Figure 12B or Figure 12C The details of implantation process 90 are essentially the same, therefore they will not be repeated. According to other embodiments, additional implantation process 90 is not performed. Whether or not additional implantation process 90 is performed may be related to the primary materials of contact plugs 86 and 88. For example, cobalt shrinks more than tungsten during implantation process 90. Therefore, when cobalt is used to form the source / drain contact plugs 86 and gate contact plugs 88, implantation process 90 may be performed, while if tungsten is used to form the source / drain contact plugs 86 and gate contact plugs 88, the shrinkage is less significant compared to cobalt, and implantation process 90 may or may not be performed, depending on performance requirements.

[0056] Figure 18 The leakage current is shown based on the overlap offset. Line 102 shows the results obtained from a sample formed using an embodiment of the present disclosure. Line 104 shows the results obtained from a sample whose contact plug formation does not include the injection for shrinking the contact plug. The overlap position 106 indicates that the contact plug 70 is located in the middle of two adjacent gate contact plugs, such that the leakage current increases regardless of whether the contact plug 70 is formed offset to the left or right. Assumption 108 is the upper limit of the leakage current allowed by the specification. Window (process margin) M1 is the process window of the conventional formation method, and window W2 is the process window of the embodiment of the present disclosure. Figure 18An embodiment of the present disclosure is shown where the process window is increased from W1 to W2.

[0057] The embodiments disclosed have several advantageous features. By injecting into the top of the ILD in which the contact plug is formed, the spacing between the contact plug and its adjacent conductive features is increased, thereby reducing leakage current. On the other hand, the size of the transistor is not increased, and the resistance value of the contact plug is not significantly increased.

[0058] According to some embodiments of this disclosure, a method includes: forming a first dielectric layer over a source / drain region; forming a source / drain contact plug over the source / drain region and electrically connecting the source / drain contact plug to the source / drain region, wherein the top of the source / drain contact plug has a first lateral dimension; performing an implantation process to implant a dopant into the first dielectric layer, wherein the implantation process causes the source / drain contact plug to have a second lateral dimension smaller than the first lateral dimension; forming a second dielectric layer over an etch stop layer; and forming a gate contact plug adjacent to the source / drain contact plug. According to one embodiment, in the implantation process, an element selected from the group consisting of Ge, Xe, Ar, Si, and combinations thereof is implanted. According to one embodiment, in the implantation process, germanium is implanted. According to one embodiment, in the implantation process, an additional top of the first dielectric layer is implanted, and an additional bottom of the first dielectric layer is not implanted. According to one embodiment, the difference between the second lateral dimension and the first lateral dimension is greater than about 1 nm. According to one embodiment, the implantation process results in an increased height for the source / drain contact plug. According to one embodiment, the implantation process is performed before the etch stop layer is formed and while the first dielectric layer is exposed. According to one embodiment, the etch stop layer is implanted during the implantation process. According to one embodiment, the implantation process is performed without using a patterned implantation mask.

[0059] According to some embodiments of this disclosure, a structure includes: an interlayer dielectric; a source / drain contact plug in the interlayer dielectric, wherein an upper portion of the interlayer dielectric includes a dopant having a first dopant concentration, and a lower portion of the interlayer dielectric includes the dopant having a second dopant concentration, wherein the second dopant concentration is less than the first dopant concentration; a gate stack located on one side of the source / drain contact plug; and a gate contact plug on the gate stack and electrically coupled to the gate stack. According to one embodiment, the dopant includes germanium. According to one embodiment, the lower portion of the interlayer dielectric is substantially free of dopant. According to one embodiment, the structure further includes: an etch stop layer on the source / drain contact plug and the interlayer dielectric, wherein the etch stop layer includes a dopant. According to one embodiment, the source / drain contact plug includes a sidewall comprising: an additional lower portion, wherein the additional lower portion is vertical; and an additional upper portion, higher than the additional lower portion, wherein the additional upper portion has a first height greater than about 15% of a second height of the source / drain contact plug, and the additional upper portion is generally more vertical than the additional lower portion.

[0060] According to some embodiments of this disclosure, a structure includes: a source / drain region; a silicide region above and in contact with the source / drain region; a first interlayer dielectric; a first contact plug above and in contact with the silicide region, wherein the first contact plug extends into the first interlayer dielectric; an etch stop layer above and in contact with the first contact plug; a second interlayer dielectric above and in contact with the etch stop layer; a second contact plug extending into the second interlayer dielectric; and a dopant having a first dopant concentration at the top of the first interlayer dielectric and a second dopant concentration at the bottom of the first interlayer dielectric, wherein the first dopant concentration is at least two orders of magnitude higher than the second dopant concentration. According to one embodiment, the first dopant concentration is at least three orders of magnitude higher than the second dopant concentration. According to one embodiment, the first dopant concentration is greater than about 1E20 / cm³. 3 According to one embodiment, the bottom of the first interlayer dielectric is free of dopant. According to one embodiment, the dopant is selected from the group consisting of Ge, Xe, Ar, Si, and combinations thereof. According to one embodiment, the dopant includes germanium.

[0061] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0062] Example 1. A method for forming a semiconductor structure, comprising: forming a first dielectric layer over a source / drain region; forming a source / drain contact plug over the source / drain region and electrically connecting the source / drain contact plug to the source / drain region, wherein the top of the source / drain contact plug has a first lateral dimension; performing an implantation process to implant a dopant into the first dielectric layer, wherein the implantation process causes the source / drain contact plug to have a second lateral dimension smaller than the first lateral dimension; forming a second dielectric layer over an etch stop layer; and forming a gate contact plug adjacent to the source / drain contact plug.

[0063] Example 2. The method according to Example 1, wherein, in the implantation process, an element selected from the group consisting of: Ge, Xe, Ar, Si, and combinations thereof is implanted.

[0064] Example 3. The method according to Example 2, wherein germanium is implanted in the implantation process.

[0065] Example 4. The method according to Example 1, wherein, in the implantation process, an additional top of the first dielectric layer is implanted, and an additional bottom of the first dielectric layer is not implanted.

[0066] Example 5. The method according to Example 1, wherein the difference between the second lateral dimension and the first lateral dimension is greater than about 1 nm.

[0067] Example 6. The method according to Example 1, wherein the injection process causes the source / drain contact plug to have an increased height.

[0068] Example 7. The method according to Example 1 further includes: forming an etch stop layer on the source / drain contact plug after the implantation process.

[0069] Example 8. The method according to Example 1 further includes: forming an etch stop layer over the source / drain contact plug, wherein the implantation process is performed when a corresponding dopant passes through the etch stop layer to reach the first dielectric layer.

[0070] Example 9. The method according to Example 1, wherein the injection process is performed without using a patterned injection mask.

[0071] Example 10. A semiconductor structure comprising: an interlayer dielectric; a source / drain contact plug in the interlayer dielectric, wherein an upper portion of the interlayer dielectric includes a dopant having a first dopant concentration and a lower portion of the interlayer dielectric includes a dopant having a second dopant concentration, wherein the second dopant concentration is less than the first dopant concentration; a gate stack located on one side of the source / drain contact plug; and a gate contact plug on the gate stack and electrically coupled to the gate stack.

[0072] Example 11. The semiconductor structure according to Example 10, wherein the dopant comprises germanium.

[0073] Example 12. The semiconductor structure according to Example 10, wherein the lower portion of the interlayer dielectric is substantially free of the dopant.

[0074] Example 13. The semiconductor structure according to Example 10 further includes: an etch stop layer over the source / drain contact plug and the interlayer dielectric, wherein the etch stop layer includes the dopant.

[0075] Example 14. The semiconductor structure according to Example 10, wherein the source / drain contact plug includes a sidewall comprising: an additional lower portion, wherein the additional lower portion is vertical; and an additional upper portion, higher than the additional lower portion, wherein the additional upper portion has a first height greater than about 15% of a second height of the source / drain contact plug, and the additional upper portion is generally more vertical than the additional lower portion.

[0076] Example 15. A semiconductor structure comprising: a source / drain region; a silicide region above and in contact with the source / drain region; a first interlayer dielectric; a first contact plug above and in contact with the silicide region, wherein the first contact plug extends into the first interlayer dielectric; an etch stop layer above and in contact with the first contact plug; a second interlayer dielectric above and in contact with the etch stop layer; a second contact plug extending into the second interlayer dielectric; and a dopant having a first dopant concentration at the top of the first interlayer dielectric and a second dopant concentration at the bottom of the first interlayer dielectric, wherein the first dopant concentration is at least two orders of magnitude higher than the second dopant concentration.

[0077] Example 16. The semiconductor structure according to Example 15, wherein the concentration of the first dopant is at least three orders of magnitude higher than the concentration of the second dopant.

[0078] Example 17. The semiconductor structure according to Example 15, wherein the concentration of the first dopant is greater than about 1E20 / cm³. 3 .

[0079] Example 18. The semiconductor structure according to Example 15, wherein the bottom of the first interlayer dielectric does not contain the dopant.

[0080] Example 19. The semiconductor structure according to Example 15, wherein the dopant is selected from the group consisting of Ge, Xe, Ar, Si, and combinations thereof.

[0081] Example 20. The semiconductor structure according to Example 19, wherein the dopant comprises germanium.

Claims

1. A method for forming a semiconductor structure, comprising: forming a first dielectric layer over a source / drain region; forming a source / drain contact plug over the source / drain region and electrically connecting the source / drain contact plug to the source / drain region, wherein a top of the source / drain contact plug has a first lateral dimension; performing an implantation process to implant a dopant into the first dielectric layer, wherein the implantation process causes the top of the source / drain contact plug to have a second lateral dimension that is less than the first lateral dimension; forming a second dielectric layer over the first dielectric layer; and forming a gate contact plug adjacent to the source / drain contact plug.

2. The method of claim 1, wherein, In the implantation process, an element is implanted selected from the group consisting of: Ge, Xe, Ar, Si, and combinations thereof.

3. The method of claim 2, wherein, In the implantation process, germanium is implanted.

4. The method of claim 1, wherein, In the implantation process, an additional top of the first dielectric layer is implanted and an additional bottom of the first dielectric layer is not implanted.

5. The method of claim 1, wherein, The second lateral dimension is less than the first lateral dimension by more than 1 nm.

6. The method of claim 1, wherein, The implantation process causes the source / drain contact plug to have an increased height.

7. The method of claim 1, further comprising: forming an etch stop layer over the source / drain contact plug after the implantation process.

8. The method of claim 1, further comprising: forming an etch stop layer over the source / drain contact plug, wherein the implantation process is performed with the respective dopant reaching the first dielectric layer through the etch stop layer.

9. The method of claim 1, wherein, The implantation process is performed without employing a patterned implantation mask.

10. A semiconductor structure, comprising: an interlayer dielectric; a source / drain contact plug in the interlayer dielectric, wherein an upper portion of the interlayer dielectric includes a dopant having a first dopant concentration and a lower portion of the interlayer dielectric has the dopant at a second dopant concentration, wherein the second dopant concentration is less than the first dopant concentration; a gate stack to a side of the source / drain contact plug; and a gate contact plug over and electrically coupled to the gate stack, wherein the source / drain contact plug includes a sidewall that includes: an additional lower portion, wherein the additional lower portion is straight; and an additional upper portion above the additional lower portion, wherein the additional upper portion has a first height that is greater than 15% of a second height of the source / drain contact plug and the additional upper portion is more vertical in its entirety than the additional lower portion.

11. The semiconductor structure of claim 10, wherein, The dopant includes germanium.

12. The semiconductor structure of claim 10, wherein, The lower portion of the interlayer dielectric is substantially free of the dopant.

13. The semiconductor structure of claim 10, further comprising: an etch stop layer over the source / drain contact plug and the interlayer dielectric, wherein the etch stop layer includes the dopant.

14. A semiconductor structure, comprising: a source / drain region; a silicide region over and in contact with the source / drain region; a first interlayer dielectric; a first contact plug over and in contact with the silicide region, wherein the first contact plug extends into the first interlayer dielectric; an etch stop layer over and in contact with the first contact plug; a second interlayer dielectric over and in contact with the etch stop layer; a second contact plug extending into the second interlayer dielectric; and a dopant having a first dopant concentration at a top of the first interlayer dielectric and a second dopant concentration at a bottom of the first interlayer dielectric, wherein the first dopant concentration is at least two orders of magnitude higher than the second dopant concentration, wherein the first contact plug includes a sidewall that is more vertical at an upper portion of the sidewall than at a lower portion of the sidewall.

15. The semiconductor structure of claim 14, wherein, the first dopant concentration is at least three orders of magnitude higher than the second dopant concentration.

16. The semiconductor structure of claim 14, wherein, The first dopant concentration is greater than 1E20 / cm 3 .

17. The semiconductor structure of claim 14, wherein, the bottom of the first interlayer dielectric is free of the dopant.

18. The semiconductor structure of claim 14, wherein, the dopant is selected from the group consisting of Ge, Xe, Ar, Si, and combinations thereof.

19. The semiconductor structure of claim 18, wherein, the dopant includes germanium. a first contact plug over and in contact with the silicide region, wherein the first contact plug extends into the first interlayer dielectric; an etch stop layer over and in contact with the first contact plug; a second interlayer dielectric over and in contact with the etch stop layer; a second contact plug extending into the second interlayer dielectric; and a dopant having a first dopant concentration at a top of the first interlayer dielectric and a second dopant concentration at a bottom of the first interlayer dielectric, wherein the first dopant concentration is at least two orders of magnitude higher than the second dopant concentration, wherein the first contact plug includes a sidewall that is more vertical at an upper portion of the sidewall than at a lower portion of the sidewall. the first dopant concentration is at least three orders of magnitude higher than the second dopant concentration. the bottom of the first interlayer dielectric is free of the dopant. the dopant is selected from the group consisting of Ge, Xe, Ar, Si, and combinations thereof. the dopant includes germanium.

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