Passive filter and preparation method thereof

Abstract

The present disclosure provides a passive filter and a method for manufacturing the same, belonging to the field of radio frequency device technology. The present disclosure provides a passive filter comprising: a dielectric substrate, at least one capacitor, and at least one inductor; the capacitor comprising a first plate, a first interlayer dielectric layer, and a second plate, arranged in sequence, facing away from the dielectric substrate; wherein the dielectric constant of the first interlayer dielectric material changes with changes in the electrostatic field between the first plate and the second plate.

Description

Technical Field

[0001] The present disclosure belongs to the technical field of radio frequency devices, and particularly relates to a passive filter and a preparation method thereof. Background Art

[0002] The consumer electronics industry is rapidly evolving, with mobile communication terminals, particularly 5G phones, experiencing rapid growth. Mobile phones are required to process an increasing number of signal frequency bands, and the number of RF chips required is also increasing. Consumers are increasingly favoring mobile phone designs that are miniaturized, lightweight, and have longer battery life. Traditional mobile phones often feature a large number of discrete components on RF PCBs, such as resistors, capacitors, inductors, and filters. These components suffer from large size, high power consumption, numerous solder joints, and significant parasitic parameter variation, making them difficult to meet future demands. The interconnection and matching between RF chips require integrated passive components that are compact, high-performance, and highly consistent. Currently, the integrated passive components on the market are primarily based on Si (silicon) and GaAs (gallium arsenide) substrates. Si-based integrated passive components offer the advantage of low cost, but inherent trace impurities (poor insulation) in Si lead to high microwave loss and mediocre performance. GaAs-based integrated passive components offer excellent performance but are expensive. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a passive filter and a preparation method thereof.

[0004] In a first aspect, the present disclosure provides a passive filter comprising: a dielectric substrate, at least one capacitor, and at least one inductor; the capacitor comprising a first plate, a first interlayer dielectric layer, and a second plate, arranged in sequence away from the dielectric substrate; wherein the dielectric constant of the first interlayer dielectric material changes with changes in the electrostatic field between the first plate and the second plate.

[0005] Wherein, the material of the first interlayer dielectric layer at least includes ferroelectric material.

[0006] Wherein, the material of the first interlayer dielectric layer at least includes: Mn2O3, PbZr X Ti (1-X) O3, BiFeO3, perovskite oxide, (Pb 0.83 La 0.17 )One of TiO3.

[0007] Wherein, the material of the first interlayer dielectric layer at least includes paraelectric material.

[0008] The material of the first interlayer dielectric layer includes at least one of SrTiO3, TiO2, and CaTiO3.

[0009] The dielectric substrate further includes a first connecting via along its thickness direction and a first surface and a second surface arranged opposite to each other along the thickness direction; the inductor includes a first substructure arranged on the first surface of the dielectric substrate, a second substructure arranged on the second surface of the dielectric substrate, and a first connecting electrode arranged in the first connecting via, wherein the first connecting electrode connects the first substructure and the second substructure to form a coil structure of the inductor; and the second substructure is electrically connected to the first plate of the capacitor.

[0010] Among them, it also includes a second interlayer dielectric layer arranged away from the first interlayer dielectric layer; the second substructure includes a first conductive film layer and a second conductive film layer arranged in sequence away from one side of the dielectric substrate; the first conductive film layer is electrically connected to the first electrode plate of the capacitor; the second conductive film layer is electrically connected to the first conductive film layer through a second connecting via and a third connecting via penetrating the first and second interlayer dielectric layers; the passive filter also includes a second connecting electrode and a third connecting electrode arranged on the same layer as the second conductive film layer; the second connecting electrode is electrically connected to the second electrode plate of the capacitor through a fourth connecting via penetrating the second interlayer dielectric layer; the third connecting electrode is electrically connected to the first electrode plate of the capacitor through a fifth connecting via penetrating the second interlayer dielectric layer and the third interlayer dielectric layer; the passive filter also includes a third interlayer dielectric layer arranged away from the second conductive film layer, and a fourth interlayer dielectric layer arranged away from the first substructure.

[0011] Among them, it also includes: a first connecting pad, a second connecting pad and a third connecting pad arranged on the side away from the second conductive film layer; the first connecting pad is electrically connected to the second conductive film layer through a sixth connecting via penetrating the third interlayer dielectric layer; the second connecting pad is electrically connected to the second connecting electrode through a seventh connecting via penetrating the third interlayer dielectric layer; the third connecting pad is electrically connected to the third connecting electrode through an eighth connecting via penetrating the third interlayer dielectric layer.

[0012] Wherein, the material of the dielectric substrate at least includes a glass base.

[0013] In a second aspect, the present disclosure further provides a method for preparing a passive filter, characterized by providing a dielectric substrate; forming at least an inductor and a capacitor on the dielectric substrate; wherein the step of forming the capacitor includes: sequentially forming a first plate, a first interlayer dielectric layer, and a second plate on a side facing away from the dielectric substrate; and the dielectric constant of the first interlayer dielectric layer changes as the electrostatic field between the first plate and the second plate of the capacitor changes.

[0014] The dielectric substrate further includes a first connecting via along its thickness direction, and a first surface and a second surface disposed opposite to each other along the thickness direction; the step of forming the inductor includes: forming a first connecting electrode in the first connecting via; forming a first substructure on the first surface of the dielectric substrate; and forming a second substructure on the second surface of the dielectric substrate; the first connecting electrode connects the first substructure and the second substructure to form the coil structure of the inductor.

[0015] The preparation method further includes: forming a first conductive film layer and the first plate of the capacitor on the side of the second surface of the dielectric substrate facing away from the dielectric substrate through a single patterning process; forming a first interlayer dielectric layer on the side of the first conductive film layer facing away from the dielectric substrate; forming the second plate of the capacitor on the side of the first interlayer dielectric layer facing away from the dielectric substrate; the orthographic projections of the first plate of the capacitor and the second plate of the capacitor on the dielectric substrate at least partially overlap; forming a second interlayer dielectric layer on the side of the first interlayer dielectric layer facing away from the dielectric substrate, and a second connecting via, a third connecting via, and a fifth connecting via penetrating the first interlayer dielectric layer and the second interlayer dielectric layer, and a fourth connecting via penetrating the second interlayer dielectric layer. holes; forming a second conductive film layer, a second connecting electrode, and a third connecting electrode on a side away from the first conductive film layer through a single patterning process; the second conductive film layer is electrically connected to the first conductive film layer through the second connecting via and the third connecting via to form a second substructure; the second connecting electrode is electrically connected to the second plate of the capacitor through the fourth connecting via; the third connecting electrode is electrically connected to the first plate of the capacitor through the fifth connecting via; a third interlayer dielectric layer and a sixth connecting via, a seventh connecting via, and an eighth connecting via penetrating the third interlayer dielectric layer are formed on a side of the second conductive film layer away from the dielectric substrate; and a fourth interlayer dielectric layer is formed on a side of the first surface of the dielectric substrate away from the dielectric substrate.

[0016] Among them, the preparation method also includes: forming a first connecting pad, a second connecting pad and a third connecting pad on the side of the third interlayer dielectric layer away from the dielectric substrate; the first connecting pad is electrically connected to the second conductive film layer by passing through the sixth connecting via; the second connecting pad is electrically connected to the second connecting electrode by passing through the seventh connecting via; and the third connecting pad is electrically connected to the third connecting electrode by passing through the eighth connecting via. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A cross-sectional view of a passive filter according to an embodiment of the present disclosure;

[0018] Figure 2 A circuit diagram of a passive filter according to an embodiment of the present disclosure;

[0019] Figure 3A A schematic diagram of a hysteresis loop of the first interlayer dielectric layer according to an embodiment of the present disclosure;

[0020] Figure 3B A schematic diagram of a corresponding relationship between a dielectric constant and an electric field strength of a first interlayer dielectric layer according to an embodiment of the present disclosure;

[0021] Figure 4A This is another schematic diagram of an electric hysteresis loop of the first interlayer dielectric layer according to an embodiment of the present disclosure;

[0022] Figure 4B Schematic diagram of another correspondence between the dielectric constant and the electric field strength of the first interlayer dielectric layer according to an embodiment of the present disclosure;

[0023] Figure 5 is a top view of an inductor according to an embodiment of the present disclosure;

[0024] Figure 6 Schematic diagram of the preparation steps of the passive filter according to an embodiment of the present disclosure;

[0025] Figure 7 is a schematic diagram of step S10 of an embodiment of the present disclosure;

[0026] Figure 8 Schematic diagram of step S11 of an embodiment of the present disclosure;

[0027] Figure 9 is a schematic diagram of step S12 of an embodiment of the present disclosure;

[0028] Figure 10 Schematic diagram of step S13 of an embodiment of the present disclosure;

[0029] Figure 11 is a schematic diagram of step S14 of an embodiment of the present disclosure;

[0030] Figure 12 is a schematic diagram of step S15 of an embodiment of the present disclosure;

[0031] Figure 13 is a schematic diagram of step S16 in an embodiment of the present disclosure;

[0032] Figure 14 Schematic diagram of step S17 of an embodiment of the present disclosure. DETAILED DESCRIPTION

[0033] In order to enable those skilled in the art to better understand the technical solutions of the present disclosure, the present disclosure is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0034] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0035] The present disclosure provides a passive filter and a method for manufacturing the same. Figure 1 As shown, Figure 1 This is a cross-sectional view of an embodiment of the present disclosure. The passive filter includes a dielectric substrate 1, at least one capacitor C, and at least one inductor L. Capacitor C comprises a first plate, a first interlayer dielectric layer 7, and a second plate 2, arranged in sequence, facing away from the dielectric substrate 1. The dielectric constant of the first interlayer dielectric material varies with the electrostatic field between the first plate and the second plate 2.

[0036] In the embodiment of the present disclosure, since the dielectric constant of the first interlayer dielectric layer 7 of the capacitor C changes with the voltage of the electrostatic field applied between its two plates, the capacitance value of the capacitor C can be adjusted by adjusting the voltage of the electrostatic field applied between the two plates of the capacitor C. Specifically, since the capacitance value of the capacitor C is C0=ε0εS / d, where d is the thickness of the first interlayer dielectric layer 7, ε0 is the dielectric constant of vacuum, S is the area of ​​the overlapping part of the orthographic projection of the first plate, the second plate 2 and the first interlayer dielectric layer 7 on the dielectric substrate 1, and ε is the dielectric constant of the first interlayer dielectric layer 7. Therefore, when the dielectric constant ε of the first interlayer dielectric layer 7 is rAs the voltage of the electrostatic field applied between the two plates changes, the capacitance of the capacitor C changes. Further, by presetting the corresponding relationship between the dielectric constant of the first interlayer dielectric layer 7 and the electrostatic field voltage, it is possible to adjust the capacitance of the capacitor C in the passive device by adjusting the voltage of the electrostatic field applied between the two plates of the capacitor C. At the same time, since the capacitance of the capacitor C in the passive filter can determine the center frequency or cut-off frequency of the passive filter, the center frequency or cut-off frequency of the passive filter is adjusted in this way. This allows the passive filter to meet the requirements for specific frequencies in different frequency bands by simply adjusting the voltage of the electrostatic field between the two plates of the capacitor C without changing its structure.

[0037] Specific reference Figure 2 , Figure 2 for Figure 1 A circuit diagram of a passive filter shown. The passive filter disclosed herein includes an inductor L, a capacitor C, a resistor R, a first signal terminal, a second signal terminal and a third signal terminal. The first signal terminal is used as a signal input terminal Input, the second signal terminal is used as a signal output terminal Output, and the third signal terminal is used as a modulation voltage terminal Va. The first end of the resistor R is connected to the signal input terminal Input, and the second end of the resistor R is connected to the first lead terminal 18 of the inductor L. The first lead terminal 18 of the inductor L is connected to the signal input terminal Input, and the second lead terminal 19 of the inductor L is connected to the first plate of the capacitor C and the modulation voltage terminal Va. The first plate of the capacitor C is connected to the second lead terminal 19 of the inductor L and the modulation voltage terminal Va, and the second plate 2 of the capacitor C is connected to the signal output terminal Output. In the embodiment of the present disclosure, when the frequency of the passive filter needs to be adjusted, it is only necessary to apply an electrostatic field to the signal output terminal Output and the modulation voltage terminal Va to change the capacitance value of the capacitor C to achieve frequency adjustment of the passive filter. It should be noted that the passive filter disclosed in the present invention is only described by taking one inductor L and one capacitor C as an example. Passive filters including passive components such as multiple inductors L or multiple capacitors C are also within the protection scope of the present invention.

[0038] In some embodiments, the material of the first interlayer dielectric layer 7 of the passive filter can be a ferroelectric material or a paraelectric material. Since the dielectric constant of the ferroelectric material or the paraelectric material is very sensitive to the change of the external electrostatic field, the use of the ferroelectric material or the paraelectric material as the first interlayer dielectric layer 7 can meet the needs of the passive filter of the embodiment of the present disclosure. In some embodiments, when the material of the first interlayer dielectric layer 7 is a ferroelectric material, the material of the first interlayer dielectric layer 7 includes but is not limited to Mn2O3, PbZr X Ti (1-X) O3, BiFeO3, perovskite oxide, (Pb 0.83 La 0.17)TiO3. In some embodiments, when the material of the first interlayer dielectric layer 7 is a paraelectric material, the material of the first interlayer dielectric layer 7 includes but is not limited to one of SrTiO3, TiO2, and CaTiO3. Among them, the embodiment of the present disclosure is only described by taking the material of the first interlayer dielectric layer 7 as an example of ABO3 type perovskite. Specifically, due to the existence of its inherent dipole moment, the ferroelectric material has additional dipole polarization when the electric field acts. Therefore, the corresponding relationship between the electric polarization intensity P and the electric field intensity E of the ferroelectric material is a nonlinear corresponding relationship, which is as follows: Figure 3A At the same time, since the dielectric constant of the ferroelectric material comes from the flipping of the dipole under the action of the electric field, the corresponding relationship between the dielectric constant of the first interlayer dielectric layer 7 and the electric field strength is as follows: Figure 3B Similarly, when the material of the first interlayer dielectric layer 7 is a paraelectric material, since the paraelectric material does not have a spontaneous polarization phenomenon, the corresponding relationship between the electric polarization intensity P and the electric field intensity E of the paraelectric material is: Figure 4A The curve shown in FIG. 1 is similar to the corresponding relationship between the dielectric constant and the electric field strength of the first interlayer dielectric layer 7. Figure 4B Therefore, in the embodiment of the present disclosure, Figure 3B and Figure 4B The corresponding relationship between the electric field strength and the dielectric constant shown is used to adjust the voltage of the electrostatic field between the first plate and the second plate 2 of the capacitor C in the embodiment of the present disclosure, adjust the capacitance value of the capacitor C, and ultimately achieve frequency adjustment of the passive filter.

[0039] In some embodiments, the dielectric substrate 1 in the passive filter of the disclosed embodiments further includes a first connecting via 3 along its thickness, as well as first and second surfaces disposed oppositely along the thickness. The inductor L in the passive filter includes a first substructure 4 disposed on the first surface of the dielectric substrate 1, a second substructure 5 disposed on the second surface of the dielectric substrate 1, and a first connecting electrode 6 disposed within the first connecting via 3. The first connecting electrode 6 connects the first substructure 4 and the second substructure 5 to form the coil structure of the inductor L. The second substructure 5 is electrically connected to the first plate of the capacitor C. In this manner, a three-dimensional inductor L is integrated on the dielectric substrate 1, improving device integration and facilitating miniaturization.

[0040] Specifically, such as Figure 5 shown. Figure 5 This is a top view of the inductor L according to an embodiment of the present disclosure, referring to Figure 5, each first substructure 4 of the inductor L extends along the first direction and is arranged side by side along the second direction; each second substructure 5 of the inductor L extends along the third direction and is arranged side by side along the second direction. Among them, the first direction, the second direction, and the third direction are all different directions. In the embodiment of the present disclosure, the first direction and the second direction are perpendicular to each other, and the first direction and the third direction intersect and are arranged non-perpendicularly. Of course, the extension directions of the first substructure 4 and the second substructure 5 can also be interchanged, and are all within the protection scope of the embodiment of the present disclosure. In addition, in the embodiment of the present disclosure, the inductor L is illustrated as an example including N first substructures 4 and N-1 second substructures 5, where N≥2 and N is an integer. The first end and the second end of the first substructure 4 respectively overlap with the orthographic projection of a first connecting via 3 on the glass substrate in part. And the first end and the second end of a first substructure 4 correspond to different first connecting vias 3, that is, the orthographic projections of a first substructure 4 and two first connecting vias 3 on the glass substrate in part overlap. At this time, the first end of the i-th second substructure 5 of the inductor L is connected to the first end of the i-th first substructure 4 and the second end of the i+1-th first substructure 4 to form an inductor L coil, where 1≤i≤N-1, and i is an integer.

[0041] It should be noted that the first lead end 18 is connected to the second end of the first first substructure 4 of the inductor L coil, and the second lead end 19 is connected to the first end of the Nth first substructure 4. Furthermore, the first lead end 18 and the second lead end 19 can be arranged on the same layer as the second substructure 5 and made of the same material. In this case, the first lead end 18 can be connected to the second end of the first first substructure 4 through the first connecting via 3, and correspondingly, the second lead end 19 can be connected to the first end of the Nth first substructure 4 through the first connecting via 3.

[0042] It should be noted that in some embodiments, the resistor R can be implemented by a wire, or the resistor R can be made of a high-resistance material, such as indium tin oxide (ITO) or nickel-chromium (NiCr) alloy. Therefore, the specific structure of the resistor R is not limited in the embodiments of the present disclosure.

[0043] In some embodiments, continue to refer to Figure 1The passive filter also includes a second interlayer dielectric layer 12 disposed away from the first interlayer dielectric layer 7. The second interlayer dielectric layer 12 serves as an interlayer insulating layer in the passive filter. The second substructure 5 includes a first conductive film layer 8 and a second conductive film layer 9 disposed in sequence away from the dielectric substrate 1. The first conductive film layer 8 is electrically connected to the first plate of the capacitor C. The second conductive film layer 9 is electrically connected to the first conductive film layer 8 via a second connecting via and a third connecting via penetrating the first interlayer dielectric layer 7 and the second interlayer dielectric layer 12. The passive filter also includes a second connecting electrode 10 and a third connecting electrode 11 disposed on the same layer as the second conductive film layer 9. The second connecting electrode 10 is electrically connected to the second plate 2 of the capacitor C via a fourth connecting via penetrating the second interlayer dielectric layer 12. The third connecting electrode 11 is electrically connected to the first plate of the capacitor C via a fifth connecting via penetrating the second interlayer dielectric layer 12 and the first interlayer dielectric layer 7. The passive filter also includes a third interlayer dielectric layer 13 disposed away from the second conductive film, and a fourth interlayer dielectric layer 14 disposed away from the first substructure 4. The third interlayer dielectric layer 13 and the fourth interlayer dielectric layer 14 are used as protective layers to prevent the film layers in the passive filter from being corroded by water and oxygen.

[0044] In some embodiments, continue to refer to Figure 1 . The passive filter also includes a first connecting pad 15, a second connecting pad 16 and a third connecting pad 17 arranged on a side away from the second conductive film. The first connecting pad 15 is electrically connected to the second conductive film through a sixth connecting via penetrating the third interlayer dielectric layer 13. The second connecting pad 16 is electrically connected to the second connecting electrode 10 through a seventh connecting via penetrating the third interlayer dielectric layer 13. The third connecting pad 17 is electrically connected to the third connecting electrode 11 through an eighth connecting via penetrating the third interlayer dielectric layer 13. In the embodiment of the present disclosure, the first connecting pad 15 is used as a signal input terminal Input, the second connecting pad 16 is used as a signal output terminal Output, and the third connecting pad 17 is used as a modulation voltage terminal Va.

[0045] In some embodiments, dielectric substrate 1 includes, but is not limited to, any one of a glass substrate, a flexible substrate, and an interlayer dielectric layer comprising at least an organic insulating layer. Integrating passive components on a glass substrate offers advantages such as small size, light weight, high performance, low power consumption, and low electromagnetic loss. In the disclosed embodiments, dielectric substrate 1 preferably utilizes a glass substrate. The following description uses a glass substrate as an example.

[0046] The structural parameters of the various components of the passive filter of the embodiment of the present disclosure are described one by one in the following preparation method, and therefore will not be described in detail here.

[0047] In some embodiments, the present disclosure provides a method for preparing a passive filter. The passive filter may be the above-mentioned substrate. The preparation method includes the following steps:

[0048] A dielectric substrate 1 is provided; at least an inductor L and a capacitor C are formed on the dielectric substrate 1; wherein the step of forming the capacitor C includes:

[0049] A first plate, a first interlayer dielectric layer 7 and a second plate 2 are sequentially formed on the side away from the dielectric substrate 1; the dielectric constant of the first interlayer dielectric layer 7 changes with the electrostatic field between the first plate of the capacitor C and the second plate 2 of the capacitor C.

[0050] In order to clarify the preparation method in the embodiment of the present disclosure, the preparation method of the passive filter in the embodiment of the present disclosure is described below in conjunction with the accompanying drawings and specific embodiments. Figure 6 shown.

[0051] S10, providing a glass substrate, and processing the glass substrate to form a first connecting via 3 penetrating along the thickness direction of the glass substrate, such as Figure 7 shown.

[0052] In some examples, step S10 may include providing a glass substrate, performing laser modification on a first surface and a second surface of the glass substrate, respectively, and forming the glass substrate having the first connecting via 3 by HF etching.

[0053] For example: (1) Cleaning: The glass substrate enters the cleaning machine for cleaning.

[0054] In some examples, the thickness of the glass substrate is about 0.2 mm to 0.3 mm.

[0055] (2) Laser drilling: A laser is used to vertically incident the laser beam onto the first surface of the glass substrate to modify the surface, thereby forming a first sub-via hole on the first surface side of the glass substrate. Similarly, a laser is used to vertically incident the laser beam onto the second surface of the glass substrate to modify the surface, thereby forming a second sub-via hole on the second surface side of the glass substrate. The second sub-via hole is connected to the first sub-via hole to form a first connecting via hole 3.

[0056] Specifically, when the laser beam interacts with the glass substrate, the atoms in the glass substrate are ionized and ejected out of the first surface of the glass substrate due to the high energy of the laser photons. As time goes by, the hole drilled gradually deepens until the first sub-via is formed. The glass substrate is flipped over and the second sub-via is formed according to the same principle. Among them, the generally available laser wavelengths are 532nm, 355nm, 266nm, 248nm, 197nm, etc., the laser pulse width can be selected from 1-100fs, 1-100ps, 1-100ns, etc., and the type of laser can be selected from continuous lasers, pulsed lasers, etc. The laser drilling methods can include but are not limited to the following two methods. The first method is that when the spot diameter is large, the relative position of the laser beam and the glass substrate is fixed, and the glass substrate is directly drilled to a preset depth by relying on high energy. At this time, the shape of the first sub-via formed is an inverted frustum, and the diameter of the inverted frustum decreases from top to bottom (from the second surface to the first surface). In the second method, when the spot diameter is small, the laser beam scans in a circle on the glass substrate. The focal point of the spot is constantly changing, and the depth of the focus is also constantly changing. A spiral line is drawn from the lower surface (first surface) of the glass substrate to the upper surface (second surface) of the glass substrate, and the spiral radius decreases from bottom to top. The glass substrate is laser cut into a truncated cone shape to form a first sub-via. The shape of this first blind hole is the first sub-via. The second sub-via is formed in the same way as the first sub-via, so it will not be repeated. It can be seen that the first connecting via 3 formed by the first and second sub-vias is hourglass-shaped.

[0057] Of course, the first sub-connection via in the embodiment of the present disclosure can also be formed by laser beam irradiation of only the first surface or the second surface of the glass substrate to form a truncated cone-shaped or cylindrical connection via. The formation method can be the same as the above method, so it will not be repeated here. In the embodiment of the present disclosure, the aspect ratio of the formed first connection via 3 can be 6:1, and the aperture diameter of the first connection via 3 can be 50 microns.

[0058] (3) HF Etching: During the laser drilling process, a stress zone is formed within a range of approximately 5-20 microns on the upper surface of the inner wall of the first connecting via 3 near the hole. The glass substrate in this area is uneven and has many molten burrs, and contains a large number of microcracks and macrocracks, as well as residual stress. At this time, a 2%-20% HF etching solution is used at an appropriate temperature and for a certain period of time to wet-etch the glass in the stress zone. This makes the interior of the first connecting via 3 and the surface area near the hole smooth and flat, without microcracks or macrocracks, and completely etches away the stress zone.

[0059] S11, forming the first connection electrode 6 located at the first connection via 3, and forming the first conductive film layer 8 of the second substructure 5 of the inductor L and the first plate of the capacitor C, as shown in FIG. Figure 8 shown.

[0060] In some embodiments, step S11 may specifically include the following steps:

[0061] (1) Growing a seed layer: depositing a first metal material on the second surface of the glass substrate by magnetron sputtering, flipping the glass substrate, and depositing the first metal material on the first surface by magnetron sputtering. At this time, the first metal material is formed on the side wall of the first connecting via 3 as a seed layer.

[0062] In some examples, the first metal material includes, but is not limited to, at least one of copper (Cu), aluminum (Al), molybdenum (Mo), and silver (Ag), and the thickness of the first metal material is approximately 0.2 μm to 10 μm. The following description uses copper as the first metal material as an example.

[0063] In some examples, to enhance adhesion between the first metal material and the first surface of the glass substrate, an auxiliary metal film layer may be formed on the first surface of the glass substrate by methods including, but not limited to, magnetron sputtering before forming the first metal material. The material of the auxiliary metal film layer includes, but is not limited to, at least one of nickel (Ni), molybdenum (Mo) alloy, and titanium (Ti) alloy, such as MoNb, and the thickness of the auxiliary metal film layer is approximately 2 nm to 20 nm.

[0064] (2) Electroplating: Place the glass substrate on the electroplating machine carrier, press the power pad (pad), and place it in the hole-filling electroplating tank (a special hole-filling electrolyte is used in the tank). Apply current, and keep the electroplating solution flowing rapidly on the first surface of the glass substrate. The cations in the electroplating solution on the inner wall of the first connecting via 3 obtain electrons and become atoms and deposit on the inner wall. Through the special hole-filling electrolyte with a special ratio, it is possible to achieve high-speed deposition of metal copper (deposition rate 0.5-3um / min) mainly in the first blind hole. The first surface of the glass substrate is a flat area, and the deposition rate of metal copper on these two surfaces is extremely low (0.005-0.05um / min). As time goes by, the metal copper on the inner wall of the first connecting hole gradually grows thicker to form a first metal film layer. At this time, the first metal film layer grows more than 5μm compared to the first metal material. At this time, the first metal film layer fills the first connecting via 3.

[0065] In some examples, the first metal film layer may not completely fill the first connection via 3. In this step, a filling structure needs to be formed in the first connection via 3 to flatten the second surface of the glass substrate. The filling structure can be made of an organic insulating material, such as a resin material such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, or silicone. For another example, the organic insulating material can be an elastic material such as urethane or thermoplastic polyurethane (TPU).

[0066] It should be noted that, in the embodiment of the present disclosure, the first metal film layer is used as an example to fully fill the first connection via hole 3 .

[0067] (3) Patterning of the metal film layer on the second surface: Glue coating, exposure, and development are performed on the first metal film layer on the second surface, followed by etching. After etching, the stripping is performed to remove the glue. The patterning of the first metal film layer on the second surface is completed. At this time, the first conductive film layer 8 of the second substructure 5 of the inductor coil and the first plate of the capacitor C located on the first surface are formed.

[0068] In some examples, the step of forming the first conductive film layer 8 and the first electrode plate of the capacitor C also includes grinding the two-layer structure to avoid smoothness of the first conductive film layer 8 and the first electrode plate of the capacitor C and to ensure that the thickness meets the requirements of the capacitor C.

[0069] S12, forming a first interlayer dielectric layer 7 on the side of the second substructure 5 of the inductor L coil away from the glass substrate, and forming a pattern including the second plate 2 of the capacitor C on the side of the first interlayer dielectric layer 7 away from the glass substrate, as shown in FIG. Figure 9 shown.

[0070] In some embodiments, the material of the first interlayer dielectric layer 7 is a ferroelectric material or a paraelectric material. For example: (Pb 0.83 La 0.17 In the embodiment of the present disclosure, a ferroelectric thin film with a thickness of 50-100 nm can be deposited by sputtering, pulsed laser deposition, metal organic chemical vapor deposition or sol-gel method.

[0071] In some embodiments, the second plate 2 of capacitor C can be formed by magnetron sputtering on the side of the first interlayer dielectric layer 7 facing away from the glass substrate. The second metal film layer can be 100 nm thick. Then, resist coating, exposure, and development are performed, followed by wet etching. After etching, the resist is stripped to form a pattern including the second plate 2 of capacitor C.

[0072] S13, forming a second interlayer dielectric layer 12 on the side of the second electrode 2 of the capacitor C away from the glass substrate, and forming a second connecting via hole, a third connecting via hole and a fifth connecting via hole penetrating the first dielectric layer and the second interlayer dielectric layer 12, and a fourth connecting via hole penetrating the second interlayer dielectric layer 12, as shown in FIG. Figure 10 .

[0073] In some embodiments, the second interlayer dielectric layer 12 is made of an inorganic insulating material. For example, the second interlayer dielectric layer 12 is an inorganic insulating layer formed of silicon nitride (SiNx), or an inorganic insulating layer formed of silicon oxide (SiO2), or a stacked combination of a SiNx inorganic insulating layer and a SiO2 inorganic insulating layer.

[0074] S14. On the side of the second interlayer dielectric layer 12 facing away from the glass substrate, a pattern including a second conductive film layer 9, a second connecting electrode 10, and a third connecting electrode 11 of the second substructure 5 is formed by a patterning process. The second conductive film layer 9 is connected to the first conductive film layer 8 through the second connecting via and the third connecting via; the second connecting electrode 10 is connected to the second plate 2 of the capacitor C through the fourth connecting via; and the third connecting electrode 11 is connected to the first plate of the capacitor C through the fifth connecting via. Figure 11 shown.

[0075] In some embodiments, step S14 may include forming a third metal film layer by magnetron sputtering, applying a resist, exposing, developing, and then performing wet etching. After etching, stripping the resist to form a pattern including the second conductive film layer 9 of the second substructure 5, the second connection electrode 10, and the third connection electrode 11. The material of the third metal film layer may be the same as that of the first metal film layer, and therefore will not be described in detail here.

[0076] In some embodiments, the thickness of the third metal film layer is greater than 5 μm, and the thickness of the formed second conductive film layer 9 is greater than the thickness of the first conductive film layer 8 .

[0077] S15, forming a third interlayer dielectric layer 13 on the side of the second conductive film layer 9 away from the glass substrate; and forming a sixth connecting via hole, a seventh connecting via hole and an eighth connecting via hole penetrating the third interlayer dielectric layer 13, such as Figure 12 shown.

[0078] The third interlayer dielectric layer 13 is used to prevent water and oxygen from corroding the devices formed on the second surface of the glass substrate. The thickness of the third interlayer dielectric layer 13 is between 0.1 μm and 2 μm. The material of the third interlayer dielectric layer 13 can be an inorganic insulating material. For example, the third interlayer dielectric layer 13 can be an inorganic insulating layer formed of silicon nitride (SiNx), an inorganic insulating layer formed of silicon oxide (SiO2), or a stacked film layer composed of a SiNx inorganic insulating layer and a SiO2 inorganic insulating layer.

[0079] S16, flipping the glass substrate, and forming a pattern of the first substructure 4 including the inductor L coil by a patterning process, as shown in FIG. Figure 13 shown.

[0080] In some examples, step S16 may include forming a fourth metal film layer on the first surface of the glass substrate by magnetron sputtering, and then coating, exposing, developing, and then wet etching. After etching, stripping to form a first substructure 4 pattern including the inductor L coil.

[0081] The thickness of the fourth metal film layer is greater than 5 μm. The material of the fourth metal film layer can be the same as that of the first metal film layer, so it will not be described in detail here.

[0082] S17, forming a fourth interlayer dielectric layer 14 on the side of the first substructure 4 facing away from the glass substrate, as shown in FIG. Figure 14 shown.

[0083] The fourth interlayer dielectric layer 14 has a thickness of greater than 2 μm. The material of the fourth interlayer dielectric layer 14 may include an organic insulating material, such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, silicone, or other resin materials. For another example, the organic insulating material may include an elastic material, such as urethane, thermoplastic polyurethane (TPU), or the like.

[0084] S18, flip the glass substrate over again, and form a first connecting pad 15, a second connecting pad 16, and a third connecting pad 17 in the sixth connecting via hole, the seventh connecting via hole, and the eighth connecting via hole, respectively. The first connecting pad 15, the second connecting pad 16, and the third connecting pad 17 may be solder.

[0085] This completes the preparation of the passive filter.

[0086] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A passive filter, characterized in that: include: A dielectric substrate, at least one capacitor, and at least one inductor; the capacitor comprising a first plate, a first interlayer dielectric layer, and a second plate, arranged in sequence away from the dielectric substrate; wherein the dielectric constant of the first interlayer dielectric material changes with the electrostatic field between the first plate and the second plate; The dielectric substrate further includes a first connecting via along the thickness direction thereof and a first surface and a second surface arranged opposite to each other along the thickness direction; The inductor includes a first substructure disposed on the first surface of the dielectric substrate, a second substructure disposed on the second surface of the dielectric substrate, and a first connecting electrode disposed in the first connecting via, wherein the first connecting electrode connects the first substructure and the second substructure to form a coil structure of the inductor; the second substructure is electrically connected to the first plate of the capacitor; The passive filter further includes a second interlayer dielectric layer disposed away from the first interlayer dielectric layer; the second substructure includes a first conductive film layer and a second conductive film layer sequentially disposed away from the dielectric substrate; the first conductive film layer is electrically connected to the first plate of the capacitor; the second conductive film layer is electrically connected to the first conductive film layer via a second connecting via and a third connecting via penetrating the first and second interlayer dielectric layers; The passive filter further includes a second connecting electrode and a third connecting electrode provided in the same layer as the second conductive film layer; the second connecting electrode is electrically connected to the second plate of the capacitor via a fourth connecting via penetrating the second interlayer dielectric layer; The third connecting electrode is electrically connected to the first electrode plate of the capacitor through a fifth connecting via hole penetrating the second interlayer dielectric layer and the third interlayer dielectric layer; The passive filter further includes a third interlayer dielectric layer disposed on a side away from the second conductive film layer, and a fourth interlayer dielectric layer disposed on a side away from the first substructure.

2. The passive filter according to claim 1, wherein The material of the first interlayer dielectric layer at least includes ferroelectric material.

3. The passive filter according to claim 2, characterized in that The material of the first interlayer dielectric layer at least includes: Mn2O3, PbZr X Ti (1-X) O3, BiFeO3, perovskite oxide, (Pb 0.83 La 0.17 )One of TiO3.

4. The passive filter according to claim 1, wherein The material of the first interlayer dielectric layer at least includes a paraelectric material.

5. The passive filter according to claim 4, characterized in that The material of the first interlayer dielectric layer includes at least one of SrTiO3, TiO2, and CaTiO3.

6. The passive filter according to claim 1, characterized in that Also includes: a first connecting pad, a second connecting pad, and a third connecting pad disposed on a side away from the second conductive film layer; The first connection pad is electrically connected to the second conductive film layer through a sixth connection via penetrating the third interlayer dielectric layer; The second connection pad is electrically connected to the second connection electrode through a seventh connection via penetrating the third interlayer dielectric layer; The third connection pad is electrically connected to the third connection electrode through an eighth connection via hole penetrating the third interlayer dielectric layer.

7. The passive filter according to any one of claims 1 to 6, characterized in that: The material of the dielectric substrate at least includes a glass base.

8. A method for preparing a passive filter, characterized in that: A dielectric substrate is provided; at least an inductor and a capacitor are formed on the dielectric substrate; wherein the dielectric substrate further comprises a first connecting via along its thickness direction and a first surface and a second surface disposed opposite to each other along the thickness direction; The step of forming the inductor comprises: forming a first connecting electrode in the first connecting via; forming a first substructure on the first surface of the dielectric substrate; forming a second substructure on the second surface of the dielectric substrate; the first connecting electrode connects the first substructure and the second substructure to form a coil structure of the inductor; The step of forming the capacitor comprises: A first electrode plate, a first interlayer dielectric layer, and a second electrode plate are sequentially formed on a side away from the dielectric substrate; the dielectric constant of the first interlayer dielectric layer changes as the electrostatic field between the first electrode plate and the second electrode plate of the capacitor changes; forming a first conductive film layer and the first electrode plate of the capacitor on the side of the second surface of the dielectric substrate facing away from the dielectric substrate through a single patterning process; forming a first interlayer dielectric layer on a side of the first conductive film layer facing away from the dielectric substrate; The second plate of the capacitor is formed on a side of the first interlayer dielectric layer facing away from the dielectric substrate; the orthographic projections of the first plate of the capacitor and the second plate of the capacitor on the dielectric substrate at least partially overlap; forming a second interlayer dielectric layer on a side of the first interlayer dielectric layer facing away from the dielectric substrate, and forming a second connecting via hole, a third connecting via hole, and a fifth connecting via hole penetrating the first interlayer dielectric layer and the second interlayer dielectric layer, and a fourth connecting via hole penetrating the second interlayer dielectric layer; A second conductive film layer, a second connecting electrode, and a third connecting electrode are formed on a side away from the first conductive film layer through a single patterning process; the second conductive film layer is electrically connected to the first conductive film layer through the second connecting via and the third connecting via to form a second substructure; the second connecting electrode is electrically connected to the second plate of the capacitor through the fourth connecting via; and the third connecting electrode is electrically connected to the first plate of the capacitor through the fifth connecting via. forming a third interlayer dielectric layer, and a sixth connecting via hole, a seventh connecting via hole, and an eighth connecting via hole penetrating the third interlayer dielectric layer on a side of the second conductive film layer facing away from the dielectric substrate; A fourth interlayer dielectric layer is formed on a side of the first surface of the dielectric substrate facing away from the dielectric substrate.

9. The preparation method according to claim 8, characterized in that A first connecting pad, a second connecting pad, and a third connecting pad are formed on a side of the third interlayer dielectric layer facing away from the dielectric substrate; the first connecting pad is electrically connected to the second conductive film layer by passing through the sixth connecting via; the second connecting pad is electrically connected to the second connecting electrode by passing through the seventh connecting via; and the third connecting pad is electrically connected to the third connecting electrode by passing through the eighth connecting via.

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