High voltage semiconductor device

Abstract

A high voltage semiconductor device includes a substrate, a first well region, a second well region, a first insulating layer, a source, a drain, a first electrode structure, and a second electrode structure. The first well region and the second well region are disposed within the substrate and have a first conductivity type and a second conductivity type, respectively, that are complementary. The first insulating layer is disposed on the first well region. The source and the drain are disposed within the second well region and the first well region, respectively. The first electrode structure and the second electrode structure are disposed on the substrate, a distance between an electrode top surface of the first electrode structure and a substrate top surface has a first height and a second height that are not equal, and one of the first electrode structure and the second electrode structure is a gate structure.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a high-voltage semiconductor device. Background Technology

[0002] With advancements in semiconductor technology, the industry can now integrate control circuits, memory, low-voltage operating circuits, and high-voltage operating circuits and related components onto a single chip, reducing costs and improving operational performance. Transistors, commonly used in amplifying current or voltage signals in circuits, as oscillators, or as switching elements controlling circuit switching, are increasingly being used as high-power or high-voltage devices thanks to advancements in semiconductor manufacturing processes. For example, semiconductor devices used as high-voltage components are positioned between the chip's internal circuitry and input / output (I / O) pins to prevent large amounts of charge from entering the internal circuitry via the I / O pins in a very short time and causing damage.

[0003] In current high-voltage semiconductor devices, to improve the breakdown voltage, in addition to introducing drift regions structurally, field plates can be formed, such as extending the gate terminal further above an isolation structure, so that the surface electric field at the gate terminal can be more dispersed. However, existing high-voltage semiconductor devices are not satisfactory in all aspects and still need further improvement to meet practical requirements. Summary of the Invention

[0004] One object of the present invention is to provide a high-voltage semiconductor device having a field plate structure of various heights, which avoids excessively increasing the lateral distance between the gate and drain. Therefore, the high-voltage semiconductor device can effectively reduce parasitic capacitance and increase breakdown voltage, thereby improving the component reliability of the high-voltage semiconductor device.

[0005] To achieve the above objectives, a preferred embodiment of the present invention provides a high-voltage semiconductor device, comprising a substrate, a first well region, a second well region, a first insulating layer, a source electrode, a drain electrode, a first electrode structure, and a second electrode structure. The first well region is disposed within the substrate and has a first conductivity type. The second well region is disposed within the substrate adjacent to the first well region and has a second conductivity type complementary to the first conductivity type. The first insulating layer is disposed on the first well region. The source electrode is disposed within the second well region, and the drain electrode is disposed within the first well region. The first electrode structure and the second electrode structure are disposed on the substrate, and the distance between the top surface of the first electrode structure and the top surface of the substrate has unequal first and second heights, wherein at least one of the first electrode structure and the second electrode structure is a gate structure.

[0006] The high-voltage semiconductor device of the present invention comprises two or more independently disposed electrode structures, such as gate structures or capacitor structures consisting of polysilicon, insulating layers and conductor layers stacked in sequence. Insulating layers of different thicknesses, positions, or coverage degrees are disposed between the electrode structures and the substrate, allowing for various distances between the top surface of each electrode structure and the top surface of the substrate, or between the top surface of the electrode structure passing through different insulating layers, dielectric layers, or combinations of insulating and dielectric layers and reaching the top surface of the substrate. This enables the high-voltage semiconductor device to achieve field plates of various heights and thus exhibit significantly higher breakdown voltages. Attached Figure Description

[0007] Figure 1 A cross-sectional schematic diagram of a high-voltage semiconductor device according to a first embodiment of the present invention is shown.

[0008] Figure 2 A cross-sectional schematic diagram of a high-voltage semiconductor device according to a second embodiment of the present invention is shown.

[0009] Figure 3 A cross-sectional schematic diagram of a high-voltage semiconductor device according to a third embodiment of the present invention is shown.

[0010] Figure 4 A cross-sectional schematic diagram of a high-voltage semiconductor device according to a fourth embodiment of the present invention is shown.

[0011] Figure 5 A cross-sectional schematic diagram of a high-voltage semiconductor device according to a fifth embodiment of the present invention is shown.

[0012] Figure 6 A cross-sectional schematic diagram of a high-voltage semiconductor device according to a sixth embodiment of the present invention is shown.

[0013] Figure 7A cross-sectional schematic diagram of a high-voltage semiconductor device according to a seventh embodiment of the present invention is shown.

[0014] Figure 8 A cross-sectional schematic diagram of a high-voltage semiconductor device according to the eighth embodiment of the present invention is shown.

[0015] The reference numerals in the attached figures are explained as follows:

[0016] 100, 300, 400, 500, 600, 700, 800, 900: High-voltage semiconductor devices

[0017] 110: Base

[0018] 120: Buried layer

[0019] 130: Second Well Area

[0020] 135: matrix area

[0021] 140: Fourth Well Area

[0022] 145: matrix area

[0023] 150: Deep Well Area

[0024] 155: Quarantine Zone

[0025] 160: First Well Area

[0026] 165: Drain

[0027] 170: Third Well Area

[0028] 175: Source Extreme

[0029] 175a: First doped region

[0030] 175b: Second doped region

[0031] 180, 380, 480, 580, 680, 780, 880, 980: First gate structure

[0032] 181, 381, 481, 581, 681, 781, 881, 981: Gate dielectric layer

[0033] 183, 383, 483, 583, 683, 783, 883, 983: Gate electrode

[0034] 185, 385, 485, 585, 685, 785, 885, 985: Sidewall

[0035] 190, 390, 490, 590, 690, 790, 990: Second gate structure

[0036] 191, 391, 491, 591, 691, 791, 991: Gate dielectric layer

[0037] 193, 393, 493, 593, 693, 793, 993: Gate electrode

[0038] 195, 395, 495, 595, 695, 795, 995: Sidewall

[0039] 200, 201, 203, 205, 207: Insulation structure

[0040] 301: Insulation layer

[0041] 401: Insulation layer

[0042] 501: Insulation layer

[0043] 601: Insulation layer

[0044] 701: Insulation layer

[0045] 703: Insulation layer

[0046] 770: Capacitor Structure

[0047] 771: Dielectric layer

[0048] 773: Conductor layer

[0049] 801: Insulation layer

[0050] 801a: Part 1

[0051] 801b: Part Two

[0052] 803: Insulation layer

[0053] 870: Electrode Structure

[0054] 871: Dielectric layer

[0055] 873: Conductor layer

[0056] 901: Insulation layer

[0057] 901a: Part 1

[0058] 901b: Part Two

[0059] 903: Insulation layer

[0060] 970: Electrode Structure

[0061] 971: Dielectric layer

[0062] 973: Conductor layer

[0063] g1, g2, g3, g4, g5, g6, g7: Distance

[0064] H31, H32, H33: Distance

[0065] H41, H42: Distance

[0066] H51, H52: Distance

[0067] H61, H62: Distance

[0068] H71, H72, H73, H74: Distance

[0069] H81, H82, H83, H84, H85: Distance

[0070] H91, H92, H93, H94, H95, H96: Distance Detailed Implementation

[0071] To enable those skilled in the art to further understand the present invention, several preferred embodiments are listed below, and the composition and desired effects of the present invention are described in detail with reference to the accompanying drawings.

[0072] In this invention, the description of "a first component being formed on or above a second component" can refer to either "the first component and the second component being in direct contact" or "other components existing between the first component and the second component," resulting in the first component and the second component not being in direct contact. Furthermore, various embodiments of this invention may use repeated component symbols and / or textual annotations. The use of these repeated component symbols and textual annotations is for the purpose of making the description more concise and clear, rather than to indicate the relationship between different embodiments and / or configurations. Additionally, regarding spatially related descriptive terms mentioned in this invention, such as "below," "above," "low," "high," "below," "above," "under," "above," "bottom," "top," and similar terms, for ease of description, their usage is to describe the relative relationship between one component or feature and another (or more) components or features in the drawings. Besides the orientation shown in the drawings, these spatially related terms are also used to describe the possible orientation of the semiconductor device during fabrication, use, and operation. For example, when a semiconductor device is rotated 180 degrees, a component that was originally positioned "above" other components will now be positioned "below" them. Therefore, as the orientation of the semiconductor device changes (rotating 90 degrees or other angles), the spatial descriptions used to describe its orientation should also be interpreted accordingly.

[0073] Although the present invention uses terms such as first, second, and third to describe various elements, components, regions, layers, and / or sections, it should be understood that such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, and / or section from another, and do not in themselves imply or represent any prior ordinal number of the element, nor do they represent the arrangement order of one element with another, or the order of manufacturing processes. Therefore, without departing from the scope of the specific embodiments of the present invention, the first element, component, region, layer, or section discussed below may also be referred to as the second element, component, region, layer, or section, etc.

[0074] The terms "about" or "substantially" as used in this invention generally mean within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. It should be noted that the quantities provided in the specification are approximate quantities; that is, the meaning of "about" or "substantially" may be implied even without specific specification.

[0075] Please refer to Figure 1 The diagram illustrates a schematic of a high-voltage semiconductor device 100 according to a first embodiment of the present invention. The high-voltage semiconductor device of the present invention refers to a semiconductor device with an operating voltage of approximately 20 to 40 volts (V), such as a laterally diffused metal oxide semiconductor transistor (LDMOS transistor). It can be a laterally diffused N-type LDMOS transistor or a laterally diffused P-type LDMOS transistor. In this embodiment, the high-voltage semiconductor device 100 is described using a laterally diffused N-type LDMOS transistor as an example, but is not limited thereto.

[0076] First, such as Figure 1As shown, the high-voltage semiconductor device 100 includes a substrate 110, such as a silicon substrate, epitaxial silicon substrate, silicon-germanium substrate, silicon carbide substrate, or silicon-on-insulator (SOI) substrate, and a buried layer 120, a first well region 160, and a second well region 130 disposed within the substrate 110. Specifically, the first well region 160 has a first conductivity type (e.g., N-type), and a drain 165 is formed within the first well region 160. The drain 165 is, for example, a doped region also having the first conductivity type (e.g., N-type), but with a doping concentration greater than that of the first well region 160. On the other hand, the second well region 130 is disposed adjacent to the first well region 160 and has a second conductivity type (e.g., P-type), which is complementary to the first conductivity type (e.g., N-type). In this embodiment, the depth of the second well region 130 within the substrate 110 is, for example, slightly greater than the depth of the first well region 160 within the substrate 110, thus, in such a way... Figure 1 In the cross-sectional view shown, the second well region 130 may be disposed around the outside of the first well region 160. In other words, the second well region 130, viewed from a top view (not shown), may appear to surround the outside of the first well region 160 as a whole, but is not limited thereto.

[0077] A source 175 is formed within the second well region 130. In one embodiment, a third well region 170 may be further formed within the second well region 130. The third well region 170 also has the second conductivity type (e.g., P-type), and the doping concentration of the third well region 170 is preferably greater than that of the second well region 130. The source 175 may be disposed within the third well region 170 and includes an adjacent first doped region 175a and a second doped region 175b. The first doped region 175a and the second doped region 175b respectively include the first conductivity type (e.g., N-type) and the second conductivity type (e.g., P-type), and the doping concentration of the first doped region 175a and the second doped region 175b is preferably greater than that of the second well region 130 or the third well region 170. For example... Figure 1 As shown, the buried layer 120 is further disposed below the first well region 160 and the second well region 130 to serve as an isolation structure or anti-punch-through structure for the high-voltage semiconductor device 100, so as to prevent current from directly punching through the bottom or interior of the substrate 110 from the first well region 160, thereby affecting the device performance of the high-voltage semiconductor device 100. In this embodiment, the buried layer 120 has, for example, the first conductivity type (such as N-type), and its doping concentration is preferably higher than that of the first well region 160 or the second well region 130.

[0078] A body region 135 is also formed within the second well region 130. The body region 135 has the second conductivity type (e.g., P-type) and its doping concentration is greater than that of the second well region 130. Preferably, the body region 135 does not directly contact the drain 165 disposed within the first well region 160, or it does not directly contact the source 175 also disposed within the second well region 130. For example, a plurality of insulating structures 200 may be formed on the substrate 110. The insulating structures 200 are, for example, field oxides (FOX) formed by local oxidation of silicon (LOCOS). Figure 1 (As shown), it can also be shallow trench isolation (STI) formed through a deposition process. In this process, insulating structures 205 and 207 are respectively provided on two opposite sides of the substrate region 135. The insulating structure 205 can separate the substrate region 135 from the drain 165, or the substrate region 135 from the source 175, as shown. Figure 1 As shown. Thus, the substrate region 135 and the drain 165 can be electrically isolated from each other. The substrate region 135 can also be electrically connected to the first doped region 175a and the second doped region 175b of the source 175 via an external circuit (not shown), allowing the substrate region 135 and the source 175 to be at the same potential, but this is not a limitation. In other words, the substrate region 175 and each insulating structure 200 (such as insulating structure 205 or insulating structure 207) can present a ring-shaped structure from a top view (not shown), such as a rectangular frame, a circular ring, or a racetrack-shaped structure, allowing the substrate region 135 to be arranged around the periphery of the drain 165 and the source 175, while the insulating structures 205 and 207 are arranged around the inner and outer sides of the substrate region 135, respectively, but their specific arrangement is not limited to this.

[0079] Furthermore, in one embodiment, the substrate 110 of the high-voltage semiconductor device 100 may further include an isolation region, which can be externally connected to an isolation voltage (V). iso This isolation region isolates the high-voltage circuitry inside the high-voltage semiconductor device 100. The isolation region may include, for example, a deep well region 150 surrounding the outer side of the second well region 130 and an isolation region 155 located within the deep well region 150, such as... Figure 1As shown, both the deep well region 150 and the isolation region 155 have the first conductivity type (e.g., N-type), and the doping concentration of the isolation region 155 is preferably greater than that of the deep well region 150. In another embodiment, the substrate 110 of the high-voltage semiconductor device 100 may further include another substrate region 145, which is disposed within a fourth well region 140 and surrounds the outside of the high-voltage semiconductor device 100 entirely through the fourth well region 140. The other substrate region 145 and the fourth well region 140 also have the second conductivity type (e.g., P-type), thereby further isolating the high-voltage semiconductor device 100 from other active components, such as another high-voltage semiconductor device. Insulating structures 201 and 203 may be respectively provided on opposite sides of the other substrate region 145 to separate the aforementioned isolation region 155 through the insulating structure 201. Figure 1 As shown.

[0080] The high-voltage semiconductor device 100 of this embodiment can optionally have two independent electrode structures between the source 175 and the drain 165. For example, the electrode structures can be a first gate structure 180 and a second gate structure 190 that are separated from each other. Figure 1 As shown. In detail, the first gate structure 180 and the second gate structure 190 may each include a gate dielectric layer 181, 191, a gate electrode 183, 193, and a sidewall 185, 195 surrounding the gate dielectric layer 181, 191 and the gate electrode 183, 193, respectively, stacked sequentially on the substrate 110. The gate electrodes 183, 193 of the first gate structure 180 and the second gate structure 190 are separated from each other, with a spacing g1 of, for example, approximately 0.1 to 0.2 micrometers (μm), preferably 0.13 to 0.16 micrometers, but not limited thereto. Preferably, the gap g1 between the gate electrodes 183 and 193 of the first gate structure 180 and the second gate structure 190 is located within the range of the first well region 160, and the gap g1 can be minimized as much as possible so that the sidewalls 185 and 195 on one side of the first gate structure 180 and the second gate structure 190 can be directly adjacent, such as... Figure 1 As shown, or they may be integrated into one unit (not shown). In this configuration, the first gate structure 180 and the second gate structure 190 can provide different voltages, thereby improving the device performance of the high-voltage semiconductor device 100.

[0081] Those skilled in the art will readily understand that, to meet actual product requirements, the high-voltage semiconductor device of the present invention may also have other forms, and is not limited to those described above. For example, in the aforementioned embodiments, while shortening the distance between the gate structure and the drain 165, the electric field strength as the gate structure gets closer to the drain 165 may lead to a decrease in the breakdown voltage of the high-voltage semiconductor device 100. Therefore, according to another embodiment of the present invention, a high-voltage semiconductor device is provided that can reduce the parasitic capacitance between the gate structure and the drain while simultaneously increasing the breakdown voltage of the high-voltage semiconductor device, thereby improving the overall component reliability of the high-voltage semiconductor device. Other embodiments or variations of the high-voltage semiconductor device will be further described below. For the sake of simplicity, the following description mainly focuses on the differences between the embodiments, and will not repeat the same points. In addition, the same components in the embodiments of the present invention are labeled with the same reference numerals to facilitate comparison between the embodiments.

[0082] Please refer to Figure 2 The diagram shows a cross-sectional view of a high-voltage semiconductor device 300 according to a second embodiment of the present invention. The structure of the high-voltage semiconductor device 300 in this embodiment is generally the same as that of the high-voltage semiconductor device 100 described in the first embodiment, also including a substrate 110, a first well region 160, a second well region 130, a drain 165, a source 175, a substrate region 135, and an insulating structure 200, etc. The similarities will not be repeated here. The main difference between this embodiment and the previous embodiment is that the high-voltage semiconductor device 300 may optionally have an insulating layer 301 added to the first well region 160 between the source 175 and the drain 165, so that the two independently configured electrode structures (such as...) Figure 2 The first gate structure 380 and the second gate structure 390 shown can be completely or partially disposed across the insulating layer 301.

[0083] In detail, the first gate structure 380 and the second gate structure 390 may also include a gate dielectric layer 381, 391, a gate electrode 383, 393, and a sidewall 385, 395 surrounding the gate dielectric layer 381, 391 and the gate electrode 383, 393, respectively, stacked sequentially on the substrate 110. The first gate structure 380 is, for example, located at the boundary between the first well region 160 and the second well region 130 (or, it can be considered that the first gate structure 380 spans the boundary between the first well region 160 and the second well region 130), while the second gate structure 390 is completely located within the first well region 160, so that the second gate structure 390 does not overlap the second well region 130, and the second gate structure 390 may be adjacent to the first gate structure 380. In this configuration, the gate electrodes 383 and 393 of the first gate structure 380 and the second gate structure 390 can be separated from each other, with a spacing g2 between them being, for example, approximately 0.1 to 0.2 micrometers, preferably 0.13 to 0.16 micrometers, but not limited thereto. Preferably, the spacing g2 between the gate electrodes 383 and 393 of the first gate structure 380 and the second gate structure 390 can be located within the first well region 160 and above the insulating layer 301, such as... Figure 2 As shown. The insulating layer 301 is, for example, a dielectric material layer formed by a deposition process, such as a silicon monoxide layer, but is not limited thereto. Preferably, the thickness of the insulating layer 301 is greater than the thickness of the gate dielectric layers 381 and 391 of the first gate structure 380 or the second gate structure 390. However, those skilled in the art will understand that the specific thickness, oxygen content, and density of the insulating layer 301 can be adjusted according to actual product requirements.

[0084] In this embodiment, the second gate structure 390 is completely disposed across the insulating layer 301, such that the distance H31 between the gate electrode 393 as a whole and the substrate 110 (i.e., the distance between the top surface of the gate electrode 393 and the top surface of the substrate 110) is a constant value; while the first gate structure 380 is partially disposed across the insulating layer 301 and partially disposed directly on the substrate 110, such that the distance H32 between the gate electrode 383 of the first part (such as the part disposed across the insulating layer 301) and the substrate 110 is different from the distance H33 between the gate electrode 383 of the second part (such as the part disposed directly on the substrate 110) and the substrate 110. For example, the distance H31 from the top surface of the gate electrode 393 of the second gate structure 390 through the insulating layer 301 to the top surface of the substrate 110, the distance H33 from the top surface of the gate electrode 383 of the first gate structure 380 directly to the top surface of the substrate 110, and the distance H32 from the top surface of the gate electrode 383 of the first gate structure 380 through the insulating layer 301 to the top surface of the substrate 110 can achieve field plates of different heights, thereby reducing the surface field (RESURF) and helping to improve the breakdown voltage of the high-voltage semiconductor device 300.

[0085] Furthermore, you can refer to Figure 3 The diagram shows a cross-sectional view of the high-voltage semiconductor device 400 in the third embodiment of the present invention. The structure of the high-voltage semiconductor device 400 in this embodiment is generally the same as that of the high-voltage semiconductor device 300 described in the second embodiment, and the similarities will not be repeated. The main difference between this embodiment and the previous embodiment is that the high-voltage semiconductor device 400 selects to directly mount the first gate structure 480 on the substrate 110, while the second gate structure 490 is partially mounted on an insulating layer 401. The insulating layer 401 in this embodiment is also a dielectric material layer, such as a silicon oxide layer, formed by a deposition process, and the various parameters of the insulating layer 401 can be adjusted according to actual product requirements. Preferably, the thickness of the insulating layer 401 is greater than the thickness of the gate dielectric layers 481 and 491 of the first gate structure 480 or the second gate structure 490, but this is not a limitation.

[0086] In detail, the first gate structure 480 and the second gate structure 490 may also include a gate dielectric layer 481, 491, a gate electrode 483, 493, and a sidewall 485, 495 surrounding the gate dielectric layer 481, 491 and the gate electrode 483, 493, respectively, stacked sequentially on the substrate 110. In this embodiment, the first gate structure 480 is also disposed at the boundary between the first well region 160 and the second well region 130, while the second gate structure 490 is completely disposed within the first well region 160 and adjacent to the first gate structure 480. Under this arrangement, the gate electrodes 483, 493 of the first gate structure 480 and the second gate structure 490 are also separated from each other, with a spacing g3 of approximately 0.1 to 0.2 micrometers, preferably 0.13 to 0.16 micrometers, but not limited thereto. It should be noted that in this embodiment, due to the small spacing g3, the sidewalls 485 and 495 on one side of the first gate structure 480 and the second gate structure 490 can be fused together. Simultaneously, the gate dielectric layers 481 and 491 of the first gate structure 480 and the second gate structure 490 can also be interconnected to form a single integrated structure. Figure 3 As shown. Thus, the gap g3 between the gate electrodes 483 and 493 of the first gate structure 480 and the second gate structure 490 can be located on the gate dielectric layers 481 and 491, and still within the range of the first well region 160, as... Figure 3 As shown.

[0087] Furthermore, the second gate structure 490 is partially disposed across the insulating layer 401, while another portion is directly disposed on the substrate 110. This allows the distance H41 between the gate electrode 493 of the first gate structure 480 (such as the portion disposed across the insulating layer 401) and the substrate 110 to be different from the distance H42 between the gate electrode 493 of the second gate structure 490 (such as the portion directly disposed on the substrate 110) and the substrate 110. For example, the distance H42 between the top surface of the gate electrode 483 of the first gate structure 480 and the top surface of the substrate 110, the distance H42 between the top surface of the gate electrode 493 of the second gate structure 490 and the top surface of the substrate 110 through the insulating layer 401, and the distance H41 between the top surface of the gate electrode 493 of the second gate structure 490 and the top surface of the substrate 110 can achieve two different heights of field plates. This also helps to improve the breakdown voltage of the high-voltage semiconductor device 400.

[0088] Next, please refer to Figure 4The diagram shows a cross-sectional view of the high-voltage semiconductor device 500 in the fourth embodiment of the present invention. The structure of the high-voltage semiconductor device 500 in this embodiment is generally the same as that of the high-voltage semiconductor device 300 described in the second embodiment or the high-voltage semiconductor device 400 described in the third embodiment, and the similarities will not be repeated. The main difference between this embodiment and the previous embodiments is that the high-voltage semiconductor device 500 adds an insulating layer 501 between the source electrode 175 and the drain electrode 165. The insulating layer 501 is, for example, a field oxide layer formed by the local silicon oxidation method, and its fabrication process can be selectively performed concurrently with the fabrication process of the aforementioned insulating structure 200. Thus, the insulating layer 501 can be partially disposed within the substrate 110 and partially protrude from the top surface of the substrate 110, while the two independently disposed electrode structures (such as...) Figure 4 The first gate structure 580 and the second gate structure 590 shown can be selected to be fully or partially spanned on the insulating layer 501 in subsequent processes.

[0089] In detail, the first gate structure 580 and the second gate structure 590 may also include a gate dielectric layer 581, 591, a gate electrode 583, 593, and a sidewall 585, 595 surrounding the gate dielectric layer 581, 591 and the gate electrode 583, 593, respectively, stacked sequentially on the substrate 110. The first gate structure 580 is also located at the boundary between the first well region 160 and the second well region 130, while the second gate structure 590 is completely located within the first well region 160 and adjacent to the first gate structure 580. In this configuration, the gate electrodes 583, 593 of the first gate structure 580 and the second gate structure 590 can be separated from each other, with a spacing g4 of, for example, approximately 0.1 to 0.2 micrometers, preferably 0.13 to 0.16 micrometers, but not limited thereto. Preferably, the spacing g4 between the gate electrodes 583 and 593 of the first gate structure 580 and the second gate structure 590 is also located within the first well region 160 and above the insulating layer 501, as shown below. Figure 4 As shown.

[0090] It should be noted that in this embodiment, the second gate structure 590 is completely disposed across the insulating layer 501, so that the distance H51 between the gate electrode 593 and the substrate 110 (i.e., the distance between the top surface of the gate electrode 593 and the top surface of the substrate 110) is a constant value; while the first gate structure 580 is partially disposed across the insulating layer 501 and partially disposed directly on the substrate 110, so that the distance H51 between the gate electrode 583 (such as the part disposed across the insulating layer 501) and the substrate 110 is different from the distance H52 between the gate electrode 583 (such as the part directly disposed on the substrate 110) and the substrate 110. For example, the distance H51 from the top surface of the gate electrode 583 of the first gate structure 580 through the insulating layer 501 to the top surface of the substrate 110, the distance H52 from the top surface of the gate electrode 583 of the first gate structure 580 directly to the top surface of the substrate 110, and the distance H52 from the second gate structure 590 through the insulating layer 501 to the top surface of the substrate 110 can achieve two different heights of field plates, and can also enable the high voltage semiconductor device 500 to have a higher breakdown voltage.

[0091] Furthermore, you can refer to Figure 5 The diagram illustrates a cross-sectional view of the high-voltage semiconductor device 600 according to the fifth embodiment of the present invention. The structure of the high-voltage semiconductor device 600 in this embodiment is generally the same as that of the high-voltage semiconductor device 500 described in the fourth embodiment, and the similarities will not be repeated. The main difference between this embodiment and the previous embodiments is that the high-voltage semiconductor device 600 selects to directly mount the first gate structure 680 on the substrate 110, while the second gate structure 690 is partially mounted across an insulating layer 601. The insulating layer 601 in this embodiment is also a field oxide layer formed by the local silicon oxidation method, and its fabrication process can be selectively performed concurrently with the fabrication process of the aforementioned insulating structure 200.

[0092] The first gate structure 680 and the second gate structure 690 may also include a gate dielectric layer 681, 691, a gate electrode 683, 693, and a sidewall 685, 695 surrounding the gate dielectric layer 681, 691 and the gate electrode 683, 693, respectively, stacked sequentially on the substrate 110. In this embodiment, the first gate structure 680 is also disposed at the boundary between the first well region 160 and the second well region 130, while the second gate structure 690 is completely disposed within the first well region 160 and adjacent to the first gate structure 680. Under this arrangement, the gate electrodes 683, 693 of the first gate structure 680 and the second gate structure 690 may also be separated from each other, with a spacing g5 of, for example, about 0.1 to 0.2 micrometers, preferably 0.13 to 0.16 micrometers, but not limited thereto. It should be noted that in this embodiment, due to the small spacing g5, the sidewalls 685 and 695 on one side of the first gate structure 680 and the second gate structure 690 can be fused together to fill the spacing g5. Simultaneously, the gate dielectric layers 681 and 691 of the first gate structure 680 and the second gate structure 690 can also be interconnected to form a single integral structure. Figure 5 As shown. Thus, the gap g5 between the gate electrodes 683 and 693 of the first gate structure 680 and the second gate structure 690 can be located on the gate dielectric layers 681 and 691, and still within the range of the first well region 160, as... Figure 5 As shown.

[0093] Furthermore, the second gate structure 690 is partially disposed across the insulating layer 601, while another portion is directly disposed on the substrate 110. This allows the distance H61 between the gate electrode 693 of the first portion (such as the portion disposed across the insulating layer 601) and the substrate 110 to be different from the distance H62 between the gate electrode 693 of the second portion (such as the portion directly disposed on the substrate 110) and the substrate 110. For example, the distance H62 between the top surface of the gate electrode 683 of the first gate structure 680 and the top surface of the substrate 110, the distance H62 between the top surface of the gate electrode 693 of the second gate structure 690 and the top surface of the substrate 110, and the distance H61 between the second gate structure 690 through the insulating layer 601 and the top surface of the substrate 110 can achieve two different heights of field plates, which also helps to improve the breakdown voltage of the high-voltage semiconductor device 600.

[0094] Then, please refer to Figure 6The diagram shows a cross-sectional view of a high-voltage semiconductor device 700 according to the sixth embodiment of the present invention. The structure of the high-voltage semiconductor device 700 in this embodiment is generally the same as that of the high-voltage semiconductor device 400 described in the third embodiment, and the similarities will not be repeated. The main difference between this embodiment and the previous embodiments is that an insulating layer 701 is added between the source electrode 175 and the drain electrode 165 in the high-voltage semiconductor device 700, so that the second gate structure 790 can be partially disposed across the insulating layer 701. The insulating layer 701 is also a dielectric material layer, such as a silicon oxide layer, formed by the deposition process, and the various parameters of the insulating layer 701 can be adjusted according to actual product requirements. Furthermore, the high-voltage semiconductor device 700 in this embodiment may additionally include another electrode structure, such as a capacitor structure 770, disposed on the insulating layer 701 and the second gate structure 790.

[0095] In detail, the first gate structure 780 and the second gate structure 790 may also include a gate dielectric layer 781, 791, a gate electrode 783, 793, and a sidewall 785, 795 surrounding the gate dielectric layer 781, 791 and the gate electrode 783, 793, respectively, stacked sequentially on the substrate 110. The first gate structure 780 is also located at the boundary between the first well region 160 and the second well region 130, while the second gate structure 790 is completely located within the first well region 160 and adjacent to the first gate structure 780. In this configuration, the gate electrodes 783, 793 of the first gate structure 780 and the second gate structure 790 are also separated from each other, with the interval g6 located, for example, within the range of the first well region 160. Figure 6 As shown, the size is generally about 0.1 to 0.2 micrometers, preferably 0.13 to 0.16 micrometers, but not limited thereto.

[0096] In this embodiment, an insulating layer 703 is further formed above the second gate structure 790, and a portion of the insulating layer 703 covers the lower first well region 160, the insulating layer 701, and the second gate structure 790, such as... Figure 6As shown. The insulating layer 703 is, for example, a dielectric material layer formed by another deposition process, such as a silicon oxide layer, but is not limited thereto. Preferably, the process of the insulating layer 703 can be performed concurrently with the general process of the high-voltage semiconductor device 700, for example, it can be formed concurrently with a protective layer (not shown) on the partially shielding substrate 110 to prevent the formation of metal silicides, but it can also be formed by other processes. Then, a dielectric layer (MIP insulator) 771 and a conductor layer 773 are sequentially formed on the insulating layer 703, partially overlapping the underlying second gate structure 790. In one embodiment, the conductor layer 773 can provide different voltages to achieve different functions. For example, when the conductor layer 773 is electrically connected to the source 175 via an external circuit (not shown), the conductor layer 773, the dielectric layer 771, and the gate electrode 793 of the second gate structure 790 can together form a capacitor structure 770, such as a metal-insulator-polysilicon (MIP) capacitor structure stacked from polysilicon, an insulating layer, and a conductor layer. In this configuration, the breakdown voltage can be increased, and the parasitic capacitance (C) between the gate structure and the drain 165 of the high-voltage semiconductor device 700 can be reduced. gd On the other hand, when the conductor layer 773 is connected to the first gate 780 through another external circuit (not shown), the on-resistance of the semiconductor device 700 can be reduced.

[0097] Therefore, the second gate structure 790 partially disposed on the insulating layer 701 can also achieve two different heights of field plate effect. For example, it can include different field plates achieved by the distance H71 from the top surface of the gate electrode 793 of the second gate structure 790 directly to the top surface of the substrate 110 and by the distance H72 from the top surface of the gate electrode 793 of the second gate structure 790 through the insulating layer 701 to the top surface of the substrate 110. In addition, the distance H73 from the conductor layer 773 of the capacitor structure 770 through the dielectric layer 771 and the insulating layer 703 to the top surface of the substrate 110, or the distance H74 from the conductor layer 773 of the capacitor structure 770 through the dielectric layer 771, the insulating layer 703 and the insulating layer 701 to the surface of the first well region 160, can also achieve different heights of field plate effect, so that the breakdown voltage of the high voltage semiconductor device 700 of this embodiment can be further improved.

[0098] Please refer to again Figure 7The diagram shows a cross-sectional view of a high-voltage semiconductor device 800 according to the seventh embodiment of the present invention. The structure of the high-voltage semiconductor device 800 in this embodiment is generally the same as that of the high-voltage semiconductor device 300 described in the second embodiment above; the similarities will not be repeated. The main difference between this embodiment and the previous embodiments is that the high-voltage semiconductor device 800 adds an insulating layer 801 between the source electrode 175 and the drain electrode 165, and the insulating layer 801 may further include two mutually separated parts 801a and 801b, such that two independently disposed electrode structures (e.g., Figure 7 The gate structure 880 and capacitor structure 870 shown can be respectively disposed across the insulating layer 801 to achieve field plate effects at more different heights. The insulating layer 801 is also a dielectric material layer, such as a silicon monoxide layer, formed by the deposition process, and then formed into two parts 801a and 801b by a patterning process.

[0099] In detail, the gate structure 880 is located at the boundary between the first well region 160 and the second well region 130, and partially spans across the second portion 801b of the insulating layer 801. For example... Figure 7 As shown, the gate structure 880 includes a gate dielectric layer 881, a gate electrode 883, and a sidewall 885 surrounding the gate dielectric layer 881 and the gate electrode 883, which are sequentially stacked on the substrate 110. On the other hand, the capacitor structure 870 is, for example, composed of a conductor layer 873, a dielectric layer 871, and an electrode structure 883. The electrode structure 870 is completely disposed within the first well region 160 and partially overlaps the lower gate structure 880 and the second portion 801b of the insulating layer 801. Furthermore, in this embodiment, an insulating layer 803 is further formed between the capacitor structure 870 and the insulating layer 801 to partially cover the lower first well region 160 and the first portion 801a of the insulating layer 801. The insulating layer 803 is also a dielectric material layer, such as a silicon oxide layer, formed by another deposition process, and can be formed together with a protective layer (not shown) that partially shields the substrate 110 to prevent the formation of metal silicides, or formed separately.

[0100] In this embodiment, the distance H81 from the top surface of the gate electrode 883 of the gate structure 880 directly to the top surface of the substrate 110, and the distance H82 from the top surface of the gate electrode 883 of the gate structure 880 through the second part 801b of the insulating layer 801 to the top surface of the substrate 110, can achieve two heights (i.e., H81, H82) of the field plate effect. Furthermore, the distance H83 from the top surface of the conductor layer 873 of the capacitor structure 870 through the dielectric layer 871 and the second portion 801b of the insulating layer 801 to the top surface of the substrate 110, the distance H84 from the top surface of the portion of the conductor layer 873 of the capacitor structure 870 spanning the gate structure 880 through the dielectric layer 871 and the second portion 801b of the insulating layer 801 to the surface of the substrate 110, and the distance H85 from the conductor layer 873 of the capacitor structure 870 through the dielectric layer 871, the insulating layer 803 and the first portion 801a of the insulating layer 801 to the surface of the substrate 110, etc., can provide at least five field plates of different heights (i.e., H81, H82, H83, H84 and H85), effectively reducing the surface electric field (RESURF), so that the breakdown voltage of the high voltage semiconductor device 800 of this embodiment can be further improved.

[0101] Please refer to Figure 8 The diagram shows a cross-sectional view of the high-voltage semiconductor device 900 in the eighth embodiment of the present invention. The structure of the high-voltage semiconductor device 900 in this embodiment is generally the same as that of the high-voltage semiconductor device 700 described in the sixth embodiment, and the similarities will not be repeated. The main difference between this embodiment and the previous embodiments is that the high-voltage semiconductor device 900 selects to provide an insulating layer 901 between the source electrode 175 and the drain electrode 165. The insulating layer 901 may include two mutually separated parts 901a and 901b, so that three independently arranged electrode structures (such as...) Figure 8 The first gate structure 980, the second electrode structure 990, and the capacitor structure 970 shown can be respectively disposed across the two parts 901a and 901b of the insulating layer 901, providing that the conductor layer 973 can have a gradually varying height, thereby achieving more field plates of different heights to reduce the surface electric field.

[0102] In detail, the first gate structure 980 and the second gate structure 990 may also include a gate dielectric layer 981, 991, a gate electrode 983, 993, and a sidewall 985, 995 surrounding the gate dielectric layer 981, 991 and the gate electrode 983, 993, respectively, stacked sequentially on the substrate 110. The first gate structure 980 is also disposed at the boundary between the first well region 160 and the second well region 130, while the second gate structure 990 is completely disposed within the first well region 160, partially spanning the second portion 901b of the insulating layer 901 and adjacent to the first gate structure 980, such as... Figure 8As shown. In this configuration, the gate electrodes 983 and 993 of the first gate structure 980 and the second gate structure 990 are also separated from each other, and the interval g7 between them is, for example, located within the range of the first well region 160, and is generally about 0.1 to 0.2 micrometers, preferably 0.13 to 0.16 micrometers, but not limited thereto.

[0103] Furthermore, in this embodiment, an insulating layer 903 is further formed to partially cover the underlying first well region 160 and the first portion 901a of the insulating layer 901. The insulating layer 903 is also a dielectric material layer, such as a silicon oxide layer, formed through another deposition process. It can be formed together with a protective layer (not shown) that partially shields the substrate 110 to prevent the formation of metal silicides, or it can be formed separately. Then, a capacitor structure 970 is formed on the insulating layer 903, for example, composed of a conductor layer 973, a dielectric layer 971, and an electrode structure 993. The capacitor structure 970 is completely disposed within the area of ​​the first well region 160, thus completely overlapping the underlying insulating layer 903 and the first portion 901a of the insulating layer 901, and partially overlapping the second portion 901b of the insulating layer 901 and the second gate structure 990, such as... Figure 8 As shown.

[0104] In this embodiment, the distance H91 from the top surface of the gate electrode 993 of the gate structure 990 directly to the top surface of the substrate 110, and the distance H92 from the top surface of the gate electrode 993 of the gate structure 990 through the second part 901b of the insulating layer 901 to the top surface of the substrate 110, can also achieve the field plate effect at two heights (i.e., H91 and H92). Furthermore, the conductor layer 973 of the capacitor structure 970 passes through the dielectric layer 971 and the second portion 901b of the insulating layer 901 to the top surface of the substrate 110 at a distance H93; the conductor layer 973 of the capacitor structure 970 passes through the dielectric layer 971 and the insulating layer 903 to the top surface of the substrate 110 at a distance H94; the top surface of the portion of the conductor layer 973 of the capacitor structure 970 spanning the gate structure 990 passes through the dielectric layer 971 and the second portion 901b of the insulating layer 901 to the top surface of the substrate 110 at a distance H95; and the conductor layer 973 of the capacitor structure 970 passes through the dielectric layer 971, the insulating layer 903, and the first portion 901a of the insulating layer 901 to the surface of the substrate 110 at a distance H96, etc., which can provide at least six field plates of different heights (i.e., H91, H92, H93, H94, H95, and H96), effectively reducing the surface electric field and further increasing the breakdown voltage of the high-voltage semiconductor device 900 of this embodiment.

[0105] In general, the high-voltage semiconductor device of the present invention comprises two or more independently disposed electrode structures, such as gate structures or capacitor structures consisting of polysilicon, insulating layers, and conductor layers stacked sequentially. Insulating layers of varying thicknesses, positions, or coverage degrees are disposed between these electrode structures and the substrate. This allows for a variety of heights in the distance between the top surface of each electrode structure and the top surface of the substrate, or the distance through which the top surface of the electrode structure passes through different insulating layers, dielectric layers, or combinations of insulating and dielectric layers to the top surface of the substrate. This enables the high-voltage semiconductor device to achieve field plate effects at various heights, resulting in significantly higher breakdown voltages. With the configuration of the present invention, current gain can be effectively increased without increasing the lateral length of the field plate structure, thereby enabling the high-voltage semiconductor device to achieve higher breakdown voltages. Furthermore, the present invention also addresses the problem of excessively high parasitic capacitance between the gate and drain, improving the component reliability and device performance of the high-voltage semiconductor device. Therefore, the configuration of the present invention can be applied to various high-voltage semiconductor devices. Although the foregoing embodiments are described with a laterally diffused N-type metal-oxide-semiconductor transistor as the embodiment, those skilled in the art should easily understand that it can also be applied to other types of high-voltage semiconductor devices in other embodiments.

[0106] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the protection scope of the present invention.

Claims

1. A high voltage semiconductor device, characterized by, A substrate; a first well region disposed in the substrate, the first well region having a first conductivity type; a second well region disposed in the substrate adjacent to the first well region, the second well region having a second conductivity type, the second conductivity type being complementary to the first conductivity type; a first insulating layer disposed on the first well region; a source disposed in the second well region; a drain disposed in the first well region; and a first electrode structure and a second electrode structure disposed on the substrate, wherein the first electrode structure and the second electrode structure each comprise a gate dielectric layer and a gate electrode stacked from bottom to top, the gate dielectric layer of the first electrode structure directly contacting a top surface of the first insulating layer and a top surface of the substrate, a distance between a top surface of the electrode of the first electrode structure to the top surface of the substrate having a first height and a second height which are different, and wherein at least one of the first electrode structure and the second electrode structure is a gate structure, and the first electrode structure and the second electrode structure partially overlap or sidewalls between the first electrode structure and the second electrode structure directly contact or merge into one. The first electrode structure covers a portion of the first insulating layer and is located at an interface between the first well region and the second well region, and the second electrode structure is located on the first well region. The first electrode structure covers a portion of the first insulating layer and is located at an interface between the first well region and the second well region, and the second electrode structure is located on the first well region.

2. The high voltage semiconductor device of claim 1, wherein The second electrode structure includes a capacitor structure, the capacitor structure including the gate electrode of the first electrode structure, a dielectric layer, and a conductor layer stacked in sequence.

3. The high voltage semiconductor device of claim 1, wherein The first electrode structure and the second electrode structure share the gate electrode.

4. The high voltage semiconductor device of claim 1, wherein A distance between a top surface of the electrode of the second electrode structure to the top surface of the substrate includes a third height, a fourth height, and a fifth height, wherein the first height, the second height, the third height, the fourth height, and the fifth height are all different.

5. The high voltage semiconductor device of claim 4, wherein The second electrode structure is disposed at an interface between the first well region and the second well region.

6. The high voltage semiconductor device of claim 4, wherein The second well region is disposed in the substrate adjacent to and surrounding the first well region.

7. The high voltage semiconductor device of claim 3, wherein The first insulating layer includes a first portion and a second portion separated from each other.

8. The high voltage semiconductor device of claim 1, wherein, Further comprising:

9. The high voltage semiconductor device of claim 1, wherein, a second insulating layer disposed on the first insulating layer, the second electrode structure being partially disposed on the second insulating layer.

10. The high voltage semiconductor device of claim 1, wherein, Further comprising: a third electrode structure disposed separately from the first electrode structure, wherein the second electrode structure and the third electrode structure each comprise a gate structure and a capacitor structure, respectively.

11. The high voltage semiconductor device of claim 10, wherein ​ ​

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