Display devices

Abstract

This application relates to a display device. The display device includes pixels and first gate lines, second gate lines, and third gate lines connected to the pixels, as well as data lines. At least one of the pixels includes: a light-emitting element; a first transistor connected between a first power supply and the light-emitting element for driving the light-emitting element according to a voltage of a first node; a second transistor connected between the first node and a corresponding data line in the data lines, and driven according to a voltage of a corresponding first gate line in the first gate lines; a capacitor connected between a first node and a second node, the second node being between the first transistor and the light-emitting element; a third transistor between the second node and an initialization power supply line, and driven according to a voltage of a corresponding second gate line in the second gate lines; and a fourth transistor connected between the first node and the second node, and driven according to a voltage of a corresponding third gate line in the third gate lines.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0147159, filed on November 5, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to display devices. Background Technology

[0004] Recently, there has been a growing interest in information display. Therefore, research and development of display devices are ongoing. Summary of the Invention

[0005] This disclosure provides a display device capable of reducing or preventing residual images.

[0006] The aspects of this disclosure are not limited to those described above, and other aspects not mentioned herein will be clearly understood by those skilled in the art from the following description.

[0007] A display device according to some embodiments of the present disclosure includes a pixel, a first gate line, a second gate line, and a third gate line connected to the pixel, and a data line connected to the pixel, wherein at least one of the pixels includes: a light-emitting element connected between a first power supply and a second power supply; a first transistor connected between the first power supply and the light-emitting element for driving the light-emitting element according to a voltage of a first node; a second transistor connected between the first node and a corresponding data line in the data line, and configured to be driven according to a voltage of a corresponding first gate line in the first gate line; a capacitor connected between the first node and the second node, the second node being between the first transistor and the light-emitting element; a third transistor connected between the second node and an initialization power line, and configured to be driven according to a voltage of a corresponding second gate line in the second gate line; and a fourth transistor connected between the first node and the second node, and configured to be driven according to a voltage of a corresponding third gate line in the third gate line.

[0008] The fourth transistor can be directly connected between the first and second electrodes of the capacitor and is configured to connect the first and second electrodes of the capacitor during the period when the third gate signal is provided to the corresponding third gate line.

[0009] The display device may further include a gate driver for providing a first gate signal, a second gate signal, and a third gate signal to a first gate line, a second gate line, and a third gate line, respectively, wherein pixels are arranged on horizontal lines, wherein the first gate line, the second gate line, and the third gate line are arranged on each horizontal line and connected to the pixels of each horizontal line, and wherein the gate driver is configured to provide the first gate signal and the second gate signal in parallel to the respective first gate line and the second gate line of the horizontal line for each horizontal time period constituting a frame time period.

[0010] The gate driver can be configured to sequentially provide a first gate signal and a second gate signal to respective first and second gate lines of a horizontal line, one line at a time, during a frame period.

[0011] The gate driver can be configured to provide the corresponding third gate signal in the third gate signal to the corresponding third gate line during a frame period, for one of the horizontal lines, after a period of time has elapsed since the corresponding first gate signal in the first gate signal and the corresponding second gate signal in the second gate signal were provided to the corresponding first gate line and the corresponding second gate line.

[0012] The gate driver can be configured to sequentially provide a third gate signal to a third gate line of a horizontal line in units of at least one of the horizontal lines during a frame period.

[0013] The gate driver may include: a first gate driver for providing a first gate signal and a second gate signal to a first gate line and a second gate line of the horizontal line; and a second gate driver for providing a third gate signal to a third gate line of the horizontal line.

[0014] The display device may also include a data driver for providing a data signal to a data line corresponding to a pixel of a single line in the horizontal time segment.

[0015] A display device according to some embodiments of the present disclosure includes a pixel, a first gate line, a second gate line, and a third gate line connected to the pixel, and a data line connected to the pixel, wherein at least one of the pixels includes: a light-emitting element connected between a first power supply and a second power supply; a first transistor connected between the first power supply and the light-emitting element for driving the light-emitting element according to a voltage of a first node; a second transistor connected between the first node and a corresponding data line in the data line, and configured to be driven according to a voltage of a corresponding first gate line in the first gate line; a capacitor connected between the first node and the second node, the second node being between the first transistor and the light-emitting element; a third transistor connected between the second node and an initialization power line, and configured to be driven according to a voltage of a corresponding second gate line in the second gate line; and a fourth transistor connected between the first node and a bias power line separate from the initialization power line, and configured to be driven according to a voltage of a corresponding third gate line in the third gate line.

[0016] The fourth transistor can be directly connected between the first node and the bias power supply line, and is configured to transmit the voltage of the bias power supply to the first node during the period when the third gate signal is provided to the corresponding third gate line.

[0017] The bias power supply voltage can be configured to be set to the cutoff voltage of the first transistor or to be set to a low gray level voltage that is less than or equal to the reference gray level.

[0018] The display device may further include a gate driver for providing a first gate signal, a second gate signal, and a third gate signal to a first gate line, a second gate line, and a third gate line, respectively, wherein pixels are arranged on horizontal lines, wherein the first gate line, the second gate line, and the third gate line are arranged on each horizontal line and connected to the pixels of each horizontal line, and wherein the gate driver is configured to provide the first gate signal and the second gate signal in parallel to the respective first gate line and the second gate line of the horizontal line for each horizontal time period constituting a frame time period.

[0019] The gate driver can be configured to sequentially provide a first gate signal and a second gate signal to respective first and second gate lines of a horizontal line, one line at a time, during a frame period.

[0020] The gate driver can be configured to provide the corresponding third gate signal in the third gate signal to the corresponding third gate line during a frame period, for one of the horizontal lines, after a period of time has elapsed since the corresponding first gate signal in the first gate signal and the corresponding second gate signal in the second gate signal were provided to the corresponding first gate line and the corresponding second gate line.

[0021] The gate driver can be configured to sequentially provide a third gate signal to a third gate line of a horizontal line in units of at least one of the horizontal lines during a frame period.

[0022] The gate driver may include a first gate driver for providing a first gate signal and a second gate signal to a first gate line and a second gate line; and a second gate driver for providing a third gate signal to a third gate line.

[0023] The display device may also include a data driver for providing a data signal to a data line corresponding to a pixel of a single line in the horizontal time segment.

[0024] Details of other embodiments are included in the detailed description and accompanying drawings. Attached Figure Description

[0025] Figure 1 A display device according to some embodiments of the present disclosure is shown.

[0026] Figure 2 A display device according to some embodiments of the present disclosure is shown.

[0027] Figure 3 The driving time period of a display device according to some embodiments of the present disclosure is shown.

[0028] Figure 4 The display period of a display device according to some embodiments of the present disclosure is shown.

[0029] Figure 5 Pixels are shown according to some embodiments of this disclosure.

[0030] Figure 6 The driving timing of pixels according to some embodiments of this disclosure is shown.

[0031] Figures 7 to 9 The following are shown in sequence according to Figure 5 and Figure 6 The method for driving pixels in the implementation of the above method.

[0032] Figure 10 Pixels are shown according to some embodiments of this disclosure.

[0033] Figure 11 Methods for driving pixels according to some embodiments of the present disclosure are shown.

[0034] Figure 12 The bias voltage and drive voltage of a first transistor according to some embodiments of the present disclosure are shown. Detailed Implementation

[0035] Some aspects of this disclosure and its implementation methods can be more readily understood by referring to the detailed description and accompanying drawings of the embodiments. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments may be implemented in various different forms and should not be construed as limited to the embodiments shown herein. These embodiments are provided precisely as examples so that this disclosure will be thorough and complete, and will fully convey aspects of this disclosure to those skilled in the art. Therefore, processes, elements, and techniques not essential for a full understanding of aspects of this disclosure by those skilled in the art are not described.

[0036] Unless otherwise stated, throughout the accompanying drawings and the written specification, the same reference numerals, symbols, or combinations thereof denote the same elements, and therefore, their description will not be repeated. Furthermore, for clarity, parts unrelated to the description of the embodiments may not be shown.

[0037] In the accompanying drawings, the relative dimensions of elements, layers, and regions may be exaggerated for clarity. Furthermore, the use of crosshairs and / or shading in the drawings is generally used to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, scale, commonalities between the elements shown, and / or any other characteristics, properties, or characteristics of the elements.

[0038] Therefore, the areas shown in the accompanying drawings are schematic in nature, and their shapes are not intended to represent the actual shape of the areas of the device, nor are they intended to be limiting. Furthermore, as those skilled in the art will recognize, the described embodiments can be modified in various different ways without departing entirely from the spirit or scope of this disclosure.

[0039] In the detailed description, numerous specific details are set forth for illustrative purposes to provide a thorough understanding of the various embodiments. However, it will be apparent that the embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the embodiments.

[0040] It will be understood that when a component, layer, region, or assembly is referred to as "formed on," "on," "connected to," or "linked to" another component, layer, region, or assembly, it can be directly formed on, directly on, directly connected to, or linked to another component, layer, region, or assembly, or indirectly formed on, indirectly on, indirectly connected to, or linked to another component, layer, region, or assembly, such that one or more intermediary components, layers, regions, or assemblies may exist. For example, when a layer, region, or assembly is referred to as "electrically connected" or "electrically linked" to another layer, region, or assembly, it can be directly electrically connected or electrically linked to other layers, regions, and / or assemblies, or an intermediary layer, region, or assembly may exist. However, "direct connection / direct link" refers to a component being directly connected or linked to another component without any intermediate components. Similarly, other expressions describing relationships between components (such as "between," "directly between," or "adjacent to" and "directly adjacent to") can be interpreted in a similar way. Furthermore, it will be understood that when an element or layer is referred to as "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there can be one or more intervening elements or layers.

[0041] For the purposes of this disclosure, when following a list of elements, expressions such as “at least one of…” modify the entire list of elements, not individual elements within the list. For example, “at least one of X, Y, and Z,” “at least one of X, Y, or Z,” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted as any combination of two or more of X, Y, Z (e.g., XYZ, XYY, YZ, and ZZ, or any variations thereof). Similarly, expressions such as “at least one of A and B” can include A, B, or A and B. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. For example, expressions such as “A and / or B” can include A, B, or A and B.

[0042] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the spirit and scope of this disclosure, the first element, component, region, layer, or part described below may be referred to as the second element, component, region, layer, or part. Describing an element as a “first” element may not require or indicate the presence of a second element or other elements. The terms “first,” “second,” etc., may also be used herein to distinguish elements of different categories or groups. For the sake of brevity, the terms “first,” “second,” etc., may respectively represent “first category (or first group),” “second category (or second group),” etc.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. Unless the context clearly indicates otherwise, the singular forms “a” and “an” are intended to include the plural forms as used herein. It will also be understood that, when used in this specification, the terms “comprises,” “comprising,” “have,” “having,” “includes,” and “including” specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0044] As used herein, the terms “approximately,” “about,” “approximately,” and similar terms are used as terms of approximation, not as terms of degree, and are intended to explain the inherent biases in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, “about” or “approximately” includes the value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations or within ±30%, ±20%, ±10%, ±5% of the value. Furthermore, the word “may” as used in describing embodiments of this disclosure means “one or more embodiments of this disclosure.”

[0045] When one or more implementation methods can be carried out differently, the specific process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of their description.

[0046] Electronic or electrical devices and / or any other related devices or components according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, components of these devices may be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, components of these devices may be implemented on a flexible printed circuit film, a tape-on package (TCP), a printed circuit board (PCB), or formed on a substrate.

[0047] Furthermore, the components of these devices may be processes or threads that run on one or more processors in one or more computing devices, execute computer program instructions, and interact with other system components for performing the various functions described herein. The computer program instructions are stored in memory, which may be implemented in the computing device using standard memory devices such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Moreover, those skilled in the art will recognize that, without departing from the spirit and scope of the embodiments of this disclosure, the functions of various computing devices may be combined or integrated into a single computing device, or the functions of a particular computing device may be distributed across one or more other computing devices.

[0048] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and / or in this specification, and shall not be interpreted in an idealized or overly formal sense.

[0049] Figure 1 and Figure 2 Display devices 100 according to some embodiments of the present disclosure are shown respectively. Figure 1 compared to, Figure 2 Other embodiments of the gate driver 120 are shown.

[0050] refer to Figure 1 and Figure 2 According to some embodiments of the present disclosure, a display device 100 includes a display area 110 (or a display panel including the display area 110) in which pixels PX are arranged, and a gate driver 120, a data driver 130 and a controller 140 for driving the pixels PX.

[0051] Display area 110 includes pixels PX arranged on multiple horizontal lines HL[1] to HL[n] (where n is a natural number greater than or equal to 2). Furthermore, display area 110 includes first gate lines GL1[1] to GL1[n], second gate lines GL2[1] to GL2[n], and third gate lines GL3[1] to GL3[n] formed for each of the horizontal lines HL[1] to HL[n], and data lines DL[1] to DL[m] formed for each vertical line (where m is a natural number greater than or equal to 2). For example, the j-th first gate line GL1[j], the j-th second gate line GL2[j], and the j-th third gate line GL3[j] can be located on the j-th horizontal line (where j is a natural number greater than 0), and the k-th data line DL[k] can be located on the k-th vertical line (where k is a natural number greater than 0).

[0052] For convenience, in describing the following embodiments, at least one first gate line is arbitrarily or generally referred to as "(multiple) first gate lines GL1", at least one second gate line is arbitrarily or generally referred to as "(multiple) second gate lines GL2", and at least one third gate line is arbitrarily or generally referred to as "(multiple) third gate lines GL3". Similarly, at least one data line is arbitrarily or generally referred to as "(multiple) data lines DL". In addition, at least one horizontal line is arbitrarily referred to as "(multiple) horizontal lines HL".

[0053] Pixel PX can be connected to a first gate line GL1, a second gate line GL2, and a third gate line GL3 disposed on each horizontal line HL, and to a data line DL disposed on each vertical line. For example, a pixel PX located on the j-th horizontal line HL[j] and the k-th vertical line can be connected to the j-th first gate line GL1[j], the j-th second gate line GL2[j], the j-th third gate line GL3[j], and the k-th data line DL[k]. In describing embodiments of this disclosure, the term "connection (or linkage)" can generally mean physical connection (or linkage) and / or electrical connection (or linkage). Furthermore, the term "connection (or linkage)" can generally mean direct or indirect connection (or linkage) and integrated or non-integrated connection (or linkage).

[0054] Pixel PX receives a first gate signal, a second gate signal, and a third gate signal from a first gate line GL1, a second gate line GL2, and a third gate line GL3, respectively. The first gate signal, the second gate signal, and the third gate signal can be control signals used to control the operating timing of pixel PX, and can also be scan signals used to control the timing of the data signals provided to pixel PX for each horizontal line HL.

[0055] For example, the first gate signal can be a scan signal used to select (e.g., sequentially select) pixels PX on a horizontal line HL to provide a data signal to the pixels PX of each horizontal line HL. In this case, the first gate line GL1 can be a scan line for each horizontal line HL.

[0056] The second gate signal can be an initialization control signal for providing an initial power supply voltage to the pixel PX of each horizontal line HL during the display period of driving the pixel PX. Furthermore, in some embodiments, the second gate signal can also be used as a sensing control signal for connecting the pixel PX of each horizontal line HL to a sensing unit during a sensing period (e.g., a predetermined sensing period) to extract feature information of the pixel PX.

[0057] The third gate signal may be a non-emission control signal for driving each horizontal line HL at a low gray level (e.g., a predetermined reference gray level) during the display period of the driving pixel PX, or for controlling the pixel PX of each horizontal line HL not to emit light.

[0058] Pixel PX receives data signals for each frame from each data line DL. During the display period when the display device 100 displays an image through pixel PX, the emission brightness of pixel PX can be controlled during each frame period using the data signals for each frame.

[0059] Furthermore, the pixel PX can be connected to at least one driving power supply. For example, the pixel PX can be connected to a first power supply VDD as a high-potential pixel power supply and a second power supply VSS as a low-potential pixel power supply. Additionally, the pixel PX can be connected to at least one other driving power supply. For example, the pixel PX can also be connected to an initialization power supply and / or a bias power supply.

[0060] During the display period, pixel PX receives a first gate signal and a second gate signal from the first gate line GL1 and the second gate line GL2 for each frame period to display an image corresponding to the input data. Furthermore, during the period when the first and second gate signals are provided, pixel PX receives a data signal corresponding to the input data for each frame from the data line DL, and emits light with a brightness corresponding to the data signal to display the image for each frame.

[0061] Furthermore, pixel PX can receive a third gate signal from third gate line GL3 during each frame period. In response to the third gate signal provided to the third gate line GL3 of the horizontal line HL, pixel PX of each horizontal line HL may not emit light or may be driven at a low gray level (e.g., a predetermined reference gray level). For example, pixel PX may display a black image or a dim image with a gray level (e.g., a predetermined gray level) via the third gate signal.

[0062] In some implementations, the first gate line GL1 and the second gate line GL2 can be driven sequentially in units of horizontal lines HL. The third gate line GL3 can also be driven sequentially in units of horizontal lines HL. In this case, after first driving the first gate line GL1 and the second gate line GL2 for each horizontal line HL, the third gate line GL3 can be driven after a certain period of time (e.g., a predetermined time). Driving the first gate line GL1, the second gate line GL2, and the third gate line GL3 can mean that a first gate signal, a second gate signal, and a third gate signal are respectively provided to the first gate line GL1, the second gate line GL2, and the third gate line GL3. Furthermore, each of the first gate signal, the second gate signal, and the third gate signal can refer to a signal or pulse having a gate on-voltage.

[0063] For example, during each frame period, pixel PX can store the data signal of the corresponding frame through the first gate signal and the second gate signal, can emit light with a brightness corresponding to the data signal during a period of time (e.g., a predetermined period of time), and can sequentially switch to a non-emission state in units of horizontal lines HL. Simultaneously, when pixel PX receives a data signal corresponding to a black grayscale level (e.g., the grayscale level (0 grayscale) of black data included in the first image data DATA1 or the second image data DATA2) during the corresponding frame period, the first transistor M1 (see...) Figure 5 The data signal is cut off, and the pixel PX remains largely non-emitting during the emission period of the corresponding frame time, thus presenting a black grayscale level.

[0064] In some embodiments, pixels PX may be self-emissive pixels, each including at least one light-emitting element, but this disclosure is not limited thereto. For example, the type, structure, and / or driving method of pixels PX may vary depending on the implementation. The structure and driving method of pixels PX will be described in detail later.

[0065] Gate driver 120 receives a gate control signal GCS from controller 140 and, in response to the gate control signal GCS, provides a first gate signal, a second gate signal, and a third gate signal to first gate line GL1, second gate line GL2, and third gate line GL3. For example, gate driver 120 may receive a gate control signal GCS that includes a start signal (e.g., a first sampling pulse input to a first shift register for generating the first gate signal, a second sampling pulse input to a second shift register for generating the second gate signal, and a third sampling pulse input to a third shift register for generating the third gate signal) and a clock signal (e.g., a clock signal for controlling the operation timing of the first shift register, second shift register, and third shift register) for controlling the timing of the first gate signal, second gate signal, and third shift register, and may provide the first gate signal, second gate signal, and third gate signal to first gate line GL1, second gate line GL2, and third gate line GL3 in response to the gate control signal GCS.

[0066] In some embodiments, the gate driver 120 may provide a first gate signal and a second gate signal simultaneously or substantially simultaneously (e.g., in parallel) to a first gate line GL1 and a second gate line GL2 corresponding to a horizontal line HL for each horizontal period constituting a frame period, or may provide the first gate signal and the second gate signal sequentially to the first gate line GL1 and the second gate line GL2 arranged in the display area 110 in units of a horizontal line HL during a frame period.

[0067] Furthermore, during a frame period, after the first gate signal and the second gate signal are provided to the first gate line GL1 and the second gate line GL2 of each horizontal line HL, the gate driver 120 may provide a third gate signal to the third gate line GL3 of the horizontal line HL at a point in time after a certain period (e.g., a predetermined time), and may provide the third gate signal sequentially to the third gate line GL3 arranged in the display area 110 on a per-horizontal-line-HL (or a group of horizontal lines including at least two horizontal lines HL) during a frame period. For example, during each frame period, after the first gate signal and the second gate signal are provided simultaneously or substantially simultaneously to the first gate line GL1 and the second gate line GL2 of each horizontal line HL, the third gate signal may be provided to the third gate line GL3.

[0068] In some embodiments, the gate driver 120 may include a first shift register for driving a first gate line GL1, a second shift register for driving a second gate line GL2, and a third shift register for driving a third gate line GL3. For example, when the first gate line GL1 and the second gate line GL2 can be driven in different timing sequences or simultaneously or substantially simultaneously depending on the operating mode of the display device 100, the first shift register for driving the first gate line GL1 and the second shift register for driving the second gate line GL2 can be configured independently and driven by their respective gate control signals GCS. For example, when the second gate line GL2 is used in a sensing operation that senses feature information of a pixel PX, the first shift register and the second shift register can be configured independently.

[0069] In other embodiments, a first shift register for driving the first gate line GL1 and a second shift register for driving the second gate line GL2 can be integrated into a single shift register. For example, when the first gate line GL1 and the second gate line GL2 are driven simultaneously or substantially simultaneously regardless of the operating mode of the display device 100, the first gate line GL1 and the second gate line GL2 of each horizontal line HL can be connected integrally or non-integrally, and can be driven simultaneously or substantially simultaneously through a single shift register.

[0070] The configuration of the gate driver 120 can vary depending on the implementation. For example, the gate driver 120 can be integrated into a single drive circuit or it can be divided into multiple drive circuits.

[0071] In some implementations, such as Figure 1 As shown, the first shift register, the second shift register, and the third shift register used to drive the first gate line GL1, the second gate line GL2, and the third gate line GL3 can be integrated into a single gate driver 120.

[0072] In other embodiments, such as Figure 2As shown, the gate driver 120 can be divided into a first gate driver 120A and a second gate driver 120B, and each of the first gate driver 120A and the second gate driver 120B may include at least one shift register. As an example, the first gate driver 120A may include a first shift register and a second shift register for driving the first gate line GL1 and the second gate line GL2, and the second gate driver 120B may include a third shift register for driving the third gate line GL3. In this case, the first gate driver 120A and the second gate driver 120B may be provided with a first gate control signal GCS1 and a second gate control signal GCS2 from the controller 140, and driven by the first gate control signal GCS1 and the second gate control signal GCS2 from the controller 140.

[0073] Data driver 130 receives a data control signal DCS and second image data DATA2 from controller 140, and generates a data signal in response to the data control signal DCS and the second image data DATA2. For example, data driver 130 may receive the second image data DATA2 and the data control signal DCS, which includes a source sampling pulse, a source sampling clock, and / or a source output enable signal, and may generate a data signal corresponding to the second image data DATA2. In some embodiments, the data signal may be generated in the form of a data voltage corresponding to the brightness to be displayed by pixel PX, but this disclosure is not limited thereto.

[0074] The data driver 130 can provide data signals to the pixel PX via the data line DL. For example, the data driver 130 can provide a data signal to the data line DL corresponding to the pixel PX of the horizontal line HL corresponding to each horizontal time segment constituting a frame time segment. The data signal provided to the data line DL is provided to the pixel PX of the horizontal line HL selected by the first gate signal.

[0075] The controller 140 receives a control signal CON and first image data DATA1 from an external source (e.g., a main processor), and can drive the gate driver 120 and the data driver 130 in response to the control signal CON and the first image data DATA1.

[0076] For example, controller 140 may receive a control signal CON including a vertical synchronization signal, a horizontal synchronization signal, and / or a master clock signal, and may generate a gate control signal GCS and a data control signal DCS in response to the control signal CON. The gate control signal GCS may be provided to gate driver 120, and the data control signal DCS may be provided to data driver 130.

[0077] In addition, the controller 140 receives first image data DATA1 (e.g., input image data) from an external source (e.g., from the main processor) and can generate second image data DATA2 by converting and / or rearranging the first image data DATA1 according to the specifications of the display device 100.

[0078] The second image data DATA2 is provided to the data driver 130 and used to generate a data signal. Therefore, an image corresponding to the second image data DATA2 can be displayed in the display area 110.

[0079] In some embodiments, the display device 100 may further include a sensing unit for sensing feature information of pixel PX during a sensing period (e.g., a predetermined sensing period), and may store compensation values ​​to compensate for feature deviations of pixel PX sensed by the sensing unit. In this case, the controller 140 can convert first image data DATA1 into second image data DATA2 by applying the compensation values. Therefore, the feature deviations of pixel PX are compensated, and thus an image of consistent quality can be displayed in the display area 110.

[0080] Figure 3 The driving time periods of a display device 100 according to some embodiments of the present disclosure are shown.

[0081] refer to Figures 1 to 3 According to some embodiments of the present disclosure, the driving period of the display device 100 includes a first non-display period NDP1, a second non-display period NDP2, and a display period DP. The display period DP is the period during which pixels PX are driven in response to input image data (e.g., first image data DATA1), and may include at least one frame period DF. The first non-display period NDP1 and the second non-display period NDP2 may include periods in the driving period of the display device 100 other than the display period DP.

[0082] The first non-display period NDP1 can be the period during which the display device 100 is prepared to drive. As an example, the first non-display period NDP1 can be a period of tens to hundreds of frames starting from the time point of the power-on command Pon input to the display device 100.

[0083] The second non-display period NDP2 can be the period when the drive of the display device 100 ends. As an example, the second non-display period NDP2 can be a period of tens to hundreds of frames starting from the time point of the power-off command Poff input to the display device 100.

[0084] In some implementations, the sensing operation for sensing feature information of pixel PX can be performed during a first non-display period NDP1 and / or a second non-display period NDP2. The sensed feature information can be used to transform input image data (e.g., first image data DATA1) to compensate for feature deviations of pixel PX during the display period DP.

[0085] However, this disclosure is not limited thereto. For example, in other embodiments, feature information of pixel PX can be sensed in real time during the display period DP, and the feature information of pixel PX can be used to transform input image data.

[0086] Display time period DP is a time period that drives pixels PX according to the input image data of each frame, and can be a time period in display area 110 that displays the image corresponding to the input image data. Display time period DP can include frame time period DF (also called "display frame time period") for displaying the image of each frame and vertical blank time period VB located between frame time periods DF. For example, a vertical blank time period VB can begin whenever a frame time period DF ends. For example, each vertical blank time period VB can begin after the data input time period of each frame time period DF ends.

[0087] Figure 4 The display period DP of a display device 100 according to some embodiments of the present disclosure is shown. For convenience, Figure 4 Each frame time period DF is shown in the display time period DP based on the first horizontal line HL[1].

[0088] refer to Figures 1 to 4 Each frame time period DF may include a data input time period Tw, a transmission time period Te, a data reset time period Tr, and a non-transmission time period Tb (also referred to as a "black frame time period" or "black interpolation time period"). In addition, each frame time period DF may start sequentially from the first horizontal line HL[1] to the nth horizontal line HL[n] (e.g., the last horizontal line) of the display area 110.

[0089] For example, a frame period 1F may include multiple horizontal periods corresponding to the first horizontal line HL[1] to the nth horizontal line HL[n], and the pixel PX of the corresponding horizontal line HL can be selected by the first gate signal during each horizontal period. In this way, the pixel PX of the first horizontal line HL[1] to the nth horizontal line HL[n] can be selected sequentially to receive the data signal of each frame, and can emit light with a brightness corresponding to the data signal in sequence. In addition, during a frame period 1F, when the first horizontal line HL[1] to the nth horizontal line HL[n] are selected sequentially at the time point when the pixel PX of each horizontal line HL emits light during a specific period, the voltage of the cutoff voltage or bias power supply (e.g., a predetermined bias power supply) can be sequentially input to the pixel PX of each horizontal line HL (e.g., the gate node of the driving transistor in the pixel PX). When the voltage of the cutoff voltage or bias power supply is transmitted to the pixel PX, the pixel PX may not emit light, or may be driven at a low gray level less than or equal to the reference gray level (e.g., a predetermined reference gray level).

[0090] Therefore, pixel PX can display an image corresponding to the data signal during the emission period (e.g., a predetermined emission period) Te in a frame time period 1F, and may not emit light or may emit light with a low gray level less than or equal to the reference gray level during the non-emission period Tb following the emission period Te. The non-emission period Tb of pixel PX can be maintained until the data signal of the next frame is provided.

[0091] Thus, during each frame period DF, after displaying the image corresponding to the data signal, the image is erased by either preventing pixel PX from emitting light or by making pixel PX emit light in a minute manner, thereby reducing or preventing residual images from appearing in the display area 110. For example, even when the display device 100 displays video at high speed, motion blur can be effectively prevented or reduced by performing an erasure operation after each transmission period Te.

[0092] Furthermore, when performing an erasure operation by sequentially preventing pixel PX from emitting light (or emitting only a small amount of light) on a per-horizontal-line-HL basis, a data reset period Tr and / or a non-emission period Tb can be performed on at least one other horizontal-line-HL during the data input period Tw and / or emission period Te of at least one horizontal-line-HL. In this case, pixel PX can sequentially emit light without applying the simultaneous light emission method of pixels PX arranged in the display area 110. Therefore, the load on the display panel can be distributed, and the rapid increase in instantaneous current of the display panel can be slowed down or prevented.

[0093] Furthermore, in some embodiments of this disclosure, the third gate signal is provided to the pixel PX separately from the first gate signal and the second gate signal, and the data reset period Tr and non-emission period Tb of the pixel PX located on each horizontal line HL are controlled by the third gate signal. Therefore, regardless of the data input period Tw of the pixel PX located on each horizontal line HL, the pixel PX can be turned off (e.g., it can not emit light) or driven at a low grayscale level at a desired time point. Thus, the image quality of the display device 100 can be improved by reducing or preventing residual images while sufficiently guaranteeing the data input period Tw and the emission period Tb. Furthermore, the ratio of the data reset period Tr to the non-emission period Tb of each horizontal line HL can be freely adjusted by the third gate signal.

[0094] Simultaneously, each vertical blank period VB may not overlap with the data input period Tw of the horizontal lines HL. For example, the vertical blank period VB may begin after the data input periods Tw of all horizontal lines HL have ended during each frame period DF. In some embodiments, for at least some horizontal lines HL, each vertical blank period VB may overlap with the transmit period Te, the data reset period Tr, and / or the non-transmit period Tb, but this disclosure is not limited thereto.

[0095] Figure 5 Pixels PX according to some embodiments of this disclosure are shown. For example, Figure 5 It shows that it can be located in Figure 1 and Figure 2 Examples of pixels PX in display area 110, and pixels PX in display area 110 may have substantially the same or similar structure.

[0096] refer to Figures 1 to 5 According to some embodiments of the present disclosure, a pixel PX includes a light-emitting element LD and a pixel circuit PXC for driving the light-emitting element LD.

[0097] The light-emitting element (LD) is connected between a first power supply VDD and a second power supply VSS. For example, one electrode of the LD (e.g., the anode electrode) can be connected to the first power supply VDD via the pixel circuit PXC and the first power supply line PL1, and the other electrode of the LD (e.g., the cathode electrode) can be connected to the second power supply VSS via the second power supply line PL2.

[0098] The first power supply VDD and the second power supply VSS can have different voltages (or potentials) so that the light-emitting element LD can emit light. As an example, the first power supply VDD can be a high-potential pixel power supply, and the second power supply VSS can be a low-potential pixel power supply with a voltage lower than the threshold voltage of the light-emitting element LD than the potential of the first power supply VDD.

[0099] When a drive current is supplied from the pixel circuit PXC, the light-emitting element LD generates light with a brightness corresponding to the drive current. Therefore, each pixel PX can emit light with a brightness corresponding to the data signal DS during each frame time period DF. Simultaneously, when a pixel PX receives the data signal DS corresponding to a black grayscale level (e.g., 0 grayscale) during frame time period DF, the first transistor M1 is turned off to prevent the generation of a drive current. Therefore, the pixel PX can remain in a non-emitting state during frame time period DF.

[0100] In some embodiments, the light-emitting element LD can be a light-emitting diode including an organic or inorganic light-emitting layer. For example, the light-emitting element LD can be an organic light-emitting diode, an inorganic light-emitting diode, a quantum dot / well light-emitting diode, etc., but this disclosure is not limited thereto.

[0101] Furthermore, despite Figure 5 Some embodiments of a pixel PX including a light-emitting element LD are shown, but this disclosure is not limited thereto. For example, a pixel PX may include multiple light-emitting elements LD connected in series, in parallel, or in a series-parallel connection.

[0102] That is, in this disclosure, the type, structure, shape, size, quantity and / or connection structure of the light-emitting elements (LD) are not particularly limited, and these can be varied depending on the implementation.

[0103] The pixel circuit PXC can be connected between the first power supply VDD and the light-emitting element LD. Furthermore, the pixel circuit PXC can also be connected to the first gate line GL1, the second gate line GL2, and the third gate line GL3 of the pixel PX, the data line DL, and the initialization power line INL. The first gate signal SC, the second gate signal SS, and the third gate signal BI provided from the first gate line GL1, the second gate line GL2, and the third gate line GL3 can control the driving timing of the pixel PX, and the data signal DS provided from the data line DL can control the emission brightness of the pixel PX. The voltage of the initialization power supply VINIT is provided to the initialization power line INL. In some embodiments, the second gate line GL2 and the initialization power line INL can also be used as a sensing control line and a sensing line for sensing feature information of the pixel PX, respectively, but this disclosure is not limited thereto.

[0104] The pixel circuit PXC may include a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a capacitor Cst.

[0105] A first transistor M1 is connected between a first power supply VDD and a light-emitting element LD, and the gate electrode of the first transistor M1 is connected to a first node N1. The first transistor M1 drives the light-emitting element LD by controlling the drive current supplied to the light-emitting element LD according to the voltage of the first node N1. That is, the first transistor M1 can be a drive transistor for controlling the drive current of pixel PX according to the voltage of the first node N1.

[0106] A second transistor M2 is connected between the data line DL and the first node N1, and the gate electrode of the second transistor M2 is connected to the first gate line GL1. The second transistor M2 can be driven according to the voltage of the first gate line GL1. For example, when a first gate signal SC with a gate turn-on voltage (e.g., a high-level scan signal) is provided to the first gate line GL1, the second transistor M2 turns on to electrically connect the data line DL to the first node N1.

[0107] During each frame time period DF (e.g., each horizontal time period), the frame data signal DS is provided to the data line DL, and during the time period when the first gate signal SC is provided, the data signal DS is transmitted to the first node N1 through the turned-on second transistor M2. That is, the second transistor M2 may be a switching transistor used to transmit the data signal DS of each frame to the inside of the pixel PX.

[0108] A capacitor Cst is connected between a first node N1 and a second node N2, and is charged with a voltage corresponding to the voltage difference between the first node N1 and the second node N2. The first node N1 can be a gate node connected to the gate electrode of the first transistor M1, and the second node N2 can be a node between the first transistor M1 and the light-emitting element LD. That is, the capacitor Cst can be a storage capacitor connected between one electrode (e.g., the source electrode) of the first transistor M1 and the gate electrode of the first transistor M1, and stores the gate-source voltage of the first transistor M1.

[0109] The third transistor M3 is connected between the second node N2 and the initialization power line INL, and the gate electrode of the third transistor M3 is connected to the second gate line GL2. The third transistor M3 can be driven according to the voltage of the second gate line GL2. For example, when a second gate signal SS with a gate turn-on voltage (e.g., an initialization control signal (or sense control signal) with a high-level voltage) is provided to the second gate line GL2, the third transistor M3 turns on to electrically connect the second node N2 to the initialization power line INL. Therefore, the voltage of the initialization power supply VINIT can be transmitted to the second node N2.

[0110] The fourth transistor M4 is connected between the first node N1 and the second node N2, and the gate electrode of the fourth transistor M4 is connected to the third gate line GL3. For example, the fourth transistor M4 can be directly connected between the first electrode and the second electrode of the capacitor Cst. That is, the fourth transistor M4 can be connected in parallel to the capacitor Cst between the first node N1 and the second node N2.

[0111] The fourth transistor M4 can be driven based on the voltage of the third gate line GL3. For example, when a third gate signal BI (e.g., a high-level non-emitter control signal) with a gate turn-on voltage is provided to the third gate line GL3, the fourth transistor M4 turns on to connect the first node N1 to the second node N2. When the fourth transistor M4 is on, the two electrodes of the capacitor Cst can be connected to become equipotential, and therefore, the charge accumulated in the capacitor Cst can be released.

[0112] At the same time, despite Figure 5 The transistors included in the pixel circuit PXC (e.g., first transistor M1 to fourth transistor M4) are shown to be N-type transistors, but this disclosure is not limited thereto. That is, at least one of the first transistor M1 to fourth transistor M4 can be changed to a P-type transistor. In this case, the level of the gate turn-on voltage used to turn on the respective transistor can be changed.

[0113] For example, in other embodiments, the first transistor M1 to the fourth transistor M4 may be P-type transistors. In this case, the gate turn-on voltage for turning on the first transistor M1 to the fourth transistor M4 may be a low-level voltage.

[0114] In other embodiments, the pixel PX may include both P-type transistors and N-type transistors. For example, some of the first transistors M1 to the fourth transistors M4 may be N-type transistors, while the others may be P-type transistors.

[0115] Furthermore, according to some implementations, the position of capacitor Cst can be changed. For example, capacitor Cst can be connected between the first power line PL1 (or, if changed, the source electrode of the first transistor M1, a P-type transistor) and the first node N1.

[0116] Figure 6 The driving timing of a pixel PX according to some embodiments of the present disclosure is shown. For example, Figure 6 It shows that according to Figure 5 (or Figure 10 The implementation of the first gate signal SC, the second gate signal SS, and the third gate signal BI for each pixel PX is provided in some implementations.

[0117] For convenience, Figure 6 The frame time period DF based on the pixels PX arranged on the first horizontal line HL[1] is shown, as well as the first time period T1 to the fourth time period T4 constituting the frame time period DF. The first time period T1 to the fourth time period T4 of the remaining horizontal lines HL can start sequentially after the first time period T1 to the fourth time period T4 of the first horizontal line HL[1].

[0118] refer to Figures 1 to 6 During a frame period 1F, the first gate signals SC[1] to SC[n] can be sequentially provided to the first gate lines GL1[1] to GL1[n]. Furthermore, the second gate signals SS[1] to SS[n] can be sequentially provided to the second gate lines GL2[1] to GL2[n] to synchronize with the first gate signals SC[1] to SC[n] during a frame period 1F. For example, the first gate signal SC and the second gate signal SS can be provided simultaneously or substantially simultaneously to the first gate line GL1 and the second gate line GL2 of each horizontal line HL.

[0119] For each horizontal line HL, a frame time period 1F will consist of a first time period T1, a second time period T2, a third time period T3, and a fourth time period T4, performed sequentially. In some implementations, the first time period T1, the second time period T2, and / or the third time period T3 of the current frame of some horizontal lines HL, including the first horizontal line HL[1], may overlap temporally (e.g., in the time domain) with the second time period T2, the third time period T3, and / or the fourth time period T4 of the previous frame of some other horizontal lines HL, including the nth horizontal line HL[n], etc.

[0120] The first time period T1 can be the time period during which the data signal DS of the corresponding frame is input to the pixel PX of each horizontal line HL. For example, the first time period T1 can be... Figure 4 The data input period corresponds to Tw.

[0121] During the first time period T1, the first gate signal SC and the second gate signal SS can be provided simultaneously or substantially simultaneously to the first gate line GL1 and the second gate line GL2 of the horizontal line HL. For example, during the first horizontal time period of each frame time period DF, the first gate signal SC[1] and the second gate signal SS[1] with gate on voltage can be provided to the first gate line GL1[1] and the second gate line GL2[1] of the first horizontal line HL[1], and during the second horizontal time period after the first horizontal time period, the first gate signal SC[2] and the second gate signal SS[2] with gate on voltage can be provided to the first gate line GL1[2] and the second gate line GL2[2] of the second horizontal line HL[2]. Thus, when the first gate signal SC[1] to SC[n] is provided sequentially to the first gate lines GL1[1] to GL1[n] of multiple horizontal lines HL[1] to HL[n] during each frame time period DF, the second gate signal SS[1] to SS[n] can be provided sequentially to the second gate lines GL2[1] to GL2[n] of multiple horizontal lines HL[1] to HL[n].

[0122] The second time period T2 can be the time period during which pixels PX of each horizontal line HL emit light with a brightness corresponding to the data signal DS of the corresponding frame. For example, the second time period T2 can be... Figure 4 The launch time period Te corresponds to.

[0123] The third time period T3 is the period during which the third gate signal BI is input to the pixel PX of each horizontal line HL, and can also be the period during which the voltage charged into the pixel PX of the corresponding horizontal line HL is reset by the third gate signal BI. For example, the third time period T3 can be combined with... Figure 4 The data reset period corresponds to Tr.

[0124] For example, during a frame period 1F, the third gate signals BI[1] to BI[n] can be sequentially provided to the third gate lines GL3[1] to GL3[n] of multiple horizontal lines HL[1] to HL[n]. Therefore, the voltage stored in the pixel PX of the multiple horizontal lines HL[1] to HL[n] during each frame period DF can be sequentially discharged, and the pixel PX can be reset.

[0125] For each horizontal line HL, a third gate signal BI can be provided so that it does not overlap with the first gate signal SC and the second gate signal SS during each frame time period DF. For example, the third time period T3 can begin after a certain period of time (e.g., a predetermined time) from the start of the second time period T2.

[0126] When the voltage charged into pixel PX discharges during the third time period T3, pixel PX may not emit light during the fourth time period T4 following the third time period T3. For example, the fourth time period T4 may be... Figure 4 The non-transmitting period Tb corresponds to this. Pixel PX can remain in a non-transmitting state until the data signal DS for the next frame is provided.

[0127] Figures 7 to 9 The following are shown in sequence according to Figure 5 and Figure 6 The method for driving pixel PX in the implementation of the above method. For convenience, Figures 7 to 9 Some embodiments are shown of a pixel PX arranged on an arbitrary horizontal line HL and a first gate signal SC, a second gate signal SS and a third gate signal BI provided to the pixel PX.

[0128] First, refer to Figures 1 to 7 During the first time period T1 of a frame time period 1F, a first gate signal SC and a second gate signal SS having gate turn-on voltages (e.g., high-level voltages) can be provided to a first gate line GL1 and a second gate line GL2 of a horizontal line HL. Therefore, the second transistor M2 and the third transistor M3 of the pixel PX located on the horizontal line HL can be turned on.

[0129] When the second transistor M2 of each pixel PX is turned on, the data signal DS from the data line DL can be transmitted into the interior of the pixel PX, for example, the first node N1. When the third transistor M3 of each pixel PX is turned on, the voltage Vi (hereinafter referred to as the "initialization voltage") of the initialization power supply VINIT from the initialization power supply line INL can be transmitted into the interior of the pixel PX, for example, the second node N2.

[0130] Therefore, the voltage corresponding to the voltage Vd of the data signal DS (hereinafter referred to as the "data voltage") (e.g., the voltage difference between the data voltage Vd and the initialization voltage Vi) can be stored in the capacitor Cst. Furthermore, the light-emitting element LD can be initialized when the initialization voltage Vi is applied to one of its electrodes (e.g., the anode electrode). For example, the charge accumulated in the parasitic capacitor of the light-emitting element LD can be released.

[0131] refer to Figures 1 to 8 During the second time period T2 following the first time period T1, the voltages of the first gate line GL1, the second gate line GL2, and the third gate line GL3 of the horizontal line HL can be maintained at the gate cutoff voltage (e.g., a low-level voltage). Therefore, the second transistor M2, the third transistor M3, and the fourth transistor M4 of the pixel PX located on the horizontal line HL can be turned off.

[0132] During the second time period T2, the gate-source voltage Vgs of the first transistor M1 can be maintained at the voltage charged into the capacitor Cst during the first time period T1. Therefore, the first transistor M1 can generate a drive current Id corresponding to the data voltage Vd during the second time period T2, and the drive current Id can flow from the first power supply VDD to the second power supply VSS through the first transistor M1 and the light-emitting element LD. Therefore, during the second time period T2, the pixel PX of the horizontal line HL can emit light with a brightness corresponding to the data signal DS. At the same time, the pixel PX that receives the data signal DS corresponding to the black gray level during the frame time period DF can remain in a non-emitting state during the second time period T2.

[0133] refer to Figures 1 to 9 During the third time period T3 following the second time period T2, the third gate signal BI, with a gate turn-on voltage (e.g., a high-level voltage), can be provided to the third gate line GL3 of the horizontal line HL. Therefore, the fourth transistor M4 of the pixel PX located on the horizontal line HL can be turned on.

[0134] When the fourth transistor M4 of each pixel PX is turned on, a cutoff voltage can be applied to the first transistor M1 of the pixel PX. For example, during the third time period T3, the gate and source electrodes of the first transistor M1 can be connected through the fourth transistor M4, and therefore the source voltage Vs of the first transistor M1 can be transmitted to the first node N1. Furthermore, the two electrodes of the capacitor Cst connected between the gate and source electrodes of the first transistor M1 can be connected to each other to become equipotential, and therefore the capacitor Cst can discharge. Thus, the voltage of the first node N1 can be reset to the cutoff voltage of the first transistor M1.

[0135] Subsequently, during the fourth time period T4 following the third time period T3, the voltages of the first gate line GL1, the second gate line GL2, and the third gate line GL3 of the horizontal line HL can be maintained at the gate cutoff voltage (e.g., a low-level voltage). Therefore, the second transistor M2, the third transistor M3, and the fourth transistor M4 of the pixel PX located on the horizontal line HL can be turned off.

[0136] During the fourth time period T4, while maintaining the voltage of the first node N1 of pixel PX, the gate-source voltage Vgs of the first transistor M1 can remain in a discharged state (e.g., 0V). Therefore, when the first transistor M1 remains in the off state during the fourth time period T4, pixel PX of the horizontal line HL can remain in a non-emitting state.

[0137] Figure 10 Pixels PX according to some embodiments of this disclosure are shown. For example, Figure 10 It shows Figure 5Modifications to the implementation of the fourth transistor M4.

[0138] Figure 11 Methods for driving pixels PX according to some embodiments of the present disclosure are illustrated. For example, Figure 11 It shows Figure 9 Modifications to the implementation of the method regarding the operations in the third time period T3 and the fourth time period T4.

[0139] Figure 12 The bias voltage Vb and the drive voltage of the first transistor M1 according to some embodiments of the present disclosure are shown. For example, Figure 12 The bias voltage Vb that can be applied to pixel PX is shown, and according to... Figure 10 The gate-source voltage Vgs of the first transistor M1 in the embodiment.

[0140] exist Figures 10 to 12 In the implementation, the same reference mark indicates and Figures 5 to 9 The components of the embodiments are similar to or the same as those in the embodiments, and their detailed descriptions will be omitted.

[0141] Combination Figures 1 to 9 ,refer to Figures 10 to 12 The fourth transistor M4 can be connected between the first node N1 and the bias power supply line BIL. For example, the fourth transistor M4 can be directly connected between the first node N1 and the bias power supply line BIL, and the bias voltage Vb can be transmitted to the first node N1 during the third time period T3 in which the third gate signal BI is provided to the third gate line GL3.

[0142] Since the bias power line BIL is connected to the bias power supply Vbi and the fourth transistor M4 is turned on, the bias voltage Vb from the bias power supply Vbi can be transmitted to the pixel PX. According to some embodiments, the bias power supply Vbi can be an independent power supply separate from the initialization power supply VINIT, and can be a different power supply than the initialization power supply VINIT. Furthermore, the bias power line BIL can be an independent power line separate from the initialization power line INL. Therefore, regardless of the initialization voltage Vi, the bias voltage Vb can be adjusted to the desired level.

[0143] In some implementations, the bias voltage Vb can be lower than or equal to the cutoff voltage of the first transistor M1. For example, the bias voltage Vb can be a cutoff voltage (e.g., a negative voltage) used to reset the gate-source voltage Vgs of the first transistor M1 to 0V or lower. In this case, since the first transistor M1 is cut off at least during the fourth time period T4, the light-emitting element LD does not emit light, and the pixel PX can accordingly present a black grayscale level.

[0144] In other embodiments, the bias voltage Vb can be a low grayscale voltage less than or equal to a reference grayscale level (e.g., a predetermined reference grayscale level). For example, the bias voltage Vb can be a low grayscale voltage (e.g., a positive voltage with a small absolute value) at a level (e.g., a predetermined level) used to slightly turn on the first transistor M1. In this case, since the voltage of the first node N1 can be maintained at a low grayscale voltage at least during the fourth time period T4, the first transistor M1 can be slightly turned on. Therefore, the first transistor M1 can provide a drive current Id with an amplitude corresponding to the low grayscale voltage to the light-emitting element LD, and the light-emitting element LD can slightly emit light with a brightness corresponding to the low grayscale voltage. Therefore, the pixel PX can emit light with a brightness corresponding to the low grayscale voltage, and can perform an erasure operation of the displayed image as a low grayscale image (e.g., a grayscale image less than or equal to one grayscale level (e.g., a predetermined grayscale level)) corresponding to the low grayscale voltage.

[0145] During the fourth time period T4, the grayscale level displayed by each pixel PX can be changed according to the bias voltage Vb, and the level of the bias voltage Vb can be changed according to different implementation methods. For example, the bias voltage Vb can be adjusted or set to a desired level for various purposes, such as effectively compensating for characteristic changes caused by the hysteresis of the first transistor M1 and / or characteristic changes caused by the degradation of the light-emitting element LD, effectively correcting the brightness of the pixel PX in conjunction with brightness compensation based on external compensation, or effectively and stably initializing the parasitic capacitor of the light-emitting element LD.

[0146] Furthermore, according to some implementations, the horizontal line HL can be divided into multiple groups, each including at least one horizontal line HL, and bias voltages Vb of different levels can be provided to each group. Therefore, the black brightness (or low grayscale brightness (e.g., predetermined low grayscale brightness)) of the non-emission period Tb can be adjusted for each region, or feature deviations of the pixel PX can be compensated more precisely.

[0147] At the same time, Figures 10 to 12 In this embodiment, the operation of pixel PX during the first time period T1 and the second time period T2 can be largely the same as in the embodiment described above. Therefore, its detailed description will be omitted.

[0148] As mentioned above, in Figures 10 to 12In this embodiment, the fourth transistor M4 can be connected to a bias power supply Vbi configured as a separate independent power supply, and during the non-emission period Tb (or low grayscale driving period) of each horizontal line HL, a separate bias voltage Vb (e.g., a cutoff voltage or a low grayscale voltage of a certain level (e.g., a predetermined level)) can be applied to the pixel PX of the horizontal line HL. According to the above embodiment, the bias voltage Vb can be adjusted with consideration of the desired purpose and / or the characteristics of the pixel PX. For example, the bias voltage Vb can be set to a voltage capable of effectively compensating for characteristic changes caused by the hysteresis of the first transistor M1, and / or the bias voltage Vb can be set to a voltage capable of effectively releasing the charge accumulated in the light-emitting element LD to enhance the low grayscale rendering. Therefore, the image quality of the display panel can be improved, and the reliability can be enhanced.

[0149] Furthermore, according to the above embodiment, since the bias voltage Vb can be adjusted in units of at least one horizontal line HL, the black (or grayscale) brightness can also be adjusted for each region. Therefore, by applying an optimized bias voltage Vb to each region according to the characteristics of pixel PX, the image quality of the display device 100 can be improved, and power consumption can be reduced or optimized.

[0150] According to embodiments of this disclosure, regardless of the data input period of the pixel PX located on each horizontal line HL, the pixel PX can be turned off at a desired time point or driven at a low gray level. Therefore, while ensuring sufficient data input period, the image quality of the display device 100 can be improved by reducing or preventing residual images (e.g., motion blur).

[0151] Furthermore, according to embodiments of this disclosure, non-emission periods Tb can be sequentially turned off in units of horizontal lines HL, or sequentially interpolated in a low grayscale driving manner, with each pixel PX turned off in turn. Therefore, by distributing the load on the display panel and reducing, preventing, or minimizing the increase in instantaneous current, the voltage drop and power consumption of the display panel can be reduced, prevented, or minimized.

[0152] Furthermore, according to the implementation that provides a separate bias voltage Vb to the pixel PX of the corresponding horizontal line HL during the non-emission period Tb (or low grayscale driving period) of each horizontal line HL, the bias voltage Vb can be controlled to a desired level. Therefore, characteristic variations of the driving transistor can be effectively compensated, and accumulated charge in the light-emitting element LD can be released, thereby enhancing the ability to render low grayscale levels.

[0153] The aspects of the embodiments are not limited to those presented above, and many more different aspects are incorporated herein.

[0154] Although this disclosure has been described in detail with reference to the above embodiments, it should be noted that the above embodiments are for illustrative purposes and not intended to limit this disclosure. Furthermore, those skilled in the art will understand that various modifications can be made within the scope of this disclosure.

[0155] Therefore, the scope of this disclosure should not be limited to what is described in the detailed description of the specification, but should be determined by the appended claims. Furthermore, it should be understood that all changes or modifications made to the meaning and scope of the claims, and their functional equivalents, fall within the scope of this disclosure.

Claims

1. A display device comprising: pixels; first, second, and third gate lines connected to the pixels; and data lines connected to the pixels, wherein at least one of the pixels comprises: a light emitting element connected between a first power supply and a second power supply; a first transistor connected between the first power supply and the light emitting element for driving the light emitting element in accordance with a voltage of a first node; a second transistor connected between the first node and a respective one of the data lines and configured to be driven in accordance with a voltage of a respective one of the first gate lines; a capacitor connected between the first node and a second node between the first transistor and the light emitting element; a third transistor connected between the second node and an initialization power supply line and configured to be driven in accordance with a voltage of a respective one of the second gate lines; and a fourth transistor connected between the first node and the second node and configured to be driven in accordance with a voltage of a respective one of the third gate lines; the display device further comprising a gate driver for supplying first, second, and third gate signals to the first, second, and third gate lines, respectively, wherein the pixels are arranged on horizontal lines, wherein the first, second, and third gate lines are arranged on respective ones of the horizontal lines and connected to the pixels of the respective horizontal lines, and wherein the gate driver is configured to supply the first and second gate signals to respective ones of the first and second gate lines of a horizontal line in parallel for respective horizontal periods constituting one frame period; wherein the gate driver is configured to supply a respective one of the third gate signals to a respective one of the third gate lines of the horizontal line when a time has elapsed after the respective one of the first gate signals and the respective one of the second gate signals are supplied to the respective one of the first gate lines and the respective one of the second gate lines, for the respective horizontal period. the fourth transistor is connected directly between first and second electrodes of the capacitor and configured to connect the first and second electrodes of the capacitor during a period when a third gate signal is supplied to the respective one of the third gate lines.

2. The display device of claim 1, wherein, the gate driver is configured to supply the first and second gate signals to the respective ones of the first and second gate lines of the horizontal line in sequence for respective units of the horizontal line during the one frame period.

3. The display device of claim 1, wherein, the gate driver is configured to supply the third gate signals to the third gate lines of the horizontal line in sequence for respective units of at least one of the horizontal line during the one frame period.

4. The display device of claim 1, wherein, the gate driver comprises:

5. The display device of claim 1, wherein, ​ a first gate driver configured to supply the first gate signal and the second gate signal to the first gate line and the second gate line of the horizontal line; and a second gate driver configured to supply the third gate signal to the third gate line of the horizontal line.

6. The display device according to claim 1, further comprising a data driver configured to supply, for an individual one of the horizontal periods, a data signal corresponding to the pixels of a respective one of the horizontal lines to the data line.

7. A display device comprising: pixels; a first gate line, a second gate line, and a third gate line connected to the pixels; and a data line connected to the pixels, wherein at least one of the pixels comprises: a light emitting element connected between a first power supply and a second power supply; a first transistor connected between the first power supply and the light emitting element, configured to drive the light emitting element in accordance with a voltage of a first node; a second transistor connected between the first node and a respective one of the data line, and configured to be driven in accordance with a voltage of a respective one of the first gate line; a capacitor connected between the first node and a second node between the first transistor and the light emitting element; a third transistor connected between the second node and an initialization power supply line, and configured to be driven in accordance with a voltage of a respective one of the second gate line; and a fourth transistor connected between the first node and a bias power supply line separate from the initialization power supply line, and configured to be driven in accordance with a voltage of a respective one of the third gate line; the display device further comprising a gate driver configured to supply a first gate signal, a second gate signal, and a third gate signal to the first gate line, the second gate line, and the third gate line, respectively, wherein the pixels are arranged on a horizontal line, wherein the first gate line, the second gate line, and the third gate line are arranged on each of the horizontal lines, and connected to the pixels of the respective horizontal line, and wherein the gate driver is configured to supply the first gate signal and the second gate signal to respective first gate line and second gate line of the horizontal line in parallel for each horizontal period constituting one frame period; wherein the gate driver is configured to supply a respective one of the third gate signal to a respective one of the third gate line when a time has elapsed after the respective one of the first gate signal and the respective one of the second gate signal is supplied to the respective one of the first gate line and the respective one of the second gate line for one of the horizontal lines during the one frame period. the fourth transistor is directly connected between the first node and the bias power supply line, and configured to transmit a voltage of the bias power supply to the first node during a period when the respective one of the third gate signal is supplied to the respective one of the third gate line.

8. The display device of claim 7, wherein, ​ 9. The display device of claim 8, wherein, The voltage of the bias power supply is configured to be set to an off voltage of the first transistor or to a low gray level voltage that is less than or equal to a reference gray level.

10. The display device of claim 7, wherein, The gate driver is configured to sequentially provide the first and second gate signals to the respective first and second gate lines of the horizontal lines in respective units of one of the horizontal lines during the one frame period.

11. The display device of claim 7, wherein, The gate driver is configured to sequentially provide the third gate signal to the third gate line of the horizontal lines in respective units of at least one of the horizontal lines during the one frame period.

12. The display device of claim 7, wherein, The gate driver includes: a first gate driver configured to provide the first and second gate signals to the first and second gate lines; and a second gate driver configured to provide the third gate signal to the third gate line.

13. The display device of claim 7, further comprising a data driver configured to provide data signals corresponding to the pixels of a respective one of the horizontal lines to the data lines for individual ones of the horizontal periods.

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