Method for forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing an etching layer to be etched, where the etching layer to be etched includes a first region and a second region surrounding the first region, and a top surface of the second region is lower than a top surface of the first region; forming a first pattern material layer on the etching layer to be etched; injecting first ions onto a surface of the first pattern material layer to cause the first pattern material layer located on the second region to fall off, and at least a part of the fallen-off first pattern material layer adheres to a surface of the etching layer to form residues; cleaning and removing the residues, so that the first pattern material layer with weak adhesion on a surface of the second region detaches and is removed before a subsequent process, avoiding affecting the subsequent etching process, reducing the influence of the height difference of the etching layer to be etched at the edge of the wafer on the etching process in subsequent pattern definition, improving the accuracy of pattern definition, and thus improving the performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a method for forming a semiconductor structure. Background Art

[0002] With the continuous development of integrated circuit manufacturing technology, in order to achieve faster computing speed, larger data storage capacity, and more functions, integrated circuit chips are developing towards higher device density and higher integration.

[0003] As the integration of semiconductor chips continues to increase, the feature size of transistors continues to shrink, posing an increasing challenge to the lithography process. Controlling the critical dimension of the pattern linewidth has become an important direction for semiconductor development. In order to form more refined patterns and achieve higher fidelity during the process, self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), etc. are introduced to achieve smaller-sized patterns.

[0004] However, existing lithography technologies need to be further improved. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance of the formed semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing an etching layer to be etched, where the etching layer to be etched includes a first region and a second region surrounding the first region, and the top surface of the second region is lower than the top surface of the first region; forming a first pattern material layer on the etching layer to be etched; injecting a first ion onto the surface of the first pattern material layer to cause the first pattern material layer located on the second region to fall off, and at least part of the fallen-off first pattern material layer adheres to the surface of the etching layer to be etched to form a residue; cleaning and removing the residue; after cleaning and removing the residue, forming an imaged structure on the surface of the first pattern material layer.

[0007] Optionally, the imaged structure has a first opening, and the bottom of the first opening exposes a part of the first pattern material layer; the forming method further includes: injecting a second ion onto the bottom of the first opening to form a modified region on the first pattern material layer exposed at the bottom of the first opening; removing the modified region to form a first pattern layer from the first pattern material layer.

[0008] Optionally, before forming the first pattern material layer, it further includes: forming a second pattern material layer on the surface of the etching layer to be etched, and the second pattern material layer is located between the first pattern material layer and the etching layer to be etched.

[0009] Optionally, the material of the second graphic material layer includes one or more of titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride, carbon silicon nitride, and carbon silicon oxynitride.

[0010] Optionally, a first ion is implanted into the surface of the first graphic material layer, so that while the first graphic material layer located on the second region falls off, the second graphic material layer located on the second region also falls off.

[0011] Optionally, it further includes: forming sidewalls on the sidewalls of the first graphic layer.

[0012] Optionally, it further includes: before forming the sidewalls, removing the patterning structure; after forming the sidewalls, removing the first graphic layer.

[0013] Optionally, the material of the sidewalls includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxynitride, carbon silicon nitride, and carbon silicon oxynitride.

[0014] Optionally, it further includes: etching the second graphic material layer using the sidewalls as a mask until the surface of the layer to be etched is exposed to form a second graphic layer.

[0015] Optionally, the patterning structure includes a first anti-reflection layer on the surface of the first graphic layer, a second anti-reflection layer on the surface of the first anti-reflection layer, and a photoresist layer on the surface of the second anti-reflection layer.

[0016] Optionally, the material of the first anti-reflection layer includes a carbon-containing polymer.

[0017] Optionally, the material of the second anti-reflection layer includes an organic polymer.

[0018] Optionally, the material of the first graphic material layer includes silicon.

[0019] Optionally, the process for cleaning and removing the residue is a wet process.

[0020] Optionally, the cleaning solution for the wet process includes deionized water containing carbon dioxide.

[0021] Optionally, the process parameters of the first ion implantation include: the first ion includes one or more of carbon ions, nitrogen ions, and oxygen ions, the energy range of the implanted ions is 5 keV to 20 keV, and the concentration range of the implanted ions is 1.0E14 atom / cm3 to 1.0E20 atom / cm3.

[0022] Optionally, the material of the first graphic material layer includes silicon.

[0023] Optionally, the process parameters for implanting the second ions include: the second ions include P-type ions or N-type ions, and the energy range is 5 keV to 20 keV.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0025] In the method for forming a semiconductor structure provided by the technical solution of the present invention, when the first ions are implanted into the surface of the first pattern material layer, due to the implantation of the first ions, stress and surface static electricity are generated in the first pattern material layer. The stress causes the first pattern material layer with poor adhesion on the surface of the second region to tear and detach from the weak adhesion point, and the residue formed by the part of the detached first pattern material layer adhering to the layer to be etched is removed by cleaning, so that the first pattern material layer with poor adhesion on the surface of the second region detaches and is removed before the subsequent process, avoiding affecting the subsequent etching process, reducing the influence of the height difference of the layer to be etched at the edge of the wafer on the etching process in the subsequent pattern definition, improving the accuracy of the pattern definition, and thus improving the performance of the device.

[0026] Further, when the first ions are implanted into the surface of the first pattern material layer, while causing the first pattern material layer on the second region to fall off, it also causes the second pattern material layer on the second region to fall off, so that the second pattern material layer with poor adhesion on the surface of the second region detaches and is removed before the subsequent process, without affecting the subsequent etching process, reducing the influence of the height difference of the layer to be etched at the edge of the wafer on the etching process in the subsequent pattern definition, improving the accuracy of the pattern definition, and thus improving the performance of the device.

[0027] Further, the process parameters of the first ion implantation include: the implanted ions include one or more of carbon ions, nitrogen ions, and oxygen ions, the energy range of the implanted ions is 5 keV to 20 keV, and the concentration range of the implanted ions is 1.0E14 atom / cm 3 to 1.0E20 atom / cm 3 . The process parameters for implanting the second ions include: the second ions include P-type ions or N-type ions, and the energy range is 5 keV to 20 keV. The ion types of the first ion implantation process and the second ion implantation process are different, avoiding affecting the implantation process of the second ions, and thus not affecting the subsequent pattern definition. Description of the Drawings

[0028] Figures 1 to 3 is a schematic cross-sectional view of a semiconductor structure formation process;

[0029] Figures 4 to 15 is a schematic structural diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention. Detailed implementation mode

[0030] It should be noted that the "surface" and "upper" in this specification are used to describe the relative positional relationship in space and do not limit whether there is direct contact.

[0031] As described in the background art, the performance of the semiconductor structure formed by the existing lithography technology needs to be improved urgently. A semiconductor structure is now combined for explanation and analysis.

[0032] Figures 1 to 3 It is a schematic cross-sectional view of a semiconductor structure forming process.

[0033] Please refer to Figure 1 , a layer to be etched 101 is provided, and the layer to be etched 101 includes a first region Ⅰ and a second region Ⅱ; a patterned material layer 102 is formed on the layer to be etched 101; an amorphous silicon material layer 103 is formed on the patterned material layer 102; a patterned photoresist layer 104 is formed on the surface of the amorphous silicon material layer 103, and an opening 105 is formed in the photoresist layer 104, and a part of the amorphous silicon material layer 103 on the first region Ⅰ and the amorphous silicon material layer 103 on the second region Ⅱ are exposed at the bottom of the opening 105.

[0034] Please refer to Figure 2 , ions are implanted into the bottom of the opening 105, so that the amorphous silicon material layer 103 exposed by the opening 105 forms a modified region 106, and the amorphous silicon material layer 103 located under the photoresist layer 104 forms a pattern layer 107.

[0035] The above method is used in the graphic definition process. A bottom anti-reflection coating will be used in the etching process before the graphic definition process. The material of the bottom anti-reflection coating is a fluid organic polymer, which is usually formed by spin coating. The second region Ⅱ is located at the edge of the wafer. Due to the centrifugal force, the liquid is easy to accumulate at the edge of the wafer, which will cause the bottom anti-reflection coating material at the edge of the wafer to be difficult to remove due to its relatively thick thickness. The residual bottom anti-reflection coating material will make the adhesion between the film formed by subsequent deposition and the lower film poor, resulting in the detachment of the film formed subsequently, and thus the height of the top surface of the second region Ⅱ is lower than that of the top surface of the first region Ⅰ.

[0036] During the process of injecting ions into the bottom of the opening 105, due to the large stress generated by ion implantation and the height difference between the first region I and the second region II, the amorphous silicon material layer 103 and the pattern material layer 102 on the second region II will be torn, such as cracks A formed at the weak adhesion points, resulting in partial detachment of the amorphous silicon material layer 103 and the pattern material layer 102 on the second region II. The residue B formed by the detached material will adhere to the surface of the wafer with a large amount of static electricity (such as Figure 3 shown). When the residue B covers the opening 105, it will block the ion implantation into the amorphous silicon material layer 103 exposed by the opening 105 (such as Figure 1 shown), so that the amorphous silicon material layer 103 at region C ( Figure 3 the region marked by the dashed line) cannot form the modified region required by the target. Whether the amorphous silicon material layer 103 is implanted with ions will result in different etching rates. Subsequently, the modified region 106 will be removed, and sidewalls will be formed on the sidewalls of the pattern layer 107. The sidewalls are used for subsequent pattern definition. Since the modified region required by the target cannot be formed at region C, the sidewalls at the corresponding positions will be missing, and uniform sidewalls cannot be formed on the surface of the pattern material layer 102, making the sidewalls unable to be used for subsequent accurate pattern definition. When the sidewalls are used as mask patterns to form metal interconnections, the positions of the metal interconnections cannot be accurately defined, which may cause bridging between the metal interconnections, resulting in leakage and affecting the yield of the device, etc.

[0037] To solve the above problems, in a method for forming a semiconductor structure provided by the present invention, first ions are injected into the surface of the first pattern material layer. Due to the stress and surface static electricity generated by the first ion implantation in the first pattern material layer, the first pattern material layer with weak adhesion on the surface of the second region is torn and detached from the weak adhesion points. The residue formed by the part of the detached first pattern material layer adhering to the layer to be etched is removed by cleaning, so that the first pattern material layer with weak adhesion on the surface of the second region is detached and removed before the subsequent process, which will not affect the subsequent etching process, reduces the influence of the height difference of the layer to be etched at the edge of the wafer on the etching process in the subsequent pattern definition, improves the accuracy of pattern definition, and thus improves the performance of the device.

[0038] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description will be given to the specific embodiments of the present invention with reference to the accompanying drawings.

[0039] Figures 4 to 15 It is a schematic structural diagram of each step of the method for forming a semiconductor structure in an embodiment of the present invention.

[0040] Please refer to Figure 4 andFigure 5 , Figure 5 is a top view, Figure 4 is Figure 5 a cross-sectional view of region A of along the XY direction, providing an etch layer 201, the etch layer 201 including a first region Ⅰ and a second region Ⅱ surrounding the first region Ⅰ, the top surface of the second region Ⅱ being lower than the top surface of the first region Ⅰ.

[0041] The material of the etch layer 201 can be any material that needs to be etched, such as a dielectric material, a metal material, a semiconductor material, etc. The etch layer 201 can be a single layer or a multi-layer stacked structure. The etch layer 201 to be etched is located on a substrate (not shown in the figure), and the substrate is a silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-silicon substrate, a gallium arsenide substrate, or a germanium-on-insulator substrate. In one embodiment, the substrate has a metal interconnect structure, etc. In this embodiment, the material of the etch layer 201 to be etched is a metal material, and the substrate is a silicon wafer with transistor devices.

[0042] In this embodiment, the substrate has a device structure. Before forming the etch layer 201, during the formation of the device structure, a lithography process exists, which will form a bottom anti-reflection coating on the surface of the substrate. The material of the bottom anti-reflection coating is a fluid organic polymer, and the process of forming the bottom anti-reflection coating on the surface of the substrate is usually a spin coating process. During the formation of the bottom anti-reflection coating, the second region Ⅱ is located at the edge of the wafer. Since the liquid is prone to accumulate at the edge of the wafer under the action of centrifugal force, the bottom anti-reflection coating material on the second region Ⅱ is not easy to be removed after the lithography process due to its relatively thick thickness. After the lithography process and before forming the etch layer 201, when forming a film layer on the surface of the substrate, the non-removable bottom anti-reflection coating material makes the adhesion between the film layer and the substrate poor, resulting in the film layer on the second region Ⅱ detaching from the surface of the substrate. Thus, after forming the etch layer 201, the height of the top surface of the second region Ⅱ is lower than that of the top surface of the first region Ⅰ.

[0043] It should be noted that the subsequent Figures 6 to 15 viewing directions are the same as those of Figure 4 .

[0044] Please refer to Figure 6 , and a first pattern material layer 202 is formed on the etch layer 201 to be etched.

[0045] In this embodiment, before forming the first pattern material layer 202, a second pattern material layer 203 is further formed on the surface of the etch layer 201 to be etched, and the second pattern material layer 203 is located between the first pattern material layer 202 and the etch layer 201 to be etched.

[0046] The material of the second graphic material layer 203 includes one or more of titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon silicon nitride, and carbon silicon oxynitride.

[0047] In this embodiment, the material of the second graphic material layer 203 includes silicon oxide, titanium nitride, and carbon oxysilicon. The structure of the second graphic material layer 203 is a multi-layer structure, including a silicon oxide material layer (not marked in the figure) on the surface of the layer to be etched 201, a titanium nitride material layer (not marked in the figure) on the silicon oxide layer, and a carbon oxysilicon material layer (not marked in the figure) on the titanium nitride material layer. The second graphic material layer 203 is used to form a second graphic layer subsequently.

[0048] The material of the first graphic material layer 202 includes silicon. In this embodiment, the material of the first graphic material layer 202 is amorphous silicon. In other embodiments, the material of the first graphic material layer 202 can also be polycrystalline silicon, silicon oxide, silicon carbide, etc. The first graphic material layer 202 is used to form a first graphic layer subsequently.

[0049] When forming the first graphic material layer 202, the bottom anti-reflection coating material in the lithography process before forming the layer to be etched 201 remains on the second region II, resulting in poor adhesion between the first graphic material layer 202 and the layer to be etched 201. Subsequently, when injecting a first ion onto the surface of the first graphic material layer 202 to generate stress in the first graphic material layer 202, due to the height difference between the first region I and the second region II, the stress of the first graphic material layer 202 is the largest at the adjacent junction M between the first region I and the second region II, and the adjacent junction M between the first region I and the second region II is likely to become the adhesion weak point of the first graphic material layer on the second region II.

[0050] Please refer to Figure 7 and Figure 8 , inject a first ion 204 onto the surface of the first graphic material layer 202 to make the first graphic material layer 202 on the second region II fall off, and at least part of the fallen first graphic material layer 202 adheres to the surface of the layer to be etched 201 to form a residue 205.

[0051] The process parameters of the injection of the first ion 204 include: the first ion includes one or more of carbon ions, nitrogen ions, and oxygen ions, the energy range of the injected ions is 5 keV to 20 keV, and the concentration range of the injected ions is 1.0E14 atom / cm 3 to 1.0E20 atom / cm 3 .

[0052] Inject first ions 204 onto the surface of the first graphic material layer 202. Due to the injection of the first ions 204, stress and surface static electricity are generated in the first graphic material layer 202. The stress causes the first graphic material layer 202 with weak adhesion on the surface of the second region II to tear open and separate from the weak adhesion point. Specifically, the weak adhesion point is located at the adjacent position M between the first region I and the second region II. Under the action of surface static electricity and gravity, part of the detached first graphic material layer 202 will adhere to the layer to be etched 201, forming a residue 205. Subsequently, the residue 205 is removed by cleaning, so that the first graphic material layer 202 with weak adhesion on the surface of the second region II detaches and is removed before the subsequent process, avoiding affecting the subsequent etching process, reducing the influence of the height difference of the layer to be etched 201 at the edge of the wafer on the etching process in the subsequent graphic definition, improving the accuracy of the graphic definition, and thus improving the performance of the device.

[0053] In this embodiment, when injecting first ions 204 onto the surface of the first graphic material layer 202, the first graphic material layer 202 located on the second region II is detached, and at the same time, the second graphic material layer 203 located on the second region II is also detached. The residue 205 also includes the second graphic material layer 203 that has detached and adhered to the surface of the layer to be etched 201.

[0054] Subsequently, after cleaning and removing the residue, an imaged structure is formed on the surface of the first graphic material layer 202. The imaged structure has a first opening, and the bottom of the first opening exposes part of the first graphic material layer 202. Second ions are injected into the bottom of the first opening, so that the first graphic material layer exposed at the bottom of the first opening forms a modified region. The ion types of the first ion injection process and the second ion injection process are different, avoiding affecting the injection process of the second ions, and thus not affecting the subsequent graphic definition.

[0055] Please refer to Figure 9 , and clean and remove the residue 205.

[0056] The process of cleaning and removing the residue 205 is a wet process. In this embodiment, the cleaning solution of the wet process includes deionized water containing carbon dioxide. The wet process can reduce the damage to the layer to be etched 201 during the cleaning process.

[0057] Please refer to Figure 10 , after cleaning and removing the residue 205, an imaged structure 206 is formed on the surface of the first graphic material layer 202.

[0058] The image structure 206 includes a first anti-reflection layer (not shown in the figure) on the surface of the first graphic material layer 202, a second anti-reflection layer (not shown in the figure) on the surface of the first anti-reflection layer, and a photoresist layer (not shown in the figure) on the surface of the second anti-reflection layer.

[0059] The method for forming the image structure 206 includes: forming a first anti-reflection material layer (not shown in the figure) on the surface of the first graphic material layer 202, forming a second anti-reflection material layer (not shown in the figure) on the surface of the first anti-reflection material layer, and forming a photoresist material layer (not shown in the figure) on the surface of the second anti-reflection material layer; patterning the photoresist material layer to form a photoresist layer, and etching the first anti-reflection material layer and the second anti-reflection material layer using the photoresist layer as a mask until the surface of the first graphic material layer 202 is exposed, thereby forming the first anti-reflection layer and the second anti-reflection layer.

[0060] The forming process of the first anti-reflection material layer includes a spin coating process.

[0061] The material of the first anti-reflection material layer includes a carbon-containing polymer. The first anti-reflection material layer is used to form the first anti-reflection layer, and the material of the first anti-reflection layer includes a carbon-containing polymer. During the etching process of forming the image structure 206, the first anti-reflection material layer plays a role in pattern transfer, and at the same time, due to the etching resistance of the first anti-reflection material layer, the collapse of the second anti-reflection layer (and the photoresist layer on the second anti-reflection layer) supported by the first anti-reflection material layer can be reduced.

[0062] The forming process of the second anti-reflection material layer includes a spin coating process.

[0063] The material of the second anti-reflection material layer includes an organic polymer. The second anti-reflection material layer is used to form the second anti-reflection layer, and the material of the second anti-reflection layer includes an organic polymer. The second anti-reflection material layer is used to reduce the reflection of light at the bottom of the photoresist material layer during the etching process.

[0064] In this embodiment, the image structure 206 has a first opening 207, and a part of the first graphic material layer 202 is exposed at the bottom of the first opening 207. The image structure 206 is subsequently used as a mask to form a first graphic layer.

[0065] Please refer to Figure 11 , injecting a second ion 208 into the bottom of the first opening 207 to form a modified region 209 on the first graphic material layer 202 exposed at the bottom of the first opening 207.

[0066] The process parameters for injecting the second ion 208 include: the second ion includes P-type ions or N-type ions, and the energy range is 5 keV to 20 keV. In this embodiment, the second ion 208 is a P-type ion. Specifically, the second ion 208 is boron.

[0067] Subsequently, the modified region 209 is removed, so that the first graphic material layer 202 forms a first graphic layer. After injecting the second ion 208, the etching rate of the first graphic material layer 202 will be changed. During the etching process of removing the modified region 209, damage to the first graphic layer can be reduced while removing the modified region 209. On the other hand, since the residue 205 (as Figure 8 shown) is removed before forming the imaged structure 206, it does not affect the process of injecting the second ion 208, avoids the absence of the target first graphic layer, and forms a uniformly distributed first graphic layer on the second graphic material layer 203.

[0068] Please refer to Figure 12 , the modified region 209 (as Figure 11 shown) is removed, so that the first graphic material layer 202 forms a first graphic layer 210.

[0069] The first graphic layer 210 can be used as a mask layer for graphic definition, or as a mandrel during the process of graphic definition (such as self-aligned double patterning technology (SADP)). Subsequently, a sidewall is formed on the sidewall of the first graphic layer 210, and the sidewall is used to define a smaller-sized graphic. In this embodiment, the first graphic layer 210 is used as a mandrel, and a sidewall is subsequently formed on the sidewall of the first graphic layer 210.

[0070] In this embodiment, before forming the sidewall, the imaged structure 206 is also removed.

[0071] The process of removing the imaged structure 206 includes one or a combination of dry processes and wet processes. In this embodiment, the process of removing the imaged structure 206 is a dry process. Specifically, the process of the imaged structure 206 is an ashing process. The ashing process can improve the removal rate of the imaged structure 206, reduce the damage to the first graphic layer 210 and the second graphic material layer 203 during the process of removing the imaged structure 206, and has high reliability.

[0072] Please refer to Figure 13 , a sidewall 211 is formed on the sidewall of the first graphic layer 210.

[0073] The material of the sidewall 211 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon oxysilicon, carbon silicon nitride, and carbon oxynitride silicon.

[0074] The forming method of the sidewall 211 includes: depositing a sidewall material layer (not marked in the figure) on the surfaces of the first pattern layer 210 and the second pattern material layer 203, and etching back the sidewall material layer until the top surfaces of the first pattern layer 210 and the second pattern material layer 203 are exposed, so as to form the sidewall 211.

[0075] The width of the sidewall 211 is determined by the thickness of the sidewall material layer, and the thickness of the sidewall material layer can be adjusted to control the width of the sidewall 211. The sidewall 211 can be used as a mask for pattern definition. To improve the accuracy of pattern transfer, in this embodiment, the sidewall 211 is further used to form a second pattern layer, and the second pattern layer is used as a mask for pattern definition. For the method of forming the second pattern layer, please refer to Figures 14 to 15 。

[0076] Please refer to Figure 14 After forming the sidewall 211, the first pattern layer 210 is removed.

[0077] The process of removing the first pattern layer 210 includes one or a combination of a wet etching process and a dry etching process.

[0078] In this embodiment, the material of the first pattern layer 210 is determined by the material of the first pattern material layer 202. The first pattern layer 210 is amorphous silicon, and the process of removing the first pattern layer 210 is a wet etching process. The parameters of the wet etching process include: the solution used includes an ammonia water solution, the temperature is 30 degrees to 80 degrees, and the concentration of ammonia water is 30%-70% (volume ratio). Since the ammonia water solution has a high selectivity ratio for amorphous silicon materials and silicon oxide materials, it is beneficial to reduce the damage to the sidewall 211 during the process of removing the first pattern layer 210.

[0079] Since the first pattern layer 210 has the characteristic of uniform distribution, the formed sidewall 211 has the characteristic of uniform distribution on the second pattern material layer 203. Using the sidewall 211 as a mask can improve the accuracy of pattern definition.

[0080] Please refer to Figure 15 Using the sidewall 211 as a mask, the second pattern material layer 203 is etched until the surface of the layer to be etched 201 is exposed, so as to form a second pattern layer 212.

[0081] The process of etching the second graphic material layer 203 includes a dry etching process and a wet etching process. In this embodiment, the process of etching the second graphic material layer 203 is a dry etching process. The process parameters of the dry etching process include: the etching gas includes CF4 and CHF3, and the power range is from 300 watts to 1000 watts. The dry etching process is conducive to forming a second graphic layer 212 with a better morphology.

[0082] Subsequently, the second graphic layer 212 can be used as a mask in the graphic definition process. Since the second graphic layer 212 is obtained by graphic transfer from the sidewall 211, it also has the characteristic of uniform distribution on the surface of the layer to be etched 201. Using the second graphic layer 212 as a mask can improve the accuracy of graphic definition.

[0083] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing an etch target layer, the etch target layer including a first region and a second region surrounding the first region, a top surface of the second region being lower than a top surface of the first region; Forming a first pattern material layer on the etch target layer; Injecting first ions onto a surface of the first pattern material layer, causing the first pattern material layer located on the second region to peel off, and at least a part of the peeled-off first pattern material layer adhering to a surface of the etch target layer to form a residue; Cleaning and removing the residue; After cleaning and removing the residue, forming a patterned structure on the surface of the first pattern material layer.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The patterned structure has a first opening, and a bottom of the first opening exposes a part of the first pattern material layer; The forming method further includes: injecting second ions onto a bottom of the first opening, causing the first pattern material layer exposed at the bottom of the first opening to form a modified region; Removing the modified region, causing the first pattern material layer to form a first pattern layer.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, Before forming the first pattern material layer, it further includes: forming a second pattern material layer on a surface of the etch target layer, the second pattern material layer being located between the first pattern material layer and the etch target layer.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, The material of the second pattern material layer includes one or more of titanium nitride, silicon oxide, silicon nitride, silicon oxynitride, carbon silicon oxide, carbon silicon nitride, and carbon silicon oxynitride.

5. The method for forming a semiconductor structure according to claim 3, characterized in that, When injecting first ions onto a surface of the first pattern material layer, while causing the first pattern material layer located on the second region to peel off, it also causes the second pattern material layer located on the second region to peel off.

6. The method for forming a semiconductor structure according to claim 3, characterized in that, It further includes: Forming a sidewall on a sidewall of the first pattern layer.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, It further includes: Before forming the sidewall, further removing the patterned structure; after forming the sidewall, removing the first pattern layer.

8. The method for forming a semiconductor structure according to claim 6, characterized in that, The material of the sidewall includes one or more of silicon oxide, silicon nitride, silicon oxynitride, carbon silicon oxide, carbon silicon nitride, and carbon silicon oxynitride.

9. The method for forming a semiconductor structure according to claim 7, characterized in that, It further includes: Using the sidewall as a mask to etch the second pattern material layer until the surface of the etch target layer is exposed, forming a second pattern layer.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, The patterned structure includes a first anti-reflection layer located on a surface of the first pattern material layer, a second anti-reflection layer located on a surface of the first anti-reflection layer, and a photoresist layer located on a surface of the second anti-reflection layer.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, The material of the first anti-reflection layer includes a carbon-containing polymer.

12. The method for forming a semiconductor structure according to claim 10, characterized in that, The material of the second anti-reflection layer includes an organic polymer.

13. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the first pattern material layer includes silicon.

14. The method for forming a semiconductor structure according to claim 1, characterized in that, The process of cleaning and removing the residue is a wet process.

15. The method for forming a semiconductor structure according to claim 14, characterized in that, The cleaning liquid for the wet process includes deionized water containing carbon dioxide.

16. The method for forming a semiconductor structure according to claim 1, wherein, The process parameters of the first ion implantation include: the first ion includes one or more of carbon ions, nitrogen ions and oxygen ions, the energy range of the implanted ions is 5 keV to 20 keV, and the concentration range of the implanted ions is 1.0E14 atom / cm 3 to 1.0E20 atom / cm 3 .

17. The method for forming a semiconductor structure according to claim 1, wherein, The material of the first pattern material layer includes silicon.

18. The method for forming a semiconductor structure according to claim 2, wherein, The process parameters for injecting the second ions include: the second ions include P-type ions or N-type ions, and the energy range is 5 keV to 20 keV.

Images