Method for forming memory and memory
By forming an array of gap holes between adjacent electrode layers in a DRAM device, removing the sacrificial layer, and forming a capacitor array, the problem of capacitor skew is solved, and good storage performance is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ICLEAGUE TECH CO LTD
- Filing Date
- 2021-12-31
- Publication Date
- 2026-05-29
Smart Images
Figure CN114530419B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more specifically, to a method for forming a memory and a memory. Background Technology
[0002] Dynamic random access memory (DRAM) is characterized by its fast read / write speed, low power consumption, large capacity, and low cost, making it the most widely used semiconductor memory in computer and communication systems. The DRAM memory array architecture consists of an array of memory cells (i.e., 1T1C memory cells) each containing one transistor and one capacitor. The transistor's gate is connected to the word line, its drain to the bit line, and its source to the capacitor.
[0003] As the size of DRAM devices continues to shrink, the size of capacitors also shrinks. How to ensure the performance of capacitors in DRAM devices has become an urgent problem to be solved. Summary of the Invention
[0004] In view of this, embodiments of this application propose a method for forming a memory and a memory.
[0005] According to one aspect of this application, a method for forming a memory is provided, comprising:
[0006] A substrate is provided; wherein a transistor pillar array is formed on the surface of the substrate, the transistor pillar array comprising a plurality of transistor pillars arranged in an array along a direction perpendicular to the surface of the substrate;
[0007] A stacked structure covering the transistor pillar array is formed; wherein the stacked structure includes a first sacrificial layer and a first support layer stacked sequentially along a direction away from the substrate;
[0008] A capacitor via array is formed that penetrates the stacked structure; wherein the capacitor via array includes a plurality of capacitor vias arranged in an array, the plurality of capacitor vias are disposed one-to-one with a plurality of transistor pillars, and the capacitor vias expose the transistor pillars;
[0009] A first electrode layer and a filling layer are sequentially formed on the inner wall of the capacitor hole; wherein the first electrode layer is electrically connected to the transistor pillar;
[0010] A first gap hole array is formed through the first support layer; wherein the first gap hole array includes a plurality of first gap holes arranged in an array, and each first gap hole is located between four adjacent first electrode layers;
[0011] The first sacrificial layer is removed through the first gap hole array to expose the first electrode layer;
[0012] A dielectric layer and a second electrode layer are sequentially formed to cover the first electrode layer in order to form a capacitor array.
[0013] In some embodiments, the capacitor hole array includes a first predetermined number of capacitor holes;
[0014] The formation of a first gap hole array penetrating the first support layer; wherein the first gap hole array includes a plurality of first gap holes arranged in an array, including:
[0015] A first gap hole array is formed that penetrates the first support layer. The first gap hole array includes a second preset number of first gap holes arranged in an array. The ratio of the second preset number to the first preset number is between 25% and 50%.
[0016] In some embodiments, the formation of a first gap hole array penetrating the first support layer; the first gap hole array includes a plurality of first gap holes arranged in an array, including:
[0017] A first gap hole array is formed that penetrates the first support layer; wherein the first gap hole array includes a plurality of first gap hole rows and a plurality of first gap hole columns with equal spacing, and the first gap hole rows and the first gap hole columns are perpendicular to each other.
[0018] In some embodiments, the formation of a first gap hole array penetrating the first support layer; the first gap hole array includes a plurality of first gap holes arranged in an array, including:
[0019] A first gap hole array is formed that penetrates the first support layer; wherein the gap hole array includes a plurality of first gap hole rows and a plurality of first gap hole columns with equal spacing, the first gap hole rows and the first gap hole columns are arranged at a first preset angle, the first preset angle being less than 90°.
[0020] In some embodiments, the formation of a first gap hole array penetrating the first support layer; the first gap hole array includes a plurality of first gap holes arranged in an array, including:
[0021] A first gap hole array is formed that penetrates the first support layer; the first gap hole array includes multiple rows of combined holes and multiple columns of combined holes with equal spacing, the rows of combined holes and the columns of combined holes each include multiple combined holes, and each combined hole includes multiple first gap holes that are interconnected.
[0022] In some embodiments, the formation of a first gap hole array penetrating the first support layer; the first gap hole array includes a plurality of first gap holes arranged in an array, including:
[0023] A first gap hole array is formed that penetrates the first support layer; the first gap hole array includes multiple rows of combined units and multiple columns of combined units with equal spacing, the rows of combined units and the columns of combined units each include multiple combined units, each combined unit includes a first combined hole and a second combined hole arranged at a second preset angle, the first combined hole and the second combined hole each include multiple first gap holes that are interconnected, and the first combined hole and the second combined hole are not interconnected.
[0024] In some embodiments, the stacked structure further includes a second sacrificial layer and a second support layer located between the substrate and the first sacrificial layer, wherein the second sacrificial layer is located between the substrate and the second support layer;
[0025] The removal of the first sacrificial layer through the first gap hole array includes:
[0026] The first sacrificial layer is removed through the first gap hole array, exposing part of the first electrode layer and the second support layer;
[0027] The method for forming the memory further includes:
[0028] After the first sacrificial layer is removed through the first gap hole array, a second gap hole array is formed that penetrates the second support layer; wherein the second gap hole array includes a plurality of second gap holes arranged in an array, and each second gap hole is located between four adjacent first electrode layers;
[0029] The second sacrificial layer is removed by the second gap hole array, exposing the remaining first electrode layer.
[0030] In some embodiments, the substrate includes a wafer;
[0031] The substrate is provided; wherein a transistor pillar array is formed on the surface of the substrate, including:
[0032] Provide wafers;
[0033] Partial etching is performed on the wafer from its first surface to form a grid-like etch trench and a transistor pillar array; wherein the transistor pillar array includes a plurality of transistor pillars arranged in an array, each transistor pillar being located at each grid point of the grid-like trench, and the first preset thickness of the transistor pillar is less than the initial thickness of the wafer; the first surface is perpendicular to the thickness direction of the wafer;
[0034] Insulating material is deposited in the grid-like etched trenches to form an insulating layer surrounding each of the transistor pillars;
[0035] The insulating layer is etched to expose one sidewall of each of the transistor pillars;
[0036] A gate oxide layer and a gate are sequentially formed on the exposed sidewall of each transistor pillar;
[0037] A source is formed at one of the first or second ends of the transistor pillar, and a drain is formed at the other end; wherein the first end and the second end are opposite ends of the transistor pillar in the wafer thickness direction, and the first end is located on the first surface of the wafer, and the transistor pillar between the source and the drain constitutes the channel region of the transistor.
[0038] According to a second aspect of this application, a memory is provided, comprising:
[0039] The substrate includes a wafer, in which a transistor pillar array is disposed, the transistor pillar array including a plurality of transistor pillars arranged in an array along a first surface perpendicular to the thickness direction of the wafer;
[0040] A first support layer is disposed on the wafer parallel to a first surface of the wafer. The first support layer includes a plane disposed parallel to the first surface of the wafer and a side surface perpendicular to the plane.
[0041] A capacitor array, the capacitor array comprising:
[0042] The first electrode layer array includes a plurality of first electrode layers penetrating the first support layer, wherein the plurality of first electrode layers are disposed in a one-to-one correspondence with the transistor pillars, and the first electrode layers are electrically connected to the transistor pillars.
[0043] The dielectric layer includes a first portion covering the surface of the first electrode layer and the plane of the first support layer, and a plurality of second portions covering the sides of the first support layer, each second portion being located between four adjacent first electrode layers, and the plurality of second portions being arranged in an array; and,
[0044] The second electrode layer covers the surface of the dielectric layer.
[0045] In some embodiments, the substrate further includes a first contact plug array, the first contact plug array including a plurality of first contact plugs arranged in an array, each first contact plug being located between the transistor pillar and the first electrode layer and electrically connected to the transistor pillar and the first electrode layer.
[0046] The memory formation method provided in this application proposes a scheme to form a first gap hole array by taking a first gap hole formed between four adjacent first electrode layers as a unit. The first gap hole array can remove the first sacrificial layer relatively quickly, while ensuring that the remaining first support layer can better support the capacitor array, reducing the probability of capacitor skew and ensuring that the memory has good storage performance. Attached Figure Description
[0047] Figure 1A This is a schematic diagram of the structure of a DRAM memory cell formed using planar transistors, provided in an embodiment of this application.
[0048] Figure 1B This is a schematic diagram of the structure of a DRAM memory cell formed using buried channel transistors, provided in an embodiment of this application.
[0049] Figure 2 This is a schematic diagram of the structure of a DRAM memory cell formed using vertical channel transistors, provided in an embodiment of this application.
[0050] Figure 3 A schematic flowchart illustrating a method for forming a memory according to an embodiment of this application;
[0051] Figure 4 This is a schematic diagram of a DRAM memory array formed using vertical channel transistors, provided as an embodiment of this application.
[0052] Figures 5A to 5I This is a partial structural cross-sectional view of a capacitor obtained using the capacitor array formation method provided in the embodiments of this application;
[0053] Figure 6A A schematic diagram illustrating the arrangement of a first gap hole array according to an embodiment of this application;
[0054] Figure 6B A schematic diagram illustrating another arrangement of the first gap hole array provided in an embodiment of this application;
[0055] Figure 6C A schematic diagram illustrating another arrangement of the first gap hole array provided in an embodiment of this application;
[0056] Figure 6D A schematic diagram illustrating another arrangement of the first gap hole array provided in an embodiment of this application;
[0057] Figure 6E A schematic diagram illustrating another arrangement of the first gap hole array provided in an embodiment of this application;
[0058] Figure 6FA schematic diagram illustrating yet another arrangement of the first aperture array provided in an embodiment of this application;
[0059] Figure 6G A schematic diagram illustrating yet another arrangement of the first aperture array provided in an embodiment of this application;
[0060] Figure 6H A schematic diagram illustrating yet another arrangement of the first aperture array provided in an embodiment of this application;
[0061] Figure 7 This is a schematic flowchart illustrating a method for forming a transistor pillar array according to an embodiment of this application.
[0062] Explanation of reference numerals in the attached figures:
[0063] 200: Substrate; 210: Shallow trench isolation region; 220: Active region; 230: Transistor pillar; 231: First terminal; 232: Second terminal; 233: Gate oxide layer; 234: Gate; 2341: First sub-gate; 2342: Second sub-gate; 235: Insulating isolation layer; 240: First contact plug; 250: Second contact plug; 260: Bit line;
[0064] 300: Capacitor array; 311: First sacrificial layer; 312: First support layer; 313: Second sacrificial layer; 314: Second support layer; 320: Capacitor hole; 330: First electrode layer; 340: Filling layer; 350: First gap hole; 360: Second gap hole; 370: Dielectric layer; 380: Second electrode layer. Detailed Implementation
[0065] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0066] In the description of this application, it should be understood that the terms "length", "width", "depth", "upper", "lower", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0067] The transistors used in mainstream memory include planar transistors and buried channel array transistors (BCAT). However, regardless of whether it is a planar transistor or a buried channel array transistor, in terms of structure, the source and drain are located on the horizontal sides of the gate.
[0068] Figure 1AThis is a schematic diagram of the structure of a DRAM memory cell formed using planar transistors, provided in an embodiment of this application. Figure 1B This is a schematic diagram of the structure of a DRAM memory cell formed using buried channel transistors, provided as an embodiment of this application. Figure 1A and 1B As shown, the source (or drain) 101 and drain (or source) 103 of the transistor in the DRAM memory cell are located on opposite sides of the gate 102. Thus, the source and drain occupy different positions on the horizontal plane, resulting in a large horizontal area for both planar transistors and buried channel transistors, limiting the implementation to 6F. 2 The cell layout of the structure (F is the characteristic dimension).
[0069] As electronic products become increasingly integrated, the storage density requirements for dynamic random access memory (DRAM) are also increasing. In DRAM, transistors have evolved from planar and buried designs to vertical channel transistors. Figure 2 This is a schematic diagram of the structure of a DRAM memory cell formed using vertical channel transistors, provided as an embodiment of this application. Figure 2 As shown, the source (or drain) 101 and drain (or source) 103 of the vertical channel transistor are located on the upper and lower sides of the gate 102, respectively. Thus, on the horizontal plane, the source and drain share a single location, enabling 4F... 2 The cell layout of the structure greatly improves storage density. However, as... Figure 2 As shown, as the area of a single memory cell decreases, the radial dimension of the capacitor also shrinks. In order to ensure that the capacitance value of the capacitor meets the requirements, the capacitor becomes increasingly taller, which leads to a continuously increasing risk of capacitor misalignment during the manufacturing process.
[0070] In view of this, embodiments of this application provide a method for forming a memory to improve the support of the capacitor and reduce the probability of the capacitor becoming misaligned. Figure 3 This is a schematic flowchart illustrating a method for forming a memory according to an embodiment of this application. Figure 3 As shown, the method for forming a memory provided in this application includes the following steps:
[0071] S100: Provides a substrate; wherein, a transistor pillar array is formed on the surface of the substrate, the transistor pillar array including a plurality of transistor pillars arranged in an array along a direction perpendicular to the surface of the substrate;
[0072] S200: Forming a stacked structure covering a transistor pillar array; wherein the stacked structure includes a first sacrificial layer and a first support layer stacked sequentially along a direction away from the substrate;
[0073] S300: Forming a capacitor hole array that penetrates the stacked structure; wherein, the capacitor hole array includes multiple capacitor holes arranged in an array, the multiple capacitor holes are arranged one-to-one with multiple transistor pillars, and the capacitor holes expose the transistor pillars.
[0074] S400: A first electrode layer and a filling layer are sequentially formed on the inner wall of the capacitor hole; wherein, the first electrode layer is electrically connected to the transistor pillar;
[0075] S500: Forming a first gap hole array penetrating the first support layer; wherein the first gap hole array includes a plurality of first gap holes arranged in an array, and each first gap hole is located between four adjacent first electrode layers;
[0076] S600: The first sacrificial layer is removed through the first gap hole array to expose the first electrode layer;
[0077] S700: A dielectric layer and a second electrode layer covering the first electrode layer are formed sequentially to form a capacitor array.
[0078] Please refer to the following. Figure 4 , Figures 5A to 5I The method for forming a memory provided in the embodiments of this application will be described in detail. Figure 4 This is a schematic diagram of a DRAM memory array formed using vertical channel transistors, provided as an embodiment of this application. Figure 5A-5I This is a partial structural schematic diagram of a capacitor obtained by the capacitor array formation method provided in the embodiments of this application.
[0079] In step S100, such as Figure 4 As shown, the substrate 200 includes a wafer, which includes a first surface and a second surface disposed opposite to each other, wherein the first surface and the second surface are perpendicular to the thickness direction of the wafer. Here, the thickness direction of the wafer is defined as the Z-direction. That is, both the first surface and the second surface are perpendicular to the Z-direction.
[0080] A transistor pillar array is formed in the wafer. The transistor pillar array includes multiple rows of transistor pillars and multiple columns of transistor pillars with equal spacing. The rows and columns of transistor pillars each include multiple transistor pillars 230 arranged along a direction perpendicular to the first surface of the wafer.
[0081] Here, transistor pillar rows are defined to extend along a first direction, and transistor pillar columns are defined to extend along a second direction. Both the first and second directions are parallel to the first surface of the wafer and are perpendicular to each other. Further, the first direction is defined as the X direction, and the second direction is defined as the Y direction.
[0082] In some embodiments, the row spacing between adjacent transistor pillar rows is not equal to the column spacing between adjacent transistor pillar columns, such that the transistor pillar array includes a plurality of transistor pillars 230 arranged in a rectangular array. In some embodiments, the row spacing between adjacent transistor pillar rows is equal to the column spacing between adjacent transistor pillar columns, such that the transistor pillar array includes a plurality of transistor pillars 230 arranged in a square array. The memory formation method provided in this application is applicable to both types of transistor pillar arrays.
[0083] See further Figure 4 Each transistor pillar 230 includes a first end 231 and a second end 232 disposed opposite to each other in its thickness direction (Z direction). The first end 231 is located on the first surface of the wafer. One of the first end 231 and the second end 232 forms the source, and the other forms the drain. The transistor pillar 230 between the source and drain constitutes the channel region of the transistor. A gate oxide layer 233 and a gate 234 are sequentially formed on one sidewall of the transistor pillar 230, thereby constituting a transistor in a memory cell.
[0084] In step S200, such as Figure 5A As shown, a stacked structure covering a transistor pillar array is formed. The stacked structure includes a first sacrificial layer 311 and a first support layer 312 stacked sequentially in a direction away from the substrate.
[0085] The material of the first sacrificial layer 311 includes, but is not limited to, any one of phosphosilicate glass (PSG), borosilicate glass (BPSG), or other silicon oxides. The material of the first support layer 312 includes, but is not limited to, nitrides such as silicon nitride, silicon carbide nitride, silicon oxynitride, or silicon boronitride nitride.
[0086] In some embodiments, the first sacrificial layer 311 and the first support layer 312 may be sequentially formed on the substrate by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).
[0087] In some embodiments, the stacked structure further includes a second sacrificial layer 313 and a second support layer 314 located between the substrate 200 and the first sacrificial layer 311, with the second sacrificial layer 313 located between the second support layer 314 and the substrate 200. In subsequent processes such as removing the second sacrificial layer 313 and forming the dielectric layer 370 and the second electrode layer 380, the second support layer 314, together with the first support layer 312, can support the first electrode layer 330, improving the support for the first electrode layer 330 and reducing the probability of the first electrode layer 330 becoming skewed.
[0088] The material of the second sacrificial layer 313 includes, but is not limited to, phosphosilicate glass, borosilicate glass, or any other silicon oxide. The material of the second support layer 314 includes, but is not limited to, nitrides such as silicon nitride, silicon carbide nitride, silicon oxynitride, or silicon boronitride nitride. Here, the material of the second sacrificial layer 313 can be the same as that of the first sacrificial layer 311, and the material of the second support layer 314 can be the same as that of the first support layer 312. Thus, the second support layer 314 can be etched using the same process as etching the first support layer 312, and the second sacrificial layer 313 can be removed using the same process as removing the first sacrificial layer 311, thereby simplifying the process and shortening the process cycle.
[0089] It should be noted that in some other embodiments, the stacked structure may include multiple layer groups consisting of sacrificial layers and support layers. For example, it may also include a third support layer and a third sacrificial layer located below the second sacrificial layer 313. Setting multiple layer groups can provide multiple support layers, thereby improving the support for the first electrode layer 330, but it is not advisable to set too many layer groups.
[0090] In step S300, such as Figure 5B As shown, multiple capacitor holes 320 are formed through the stacked structure. The multiple capacitor holes 320 are arranged one-to-one with multiple transistor pillars, and the capacitor holes 320 expose the transistor pillars.
[0091] like Figure 5C As shown, corresponding to the transistor pillar array, the capacitor hole array also includes multiple equally spaced rows of capacitor holes and multiple equally spaced columns of capacitor holes. The rows of capacitor holes extend along a first direction (X direction), and the columns of capacitor holes extend along a second direction (Y direction). In some embodiments, the row spacing between adjacent rows of capacitor holes is equal to the column spacing between adjacent columns of capacitor holes, and the capacitor hole array includes multiple capacitor holes 320 arranged in a square array.
[0092] In some embodiments, the capacitor hole 320 can be formed by a room-temperature plasma dry etching process or a low-temperature plasma dry etching process. Dry etching can use gases such as nitrogen trifluoride (NF3) and carbon tetrafluoride (CF4) as etchants to form the capacitor hole 320.
[0093] In step S400, such as Figure 5D As shown, a first electrode layer 330 and a filling layer 340 are sequentially deposited along the radial direction of the capacitor hole 320 on the inner wall of the capacitor hole 320.
[0094] like Figure 5EAs shown, corresponding to the capacitor aperture array, a first electrode layer array is formed after depositing a first electrode layer 330 and a filler layer 340 on the inner wall of the capacitor aperture 320. The first electrode layer array also includes multiple equally spaced first electrode layer rows and multiple equally spaced first electrode layer columns. The first electrode layer rows extend along a first direction (X direction), and the first electrode aperture columns extend along a second direction (Y direction).
[0095] In some embodiments, the first electrode layer 330 may be formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The material of the first electrode layer 330 includes, but is not limited to, metal nitrides or metal silicides, such as titanium nitride. Here, the top of the first electrode layer 330 is flush with the top of the first support layer 312.
[0096] In some embodiments, the filler layer 340 may be formed by physical vapor deposition, chemical vapor deposition, or atomic layer deposition. The material of the filler layer 340 includes, but is not limited to, silicon oxide.
[0097] In steps S500 and S600, such as Figure 5F As shown, a plurality of first gap holes 350 are formed through the first support layer 312, and the first sacrificial layer 311 is removed through the plurality of first gap holes 350 to expose the first electrode layer 330.
[0098] In some embodiments, before forming the first gap hole 350, a mask layer (not shown in the figure) covering the upper surface of the first support layer 312, the first electrode layer 330 and the filling layer 340 is deposited, then the mask layer is patterned, and then based on the patterned mask layer, a portion of the first support layer 312 is removed by a dry etching process or a wet etching process to form a plurality of first gap holes 350.
[0099] It is understandable that the size, number, and arrangement of the first gap hole 350 affect the removal speed of the first sacrificial layer 311, the support of the remaining first support layer 312 for the first electrode layer 330, and the exposure difficulty of the mask layer.
[0100] For example, the larger size and greater number of the first gap holes 350 make it easier to completely remove the first sacrificial layer 311. However, this results in a smaller area of the remaining first support layer 312 after the formation of the first gap holes, leading to poorer support for the first electrode layer 330 and reduced support for the first electrode layer 330. Furthermore, if the spacing between the first gap holes 350 is too small, exposure becomes more difficult in the patterned mask layer process.
[0101] For example, the total area of the multiple first gap holes 350 is small, resulting in a slow rate of removing the first sacrificial layer 311 and affecting the production schedule.
[0102] In view of this, refer to Figure 5G In this embodiment, each first gap hole 350 is located between four adjacent first electrode layers 330, and the multiple first gap holes 350 are arranged in an array to form a first gap hole array. In this application, firstly, the location of the first gap holes 350 between four adjacent first electrode layers 330 limits the size of the first gap holes 350. Secondly, the array arrangement of the multiple first gap holes 350 standardizes the arrangement of the first gap holes 350, ensuring that the multiple first gap holes 350 are evenly distributed on the first support layer 312. This allows the remaining first support layer 312 forming the first gap hole array to support the first electrode layers 330 more evenly and balancedly, reducing the probability of the first electrode layers 330 becoming skewed and ensuring that the final capacitor has good performance.
[0103] This application proposes a scheme to form a first gap hole array by taking the formation of a first gap hole 350 between four adjacent first electrode layers 330 as a unit. This scheme can more standardize the design of the arrangement of multiple first gap holes 350, calculate and adjust the total area of multiple first gap holes 350, shorten the design cycle, and obtain a better opening scheme.
[0104] In some embodiments, the capacitor hole array includes a first preset number of capacitor holes 320, and the first gap hole array includes a second preset number of first gap holes 350, wherein the ratio of the second preset number to the first preset number is between 25% and 50%. This ensures that the first sacrificial layer 311 can be removed relatively quickly and completely while ensuring that the remaining first support layer 312 can better support the first electrode layer 330, achieving a better compromise between the two.
[0105] It is understood that 25% to 50% is a preferred range for the ratio of the second preset quantity to the first preset quantity provided in this application, and does not mean that the ratio of the second preset quantity to the first preset quantity must be between 25% and 50%. For example, when the height of the first electrode layer is high and the support effect is required to be high, the ratio of the second preset quantity to the first preset quantity can be set to be less than 25%, and the removal time of the first sacrificial layer can be appropriately extended to obtain better support for the first electrode layer. Alternatively, to improve production efficiency, the ratio of the second preset quantity to the first preset quantity can be set to be greater than 50%, and the support effect of the remaining first support layer on the first electrode layer can be appropriately sacrificed to obtain higher production efficiency.
[0106] In some embodiments, the first gap holes 350 expose the sidewalls of four adjacent first electrode layers 330, thereby increasing the surface area of the first electrode layers 330 and thus improving the overall capacitance and performance of the capacitor. Simultaneously, to improve the support of the first electrode layers 330, up to three first gap holes 350 are located around the same electrode layer, so that the outer wall of each electrode layer is at least partially in contact with the first support layer 312, thereby reducing the probability of the first electrode layers 330 becoming misaligned under the support of the first support layer 312.
[0107] In some embodiments, the first sacrificial layer 311 can be removed by a wet etching process or the like. The wet etching process is isotropic, allowing the entire first sacrificial layer 311 to be removed through the first aperture array. It should be noted that the first sacrificial layer 311, the first support layer 312, and the first electrode layer 330 have a large etching selectivity; therefore, the removal of the first sacrificial layer 311 causes minimal or no damage to the first support layer 312 and the first electrode layer 330.
[0108] In some embodiments, such as Figure 5H As shown, after removing the first sacrificial layer 311, a plurality of second gap holes 360 are formed through the second support layer 314. Each second gap hole 360 is located between four adjacent first electrode layers 330. The plurality of second gap holes 360 are arranged in an array to form a second gap hole array.
[0109] Here, it can be understood that the second gap hole 360 is formed through the first gap hole 350. Therefore, the second gap hole 360 can be formed under each first gap hole 350, forming second gap holes 360 that correspond one-to-one with the multiple first gap holes 350, making the second gap hole array the same as the first gap hole array. Alternatively, the second gap hole 360 can be formed only under some of the first gap holes 350, making the second gap hole array different from the first gap hole array.
[0110] In some embodiments, a room temperature plasma dry etching process or a low temperature plasma dry etching process can be used to remove part of the second support layer 314 through the first gap hole 350 to form the second gap hole 360.
[0111] After the second gap hole array is formed, the second sacrificial layer 313 is removed by wet etching through the second gap hole array, exposing the entire first electrode layer 330 and the remaining surface of the substrate 200.
[0112] After exposing the entire first electrode layer 330, step S500 is performed to form a dielectric layer 370 covering the first electrode layer 330, and then to form a second electrode layer 380 covering the dielectric layer 370. The plurality of first electrode layers 330, dielectric layers 370 and second electrode layers 380 form a capacitor array 300.
[0113] In some embodiments, such as Figure 5I As shown, a dielectric layer 370 is formed covering the surface of the first electrode layer 330, the remaining first support layer 312, the remaining second support layer 314, the exposed fill layer 340, and the remaining surface of the substrate 200, and then a second electrode layer 380 is formed covering the dielectric layer 370.
[0114] In some embodiments, the dielectric layer 370 and the second electrode layer 380 may be formed by physical vapor deposition, chemical vapor deposition or atomic layer deposition processes.
[0115] In some embodiments, the material of the dielectric layer 370 may include at least one of the following: zirconium oxide, hafnium oxide, zirconium titanate, ruthenium oxide, antimony oxide, and aluminum oxide. The material of the second electrode layer 380 may include at least one of the following: metal nitride and metal silicide.
[0116] In this embodiment, the first sacrificial layer can be removed quickly through the first gap hole array, while ensuring that the remaining first support layer forming the first gap hole array can better support the first electrode layer array, reducing the probability of the first electrode layer becoming skewed, reducing the impact on the electrical connection between the first electrode layer and the transistor pillar, and ensuring that the memory has good storage performance.
[0117] To achieve better capacitor support, this application further provides various arrangements of the first gap hole array. The following describes these arrangements in conjunction with... Figures 6A to 6H The arrangement of the first gap hole array provided in the embodiments of this application is further explained.
[0118] In some embodiments, see Figure 6A Each first gap hole 350 exposes a portion of the outer wall of four adjacent first electrode layers 330. The first gap hole array includes multiple rows and columns of first gap holes at equal intervals. The rows of first gap holes extend along a first direction (X direction), and the columns and rows of first gap holes are perpendicular to each other. Further, every four capacitor holes 320 correspond to one first gap hole 350, which is equivalent to a second preset number of first gap holes 350 in the first gap array, and the ratio of this number to the first preset number of capacitor holes 320 in the capacitor hole array is 25%. This arrangement ensures good support of the remaining first support layer 312 for the first electrode layer 330 array and reduces exposure difficulty during the mask layer patterning process.
[0119] In some embodiments, the first gap hole array includes a plurality of equally spaced first gap hole rows and a plurality of equally spaced first gap hole columns. The first gap hole rows extend along a first direction (X direction), and the first gap hole columns and first gap hole rows are arranged at a first preset angle, which is less than 90°. For example, see [link to example]. Figure 6B The first gap column and the first gap hole row are set at a 45° angle, which increases the second preset number, making the ratio of the second preset number to the first preset number 50%, which reduces the difficulty of removing the first sacrificial layer through the first gap hole array and allows the first sacrificial layer to be removed more quickly.
[0120] In some embodiments, the first gap hole array includes a plurality of equally spaced rows of combined holes and a plurality of equally spaced columns of combined holes, wherein the rows of combined holes and the columns of combined holes are perpendicular to each other, or the rows of combined holes and the columns of combined holes are arranged at a third preset angle, the third preset angle being less than 90°; wherein the rows of combined holes and the columns of combined holes each include a plurality of combined holes, and each combined hole includes a plurality of interconnected first gap holes 350. Here, the number of first gap holes 350 can be set to two to four.
[0121] Reference Figure 6C Two first gap holes 350 arranged side-by-side along the first direction (X direction) are interconnected to form a combined hole. The row of combined holes extends along the first direction (X direction), and the third preset angle between the row of combined holes and the combined hole row is approximately 63°. Further, every six capacitor holes 320 correspond to two first gap holes 350, which is equivalent to a second preset number to a first preset number ratio of 33.3%. This arrangement makes removing the first sacrificial layer through the first gap hole array easier and faster, while ensuring good support of the remaining first support layer 312 for the first electrode layer 330 array, and reducing exposure difficulty in the mask layer patterning process.
[0122] Reference Figure 6D Two first gap holes 350 arranged side-by-side along the second direction (Y direction) are interconnected to form a combined hole. The row of combined holes extends along the first direction (X direction), and the third preset angle between the row of combined holes and the combined hole row is approximately 26°. Further, every six capacitor holes 320 correspond to two first gap holes 350, which is equivalent to a second preset number to a first preset number ratio of 33.3%. This arrangement makes removing the first sacrificial layer through the first gap hole array easier and faster, while ensuring good support of the remaining first support layer for the first electrode layer 330 array (312), and reducing exposure difficulty in the mask layer patterning process.
[0123] Reference Figure 6EThree first gap holes 350 arranged side-by-side along the first direction (X direction) are interconnected to form a combined hole. The row of combined holes extends along the first direction (X direction), and the row of combined holes and the combined hole row are perpendicular to each other. Furthermore, every eight capacitor holes 320 correspond to three first gap holes 350, which is equivalent to a ratio of 37.5% between the second preset number and the first preset number. This arrangement makes removing the first sacrificial layer through the first gap hole array easier and faster.
[0124] Reference Figure 6F Five first gap holes 350 arranged in a cross shape are interconnected to form a combined hole. The row of combined holes extends along the first direction (X direction), and the third preset angle between the row of combined holes and the combined hole array is approximately 45°. Furthermore, every eight capacitor holes 320 correspond to five first gap holes 350, which is equivalent to a second preset quantity to a first preset quantity ratio of 62.5%. This arrangement makes removing the first sacrificial layer through the first gap hole array easier and faster.
[0125] In some embodiments, the gap hole array includes multiple rows of combined units with equal spacing and multiple columns of combined units with equal spacing. The rows and columns of combined units each include multiple combined units. Each combined unit includes a first combined hole and a second combined hole arranged at a second preset angle. The first combined hole and the second combined hole each include multiple first gap holes 350 that are interconnected, and the first combined hole and the second combined hole are not interconnected.
[0126] Specifically, refer to Figure 6G Three first gap holes 350 arranged in an L-shape are interconnected to form a first combined hole, and a second combined hole is arranged rotationally symmetrically with the first combined hole. The first combined hole and the second combined hole constitute a combined unit. Multiple combined units constitute a row of combined units and a column of combined units, wherein the row of combined units extends along a first direction (X direction). The column of combined units and the row of combined units can be perpendicular to each other, or the column of combined units and the row of combined units can be arranged at a fourth preset angle (the column of combined units is not shown in the figure). Further, every five capacitor holes 320 correspond to two first gap holes 350, which is equivalent to a second preset number to a first preset number ratio of 40%. This arrangement makes it easier to remove the first sacrificial layer through the array of first gap holes, and allows for faster removal of the first sacrificial layer.
[0127] It should be noted that this application Figures 6A to 6G In the illustrated embodiment, each first electrode layer 330 is surrounded by at least one first gap hole 350. However, in other embodiments, some first electrode layers 330 may not have a first gap hole 350 around them. For example, in Figure 6H In comparison Figure 6AAlong the first gap hole, the even-numbered first gap holes 350 are removed, leaving only the odd-numbered first gap holes 350, so that there are no first gap holes 350 around part of the first electrode layer 330, and the ratio of the second preset number to the first preset number is 18.75%, thus further improving the support of the first electrode layer 330.
[0128] The above embodiments of this application only illustrate some of the arrangements of the first gap hole array, and do not exhaust all arrangements of the first gap hole array. Any first gap hole array that satisfies the requirement of uniform arrangement of multiple first gap holes is within the protection scope of this application.
[0129] Furthermore, in some embodiments of this application, a method for forming a transistor pillar array in a substrate 200 is also provided. Figure 7 This is a schematic flowchart illustrating a method for forming a transistor pillar array according to an embodiment of this application. See also... Figure 7 The method for forming a transistor pillar array provided in this application includes the following steps:
[0130] S101: Provides wafers;
[0131] S102: Partial etching is performed on the first surface of the wafer to form a grid-like etching trench and a transistor pillar array; wherein, the transistor pillar array includes multiple transistor pillars arranged in an array, each transistor pillar is located at each grid point of the grid-like trench, and the first preset thickness of the transistor pillar is less than the initial thickness of the wafer; the first surface is perpendicular to the thickness direction of the wafer.
[0132] S103: Deposit insulating material in the grid-like etched trenches to form an insulating layer surrounding each transistor pillar;
[0133] S104: Etch the insulating layer to expose one sidewall of each transistor pillar;
[0134] S105: A gate oxide layer and a gate are sequentially formed on the exposed sidewall of each transistor pillar;
[0135] S106: A source is formed at one of the first or second ends of the transistor pillar, and a drain is formed at the other end; wherein the first end and the second end are opposite ends of the transistor pillar in the wafer thickness direction, and the first end is located on the first surface of the wafer, and the transistor pillar between the source and the drain constitutes the channel region of the transistor.
[0136] In step S101, the constituent materials of the wafer may include semiconductor materials such as silicon and germanium.
[0137] In step S102, the transistor pillar array can be any type of transistor pillar array as described above, such as including multiple transistor pillars arranged in a rectangular array, or including multiple transistor pillars arranged in a square array.
[0138] See Figure 4 Each transistor pillar 230 has a first preset thickness A in the wafer thickness direction (Z direction), and the first preset thickness A is less than the initial thickness of the wafer.
[0139] In this step, plasma dry etching or reactive ion etching can be used to etch the wafer. It is worth noting that in this embodiment, the etching of the wafer is partial etching along the thickness direction (Z direction) of the wafer, and the etching process will not penetrate the wafer.
[0140] In step S103, the insulating material includes, but is not limited to, silicon oxide.
[0141] In step S104, see Figure 4 The transistor pillar 230 includes a first sidewall and a second sidewall disposed opposite each other along a first direction (X direction). An insulating layer is etched to expose the first sidewall of each transistor pillar 230.
[0142] For example, on the first surface of the wafer, starting from the upper edge of the first sidewall, a partial etching process is performed on the insulating layer to remove the insulating layer having a first preset size in the first direction (X direction) and a second preset thickness in the wafer thickness direction (Z direction), forming a plurality of first etched grooves arranged side by side along the first direction (X direction). Each first etched groove correspondingly exposes the first sidewall of a plurality of transistor pillars 230 arranged side by side along the second direction (Y direction).
[0143] In some embodiments, the first etched groove correspondingly exposes the bottom wall of the etched trench and the second sidewall of the adjacent transistor pillar 230. That is, the first etched groove exposes the etched trench located between adjacent transistor pillars 230.
[0144] In step S105, in some embodiments, a gate oxide layer 233 is formed on the first sidewall of the transistor pillar 230 by in-situ oxidation or deposition; a conductive material is deposited in the first etched groove where the gate oxide layer 233 is formed to form a conductive layer; the conductive layer is etched along the thickness direction (Z direction) of the wafer to remove part of the thickness of the conductive layer and form the gate 234 (i.e., word line).
[0145] In some embodiments, a gate oxide layer 233 is formed on the first sidewall of the transistor pillar 230, the bottom wall of the etch trench between adjacent transistor pillars 230, and the second sidewall of adjacent transistor pillars 230, and a gate 234 is formed within the gate oxide layer 233.
[0146] The material of the gate oxide layer 233 includes, but is not limited to, oxides, such as hafnium oxide and silicon oxide. The material of the gate 234 includes, but is not limited to, polysilicon and metals, including tungsten, copper, cobalt, etc.
[0147] In some embodiments, the gate 234 includes a first sub-gate 2341 located at the bottom of a first etched groove and a second sub-gate 2342 located on the first sub-gate 2341, wherein the first sub-gate 2341 and the second sub-gate 2342 are made of different materials. Optionally, the first sub-gate 2341 is made of polysilicon, and the second sub-gate 2342 is made of a metal, such as tungsten.
[0148] In some embodiments, after forming the gate 234, the forming method further includes: partially etching the second sidewall of the transistor pillar 230 to form a second etched groove; and filling the second etched groove to form an insulating isolation layer 235.
[0149] For example, near the second sidewall on the upper surface of the transistor pillar 230, a portion of the transistor pillar 230 having a second preset size in the first direction (X direction) and a third preset thickness B in the wafer thickness direction (Z direction) is removed to create a second etched groove between the second sidewall of the transistor pillar 230 and the gate 234 of the adjacent transistor pillar 230. The second etched groove is disposed parallel to the second direction (Y direction). The third preset thickness B may be equal to or less than the first preset thickness A.
[0150] An insulating isolation layer 235 is provided to increase the distance between the gate 234 and the second sidewall of the adjacent transistor pillar 230, so that when a voltage is applied to the gate 234, carrier accumulation will not occur in the channel region of the adjacent transistor pillar 230, that is, a single-sided channel structure is formed in the transistor pillar 230. Figure 4 The structure enclosed in the dashed box C is a transistor with a single-sided channel structure.
[0151] The material of the insulating isolation layer 235 includes, but is not limited to, oxides. The materials of the insulating isolation layer 235 and the gate oxide layer 233 can be the same or different.
[0152] In step S106, ion implantation is performed on the first end 231 and the second end 232 of the transistor pillar 230 to form the source and drain, respectively. The transistor pillar 230 between the source and drain forms the channel region of the transistor pillar 230.
[0153] In some embodiments, the substrate 200 further includes a first contact plug array to increase the contact area between the transistor pillar 230 and the first electrode layer 330, thereby improving electrical connection reliability. Correspondingly, the method for forming the memory further includes:
[0154] After forming the transistor pillar 230 array, a first contact plug array is formed on the first side of the wafer; wherein, the first contact plug array includes a plurality of first contact plugs 240 arranged in an array, each first contact plug 240 being located between the first end 231 of the transistor pillar 230 and the first electrode layer 330, and electrically connecting the first end 231 of the transistor pillar 230 and the first electrode layer 330.
[0155] In some embodiments, the substrate 200 further includes bit lines 260. The method of forming the memory further includes:
[0156] Thin the second side of the wafer to expose the insulating layer;
[0157] Multiple bit lines 260 are formed on the second side of the thinned wafer. The bit lines 260 are parallel to the second side of the wafer and perpendicular to the extension direction of the gate 234. That is, the bit lines 260 extend along the first direction (X direction), and each bit line 260 connects to multiple transistor pillars 230 extending along the first direction (X direction).
[0158] It should be noted that when thinning the second side of a wafer, a protective structure can be bonded to the first side of the wafer first, and then the wafer can be flipped over so that the second side is facing up for thinning. The protective structure includes a protective layer for the wafer.
[0159] In some embodiments, the substrate 200 further includes a second contact plug array. The method of forming the memory further includes:
[0160] After forming the transistor pillar array, a second contact plug array is formed on the second side of the wafer; wherein the second contact plug array includes a plurality of second contact plugs 250 arranged in an array, each second contact plug 250 being located between the second end 232 of the transistor pillar 230 and the bit line 260, and electrically connected to the second end 232 of the transistor pillar 230 and the bit line 260.
[0161] It should be noted that this application does not limit the specific method of forming the wafer pillar array. In addition to the above-mentioned method of forming the wafer pillar array, it also includes other methods of forming transistor pillar arrays that are available in the prior art.
[0162] Based on the above-described method for forming a memory, embodiments of this application provide a memory that includes at least a substrate 200, a first support layer 312, and a capacitor array 300, wherein:
[0163] The substrate 200 includes a wafer, in which a transistor pillar array is provided. The transistor pillar array includes a plurality of transistor pillars 230 arranged in an array along a first surface perpendicular to the wafer. The first surface is perpendicular to the thickness direction (Z direction) of the wafer.
[0164] The first support layer 312 is disposed on the wafer parallel to the first surface of the wafer. The first support layer 312 includes a plane disposed parallel to the first surface of the wafer and a side surface perpendicular to the plane.
[0165] The capacitor array 300 includes a first electrode layer array, a dielectric layer 370, and a second electrode layer 380. The first electrode layer array includes a plurality of first electrode layers 330 penetrating the first support layer 312. The plurality of first electrode layers 330 are disposed one-to-one with transistor pillars 230 and are electrically connected to the transistor pillars 230. The dielectric layer 370 includes a first portion covering the surface of the first electrode layer 330 and the plane of the first support layer 312, and a plurality of second portions covering the side of the first support layer 312. Each second portion is located between four adjacent first electrode layers 330, and the plurality of second portions are arranged in an array. The second electrode layer 380 covers the surface of the dielectric layer 370.
[0166] In some embodiments, the memory further includes a second support layer 314 disposed between the wafer and the first support layer 312, parallel to a first surface of the wafer. A first portion of the dielectric layer 370 covers the plane of the second support layer 314, and a second portion of the dielectric layer 370 covers the side surface of the second support layer 314.
[0167] In some embodiments, the first side of the wafer is divided into a shallow trench isolation region 210 and an active region 220, the shallow trench isolation region 210 and the active region 220 being alternately arranged along a second direction (Y direction), each shallow trench isolation region 210 and each active region 220 extending along a first direction (X direction), wherein the shallow trench isolation region 210 is filled with insulating material to form an insulating layer; and a transistor pillar array is located in the active region 220.
[0168] In some embodiments, the transistor pillar 230 includes a first end 231 and a second end 232 disposed opposite to each other along the thickness direction (Z direction) of the wafer, wherein the first end 231 is located on a first surface of the wafer. One of the first end 231 and the second end 232 of the transistor pillar 230 forms a source, and the other forms a drain. The transistor pillar 230 between the first end 231 and the second end 232 forms a channel region of the transistor. A first electrode layer 330 of a capacitor is electrically connected to the first end 231 of the transistor pillar 230.
[0169] The transistor pillar 230 includes a first sidewall and a second sidewall disposed opposite to each other. Both the first and second sidewalls are perpendicular to the extending direction of the shallow trench isolation region 210, i.e., perpendicular to the first direction (X direction). A gate oxide layer 233 and a gate 234 are provided on the first sidewall of the transistor pillar 230. The gate 234, the gate oxide layer 233, the source, and the drain form a transistor.
[0170] In some embodiments, an insulating isolation layer 235 is provided between the gate 234 and the second sidewall of the adjacent transistor pillar 230 to form a transistor with a single-sided channel.
[0171] In some embodiments, the substrate 200 further includes a first contact plug array, which includes a plurality of first contact plugs 240 arranged in an array. Each first contact plug 240 is located between the transistor pillar 230 and the first electrode layer 330 and is electrically connected to the transistor pillar 230 and the first electrode layer 330.
[0172] In some embodiments, the substrate 200 further includes a plurality of bit lines 260, which are parallel to the second surface of the wafer and perpendicular to the extension direction of the gate 234, i.e., the bit lines 260 extend along a first direction (X direction). Furthermore, each bit line 260 connects to a plurality of transistor pillars 230 extending along the first direction (X direction).
[0173] In some embodiments, the substrate 200 further includes a second contact plug array comprising a plurality of second contact plugs 250 arranged in an array. Each second contact plug 250 is located between the transistor pillar 230 and the bit line 260 and is electrically connected to the transistor pillar 230 and the bit line 260.
[0174] This application provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A method for forming a memory, characterized in that, include: A substrate is provided; wherein a transistor pillar array is formed on the surface of the substrate, the transistor pillar array comprising a plurality of transistor pillars arranged in an array along a direction perpendicular to the surface of the substrate; A stacked structure covering the transistor pillar array is formed; wherein the stacked structure includes a first sacrificial layer and a first support layer stacked sequentially along a direction away from the substrate; A capacitor via array is formed that penetrates the stacked structure; wherein the capacitor via array includes a plurality of capacitor vias arranged in an array, the plurality of capacitor vias are disposed one-to-one with a plurality of transistor pillars, and the capacitor vias expose the transistor pillars; A first electrode layer and a filling layer are sequentially formed on the inner wall of the capacitor hole; wherein the first electrode layer is electrically connected to the transistor pillar; A first gap hole array is formed penetrating the first support layer; wherein the first gap hole array includes a plurality of combined holes arranged in an array, each of the combined holes includes a plurality of interconnected first gap holes, and each first gap hole is located between four adjacent first electrode layers. The first sacrificial layer is removed through the first gap hole array to expose the first electrode layer; A dielectric layer and a second electrode layer are sequentially formed to cover the first electrode layer, the filling layer, and the second electrode layer to form a capacitor array.
2. The method for forming a memory according to claim 1, characterized in that, The capacitor hole array includes a first preset number of capacitor holes; The formation of a first gap hole array penetrating the first support layer; wherein the first gap hole array includes a plurality of combined holes arranged in an array, including: A first gap hole array is formed that penetrates the first support layer. The first gap hole array includes a second preset number of the first gap holes arranged in an array. The ratio of the second preset number to the first preset number is between 25% and 50%.
3. The method for forming a memory according to claim 1, characterized in that, At most three of the first gap holes are located around the same first electrode layer.
4. The method for forming a memory according to claim 1, characterized in that, The formation of a first gap hole array penetrating the first support layer; wherein the first gap hole array includes a plurality of combined holes arranged in an array, including: A first gap hole array is formed that penetrates the first support layer; the first gap hole array includes multiple rows of combined holes and multiple columns of combined holes at equal intervals, wherein each row of combined holes and each column of combined holes includes multiple combined holes.
5. The method for forming a memory according to claim 4, characterized in that, The combined hole row and the combined hole column are perpendicular to each other; or, the combined hole row and the combined hole column are set at a third preset angle, the third preset angle being less than 90°.
6. The method for forming a memory according to claim 1, characterized in that, The formation of a first gap hole array penetrating the first support layer; wherein the first gap hole array includes a plurality of combined holes arranged in an array, including: A first gap hole array is formed that penetrates the first support layer; the first gap hole array includes multiple rows of combined units and multiple columns of combined units with equal spacing, the rows of combined units and the columns of combined units each include multiple combined units, each combined unit includes a first combined hole and a second combined hole arranged at a second preset angle, the first combined hole and the second combined hole each include multiple first gap holes that are interconnected, and the first combined hole and the second combined hole are not interconnected.
7. The method for forming a memory according to claim 1, characterized in that, The stacked structure further includes a second sacrificial layer and a second support layer located between the substrate and the first sacrificial layer, wherein the second sacrificial layer is located between the substrate and the second support layer; The removal of the first sacrificial layer through the first gap hole array includes: The first sacrificial layer is removed through the first gap hole array, exposing part of the first electrode layer and the second support layer; The method for forming the memory further includes: After the first sacrificial layer is removed through the first gap hole array, a second gap hole array is formed that penetrates the second support layer; wherein the second gap hole array includes a plurality of second gap holes arranged in an array, and each second gap hole is located between four adjacent first electrode layers; The second sacrificial layer is removed by the second gap hole array, exposing the remaining first electrode layer.
8. The method for forming a memory according to claim 1, characterized in that, The substrate includes a wafer; The substrate is provided; wherein a transistor pillar array is formed on the surface of the substrate, including: Provide wafers; Partial etching is performed on the wafer from its first surface to form a grid-like etching trench and a transistor pillar array; wherein the transistor pillar array includes a plurality of transistor pillars arranged in an array, each transistor pillar being located at each grid point of the grid-like etching trench, and the first preset thickness of the transistor pillar is less than the initial thickness of the wafer; the first surface is perpendicular to the thickness direction of the wafer; An insulating material is deposited in the grid-like etched trenches to form an insulating layer surrounding each of the transistor pillars; The insulating layer is etched to expose one sidewall of each of the transistor pillars; A gate oxide layer and a gate are sequentially formed on the exposed sidewall of each transistor pillar; A source is formed at one of the first and second ends of the transistor pillar, and a drain is formed at the other end; wherein the first end and the second end are opposite ends of the transistor pillar in the wafer thickness direction, and the first end is located on the first surface of the wafer, and the transistor pillar between the source and the drain constitutes the channel region of the transistor.
9. A memory, characterized in that, include: The substrate includes a wafer, in which a transistor pillar array is disposed, the transistor pillar array including a plurality of transistor pillars arranged in an array along a first surface perpendicular to the thickness direction of the wafer; A first support layer is disposed on the wafer parallel to a first surface of the wafer. The first support layer includes a plane disposed parallel to the first surface of the wafer and a side surface perpendicular to the plane. A capacitor array, the capacitor array comprising a first electrode layer array, a dielectric layer, and a second electrode layer; The first electrode layer array includes a plurality of first electrode layers penetrating the first support layer, and the plurality of first electrode layers are disposed in a one-to-one correspondence with the transistor pillars, and the first electrode layers are electrically connected to the transistor pillars; Multiple filler layers are located within the first electrode layer, and the side and bottom surfaces of the filler layers are in contact with the first electrode layer; A first gap hole array penetrates the first support layer. The first gap hole array includes a plurality of combined holes arranged in an array. Each of the combined holes includes a plurality of interconnected first gap holes, and each first gap hole is located between four adjacent first electrode layers. The dielectric layer includes a first portion covering the outer surface of the first electrode layer and the plane of the first support layer, and a plurality of second portions covering the side of the first support layer exposed by the first gap hole; The second electrode layer covers the surface of the dielectric layer.
10. The memory according to claim 9, characterized in that, The substrate further includes a first contact plug array, which includes a plurality of first contact plugs arranged in an array, each of the first contact plugs being located between the transistor pillar and the first electrode layer and electrically connected to the transistor pillar and the first electrode layer.