Display panel, manufacturing method thereof and display device

Abstract

The application provides a display panel, a manufacturing method thereof and a display device. The display panel comprises a substrate, a first light emitting unit, a second light emitting unit, a second pixel circuit and a first pixel circuit. The first pixel circuit drives the first light emitting unit to emit light, and the second pixel circuit drives the second light emitting unit to emit light. The second pixel circuit comprises a first via and a second via. A drain electrode in the second pixel circuit has a first connecting end, a second connecting end and a connecting body. The first via is used for electrically connecting the first connecting end and an active layer in the second pixel circuit. The connecting body extends in a first direction, and its length is greater than or equal to the length of a storage capacitor in the first direction. A first trace is located on the side of the source / drain electrode layer away from the substrate, and is electrically connected with the second connecting end through the second via and the anode of the second light emitting unit through a third via. The arrangement of the first trace can be optimized, and the light transmittance of the second display area can be improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to display panels, methods of manufacturing the same, and display devices. Background Technology

[0002] Currently, to improve the light transmittance of the high-transmittance display area corresponding to the under-display camera and ensure its image quality, only the EL device is retained in the high-transmittance display area, while the signal controlling the EL device to emit light is derived from the pixel circuitry in the non-transmittance display area. However, the poor light transmittance still results in relatively poor image quality from the under-display camera.

[0003] Therefore, further research is needed on display panels with under-display cameras. Summary of the Invention

[0004] The present invention aims to at least partially solve one of the technical problems in the related art. To this end, one object of the present invention is to provide a display panel in which the second display area (corresponding to the display area where the under-display camera is located) has high light transmittance.

[0005] In one aspect, the present invention provides a display panel. According to an embodiment of the present invention, the display panel includes a first display area and a second display area, the first display area being disposed on one side of the second display area, and the second display area being disposed directly opposite an under-display camera. The display panel includes a substrate, the first display area including a plurality of first light-emitting units disposed on the substrate, and a plurality of second pixel circuits and first pixel circuits arrayed along a first direction and a second direction. The first pixel circuits are used to drive the first light-emitting units to emit light, wherein the first direction and the second direction intersect. The second display area includes a plurality of second light-emitting units disposed on the substrate, the second pixel circuits being used to drive the second light-emitting units to emit light, both the second pixel circuits and the first pixel circuits including an active layer, a source / drain electrode layer, a gate line, and a storage capacitor. The second pixel circuit further includes a first via and a second via, and the source / drain electrode layer in the second pixel circuit includes a drain electrode. The drain electrode has a first connection terminal, a second connection terminal, and a connection body portion connecting the first connection terminal and the second connection terminal. The first via is used to electrically connect the first connection terminal and the active layer in the second pixel circuit. The connection body portion extends along a first direction, and the length of the connection body portion is greater than or equal to the length of the storage capacitor in the first direction. The gate line extends along a second direction and includes a reset control signal line, a scan signal line, and a light emission control signal line. The orthographic projection of the second via on the substrate overlaps with the orthographic projection of the scan signal line on the substrate. The display panel also includes multiple first traces located on the side of the source and drain electrode layers away from the substrate. The first traces are electrically connected to the second connection terminal through the second via and electrically connected to the anode of the second light emission unit through a third via in the second display area, so as to drive the second light emission unit to emit light.

[0006] Therefore, the drain electrode of the above structure and the connection position between the first trace and the drain electrode help to optimize the arrangement of the first trace, thereby reducing the area of ​​the anode of the second light-emitting unit electrically connected to the first trace, thereby increasing the light transmittance of the second display area, thereby increasing the amount of light entering the under-display camera and improving its photo-taking effect.

[0007] According to an embodiment of the present invention, the first pixel circuit further includes a fourth via and a fifth via. The fourth via is used to electrically connect the source / drain electrode layer in the first pixel circuit and the anode in the first light-emitting unit. The fifth via is used to electrically connect the source / drain electrode layer in the first pixel circuit and the active layer. The orthographic projection of the fourth via on the substrate and the orthographic projection of the fifth via on the substrate have an overlapping area.

[0008] According to an embodiment of the present invention, the orthographic projection of the connecting body portion on the substrate overlaps with the orthographic projection of the storage capacitor on the substrate.

[0009] According to an embodiment of the present invention, the first trace includes a first sub-trace and a second sub-trace in a first direction, and the orthographic projections of the first sub-trace and the second sub-trace on the substrate do not overlap with the orthographic projection of the connecting body portion on the substrate.

[0010] According to an embodiment of the present invention, the orthographic projection of the first sub-trace on the substrate overlaps with the orthographic projection of the sixth via on the substrate, and the sixth via is used to electrically connect the data writing transistor and the data line; the orthographic projection of the second sub-trace on the substrate overlaps with the orthographic projection of the seventh via on the substrate, and the seventh via is used to electrically connect the first end of the first connection portion of the source-drain electrode layer to the threshold compensation transistor, and the first connection portion is configured to connect the source-drain electrode of the threshold compensation transistor and the source-drain electrode of the driving transistor.

[0011] According to an embodiment of the present invention, the orthographic projection of the second connecting end in the second direction and the orthographic projection of the middle main body of the first connecting portion in the second direction have an overlapping area.

[0012] According to an embodiment of the present invention, the first trace further includes a third sub-trace in a first direction, and the orthographic projection of the third sub-trace on the substrate overlaps with the orthographic projection of the connecting body portion on the substrate.

[0013] According to an embodiment of the present invention, the orthographic projection of the third sub-trace on the substrate and the orthographic projection of the eighth via on the substrate have an overlapping area, and the eighth via is used to electrically connect the second end of the first connection portion to the gate of the driving transistor.

[0014] According to an embodiment of the present invention, the anode in the second light-emitting unit has a main body and a protrusion, the first trace is disposed corresponding to the anode in the second light-emitting unit, and the first trace is electrically connected to the protrusion through the second via.

[0015] According to an embodiment of the present invention, the distance between the surface of the main body portion away from the substrate and the surface of the first trace away from the substrate is d1, and the distance between the surface of the protrusion portion away from the substrate and the surface of the first trace away from the substrate is d2, wherein the ratio of d1 to d2 is 0.8 to 1.2.

[0016] According to an embodiment of the present invention, the area ratio of the light-emitting region of the first light-emitting unit to the area of ​​the light-emitting region of the second light-emitting unit is 0.9 to 1.1.

[0017] According to an embodiment of the present invention, a transition display area is provided between the first display area and the second display area. The transition display area is provided with a third pixel circuit, a third light-emitting unit and a fourth pixel circuit. The third pixel circuit is used to drive the third light-emitting unit to emit light.

[0018] According to an embodiment of the present invention, a plurality of second traces are provided on the edge of the second display area near the transition display area. The second traces are disposed on the same layer as the source and drain electrode layer and are used to transmit the reset signal and charging signal in the first display area.

[0019] According to an embodiment of the present invention, the display panel includes: a substrate; an active layer disposed on one side of the substrate; a gate insulating layer disposed on one side of the substrate and the active layer; a gate electrode disposed on the surface of the gate insulating layer away from the substrate; an interlayer dielectric layer disposed on the surface of the gate insulating layer and the gate electrode away from the substrate, wherein a first via penetrates the gate insulating layer and the interlayer dielectric layer; a source / drain electrode layer disposed on the surface of the interlayer dielectric layer away from the substrate; a first planarization layer disposed on the side of the interlayer dielectric layer and the source / drain electrode layer away from the substrate, and having a second via penetrating the first planarization layer; a plurality of first traces disposed on the side of the first planarization layer away from the substrate, and electrically connected to a second connection terminal through the second vias; and a second planarization layer disposed on the side of the first planarization layer and the first traces away from the substrate, and having a third via penetrating the second planarization layer, wherein the first traces are electrically connected to the anode of the second light-emitting unit through the third via.

[0020] According to an embodiment of the present invention, the second display area has a plurality of patterned cathode layers, and the orthographic projection of each patterned cathode layer on the substrate covers the orthographic projection of the anode of at least one second light-emitting unit on the substrate.

[0021] According to an embodiment of the present invention, the cathodes in the light-emitting units of the first display area and the transition display area are integral structures in the same layer.

[0022] According to an embodiment of the present invention, a plurality of third traces are further included, wherein the third traces are disposed on the same layer as the first traces, and each patterned cathode layer is provided with a corresponding second trace, and the third traces are used to electrically connect the patterned cathode layer and the VSS signal line.

[0023] According to an embodiment of the present invention, it further includes a plurality of spaced sub-encapsulation layers, wherein the plurality of sub-encapsulation layers are disposed in a one-to-one correspondence with the plurality of patterned cathode layers, and the orthographic projection of each sub-encapsulation layer on the substrate covers the orthographic projection of one of the patterned cathode layers on the substrate.

[0024] According to an embodiment of the present invention, the materials of the first trace and the third trace are ITO or IZO.

[0025] In another aspect of the present invention, a method for manufacturing the aforementioned display panel is provided. According to an embodiment of the present invention, the display panel includes a first display area and a second display area. The first display area is disposed on one side of the second display area, and the second display area is directly opposite to an under-display camera. A substrate is provided. A plurality of second pixel circuits and a first pixel circuit, as well as a plurality of first light-emitting units, are arrayed along a first direction and a second direction on the substrate corresponding to the first display area. The first pixel circuits are used to drive the first light-emitting units to emit light, wherein the first direction and the second direction intersect. A plurality of second light-emitting units are formed on the substrate corresponding to the second display area. The second pixel circuits are used to drive the second light-emitting units to emit light. The steps of forming the second pixel circuits and the first pixel circuits both include forming an active layer, a source / drain electrode layer, a gate line, and a storage capacitor. Further, a first via and a second via are formed in the second pixel circuit. The drain electrode layer includes a drain electrode having a first connection terminal, a second connection terminal, and a connection body portion connecting the first connection terminal and the second connection terminal. The first via is used to electrically connect the first connection terminal and the active layer in the second pixel circuit. The connection body portion extends along a first direction, and the length of the connection body portion is greater than or equal to the length of the storage capacitor in the first direction. The gate line extends along a second direction and includes a reset control signal line, a scan signal line, and a light emission control signal line. The orthographic projection of the second via on the substrate overlaps with the orthographic projection of the scan signal line on the substrate. Multiple first traces are formed on the side of the source / drain electrode layer away from the substrate. The first traces are electrically connected to the second connection terminal through the second via and electrically connected to the anode of the second light-emitting unit through a third via in the second display area, so as to drive the second light-emitting unit to emit light.

[0026] Therefore, the drain electrode of the above structure and the connection position between the first trace and the drain electrode help to optimize the arrangement of the first trace, thereby reducing the area of ​​the anode of the second light-emitting unit electrically connected to the first trace, thereby increasing the light transmittance of the second display area, thereby increasing the amount of light entering the under-display camera and improving its photo-taking effect; moreover, the above manufacturing method is mature, easy to implement, and convenient for industrial production.

[0027] According to an embodiment of the present invention, the anode in the second light-emitting unit is formed by etching. The anode has a main body and a protrusion. The first trace is electrically connected to the protrusion through the second via.

[0028] According to an embodiment of the present invention, the method for manufacturing a display panel further includes: patterning the cathode in the second display area to obtain a plurality of patterned cathode layers, wherein the orthographic projection of each patterned cathode layer on the substrate covers the orthographic projection of the anode of at least one second light-emitting unit on the substrate.

[0029] In another aspect, the present invention provides a display device. According to an embodiment of the present invention, the display device includes: the display panel described above, or a display panel prepared using the method described above; and an under-display camera disposed on the back of the display panel, wherein the orthographic projection of the under-display camera onto the display panel overlaps with a second display area of ​​the display panel. Thus, the under-display camera in the display device has better light intake, thereby effectively improving its image quality. Those skilled in the art will understand that this display device possesses all the features and advantages of the display panel described above, and will not be elaborated further here. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the division of the display area of ​​the display panel in one embodiment of the present invention;

[0031] Figure 2 This is a plan view of a portion of the structure of the display panel in another embodiment of the present invention;

[0032] Figure 3 This is a schematic diagram of the display panel structure in another embodiment of the present invention;

[0033] Figure 4 This is a schematic diagram of the structure of the anode of the first light-emitting unit and the anode of the second light-emitting unit in another embodiment of the present invention;

[0034] Figure 5 This is a schematic diagram of the display panel structure in another embodiment of the present invention;

[0035] Figure 6This is a schematic diagram of the pixel circuit in another embodiment of the present invention;

[0036] Figure 7 This is a schematic diagram of the planar structure of the active layer in another embodiment of the present invention;

[0037] Figure 8 This is a schematic diagram of the planar structure of the grid lines in another embodiment of the present invention;

[0038] Figure 9 This is a schematic diagram of the planar structure of the conductive layer in another embodiment of the present invention;

[0039] Figure 10 This is a schematic diagram of the planar structure of the source and drain electrode layers in another embodiment of the present invention;

[0040] Figure 11 This is a schematic diagram of the planar structure of the source and drain electrode layers in another embodiment of the present invention;

[0041] Figure 12 This is a plan view of a portion of the structure of the display panel in another embodiment of the present invention;

[0042] Figure 13 This is a schematic diagram of the planar structure of the first wiring in another embodiment of the present invention;

[0043] Figure 14 This is a plan view of a portion of the structure of the display panel in another embodiment of the present invention;

[0044] Figure 15 This is a plan view of a portion of the structure of the display panel in another embodiment of the present invention;

[0045] Figure 16 This is a plan view of a portion of the structure of the display panel in another embodiment of the present invention;

[0046] Figure 17 This is a plan view of a portion of the structure of the display panel in another embodiment of the present invention;

[0047] Figure 18 This is a plan view of a portion of the structure of the display panel in another embodiment of the present invention;

[0048] Figure 19 This is a schematic diagram of the display panel structure in another embodiment of the present invention;

[0049] Figure 20 This is a schematic diagram of the display device in another embodiment of the present invention. Detailed Implementation

[0050] The embodiments of the present invention are described in detail below. The embodiments described below are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. Where specific techniques or conditions are not specified in the embodiments, they shall be performed in accordance with the techniques or conditions described in the literature in the art or in accordance with the product manual.

[0051] In one aspect of the invention, a display panel is provided. According to an embodiment of the invention, referring to... Figure 1 The display panel includes a first display area a and a second display area b. The first display area a is disposed on one side of the second display area b, and the second display area b is directly opposite to the under-display camera. Specifically, the second display area b being directly opposite to the under-display camera means that the orthographic projection of the under-display camera on the display panel completely overlaps with the second display area b, or the orthographic projection of the under-display camera on the display panel covers the second display area b, or the orthographic projection of the under-display camera on the display panel is covered by the second display area b.

[0052] There are no particular requirements regarding the specific location of the second display area b. Those skilled in the art can flexibly choose according to the actual design requirements of the under-screen functional area. For example, the second display area can be the center of the display panel, a corner of the display panel, or something else entirely. Figure 1 The second display area b is located near the edge and centered on the display panel. Furthermore, there are no special requirements for the specific shape of the second display area b; those skilled in the art can flexibly choose according to the actual situation, such as the specific design shape of the under-display camera. For example, the shape of the second display area b includes, but is not limited to, circles, ovals, quadrilaterals, pentagons, hexagons, and other polygonal or irregular shapes.

[0053] In addition, such as Figure 1 As shown, the display panel also includes a third display area c, which is located on the side of the first display area a away from the second display area b. Compared to the first and second display areas, the third display area is a high PPI (pixel density) display area; that is, the PPI of the third display area is greater than that of both the first and second display areas.

[0054] Reference Figure 2 and Figure 3The display panel includes a substrate 10. A first display area includes multiple first light-emitting units 21 disposed on the substrate 10, and multiple second pixel circuits 32 and first pixel circuits 31 arrayed along a first direction X and a second direction Y. The first pixel circuits 31 drive the first light-emitting units 21 to emit light, wherein the first direction X and the second direction Y intersect. A second display area b includes multiple second light-emitting units 22 disposed on the substrate 10. The second pixel circuits 32 drive the second light-emitting units 22 to emit light. Both the second pixel circuits 32 and the first pixel circuits 31 include an active layer 314, a source / drain electrode layer 313, a gate line 315, and a storage capacitor. The second pixel circuit 32 also includes a first via 321 and a second via 322. The source / drain electrode layer 313 in the second pixel circuit 32 includes a drain electrode 3130, which has a first connection terminal 3131, a second connection terminal 3132, and a connection connecting the first connection terminal 3131 and the second connection terminal 3132. The main body 3133 includes a first via 321 for electrically connecting the first connection terminal 3131 and the active layer 314 in the second pixel circuit 32. The main body 3133 extends along the first direction X, and the gate line 315 extends along the second direction Y. The display panel also includes a plurality of first traces 51. The first traces 51 are located on the side of the source / drain electrode layer 313 away from the substrate 10. The first traces 51 are electrically connected to the second connection terminal 3132 through the second via 322, and electrically connected to the anode 221 of the second light-emitting unit 22 through the third via 23 in the second display area b, so as to drive the second light-emitting unit 22 to emit light.

[0055] Therefore, the connection position of the drain electrode 3130 and the first trace 51 to the drain electrode 3130 in the above structure helps to optimize the arrangement of the first trace 51, thereby reducing the area of ​​the anode 221 of the second light-emitting unit 22 electrically connected to the first trace 51, thereby improving the light transmittance of the second display area, thereby increasing the amount of light entering the under-display camera and improving its photo-taking effect.

[0056] According to embodiments of the present invention, such as Figure 2 As shown, the length d of the connecting body is greater than or equal to the length of the storage capacitor in the first direction. Figure 2 The structure of the storage capacitor is shown in the figure below. (Refer to the diagram below.) Figure 12 It is evident that the length d of the connecting body is greater than or equal to the length of the storage capacitor in the first direction. This helps to rationally arrange the first trace 51, minimize the size of the anode 221 of the second light-emitting unit 22 electrically connected to the first trace, and thereby improve the light transmittance of the second display area.

[0057] In some specific embodiments, reference is made to Figure 3The display panel includes: a substrate 10; an active layer 314 disposed on one side of the substrate 10; a gate insulating layer 316 disposed on one side of the substrate 10 and the active layer 314; a gate electrode (part of a gate line 315) disposed on the surface of the gate insulating layer 316 away from the substrate 10; an interlayer dielectric layer 317 disposed on the surfaces of the gate insulating layer 316 and the gate electrode away from the substrate 10, wherein a first via 321 penetrates the gate insulating layer 316 and the interlayer dielectric layer 317; a source / drain electrode layer 313 disposed on the surface of the interlayer dielectric layer 317 away from the substrate 10; and a first planarization layer. 41. The first planarization layer 41 is disposed on the side of the interlayer dielectric layer 317 and the source / drain electrode layer 313 away from the substrate 10, and has a second via 322 penetrating the first planarization layer 41. A plurality of first traces 51 are disposed on the side of the first planarization layer 41 away from the substrate 10, and are electrically connected to the second connection terminal 3132 through the second via 322. The second planarization layer 42 is disposed on the side of the first planarization layer 41 away from the substrate 10 and the first traces 51, and has a third via 23 penetrating the second planarization layer 42. The first traces 51 are electrically connected to the anode 221 of the second light-emitting unit 22 through the third via 23.

[0058] Among them, such as Figure 3 As shown, the second light-emitting unit 22 includes an anode 221, a light-emitting layer 222, and a cathode 223. In some embodiments, the second light-emitting unit 22 may also include structures such as an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer. Those skilled in the art can flexibly select according to the actual situation.

[0059] According to an embodiment of the present invention, referring to Figure 2 and Figure 4 In (a) of the second light-emitting unit 22, the anode 221 has a main body 222 and a protrusion 223. A first trace 51 is correspondingly disposed to the anode 221 in the second light-emitting unit 22, and the first trace 51 is electrically connected to the protrusion 223 through the second via 322. Therefore, even with the electrical connection between the first trace and the anode, the effective luminous efficiency of the second light-emitting unit can be guaranteed as much as possible. It should be noted that... Figure 2The anode 221 in the second light-emitting unit 22 shown in the diagram is merely a schematic diagram and not a structural diagram of the actual product. Furthermore, the statement "the first trace 51 is correspondingly arranged with the anode 221 in the second light-emitting unit 22" means that one first trace 51 corresponds to one anode 221, i.e., one first trace 51 is electrically connected to only one anode 221 in the second light-emitting unit. Additionally, there are no special requirements regarding the position of the protrusion 223 relative to the main body 222; those skilled in the art can flexibly choose according to the actual situation. The protrusion 223 can be located on any edge around the main body 222.

[0060] According to an embodiment of the present invention, the distance between the surface of the main body away from the substrate and the surface of the first trace away from the substrate is d1, and the distance between the surface of the protrusion away from the substrate and the surface of the first trace away from the substrate is d2, wherein the ratio of d1 to d2 is 0.8 to 1.2. It should be further noted that the ratio of the thickness of the protrusion to the thickness of the main body is 0.8 to 1.2, wherein the thickness of the protrusion does not include the anode portion in the third via 23. (Refer to...) Figure 3 In the second light-emitting unit 22, the anode 221 is disposed on the surface of the second planarization layer 42 away from the substrate. The thickness of the protrusion is the distance between the surface of the protrusion away from the substrate and the surface of the second planarization layer away from the substrate. In the fabrication process, the main body and the protrusion of the anode 221 are formed by the same process step, that is, the main body and the protrusion are integrally formed, and the specific structures of the main body and the protrusion are the same, only the shapes are different. In some embodiments, the anode 221 includes a first transparent electrode (e.g., ITO), a silver electrode, and a second transparent electrode (e.g., ITO) stacked together. Therefore, the specific structures of the main body and the protrusion both include the first transparent electrode, the silver electrode, and the second transparent electrode stacked together.

[0061] According to an embodiment of the present invention, the area ratio of the light-emitting area of ​​the first light-emitting unit to the area of ​​the light-emitting area of ​​the second light-emitting unit is 0.9 to 1.1. It should be noted that the aforementioned light-emitting area refers to the region of the anode portion exposed at the opening defined by the pixel defining layer 43. This better ensures the luminous efficiency in the second light-emitting unit. It should be noted that the area ratio of the light-emitting area of ​​the first light-emitting unit to the area of ​​the second light-emitting unit being 0.9 to 1.1 means that the area ratio of the light-emitting areas of light-emitting units of the same emitting color is 0.9 to 1.1. For example, the area ratio between the light-emitting areas of the red first light-emitting unit and the red second light-emitting unit is 0.9 to 1.1, the area ratio between the light-emitting areas of the blue first light-emitting unit and the blue second light-emitting unit is 0.9 to 1.1, and the area ratio between the light-emitting areas of the green first light-emitting unit and the green second light-emitting unit is 0.9 to 1.1.

[0062] In some specific embodiments, reference is made to Figure 4 In (a) and (b) of the diagram, the main body 222 maintains a shape substantially consistent with the anode 211 of the first light-emitting unit 21 in the first display area. This ensures better luminous efficiency in the second light-emitting unit. The shape of the anode in different light-emitting units can be flexibly designed according to different luminous colors such as blue, red, and green light-emitting units, which will not be elaborated further here. It should be further explained that "the shape of the main body 222 maintaining a shape substantially consistent with the anode 211 of the first light-emitting unit 21 in the first display area" means that the shape of the main body of the second light-emitting unit of the same luminous color is substantially consistent with the shape of the anode 211 of the first light-emitting unit 21. For example, the shape of the main body of the anode of the red second light-emitting unit is substantially consistent with the shape of the anode of the red first light-emitting unit, the shape of the main body of the anode of the blue second light-emitting unit is substantially consistent with the shape of the anode of the blue first light-emitting unit, and the shape of the main body of the anode of the green second light-emitting unit is substantially consistent with the shape of the anode of the green first light-emitting unit. According to an embodiment of the present invention, referring to... Figure 5The first pixel circuit further includes a fourth via 311 and a fifth via 312. The fourth via 311 is used to electrically connect the source / drain electrode layer 313 in the first pixel circuit 31 and the anode 211 in the first light-emitting unit 21. The fifth via 312 is used to electrically connect the source / drain electrode layer 313 in the first pixel circuit and the active layer 314. The orthographic projection of the fourth via 311 on the substrate 10 overlaps with the orthographic projection of the fifth via 312 on the substrate 10. The first light-emitting unit 21 includes an anode 211, a light-emitting layer 212, and a cathode 213. In some embodiments, the first light-emitting unit 21 may also include structures such as an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer. Those skilled in the art can flexibly select the appropriate structure according to the actual situation.

[0063] According to embodiments of the present invention, the first pixel circuit and / or the second pixel circuit can be a 7T1C (i.e., seven transistors and one capacitor) structure, for example including a driving transistor T1, a data writing transistor T2, a storage capacitor, a threshold compensation transistor T3, a first reset transistor T6, a second reset transistor T7, a first light-emitting control transistor T4, and a second light-emitting control transistor T5. The circuit driving principle of the sub-pixel is as follows: Figure 6 As shown, firstly, the first reset control signal line Reset1 (reset signal 1) turns on the first reset transistor T6, and the first reset power supply terminal Vinit1 resets point N1 at the Cst (storage capacitor) end; then, the Gate signal (gate line signal) turns on the threshold compensation transistor T3 and the data writing transistor T2, and the driving transistor T1, due to the reset signal of the first reset power supply terminal Vinit1 being in the on state, charges point N1 with the data signal; simultaneously, the second reset power supply terminal Reset2 controls the second reset transistor T7 to turn on, resetting the current on the OLED device; finally, the light emission control signal line EM controls the first light emission control transistor T4 and the second light emission control transistor T5 to turn on, and the current on VDD flows through the OLED device and into the VSS terminal. At this time, the current magnitude is controlled by the gate voltage of the driving transistor T1 (i.e., the voltage at point N1), where... Figure 6 Point N4 in the diagram corresponds to the position of the second via 322.

[0064] The specific structures of the first pixel circuit and the second pixel circuit are described in detail below based on some embodiments of this application:

[0065] In some embodiments, a schematic diagram of the active layer 314 may be referred to Figure 7The active layer 314 includes the active layers of the aforementioned driving transistor T1, data writing transistor T2, threshold compensation transistor T3, first light-emitting control transistor T4, second light-emitting control transistor T5, first reset transistor T6, and second reset transistor T7. The active layer 314 includes the active layer pattern (channel region) and doped region pattern (source / drain doped region) of each transistor in each sub-pixel, and the active layer pattern and doped region pattern of each transistor in the same pixel circuit are integrally formed. It should be noted that... Figure 5 The dashed rectangles in the diagram show the portions where the gate and active layer 314 overlap in the pixel circuit, serving as the channel regions of each transistor.

[0066] In some embodiments, such as Figure 8 As shown, the gate line 315 extends along the second direction Y. Further, the gate line 315 includes a reset control signal line (Rst) 3151, a scan signal line (Ga) 3152, and a light emission control signal line (EM) 3153. The orthographic projection of the second via 322 on the substrate overlaps with the orthographic projection of the scan signal line 3152 on the substrate 10.

[0067] In the first direction X, the reset control signal line (Rst) 3151, the scan signal line (Ga) 3152, and the light emission control signal line (EM) 3153 are arranged in a repeating pattern. Furthermore, the "second via 322" mentioned above, where "the orthographic projection of the second via 322 on the substrate overlaps with the orthographic projection of the scan signal line 3152 on the substrate 10," refers to the second via 322 in a specific second pixel circuit controlled by the scan signal line 3152.

[0068] Among them, the second electrode 3154 of the storage capacitor (i.e., the gate of the driving transistor T1) is also disposed on the same layer as the gate line 315. The second electrode 3154 is located between the scan signal line 3152 and the light emission control signal line 3153.

[0069] In some embodiments, the first pixel circuit and the second pixel circuit may further include a conductive layer 330. The conductive layer 330 is disposed on the side of the gate line away from the substrate and is insulated from the gate line 315. A schematic diagram of the structure of the conductive layer 330 is shown below. Figure 9The conductive layer 330 includes a first electrode 3301 of a storage capacitor, a reset power signal line (Init) 3302, a second power signal line VDD2 (3303), and a light-shielding portion 3304. The second power signal line 3303 can be integrally formed with the first electrode 3301 of the storage capacitor. Through the second power signal line 3303 and the first electrode 3301 of the storage capacitor, multiple first power signal lines (VDD1) extending in the first direction X (described later) are connected to form a mesh wiring to reduce resistance. The first electrode 3301 and the second electrode 3154 of the storage capacitor at least partially overlap to form a storage capacitor.

[0070] In some embodiments, refer to Figure 10 As shown, the source / drain electrode layer 313 includes, in addition to the previously described drain electrode 3130, a data line (Vd) 3134, a first power signal line VDD1 (3135), a first connection portion 3136, and a second connection portion 3137. The data line Vd and the first power signal line VDD1 both extend along the first direction X. Furthermore, in some embodiments, the connection body portion 3133 of the drain electrode 3130 extends along the first direction X (e.g., ...). Figure 2 As shown in the figure, this is beneficial for better layout of multiple first routing lines 51 within a limited space.

[0071] exist Figure 11The diagram shows exemplary locations of multiple vias, through which the source / drain electrode layer 313 is connected to multiple film layers located between the source / drain electrode layer 313 and the substrate, such as the first via 321, the second via 322, the fourth via 311, the fifth via 312, the sixth via 381, the seventh via 384, the eighth via 385, the ninth via 386, and the tenth via 387. Specifically, the first via 321 is used to electrically connect the first connection terminal 3131 of the drain electrode 3130 and the active layer 314 in the second pixel circuit 32; the second via 322 is used to electrically connect the first trace 51 and the second connection terminal 3132 of the drain electrode 3130; the fourth via 311 is used to electrically connect the source / drain electrode layer 313 in the first pixel circuit 31 and the anode 211 in the first light-emitting unit 21; the fifth via 312 is used to electrically connect the source / drain electrode layer 313 and the active layer 314 in the first pixel circuit; the sixth via 381 is used to electrically connect the data writing transistor T2 and the data line Vd; and the seventh via 384 is used to electrically connect the first connection portion 313 of the source / drain electrode layer 313. The first terminal A of 6 is connected to the threshold compensation transistor T3, and the first connection portion 3136 is configured to connect the source and drain electrodes of the threshold compensation transistor T3 and the source and drain electrodes of the driving transistor T1; the eighth via 385 is used to electrically connect the second terminal B of the first connection portion 3136 to the gate of the driving transistor T1; the ninth via 386 is used to electrically connect one end of the second connection portion 3137 to the reset power supply signal line Init3302; the tenth via 387 is used to electrically connect the other end of the second connection portion 3137 to the first electrode of the second reset transistor T7, wherein the first electrode of the second reset transistor T7 is configured to be electrically connected to the second reset power supply terminal Vinit2 to receive the second reset signal.

[0072] According to an embodiment of the present invention, referring to Figure 10 and Figure 11 As shown, the orthographic projection of the second connecting end 3132 in the second direction Y and the orthographic projection of the middle main body part C of the first connecting part 3136 in the second direction Y have an overlapping area.

[0073] A schematic diagram showing the superposition of the above-mentioned active layer 314, gate line 315, conductive layer 330, and source / drain electrode layer 313 can be referred to. Figure 12 (The insulating layers between the various structures are not shown.)

[0074] According to an embodiment of the present invention, referring to Figure 12 The orthographic projection of the main body 3130 on the substrate overlaps with the orthographic projection of the storage capacitor (i.e., the area where the second electrode 3154 and the first electrode 3301 overlap) on the substrate.

[0075] According to an embodiment of the present invention, referring to Figure 13 , Figure 14 and Figure 2 The first trace 51 includes a first sub-trace 511 and a second sub-trace 512 in the first direction X. The orthographic projections of the first sub-trace 511 and the second sub-trace 512 on the substrate do not overlap with the orthographic projection of the connecting main body 3130 on the substrate. Figure 13 It can be seen that the first sub-route 511 and the second sub-route 512 extend in the second direction Y. That is, as follows Figure 13 and Figure 14 As shown, there is no overlap between the orthographic projection of the connection body 3130 in the second pixel circuit electrically connected to the first sub-line 511 on the substrate and the orthographic projection of the first sub-line 511 and the second sub-line 512 on the substrate.

[0076] According to an embodiment of the present invention, referring to Figure 14 The first sub-trace 511 has an overlapping area with the orthographic projection of the sixth via 381 on the substrate. The sixth via 381 is used to electrically connect the data writing transistor T2 and the data line 3134. The second sub-trace 512 has an overlapping area with the orthographic projection of the seventh via 384 on the substrate. The seventh via 384 is used to electrically connect the first end A of the first connection portion 3136 in the source-drain electrode layer 313 to the threshold compensation transistor T3. The first connection portion 3136 is configured to connect the source-drain electrodes of the threshold compensation transistor T3 and the source-drain electrodes of the driving transistor T1.

[0077] According to embodiments of the present invention, such as Figure 2 As shown, the first trace 51 further includes a third sub-trace 513 in the first direction X. The orthographic projection of the third sub-trace 513 on the substrate overlaps with the orthographic projection of the connecting main body 3136 on the substrate. That is, as... Figure 2 As shown, the third sub-trace 513 is electrically connected to the second connection terminal 3132 of the connection body 3130, bends towards the first connection terminal 3131, and then extends towards the second display area b, where it is electrically connected to the anode of the second light-emitting unit. In some embodiments, the orthographic projection of the third sub-trace 513 on the substrate overlaps with the orthographic projection of the eighth via 385 on the substrate. The eighth via 385 is used to electrically connect the second terminal B of the first connection portion 3136 to the gate of the driving transistor T1.

[0078] It should be noted that the first routing 51 includes not only the first sub-routes 511, the second sub-routes 512 and the third sub-routes 513 mentioned above, but also multiple other sub-routes. Those skilled in the art can flexibly arrange the routing of the sub-routes according to actual design requirements.

[0079] According to an embodiment of the present invention, the material of the first trace is either ITO or IZO. Therefore, these materials not only have good conductivity but also high light transmittance, which can better improve the light transmittance of the second display area.

[0080] According to an embodiment of the present invention, referring to Figure 15 A transition display area d is provided between the first display area a and the second display area b. The transition display area d is provided with a third pixel circuit 33, a third light-emitting unit 24, and a fourth pixel circuit 34. The third pixel circuit is used to drive the third light-emitting unit to emit light. For example... Figure 15 As shown, no light-emitting unit is provided in the pixel area corresponding to the fourth pixel circuit 34, and the fourth pixel circuit 34 is not electrically connected to the anode 221 of the second light-emitting unit in the second display area b. Therefore, it is possible to...

[0081] Furthermore, refer to Figure 16 The second display area b has multiple second traces 52 near the edge of the transition display area d. These second traces 52 are disposed on the same layer as the source and drain electrode layers and are used to transmit reset signals and charging signals from the first display area. This better ensures the display effect of the display panel.

[0082] According to an embodiment of the present invention, referring to Figure 17 The second display area b has multiple patterned cathode layers 60, and the orthographic projection of each patterned cathode layer 60 on the substrate covers the orthographic projection of at least one anode 221 of the second light-emitting unit on the substrate. That is to say, the cathode 213 of the second light-emitting unit is a patterned cathode layer 60, rather than a solid cathode structure, which reduces the coverage area of ​​the cathode and thus improves the light transmittance of the second display area.

[0083] There are no special requirements regarding the number of anodes in the second light-emitting unit covered by each patterned cathode layer; those skilled in the art can design flexibly according to actual conditions. For example, in some embodiments, one patterned cathode layer 60 covers one anode 221; in other embodiments, one patterned cathode layer covers two or three anodes 221.

[0084] According to an embodiment of the present invention, the cathodes in the light-emitting units of the first display area a and the transition display area d are integrally formed on the same layer. That is, the cathodes in the light-emitting units of the first display area a and the transition display area d are a single, solid layer, rather than a patterned cathode layer. Furthermore, when the display area of ​​the display panel includes a third display area c, the cathodes in the light-emitting units of the first display area a, the third display area c, and the transition area d are integrally formed on the same layer. That is, except for the second display area b, the cathodes in the other display areas are integrally formed on the same layer and do not require patterning.

[0085] According to an embodiment of the present invention, referring to Figure 18 It also includes multiple third traces 53, which are arranged on the same layer as the first traces 51. Each patterned cathode layer 60 is provided with one second trace 53. The third traces 53 are used to electrically connect the patterned cathode layer 61 and the VSS signal line. This ensures the electrical connection between the patterned cathode layer and the VSS signal line in the second light-emitting unit.

[0086] According to an embodiment of the present invention, the material of the third trace is either ITO or IZO. Therefore, these materials not only have good conductivity but also high light transmittance, which can better improve the light transmittance of the second display area.

[0087] According to an embodiment of the present invention, referring to Figure 19 The display panel also includes a plurality of spaced sub-encapsulation layers 70, each of which is arranged in a one-to-one correspondence with a plurality of patterned cathode layers 60 (i.e., one patterned cathode layer corresponds to one sub-encapsulation layer), and the orthographic projection of each sub-encapsulation layer 70 on the substrate 10 covers the orthographic projection of one patterned cathode layer 60 on the substrate.

[0088] In another aspect, the present invention provides a method for manufacturing the aforementioned display panel. According to embodiments of the present invention, such as... Figure 1 As shown, the display panel includes a first display area a and a second display area b. The first display area a is disposed on one side of the second display area b, and the second display area b is disposed directly opposite to the under-display camera. The direct correspondence between the second display area b and the under-display camera means that the orthographic projection of the under-display camera on the display panel completely overlaps with the second display area b, or the orthographic projection of the under-display camera on the display panel covers the second display area b, or the orthographic projection of the under-display camera on the display panel is covered by the second display area b.

[0089] In addition, such as Figure 1 As shown, the display panel also includes a third display area c, which is located on the side of the first display area a away from the second display area b. Compared to the first and second display areas, the third display area is a high PPI (pixel density) display area; that is, the PPI of the third display area is greater than that of both the first and second display areas.

[0090] Among them, reference Figure 2 and 3 Methods for creating a display panel:

[0091] S100: Provides a substrate 10;

[0092] S200: A plurality of second pixel circuits 32 and first pixel circuits 31, as well as a plurality of first light-emitting units 21, are formed on the substrate 10 corresponding to the first display area a, arranged in a column along the first direction X and the second direction Y. The first pixel circuits 31 are used to drive the first light-emitting units to emit light 21. The first direction X and the second direction Y intersect. The steps of forming the second pixel circuits 32 and the first pixel circuits 31 each include the steps of forming an active layer 314, a source / drain electrode layer 313, a gate line 315, and a storage capacitor.

[0093] In the fabrication of the second pixel circuit, a first via 321 and a second via 322 need to be further formed. The source / drain electrode layer 313 in the second pixel circuit 32 includes a drain electrode 3130. The drain electrode 3130 has a first connection terminal 3131, a second connection terminal 3132, and a connection body portion 3133 connecting the first connection terminal 3131 and the second connection terminal 3132. The first via 321 is used to electrically connect the first connection terminal 3131 and the source / drain electrode layer 312 in the second pixel circuit 32. Active layer 314, the connecting body portion 3133 extends along the first direction X, the length of the connecting body portion 3133 is greater than or equal to the length of the storage capacitor in the first direction, the gate line 315 extends along the second direction Y, the gate line 315 includes a reset control signal line (Rst) 3151, a scan signal line (Ga) 3152 and a light emission control signal line (EM) 3153, the orthographic projection of the second via 322 on the substrate overlaps with the orthographic projection of the scan signal line 3152 on the substrate 10 (e.g., Figure 8 (as shown);

[0094] S300: Multiple first traces 51 are formed on the side of the source / drain electrode layer 313 away from the substrate 10. The first traces 51 are electrically connected to the second connection terminal 3132 through the second via 322.

[0095] S400: A plurality of second light-emitting units 22 are formed on the substrate 10 corresponding to the second display area b. The second pixel circuit 32 is used to drive the second light-emitting units 22 to emit light. The first trace 51 is electrically connected to the anode 221 of the second light-emitting unit 22 through a third via 23 in the second display area, so as to drive the second light-emitting unit 22 to emit light. A schematic diagram of the structure of the display panel manufactured by the above method can be found here. Figure 2 and Figure 3 It should be noted that the above manufacturing method only mentions the formation steps of structures such as active layer, gate line, source / drain electrode layer, first trace, and first light-emitting unit, and an insulating layer is also formed between each structure.

[0096] According to an embodiment of the present invention, in the above manufacturing method, the drain electrode of the above structure and the connection position of the first trace and the drain electrode help to optimize the arrangement of the first trace, thereby reducing the area of ​​the anode of the second light-emitting unit electrically connected to the first trace, thereby increasing the light transmittance of the second display area, thereby increasing the amount of light entering the under-display camera and improving its photo-taking effect; moreover, the above manufacturing method has mature technology, is easy to implement, and is convenient for industrial production.

[0097] In some specific embodiments, a schematic diagram of the structure of the display panel produced by the above method can be referred to. Figure 3 The display panel includes: a substrate 10; an active layer 314 disposed on one side of the substrate 10; a gate insulating layer 316 disposed on the surface of the substrate 10 and covering the active layer 314; a gate (part of a gate line 315) disposed on the surface of the gate insulating layer 316 away from the substrate 10; an interlayer dielectric layer 317 disposed on the surface of the gate insulating layer 316 away from the substrate 10 and covering the gate, wherein a first via 321 penetrates the gate insulating layer 316 and the interlayer dielectric layer 317; a source / drain electrode layer 313 disposed on the surface of the interlayer dielectric layer 317 away from the substrate 10; and a first planarization layer. Layer 41, the first planarization layer 41 is disposed on the side of the interlayer dielectric layer 317 away from the substrate 10 and covers the source / drain electrode layer 313, and has a second via 322 penetrating the first planarization layer 41. A plurality of first traces 51 are disposed on the side of the first planarization layer 41 away from the substrate 10 and are electrically connected to the second connection terminal 3132 through the second via 322. Second planarization layer 42, the second planarization layer 42 is disposed on the side of the first planarization layer 41 away from the substrate 10 and covers the first traces 51, and has a third via 23 penetrating the second planarization layer 42. The first traces 51 are electrically connected to the anode 221 of the second light-emitting unit 22 through the third via 23.

[0098] According to an embodiment of the present invention, referring to Figure 2 and Figure 4 In (a) of the second light-emitting unit 22, the anode 221 is formed by etching. The anode 221 has a main body 222 and a protrusion 223. The first trace 51 is electrically connected to the protrusion 223 through the second via 322. Therefore, even with the electrical connection between the first trace and the anode, the effective luminous efficiency of the second light-emitting unit can be guaranteed as much as possible. It should be noted that... Figure 2The anode 221 in the second light-emitting unit 22 shown in the diagram is only a schematic diagram and not a structural schematic diagram of the actual product. In addition, there are no special requirements for the setting position of the protrusion 223 relative to the main body 222. Those skilled in the art can flexibly choose according to the actual situation. The protrusion 223 can be set on the edge of any side around the main body 222.

[0099] According to an embodiment of the present invention, referring to Figure 4 In (a) and (b), the shape of the main body 222 is consistent with that of the anode 211 of the first light-emitting unit 21 in the first display area. This ensures better luminous efficiency in the second light-emitting unit. The shape of the anode in different light-emitting units can be flexibly designed according to different luminous colors such as blue, red, and green light-emitting units, which will not be elaborated further here.

[0100] According to an embodiment of the present invention, referring to Figure 17 The method for manufacturing the display panel further includes: patterning the cathode in the second display area b to obtain multiple patterned cathode layers 60, wherein the orthographic projection of each patterned cathode layer 60 on the substrate covers the orthographic projection of at least one anode 221 of the second light-emitting unit 22 on the substrate. That is, the cathode 213 of the second light-emitting unit is a patterned cathode layer 60, rather than a solid cathode structure, which reduces the coverage area of ​​the cathode and thus improves the light transmittance of the second display area; moreover, the above manufacturing method is simple to implement, the process is mature, and it is convenient for industrial production.

[0101] In another aspect, the present invention provides a display device. According to an embodiment of the present invention, referring to... Figure 20 The display device 1 includes: the aforementioned display panel 1000, or a display panel 1000 prepared using the aforementioned method for preparing the display panel; and an under-display camera 2000 disposed on the back of the display panel 1000 (i.e., the under-display camera 2000 is disposed on the side away from the display screen of the display panel), and the orthographic projection of the under-display camera 2000 onto the display panel overlaps with the second display area b of the display panel. Therefore, the under-display camera in the display device has better light intake, thereby effectively improving its image quality. Those skilled in the art will understand that this display device possesses all the features and advantages of the aforementioned display panel, which will not be elaborated upon further here.

[0102] Where the orthographic projection of the under-display camera 2000 onto the display panel overlaps with the second display area b of the display panel, this can include the following three situations: the orthographic projection of the under-display camera 2000 onto the display panel overlaps with the second display area b of the display panel, such as... Figure 20As shown in (1); the orthographic projection of the under-display camera 2000 onto the display panel is covered by the second display area b of the display panel, as shown in (1); Figure 20 As shown in (2); the orthographic projection of the under-display camera 2000 onto the display panel covers the second display area b of the display panel, as shown in (2). Figure 20 As shown in (3) of the text.

[0103] According to embodiments of the present invention, there are no special requirements for the specific type of the display device. Those skilled in the art can choose flexibly according to the actual situation. For example, the specific type of display device includes, but is not limited to, mobile phones, tablets, laptops, and other display devices with display and camera functions.

[0104] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0105] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0106] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0107] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a first display area and a second display area. The first display area is disposed on one side of the second display area, and the second display area is positioned directly opposite the under-display camera. The display panel includes a substrate, and the first display area includes a plurality of first light-emitting units disposed on the substrate and a plurality of second pixel circuits and first pixel circuits arrayed along a first direction and a second direction. The first pixel circuits are used to drive the first light-emitting units to emit light, wherein the first direction and the second direction intersect. The second display area includes a plurality of second light-emitting units disposed on the substrate, and the second pixel circuit is used to drive the second light-emitting units to emit light. Both the second pixel circuit and the first pixel circuit include an active layer, a source / drain electrode layer, a gate line, and a storage capacitor. The second pixel circuit further includes a first via and a second via. The source / drain electrode layer in the second pixel circuit includes a drain electrode, which has a first connection terminal, a second connection terminal, and a connection body portion connecting the first connection terminal and the second connection terminal. The first via is used to electrically connect the first connection terminal and the active layer in the second pixel circuit. The connection body portion extends along a first direction, and the length of the connection body portion is greater than or equal to the length of the storage capacitor in the first direction. The gate line extends along a second direction and includes a reset control signal line, a scan signal line, and a light emission control signal line. The orthographic projection of the second via on the substrate overlaps with the orthographic projection of the scan signal line on the substrate. The display panel further includes multiple first traces located on the side of the source / drain electrode layer away from the substrate. The first traces are electrically connected to the second connection terminal through the second via and electrically connected to the anode of the second light-emitting unit through the third via in the second display area, so as to drive the second light-emitting unit to emit light.

2. The display panel according to claim 1, characterized in that, The first pixel circuit further includes a fourth via and a fifth via. The fourth via is used to electrically connect the source / drain electrode layer in the first pixel circuit and the anode in the first light-emitting unit. The fifth via is used to electrically connect the source / drain electrode layer in the first pixel circuit and the active layer. The orthographic projection of the fourth via on the substrate overlaps with the orthographic projection of the fifth via on the substrate.

3. The display panel according to claim 1, characterized in that, The orthographic projection of the connecting body on the substrate overlaps with the orthographic projection of the storage capacitor on the substrate.

4. The display panel according to claim 1, characterized in that, The first trace includes a first sub-trace and a second sub-trace in a first direction, and the orthographic projections of the first sub-trace and the second sub-trace on the substrate do not overlap with the orthographic projection of the connecting body portion on the substrate.

5. The display panel according to claim 4, characterized in that, The orthographic projection of the first sub-trace on the substrate overlaps with the orthographic projection of the sixth via on the substrate. The sixth via is used to electrically connect the data writing transistor and the data line. The orthographic projection of the second sub-trace on the substrate overlaps with the orthographic projection of the seventh via on the substrate. The seventh via is used to electrically connect the first end of the first connection portion of the source-drain electrode layer to the threshold compensation transistor, and the first connection portion is configured to connect the source-drain electrode of the threshold compensation transistor and the source-drain electrode of the driving transistor.

6. The display panel according to claim 5, characterized in that, The orthographic projection of the second connecting end in the second direction overlaps with the orthographic projection of the middle main body of the first connecting portion in the second direction.

7. The display panel according to claim 5, characterized in that, The first trace further includes a third sub-trace in a first direction, and the orthographic projection of the third sub-trace on the substrate overlaps with the orthographic projection of the connecting body portion on the substrate.

8. The display panel according to claim 7, characterized in that, The orthographic projection of the third sub-trace on the substrate overlaps with the orthographic projection of the eighth via on the substrate. The eighth via is used to electrically connect the second end of the first connection portion to the gate of the driving transistor.

9. The display panel according to claim 1, characterized in that, The anode in the second light-emitting unit has a main body and a protrusion. The first trace is disposed corresponding to the anode in the second light-emitting unit, and the first trace is electrically connected to the protrusion through the second via.

10. The display panel according to claim 9, characterized in that, The distance between the surface of the main body away from the substrate and the surface of the first trace away from the substrate is d1, and the distance between the surface of the protrusion away from the substrate and the surface of the first trace away from the substrate is d2, wherein the ratio of d1 to d2 is 0.8 to 1.

2.

11. The display panel according to claim 10, characterized in that, The area ratio of the light-emitting area of ​​the first light-emitting unit to the area of ​​the light-emitting area of ​​the second light-emitting unit is 0.9 to 1.

1.

12. The display panel according to claim 1, characterized in that, A transition display area is provided between the first display area and the second display area. The transition display area is provided with a third pixel circuit, a third light-emitting unit and a fourth pixel circuit. The third pixel circuit is used to drive the third light-emitting unit to emit light.

13. The display panel according to claim 12, characterized in that, The second display area has multiple second traces near the edge of the transition display area. The second traces are disposed on the same layer as the source and drain electrode layer and are used to transmit the reset signal and charging signal in the first display area.

14. The display panel according to claim 1, characterized in that, The display panel includes: The substrate; The active layer is disposed on one side of the substrate. A gate insulating layer is disposed on one side of the substrate and the active layer; A gate, the gate being disposed on the surface of the gate insulating layer away from the substrate; An interlayer dielectric layer is disposed on the surface of the gate insulating layer and the gate electrode away from the substrate, wherein the first via penetrates the gate insulating layer and the interlayer dielectric layer; The source / drain electrode layer is disposed on the surface of the interlayer dielectric layer away from the substrate. A first planarization layer is disposed on the side of the interlayer dielectric layer and the source / drain electrode layer away from the substrate, and has a second via penetrating the first planarization layer. A plurality of first traces are disposed on the side of the first planarization layer away from the substrate and are electrically connected to a second connection terminal through the second via. A second planarization layer is disposed on the side of the first planarization layer and the first trace away from the substrate, and has the third via penetrating the second planarization layer, through which the first trace is electrically connected to the anode of the second light-emitting unit.

15. The display panel according to any one of claims 1 to 14, characterized in that, The second display area has a plurality of patterned cathode layers, and the orthographic projection of each patterned cathode layer on the substrate covers the orthographic projection of the anode of at least one second light-emitting unit on the substrate.

16. The display panel according to any one of claims 12 or 13, characterized in that, The cathodes in the light-emitting units of the first display area and the transition display area are integral structures on the same layer.

17. The display panel according to claim 15, characterized in that, It also includes multiple third traces, which are arranged on the same layer as the first traces. Each patterned cathode layer is provided with one third trace, which is used to electrically connect the patterned cathode layer and the VSS signal line.

18. The display panel according to claim 15, characterized in that, It also includes multiple spaced sub-encapsulation layers, each of which corresponds to one of the multiple patterned cathode layers, and the orthographic projection of each sub-encapsulation layer on the substrate covers the orthographic projection of one of the patterned cathode layers on the substrate.

19. The display panel according to claim 17, characterized in that, The first trace and the third trace are made of ITO or IZO.

20. A method for manufacturing a display panel according to any one of claims 1 to 19, characterized in that, The display panel includes a first display area and a second display area. The first display area is disposed on one side of the second display area, and the second display area is positioned directly opposite the under-display camera. A substrate is provided, on which a plurality of second pixel circuits and first pixel circuits and a plurality of first light-emitting units are formed in an array distributed along a first direction and a second direction, the first pixel circuits being used to drive the first light-emitting units to emit light, wherein the first direction and the second direction intersect. A plurality of second light-emitting units are formed on the substrate corresponding to the second display area, and the second pixel circuit is used to drive the second light-emitting units to emit light. The steps for forming the second pixel circuit and the first pixel circuit both include forming an active layer, a source / drain electrode layer, a gate line, and a storage capacitor. Furthermore, a first via and a second via are formed in the second pixel circuit. The source / drain electrode layer in the second pixel circuit includes a drain electrode, which has a first connection terminal, a second connection terminal, and a connection body portion connecting the first connection terminal and the second connection terminal. The first via is used to electrically connect the first connection terminal and the active layer in the second pixel circuit. The connection body portion extends along a first direction, and the length of the connection body portion is greater than or equal to the length of the storage capacitor in the first direction. The gate line extends along a second direction and includes a reset control signal line, a scan signal line, and a light emission control signal line. The orthographic projection of the second via on the substrate overlaps with the orthographic projection of the scan signal line on the substrate. Multiple first traces are formed on the side of the source / drain electrode layer away from the substrate. The first traces are electrically connected to the second connection terminal through the second via and electrically connected to the anode of the second light-emitting unit through the third via in the second display area, so as to drive the second light-emitting unit to emit light.

21. The method according to claim 20, characterized in that, The anode in the second light-emitting unit is formed by etching. The anode has a main body and a protrusion. The first trace is electrically connected to the protrusion through the second via.

22. The method according to claim 20 or 21, characterized in that, The method further includes: The cathode in the second display area is patterned to obtain a plurality of patterned cathode layers, and the orthographic projection of each patterned cathode layer on the substrate covers the orthographic projection of the anode of at least one second light-emitting unit on the substrate.

23. A display device, characterized in that, include: The display panel according to any one of claims 1-19, or the display panel made using the method according to any one of claims 20-22; An under-display camera is disposed on the back of the display panel, and the orthographic projection of the under-display camera on the display panel overlaps with the second display area of ​​the display panel.

Images