An N-face GaN-based P-channel device with high current density and its preparation method

Abstract

The present invention discloses an N-face GaN-based P-channel device with high current density and a preparation method thereof, comprising: a first Si substrate layer, a P-GaN layer, a UID-In layer, and a P-GaN layer arranged in sequence from bottom to top. x GaN layer, Al y GaN barrier layer and protective layer; Al y GaN barrier layer, UID‑In x The GaN layer and the P-GaN layer form an N-face heterojunction structure; where 0.02≤x≤0.05; Al y A gate groove is opened on the GaN barrier layer; y A source electrode and a drain electrode are deposited on either side of the GaN barrier layer, respectively; where 0.2 ≤ y ≤ 0.3; both the source and drain electrodes extend into the protective layer; a gate recess is formed, with the notch facing the protective layer; a gate electrode is disposed in the gate recess; the gate electrode extends into the protective layer; and interconnect metal is deposited above the source, drain, and gate electrodes, respectively, penetrating the protective layer. This invention enables a P-channel device to have a higher hole mobility, thereby improving device performance and enabling a high current density device.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to an N-face GaN-based P-channel device with high current density and a preparation method thereof. Background Art

[0002] GaN's excellent material properties, such as wide bandgap, high electron mobility, and excellent high-temperature stability, make it an unparalleled choice for next-generation high-efficiency power devices and power electronics. Currently, demand for GaN-based HEMT devices is increasing in applications such as power switches and microwave power amplifiers. However, the Si-based CMOS devices that drive GaN-based devices exhibit significant parasitic effects due to their different material properties, severely impacting device performance. Currently, inverters coupling GaN-based enhancement-mode n-channel devices with depletion-mode n-channel devices are limited in widespread application due to significant static power consumption. Therefore, research on the fabrication of GaN-based complementary logic devices is crucial. These devices primarily consist of enhancement-mode n-channel and p-channel devices. While enhancement-mode n-channel devices have been extensively studied, the fabrication of enhancement-mode p-channel devices remains challenging. A key challenge is low hole mobility. Furthermore, ionized impurity scattering from Mg doping and interface charge introduced by the deposition of the sub-gate dielectric layer further reduce hole mobility, resulting in significantly inferior performance of the fabricated p-channel devices compared to their n-channel counterparts. Summary of the Invention

[0003] In order to solve the above problems existing in the prior art, the present invention provides an N-face GaN-based P-channel device with high current density and a method for preparing the same. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0004] A first aspect of an embodiment of the present invention provides an N-face GaN-based P-channel device with high current density, comprising:

[0005] The first Si substrate layer, P-GaN layer, UID-In layer are arranged in sequence from bottom to top. x GaN layer, Al y GaN barrier layer and protective layer;

[0006] The Al y GaN barrier layer, the UID-In x The GaN layer and the P-GaN layer form an N-face heterojunction structure; wherein 0.02≤x≤0.05;

[0007] The Al y A gate groove is provided on the GaN barrier layer; y A source electrode and a drain electrode are deposited on both sides of the GaN barrier layer, respectively; wherein 0.2≤y≤0.3;

[0008] The source electrode and the drain electrode both extend into the protective layer;

[0009] The gate groove has a notch facing the protective layer; a gate electrode is provided on the gate groove;

[0010] The gate electrode extends into the protective layer;

[0011] Interconnect metals penetrating the protective layer are deposited on the source electrode, the drain electrode, and the gate electrode.

[0012] In one embodiment of the present invention, the thickness of the P-GaN layer is 10 nm to 20 nm; the depth of the gate groove is 5 nm to 15 nm;

[0013] The UID-In x The thickness of the GaN layer is 10nm to 20nm;

[0014] The Al y The thickness of the GaN barrier layer is 15nm to 25nm; the Mg doping concentration of the P-GaN layer is 2e19 / cm 3 ~3e19 / cm 3 .

[0015] A second aspect of an embodiment of the present invention provides a method for preparing an N-face GaN-based P-channel device with high current density, comprising:

[0016] Step 1: epitaxially grow materials on the second Si substrate layer. The epitaxial layers from bottom to top are GaN buffer layer, GaN layer, Al y GaN barrier layer, UID-In x GaN layer and P-GaN layer; wherein 0.2≤y≤0.3, 0.02≤x≤0.05;

[0017] Step 2: Etching the P-GaN layer until the remaining thickness is 10 nm to 20 nm;

[0018] Step 3: bonding a first Si substrate layer on the surface of the P-GaN layer;

[0019] Step 4: Flip the product prepared in step 3 to achieve the Al y GaN barrier layer, the UID-In x An N-face heterojunction structure formed by the GaN layer and the P-GaN layer, and etching away the second Si substrate layer;

[0020] Step 5: Completely etching the GaN buffer layer and the GaN layer;

[0021] Step 6: Make a source electrode and a drain electrode on the product prepared in step 5. The source electrode and the drain electrode are respectively located on the Al y Both sides of the GaN barrier layer;

[0022] Step 7: y Etching a gate groove on the GaN barrier layer;

[0023] Step 8: preparing a gate electrode on the product prepared in step 7;

[0024] Step 9: growing a protective layer on the surface of the product;

[0025] Step 10: Photoetching an opening area of ​​the metal interconnection layer on the protective layer; the opening area corresponds to the source electrode, the drain electrode and the gate electrode;

[0026] Step 11: Evaporating interconnect metal in the opening area and leading out electrodes to prepare the device described in the first aspect of the embodiment of the present invention.

[0027] In one embodiment of the present invention, the thickness of the GaN buffer layer is 2 μm to 5 μm, the thickness of the GaN layer is 100 nm to 200 nm, and the thickness of the P-GaN layer is 30 nm to 50 nm; the depth of the gate groove is 5 nm to 15 nm;

[0028] The UID-In x The thickness of the GaN layer is 10nm to 20nm;

[0029] The Al y The thickness of the GaN barrier layer is 15nm to 25nm; the Mg doping concentration of the P-GaN layer is 2e19 / cm 3 ~3e19 / cm 3 .

[0030] In one embodiment of the present invention, the specific steps of step 2 are:

[0031] The product prepared in step 1 is baked, and then placed on a spin coater, and EPI621 photoresist is dripped onto the surface of the P-GaN layer for spin coating, followed by development, ultrapure water rinsing, and nitrogen drying;

[0032] The P-GaN layer is etched using an etcher until the remaining thickness is 10 nm to 20 nm.

[0033] In one embodiment of the present invention, the specific steps of step six include:

[0034] The product prepared in step 5 is placed on a hot plate for baking, and then the photoresist is applied and spun, and the product is placed on a hot plate for baking, and then placed in a photolithography machine to expose the photoresist in the source and drain areas; then, the product is placed in a developer to remove the photoresist in the electrical isolation area, and then the product is rinsed with ultrapure water and blown dry with nitrogen;

[0035] Al in the etched development area y GaN barrier layer and the UID-In x GaN layer up to the P-GaN layer (20);

[0036] The product prepared in the previous step is sequentially placed in an acetone solution, a stripping solution, an acetone solution, and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation area. The product is then rinsed with ultrapure water and blown dry with nitrogen gas.

[0037] The product prepared in the previous step is placed on a hot plate for baking; then, stripping glue is applied and spun, and the product is placed on a hot plate for baking; then, photoresist is applied and spun on the stripping glue, and the product is placed on a hot plate for baking; then, the product after the coating and spun glue is placed in a photolithography machine to expose the photoresist in the source electrode area and the drain electrode area; then, the exposed product is placed in a developer to remove the photoresist and stripping glue in the source electrode area and the drain electrode area, and then it is rinsed with ultrapure water and blown dry with nitrogen;

[0038] Evaporation of source and drain electrodes: Place the products with active and drain electrode photolithography patterns into a plasma stripper for bottom film processing;

[0039] Place it in an electron beam evaporation station to evaporate the ohmic metal, which is a metal stacked structure consisting of two layers of metal, Ni and Au, from bottom to top;

[0040] The product after ohmic metal evaporation is stripped to remove the ohmic metal, photoresist and stripping glue outside the source electrode area and the drain electrode area, and the product is rinsed with ultrapure water and blown dry with nitrogen;

[0041] Perform annealing treatment.

[0042] In one embodiment of the present invention, the specific steps of step eight include:

[0043] The product with the gate groove photolithography pattern is placed in a plasma stripper for bottom film treatment;

[0044] Place it in an electron beam evaporation station to evaporate the gate metal, which is a metal stacked structure consisting of two layers of metal, Ni and Au, from bottom to top;

[0045] The product after gate metal evaporation is stripped to remove the gate metal, photoresist and stripping glue outside the gate electrode area, and then the product is rinsed with ultrapure water and blown dry with nitrogen to form a product with a gate electrode.

[0046] In one embodiment of the present invention, the specific steps of step 10 include:

[0047] The product prepared in step nine is placed on a hot plate for baking, and then photoresist is applied and spun, and the product is placed on a hot plate for baking, and then the product is placed in a photolithography machine to expose the photoresist in the opening area of ​​the metal interconnect layer, and finally, the exposed product is placed in a developer to remove the photoresist in the opening area, and then the product is rinsed with ultrapure water and dried with nitrogen gas; the opening area is located above the source electrode, the drain electrode, and the gate electrode;

[0048] Under the condition that the reaction gases are CF4 and O2, the protective layer in the opening area is etched; the etching depth is to penetrate the protective layer.

[0049] In one embodiment of the present invention, the specific steps of step 11 include:

[0050] The product with the metal interconnection layer etched is placed on a hot plate for baking, and then a stripping adhesive is applied and spun on the source electrode and drain electrode in the opening area and the protective layer that has not been etched, and the product is placed on a hot plate for baking; then, a photoresist is applied and spun on the stripping adhesive, and the product is placed on a hot plate for baking, and then the product with the coated and spun adhesive is placed in a photolithography machine to expose the photoresist in the opening area; finally, the exposed product is placed in a developer to remove the photoresist and stripping adhesive in the opening area, and then the product is rinsed with ultrapure water and blown dry with nitrogen;

[0051] Putting the product with the photolithographic pattern of the opening area into a plasma stripper for bottom film treatment;

[0052] Place the interconnect metal in an electron beam evaporation station, wherein the interconnect metal is a metal stacked structure consisting of two layers of metal, Ti and Au, in order from bottom to top;

[0053] The product after the interconnect metal evaporation is stripped to remove the interconnect metal, photoresist and stripping glue outside the metal interconnect layer area, and the product is rinsed with ultrapure water and blown dry with nitrogen to complete the preparation and obtain the device described in the first aspect of the embodiment of the present invention.

[0054] Beneficial effects of the present invention:

[0055] The present invention combines P-GaN and Al y Inserting UID-In into GaN barrier layer xThe GaN layer is used to improve the mobility reduction caused by ionized impurity scattering; on the other hand, when using N-face GaN material to prepare devices, there is no need to deposit an insulating dielectric under the gate, which can avoid the influence of fixed charges introduced by the deposited insulating dielectric under the gate and the interface charge on the hole mobility, avoiding the reduction of hole mobility, and enabling P-channel devices to have higher hole mobility, thereby improving device performance and realizing high current density devices.

[0056] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 Schematic diagram of the structure of an N-face GaN-based P-channel device with high current density provided by an embodiment of the present invention:

[0058] Figure 2a-2k A preparation process diagram of a method for preparing an N-face GaN-based P-channel device with high current density provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0059] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0060] Example 1

[0061] See Figure 1 , an N-face GaN-based P-channel device with high current density, comprising:

[0062] The first Si substrate layer 11, the P-GaN layer 20, the UID-In x GaN layer 30, Al y GaN barrier layer 40 and protective layer 50 .

[0063] P-GaN layer 20, UID-In x GaN layer 30 and Al y The GaN barrier layer 40 forms an N-face heterojunction structure.

[0064] Al y A gate groove 41 is formed on the GaN barrier layer 40; y A source electrode 61 and a drain electrode 62 are deposited on both sides of the GaN barrier layer 40 , respectively, wherein 0.2≤y≤0.3. The source electrode 61 and the drain electrode 62 both extend into the protective layer 50 .

[0065] The gate groove 41 has an opening facing the protection layer 50 , and a gate electrode 42 is disposed on the gate groove 41 . The gate electrode 42 extends into the protection layer 50 .

[0066] Interconnection metals 70 are deposited on the source electrode 61 , the drain electrode 62 and the gate electrode 42 respectively, penetrating the protection layer 50 .

[0067] Furthermore, the thickness of the P-GaN layer 20 is 10nm to 20nm. In this embodiment, if the thickness of the P-GaN layer 20 is greater than 20nm, the device of this embodiment cannot be turned off normally, and the leakage current is extremely large. If the thickness is less than 10nm, it cannot provide holes. Therefore, the P-GaN layer 20 in this embodiment can not only provide holes to the device but also ensure the normal use of the device. The depth of the gate groove 41 is 5nm to 15nm. Al y The thickness of the GaN barrier layer 40 is 15 nm to 25 nm. The thickness of the protective layer 50 is 200 nm. x The thickness of the GaN layer 30 is 0 nm to 20 nm, and 0.02≤x≤0.05. The Mg doping concentration of the P-GaN layer 20 is 2e19 / cm 3 ~3e19 / cm 3 .

[0068] In this embodiment, on the one hand, by y UID-In is inserted into the GaN barrier layer 40 x GaN layer 30 inserted UID-In x The blocking effect of the GaN layer 30 reduces the scattering of ionized impurities, thereby improving the mobility of holes. x The GaN layer 30 can be y The GaN barrier layer 40 generates polarization characteristics, so that polarization charges at the interface induce the generation of holes, thereby increasing the number of holes and further improving the hole mobility.

[0069] At the same time, UID-In x The GaN layer 30 has a smaller band gap than GaN, so the Al y GaN / In x The valence band gap between GaN is larger, and the resulting two-dimensional hole concentration is higher, which further increases the number of holes and thus improves the hole mobility, thereby further optimizing the performance of the device. x In the GaN layer 30 , if x is greater than 0.05, it will lead to increased alloy disorder scattering of carriers, which will reduce the mobility of carriers, ie, holes. Preferably, x=0.04.

[0070] In addition, when the Al composition is 0.2 to 0.3, the Al y GaN Lattice Constant and UID-In x GaN has better matching, can achieve better interface properties and is easy to grow.

[0071] On the other hand, when using N-face GaN material to prepare P-channel devices, there is no need to deposit an insulating dielectric under the gate, which can avoid the influence of fixed charges introduced by the insulating dielectric deposited under the gate and the interface charge on the hole mobility, thereby avoiding the reduction of hole mobility and enabling the P-channel device to have a higher hole mobility, thereby improving the performance of the device to achieve a high current density device.

[0072] In a feasible implementation, the material of the protective layer 50 is SiN. Preferably, the thickness of the protective layer 50 is 200 nm. The Mg doping concentration of the P-GaN layer 20 is 2e19-3e19 / cm 3 .

[0073] In one possible implementation, Al y If the Al composition y in the GaN barrier layer 4050 is less than 0.2, the current characteristics of the device will deteriorate. If it is greater than 0.3, the growth requirements cannot be met, resulting in poor device quality and unusable device. Preferably, y=0.25.

[0074] In one feasible implementation, both the source electrode 61 and the drain electrode 62 are metal stack structures, comprising, from bottom to top, two metal layers: 20nm thick Ni and 40nm thick Au. The gate electrode 42 is a metal stack structure comprising, from bottom to top, two metal layers: 40nm thick Ni and 100nm thick Au. The interconnect metal 70 is a metal stack structure comprising, from bottom to top, two metal layers: 40nm thick Ti and 200nm thick Au.

[0075] Example 2

[0076] A second aspect of an embodiment of the present invention provides a method for preparing an N-face GaN-based P-channel device with high current density, comprising:

[0077] Step 1: epitaxially grow materials on the second Si substrate layer 12. The epitaxial layers from bottom to top are GaN buffer layer 80, GaN layer 90, Al y GaN barrier layer 40, UID-In x GaN layer 30 and P-GaN layer 20; wherein 0.2≤y≤0.3, 0.02≤x≤0.05.

[0078] Step 2: Etch the P-GaN layer 20 until the remaining thickness is 10 nm to 20 nm.

[0079] Step 3: Bond the first Si substrate layer 11 on the surface of the P-GaN layer 20 .

[0080] Step 4: Flip the product prepared in step 3 to achieve Al yGaN barrier layer 40, UID-In x The GaN layer 30 and the P-GaN layer 20 form an N-face heterojunction structure, and the second Si substrate layer 12 is etched away.

[0081] Step 5: Etching the GaN buffer layer 80 and the GaN layer 90 .

[0082] Step 6: Make a source electrode 61 and a drain electrode 62 on the product prepared in step 5. The source electrode 61 and the drain electrode 62 are respectively located on the Al y Both sides of the GaN barrier layer 40 .

[0083] Step 7: In Al y A gate groove 41 is etched on the GaN barrier layer 40 .

[0084] Step eight: prepare a gate electrode 42 on the product prepared in step seven.

[0085] Step nine: growing a protective layer 50 on the surface of the product.

[0086] Step 10: Photoetching an opening area of ​​the metal interconnection layer on the protective layer 50; the opening area corresponds to the source electrode 61, the drain electrode 62 and the gate electrode 42.

[0087] Step 11: Evaporate interconnect metal 70 in the opening area, lead out electrodes, and prepare the device in Example 1.

[0088] Furthermore, the thickness of the GaN buffer layer 80 is 2 μm to 5 μm, the thickness of the GaN layer 90 is 100 nm to 200 nm, and the thickness of the Al y The thickness of the GaN barrier layer 40 is 15nm to 25nm. x The thickness of the GaN layer 30 is 10nm to 20nm, and the thickness of the P-GaN layer 20 is 30nm to 50nm. The depth of the gate groove 41 is 5nm to 15nm. The Mg doping concentration of the P-GaN layer 20 is 2e19 / cm 3 ~3e19 / cm 3 Preferably, x=0.04, y=0.25. The material of the protective layer 50 is SiN. Preferably, the thickness of the protective layer 50 is 200 nm.

[0089] The source electrode 61 and drain electrode 62 are both metal stack structures, consisting of two metal layers, 20 nm thick Ni and 40 nm thick Au, from bottom to top. The gate electrode 42 is a metal stack structure consisting of two metal layers, 40 nm thick Ni and 100 nm thick Au, from bottom to top. The interconnect metal 70 is a metal stack structure consisting of two metal layers, 40 nm thick Ti and 200 nm thick Au, from bottom to top.

[0090] Example 3

[0091] An embodiment of the present invention provides a method for preparing an N-face GaN-based P-channel device with high current density, comprising the following steps:

[0092] Step 301: epitaxially grow materials on the second Si substrate layer 12 by MOCVD method. The epitaxial layers from bottom to top are GaN buffer layer 80, GaN layer 90, Al y GaN barrier layer 40, UID-In x GaN layer 30 and P-GaN layer 20; wherein 0.02≤x≤0.05, 0.2≤y≤0.3. Figure 2a shown.

[0093] The thickness of the GaN buffer layer 80 is 2 μm to 5 μm, the thickness of the GaN layer 90 is 100 nm to 200 nm, and the thickness of the Al y The thickness of the GaN barrier layer 40 is 15nm to 25nm. x The thickness of the GaN layer 30 is 10 nm to 20 nm, and the thickness of the P-GaN layer 20 is 30 nm to 50 nm. The Mg doping concentration of the P-GaN layer 20 is 2e19 / cm 3 ~3e19 / cm 3 .

[0094] Al y If the Al composition y in the GaN barrier layer 4050 is less than 0.2, the current characteristics of the device will deteriorate. If it is greater than 0.3, the growth requirements cannot be met, resulting in poor device quality and unusable device. Preferably, y=0.25 and x=0.04.

[0095] Step 302: Etching the P-GaN thin layer. The product prepared in step 301 is baked at 200°C and then placed on a spin coater. EPI621 photoresist is dripped onto the surface of the P-GaN layer 20 for spin coating. Spin coating conditions: 500 rpm for 5 seconds, then 3500 rpm for 40 seconds, and baked at 90°C. The product is then developed in a developer solution, rinsed with ultrapure water for 2 minutes, and dried with nitrogen.

[0096] Step 303: Use a chlorine-based ICP etcher to etch the P-GaN layer 20. The etching conditions are: upper electrode power 40W-60W, lower electrode power 10W-20W, pressure 5mTorr, flow ratio of Cl2 and BCl3 8 / 20sccm, and the P-GaN layer 20 is 10nm-20nm in thickness. Figure 2b shown.

[0097] Step 304: Using chemical mechanical polishing, a first Si substrate layer 11 with a thickness of 500 μm to 700 μm is bonded to the surface of the P-GaN layer 20. Figure 2c shown.

[0098] Step 305: Turn the product prepared in step 304 over to achieve Al y GaN barrier layer 40, UID-In x The N-face heterojunction structure formed by the GaN layer 30 and the P-GaN layer 20 is as follows: Figure 2d As shown, the second Si substrate layer 12 is completely etched away. Etching conditions: upper electrode power 250W-350W, lower electrode power 20W-40W, pressure 5mTorr, SF6 flow rate 50sccm.

[0099] Step 306: Completely etch the GaN buffer layer 80 and the GaN layer 90 to the Al y The GaN barrier layer 40 is etched using ICP chlorine-based conditions, with the following etching conditions: upper electrode power 40W-60W, lower electrode power 20W-30W, pressure 5mT, Cl2 flow rate 8sccm, BCl3 flow rate 20sccm. Figure 2e shown.

[0100] P-channel device fabrication source electrode 61 and drain electrode 62:

[0101] Al in the source and drain regions y GaN and UID-In x GaN etching:

[0102] Step 307: Place the product prepared in step 306 on a hot plate at 200°C for baking, then apply and spin the photoresist at a spinning speed of 3500 rpm, and bake the product on a hot plate at 90°C. Then, place it in a photolithography machine to expose the photoresist in the source and drain areas; then, place it in a developer to remove the photoresist in the electrical isolation area, and rinse it with ultrapure water and blow it dry with nitrogen.

[0103] Step 308: Use ICP process to etch the Al in the development area. y GaN barrier layer 40 and UID-In x GaN layer 30 to p-GaN layer 20. Etching conditions: upper electrode power 15W~25W, lower electrode power 3W~5W, pressure 5mT, Cl2 flow rate 4sccm, BCl3 flow rate 10sccm. Figure 2f shown.

[0104] Step 309: Place the product prepared in step 308 into acetone solution, stripping solution, acetone solution and ethanol solution in sequence for cleaning to remove the photoresist outside the electrical isolation area, rinse the product with ultrapure water and blow dry with nitrogen.

[0105] Photolithography source and drain electrode 62 area:

[0106] Step 310, bake the product prepared in step 309 on a hot plate at 200°C; then, apply and spin the stripping glue, the spinning conditions are: SF6, 2000 rpm, 40 sec, thickness 0.35 μm, and bake the product on a hot plate at 200°C; then, apply and spin the photoresist on the stripping glue, the spinning conditions are: EPI621, 5000 rpm, time 30 sec, thickness 0.77 μm, and bake on a hot plate at 90°C, after which the coated and spun product is placed in a photolithography machine to expose the photoresist in the source electrode area and the drain electrode area, after which the exposed product is placed in a developer to remove the photoresist and stripping glue in the source electrode area and the drain electrode area, and then rinsed with ultrapure water and blown dry with nitrogen.

[0107] Evaporation source electrode 61 and drain electrode 62:

[0108] Step 311: Evaporation of the source and drain electrodes 61 and 62: Place the photolithographically patterned product of the active and drain electrodes 61 and 62 in a plasma stripper for base film treatment. Processing conditions: α-plasma stripper, vacuum for 2 minutes, followed by an O2 flow rate of 100 to 150 sccm and a power of 150 to 250 W for 5 to 10 minutes.

[0109] Step 312: Place the evaporator in an electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After Torr, ohmic metal is evaporated. The ohmic metal is a metal stacked structure consisting of two layers of metal, 20nm thick Ni and 40nm thick Au, from bottom to top.

[0110] Step 313: strip the product after ohmic metal evaporation to remove the ohmic metal, photoresist and stripping glue outside the source electrode area and drain electrode area, rinse the product with ultrapure water and blow dry with nitrogen. Figure 2g shown.

[0111] Step 314: perform annealing treatment. The annealing atmosphere is O2, the annealing temperature is 500°C to 550°C, and the annealing time is 5 minutes to 10 minutes.

[0112] The source electrode 61 and the drain electrode 62 are connected to the Al yGaN barrier layer 40, UID-In x The GaN layer 30 is in contact with the p-GaN layer 20 . Since the p-GaN layer 20 is doped with Mg, the ohmic contact can be further improved, thereby optimizing the device performance.

[0113] Step 315: Etching the P-channel device gate groove 41. Chlorine-based ICP etching of Al y The GaN barrier layer is 405nm to 15nm to form a groove structure. Etching conditions: upper electrode power 15W to 25W, lower electrode power 3W to 5W, pressure 5mT, Cl2 flow rate 4sccm, BCl3 flow rate 10sccm. Figure 2h shown.

[0114] P-channel device gate electrode 42 fabrication:

[0115] Step 316: Place the product with the photolithographic pattern of the gate groove 41 into a plasma stripper for base film treatment. Treatment conditions: α-plasma plasma stripper, vacuum for 2 minutes, then O2 flow rate of 100 sccm to 150 sccm, power of 150 W to 250 W, and treatment for 5 minutes to 10 minutes.

[0116] Step 317: Place the evaporator in the electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After the Torr process, a gate metal is evaporated. The gate metal is a metal stacked structure consisting of two metal layers, Ni with a thickness of 40 nm and Au with a thickness of 100 nm, from bottom to top.

[0117] Step 318: strip the product after gate metal evaporation to remove the gate metal, photoresist and stripping glue outside the gate electrode area, then rinse the product with ultrapure water and blow dry with nitrogen to form a product with a gate electrode 42. Figure 2i shown.

[0118] Step 319: Grow SiN protective layer 50. A PECVD process is used to grow a 200nm thick SiN protective layer 50. The growth process conditions are: using NH3 and SiH4 as reaction gases, substrate temperature of about 250°C, reaction chamber pressure of 600mTorr, and RF power of 20W to 25W. Figure 2j shown.

[0119] Photolithography electrode opening:

[0120] Step 320: The product prepared in step 319 is baked on a 200°C hot plate. Then, photoresist is applied and spun at a speed of 3500 rpm. The product is baked on a 90°C hot plate. Next, the product is placed in a photolithography machine to expose the photoresist in the opening area of ​​the metal interconnect layer. Finally, the exposed product is placed in a developer to remove the photoresist in the opening area, and then rinsed with ultrapure water and dried with nitrogen. The opening area is located above the source electrode 61, the drain electrode 62, and the gate electrode 42.

[0121] Step 321 : Using ICP etching, under the condition that the reaction gases are CF 4 and O 2 , the 200 nm thick protective layer 50 in the opening area is etched to a depth that penetrates the protective layer 50 .

[0122] Lead out the electrodes and complete the device fabrication:

[0123] Step 322: Place the product with the metal interconnection layer openings etched on a hot plate at 200°C for baking. Then, apply and spin the stripping glue on the source electrode 61 and the drain electrode 62 in the opening area and the protective layer 50 that has not been etched. The thickness of the stripping glue is 0.35μm, and the product is placed on a hot plate for baking at 200°C. Next, apply and spin the photoresist on the stripping glue. The thickness of the stripping glue is 0.77μm, and the product is placed on a hot plate for baking at 90°C. After that, place the product with the coating and spinning of the glue in a photolithography machine to expose the photoresist in the opening area. Finally, place the exposed product in a developer to remove the photoresist and stripping glue in the opening area, and rinse it with ultrapure water and blow it dry with nitrogen.

[0124] Evaporated Interconnect Metal 70:

[0125] Step 323: Place the product with the photolithographic pattern of the opening area into a plasma stripper for base film treatment. Treatment conditions: α-plasma plasma stripper, vacuum for 2 minutes, then O2 flow rate of 100 sccm to 150 sccm, power of 150W to 250W, and treatment for 5 minutes to 10 minutes.

[0126] Step 324: Place the evaporator in an electron beam evaporation station and wait until the vacuum degree of the reaction chamber of the electron beam evaporation station reaches 2×10 - 6 After the Torr process, the interconnection metal 70 is evaporated. The interconnection metal 70 is a metal stacked structure consisting of two metal layers, Ti with a thickness of 40 nm and Au with a thickness of 200 nm, from bottom to top.

[0127] Step 325: strip the product after evaporation of the interconnection metal 70 to remove the interconnection metal 70, photoresist and stripping glue outside the metal interconnection layer area, rinse the product with ultrapure water and blow dry with nitrogen to complete the preparation and obtain the device in Example 1. Figure 2k shown.

[0128] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0129] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0130] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood broadly. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0131] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0132] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0133] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. An N-face GaN-based P-channel device with high current density, characterized in that: include: The first Si substrate layer (11), the P-GaN layer (20), the UID-In x GaN layer (30), Al y GaN barrier layer (40) and protective layer (50); wherein the UID represents unintentional doping; The Al y GaN barrier layer (40), the UID-In x The GaN layer (30) and the P-GaN layer (20) form an N-face heterojunction structure; wherein 0.02≤x≤0.05; The Al y A gate groove (41) is provided on the GaN barrier layer (40); the Al y A source electrode (61) and a drain electrode (62) are deposited on both sides of the GaN barrier layer (40); wherein 0.2≤y≤0.3; The tops of the source electrode (61) and the drain electrode (62) both extend into the protective layer (50); the bottoms of the source electrode (61) and the drain electrode (62) both contact the upper surface of the P-GaN layer (20); The gate groove (41) has a notch facing the protective layer (50); a gate electrode (42) is provided on the gate groove (41); The top of the gate electrode (42) extends into the protective layer (50); the bottom of the gate electrode (42) extends to the Al y within the GaN barrier layer (40); Interconnection metals (70) penetrating the protective layer (50) are deposited above the source electrode (61), the drain electrode (62), and the gate electrode (42).

2. The N-face GaN-based P-channel device with high current density according to claim 1, characterized in that: The thickness of the P-GaN layer (20) is 10 nm to 20 nm; the depth of the gate groove (41) is 5 nm to 15 nm; The UID-In x The thickness of the GaN layer (30) is 10 nm to 20 nm; The Al y The thickness of the GaN barrier layer (40) is 15 nm to 25 nm; the Mg doping concentration of the P-GaN layer (20) is 2e19 / cm 3 ~3e19 / cm 3 .

3. A method for preparing an N-face GaN-based P-channel device with high current density, characterized in that: include: Step 1: epitaxially grow materials on the second Si substrate layer (12), wherein the epitaxial layers from bottom to top are GaN buffer layer (80), GaN layer (90), Al y GaN barrier layer (40), UID-In x GaN layer (30) and P-GaN layer (20); wherein 0.2≤y≤0.3, 0.02≤x≤0.05; wherein the UID represents unintentional doping; Step 2: etching the P-GaN layer (20) until the remaining thickness is 10 nm to 20 nm; Step 3: bonding a first Si substrate layer (11) on the surface of the P-GaN layer (20); Step 4: Flip the product prepared in step 3 to achieve the Al y GaN barrier layer (40), the UID-In x An N-face heterojunction structure formed by the GaN layer (30) and the P-GaN layer (20), and etching away the second Si substrate layer (12); Step 5: Completely etching the GaN buffer layer (80) and the GaN layer (90); Step 6: Make a source electrode (61) and a drain electrode (62) on the product prepared in step 5. The source electrode (61) and the drain electrode (62) are respectively located on the Al y Both sides of the GaN barrier layer (40); Step 7: y Etching a gate groove (41) on the GaN barrier layer (40); Step eight, preparing a gate electrode (42) on the product prepared in step seven; Step nine, growing a protective layer (50) on the surface of the product; Step 10: photoetching an opening area of ​​the metal interconnection layer on the protective layer (50); the opening area corresponds to the source electrode (61), the drain electrode (62) and the gate electrode (42); Step 11: evaporate interconnect metal (70) in the opening area, lead out electrodes, and prepare the device as claimed in claim 1 or 2.

4. The method for preparing an N-face GaN-based P-channel device with high current density according to claim 3, characterized in that: The thickness of the GaN buffer layer (80) is 2 μm to 5 μm, the thickness of the GaN layer (90) is 100 nm to 200 nm, and the thickness of the P-GaN layer (20) is 30 nm to 50 nm; the depth of the gate groove (41) is 5 nm to 15 nm; The UID-In x The thickness of the GaN layer (30) is 10 nm to 20 nm; The Al y The thickness of the GaN barrier layer (40) is 15 nm to 25 nm; the Mg doping concentration of the P-GaN layer (20) is 2e19 / cm 3 ~3e19 / cm 3 .

5. The method for preparing an N-face GaN-based P-channel device with high current density according to claim 4, characterized in that: The specific steps of step 2 are: The product prepared in step 1 is baked, and then placed on a coating machine, and EPI621 photoresist is dripped onto the surface of the P-GaN layer (20) for coating, and then developed and rinsed with ultrapure water and dried with nitrogen; The P-GaN layer (20) is etched using an etcher until the remaining thickness is 10 nm to 20 nm.

6. The method for preparing an N-face GaN-based P-channel device with high current density according to claim 5, characterized in that: The specific steps of step six include: The product prepared in step 5 is placed on a hot plate for baking, and then the photoresist is applied and spun, and the product is placed on a hot plate for baking, and then placed in a photolithography machine to expose the photoresist in the source and drain areas; then, the product is placed in a developer to remove the photoresist in the electrical isolation area, and then the product is rinsed with ultrapure water and blown dry with nitrogen; Al in the etched development area y GaN barrier layer (40) and the UID-In x GaN layer (30) up to the P-GaN layer (20); The product prepared in the previous step is sequentially placed in an acetone solution, a stripping solution, an acetone solution, and an ethanol solution for cleaning to remove the photoresist outside the electrical isolation area. The product is then rinsed with ultrapure water and blown dry with nitrogen gas. The product prepared in the previous step is placed on a hot plate for baking; then, stripping glue is applied and spun, and the product is placed on a hot plate for baking; then, photoresist is applied and spun on the stripping glue, and the product is placed on a hot plate for baking; then, the product after the coating and spun glue is placed in a photolithography machine to expose the photoresist in the source electrode area and the drain electrode area; then, the exposed product is placed in a developer to remove the photoresist and stripping glue in the source electrode area and the drain electrode area, and then it is rinsed with ultrapure water and blown dry with nitrogen; Evaporating the source electrode (61) and the drain electrode (62): placing the product with the photolithographic pattern of the active electrode (61) and the drain electrode (62) into a plasma degumming machine for bottom film processing; Place it in an electron beam evaporation station to evaporate the ohmic metal, which is a metal stacked structure consisting of two layers of metal, Ni and Au, from bottom to top; The product after ohmic metal evaporation is stripped to remove the ohmic metal, photoresist and stripping glue outside the source electrode area and the drain electrode area, and the product is rinsed with ultrapure water and blown dry with nitrogen; Perform annealing treatment.

7. The method for preparing an N-face GaN-based P-channel device with high current density according to claim 6, characterized in that: The specific steps of step eight include: The product with the photolithographic pattern of the gate groove (41) is placed in a plasma stripper to perform bottom film treatment; Place it in an electron beam evaporation station to evaporate the gate metal, which is a metal stacked structure consisting of two layers of metal, Ni and Au, from bottom to top; The product after gate metal evaporation is stripped to remove the gate metal, photoresist and stripping glue outside the gate electrode area, and then the product is rinsed with ultrapure water and blown dry with nitrogen to form a product with a gate electrode (42).

8. The method for preparing an N-face GaN-based P-channel device with high current density according to claim 7, characterized in that: The specific steps of step 10 include: The product prepared in step nine is placed on a hot plate for baking, and then, the photoresist is coated and spun, and the product is placed on a hot plate for baking, and then, the product is placed in a photolithography machine to expose the photoresist in the opening area of ​​the metal interconnection layer, and finally, the product after exposure is placed in a developer to remove the photoresist in the opening area, and is then rinsed with ultrapure water and dried with nitrogen; the opening area is located above the source electrode (61), the drain electrode (62) and the gate electrode (42); Under the condition that the reaction gases are CF4 and O2, the protective layer (50) in the opening area is etched; the etching depth is through the protective layer (50).

9. The method for preparing an N-face GaN-based P-channel device with high current density according to claim 8, characterized in that: The specific steps of step 11 include: The product after the metal interconnection layer hole etching is placed on a hot plate for baking, and then the stripping glue is applied and spun on the source electrode (61) and the drain electrode (62) in the hole area and the protective layer (50) not etched by the hole, and the product is placed on a hot plate for baking; then, the photoresist is applied and spun on the stripping glue, and the product is placed on a hot plate for baking, and then the product after the coating and spun glue is placed in a photolithography machine to expose the photoresist in the hole area; finally, the exposed product is placed in a developer to remove the photoresist and stripping glue in the hole area, and is rinsed with ultrapure water and blown dry with nitrogen; Putting the product with the photolithographic pattern of the opening area into a plasma stripper for bottom film treatment; Placing the interconnection metal (70) in an electron beam evaporation table to evaporate the interconnection metal (70), wherein the interconnection metal (70) is a metal stacked structure consisting of two metal layers of Ti and Au in order from bottom to top; The product after the interconnection metal (70) evaporation is stripped to remove the interconnection metal (70), photoresist and stripping glue outside the metal interconnection layer area, and the product is rinsed with ultrapure water and blown dry with nitrogen to complete the preparation and obtain the device as claimed in claim 1 or 2.

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