Semiconductor Structure and Method for Forming the Same

Abstract

A semiconductor structure and a method for forming the same. The method includes: providing a substrate; forming a plurality of discrete gate structures, a first conductive structure and sidewall structures on the substrate, and forming a plurality of source / drain structures in the substrate on both sides of the gate structures. The first conductive structure is located on the surface of the source / drain structures, and the sidewall structures are located between the sidewalls of the gate structures and the first conductive structure. The sidewall structures include an air gap and a sealing layer located on top of the air gap, and the sealing layer is used to seal the air gap. Thus, through the air gap, the parasitic capacitance of the semiconductor structure is reduced, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly relates to a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor manufacturing, with the development trend of very large scale integrated circuits, the feature size of integrated circuits continues to decrease. To adapt to the reduction of the feature size, the channel length of MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) also continues to shorten accordingly.

[0003] As the gate electrode length continues to decrease, the most serious parasitic capacitance in MOS transistors exists between the gate electrode and the contact-plug above the source / drain regions, and reducing the parasitic capacitance is the main method to improve the response speed, power consumption, etc. of small-size MOS transistors.

[0004] However, in the current MOS transistor structure, the material of the spacer is generally silicon nitride, silicon oxide, etc. Since the dielectric constants of materials such as silicon nitride and silicon oxide are relatively large, the parasitic capacitance between the gate electrode and the contact plug of the source / drain region is relatively large, increasing the device delay and switching power consumption. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same to reduce the parasitic capacitance and reduce the device delay and switching power consumption.

[0006] To solve the above technical problem, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a plurality of gate structures located on the substrate and separated from each other; a plurality of source / drain structures located in the substrate on both sides of the gate structures; a first conductive structure located on the surface of the source / drain structures; and a spacer structure located between the sidewalls of the gate structure and the first conductive structure, the spacer structure including an air gap and a sealing layer located on the top of the air gap, the sealing layer being used to seal the air gap.

[0007] Optionally, the spacer structure further includes: a first spacer located on the sidewall of the gate structure, the air gap being located between the first spacer and the sidewall of the first conductive structure.

[0008] Optionally, the spacer structure further includes: an etch stop layer located between the first spacer and the air gap.

[0009] Optionally, the spacer structure further includes: a second spacer located on the sidewall of the first conductive structure, the air gap being located between the sidewalls of the first spacer and the second spacer.

[0010] Optionally, the sidewall structure further includes a buffer layer located between the first conductive structure and the second sidewall.

[0011] Optionally, in a direction perpendicular to the extending direction of the gate structure, the width of the air gap is below 50 angstroms.

[0012] Optionally, the top surface of the gate structure is lower than the top surface of the sidewall structure; the semiconductor structure further includes a gate protection structure located on the top surface of the gate structure, and the sidewall structure is also located on the sidewalls of the gate protection structure.

[0013] Optionally, the top surface of the first conductive structure is lower than the top surface of the sidewall structure; the semiconductor structure further includes a conductive protection structure located on the top surface of the first conductive structure, and the sidewall structure is also located on the sidewalls of the conductive protection structure.

[0014] Optionally, it further includes a second dielectric layer located on the surface of the first conductive structure, the surface of the gate structure, and the air gap. The second dielectric layer has a second conductive opening and a third conductive opening. The second conductive opening exposes the surface of the gate structure, and the third conductive opening exposes the surface of the first conductive structure; a second conductive structure located in the second conductive opening; and a third conductive structure located in the third conductive opening.

[0015] Optionally, the substrate includes a base and a plurality of fin structures located on the base and separated from each other, and the gate structure straddles a plurality of the fin structures.

[0016] Optionally, the fin structure includes a plurality of fin sacrificial layers arranged in a direction perpendicular to the surface of the substrate, and nanosheets located between adjacent fin sacrificial layers.

[0017] Correspondingly, the technical solution of the present invention further provides a method for forming a semiconductor structure, including: providing a substrate; forming a plurality of mutually separated gate structures, first conductive structures, and sidewall structures on the substrate, and forming a plurality of source-drain structures in the substrate on both sides of the gate structure. The first conductive structure is located on the surface of the source-drain structure, the sidewall structure is located between the sidewalls of the gate structure and the first conductive structure, and the sidewall structure includes an air gap and a sealing layer located on the top of the air gap, and the sealing layer is used to seal the air gap.

[0018] Optionally, the sidewall structure further includes a first sidewall located on the sidewalls of the gate structure, and the air gap is located between the first sidewall and the sidewall of the first conductive structure.

[0019] Optionally, the material of the first sidewall includes a low-k dielectric material.

[0020] Optionally, the sidewall structure further includes a second sidewall located on the sidewalls of the first conductive structure, and the air gap is located between the sidewalls of the first sidewall and the second sidewall.

[0021] Optionally, the material of the second sidewall includes a low-k dielectric material, titanium nitride, or a combination of tantalum and tantalum nitride.

[0022] Optionally, it further includes: after forming the source / drain structure and before forming the gate structure, forming a first dielectric layer on the substrate and on the surface of the source / drain structure, and the first dielectric layer also lies on the sidewalls of the first sidewall.

[0023] Optionally, the method of forming the first sidewall includes: before forming the source / drain structure, forming a plurality of discrete dummy gate structures on the substrate surface; forming the first sidewall on the sidewalls of the dummy gate structures; the method of forming the gate structure includes: after forming the first dielectric layer, removing the dummy gate structures, forming a gate opening in the first dielectric layer, and the gate opening exposes the sidewall surfaces of the first sidewall; forming the gate structure in the gate opening.

[0024] Optionally, the method of forming the second sidewall includes: after forming the gate structure, etching the first dielectric layer to form a first conductive opening in the first dielectric layer, and the first conductive opening exposes the surface of the source / drain structure; before forming the first conductive structure, forming the second sidewall on the sidewalls of the first conductive opening.

[0025] Optionally, the method of forming the air gap and the sealing layer includes: before forming the second sidewall, forming a sacrificial layer on the sidewalls of the first conductive opening, and the second sidewall is located on the sidewall surface of the sacrificial layer; after forming the first conductive structure, etching and removing part or all of the sacrificial layer to form an air groove; forming the sealing layer in the air groove at the top.

[0026] Optionally, in the process of etching and removing part or all of the sacrificial layer, the etching selectivity of the sacrificial layer to the first sidewall is above 10:1.

[0027] Optionally, in the process of etching and removing part or all of the sacrificial layer, the etching selectivity of the sacrificial layer to the second sidewall is above 10:1.

[0028] Optionally, the thickness range of the sacrificial layer is from 10 Å to 50 Å.

[0029] Optionally, the material of the sacrificial layer includes silicon, silicon oxide, carbon, or a metal compound.

[0030] Optionally, the method of forming the sacrificial layer includes: depositing a sacrificial material film on the inner wall surface of the first conductive opening, the top surface of the gate structure, and the top surface of the first sidewall; using an anisotropic etching process to etch back the sacrificial material film until the sacrificial material film on the bottom surface of the first conductive opening, the top surface of the gate structure, and the top surface of the first sidewall is removed, thereby forming the sacrificial layer.

[0031] Optionally, the sidewall structure further includes an etch stop layer located between the air gap and the first sidewall.

[0032] Optionally, the method of forming the etch stop layer includes: forming an initial etch stop layer on the surface of the substrate, the surface of the source / drain structure, and the sidewalls of the first sidewall before forming the first conductive opening; after forming the second sidewall and before forming the first conductive structure, etching the initial etch stop layer on the source / drain structure until the surface of the source / drain structure is exposed.

[0033] Optionally, in the process of etching and removing part or all of the sacrificial layer, the etching selectivity between the sacrificial layer and the etch stop layer is above 10:1.

[0034] Optionally, the material of the etch stop layer includes one or a combination of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride boron.

[0035] Optionally, the sidewall structure further includes: a buffer layer located between the sidewalls of the first conductive structure and the second sidewall.

[0036] Optionally, the material of the buffer layer includes titanium nitride, or a combination of tantalum and tantalum nitride.

[0037] Optionally, it further includes: etching back the gate structure before forming the air gap; after etching back the gate structure, forming a gate protection structure on the top surface of the gate structure, and the sidewall structure is also located on the sidewalls of the gate protection structure.

[0038] Optionally, it further includes: etching back the first conductive structure before forming the air gap; after etching back the first conductive structure, forming a conductive protection structure on the top surface of the first conductive structure, and the sidewall structure is also located on the sidewalls of the conductive protection structure.

[0039] Optionally, it further includes: forming a second dielectric layer on the surface of the first conductive structure, the surface of the gate structure, and the sealing layer; forming a second conductive opening in the second dielectric layer, the second conductive opening exposing the surface of the gate structure; forming a second conductive structure in the second conductive opening; forming a third conductive opening in the second dielectric layer, the third conductive opening exposing the surface of the first conductive structure; and forming a third conductive structure in the third conductive opening.

[0040] Optionally, the substrate includes a base and a plurality of fin structures located on the base and separated from each other, and the gate structure straddles a plurality of the fin structures.

[0041] Optionally, the process of forming the sealing layer includes an uneven chemical vapor deposition process.

[0042] Optionally, the material of the sealing layer includes silicon nitride, silicon oxide, or silicon carbide.

[0043] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0044] In the semiconductor structure provided by the technical solution of the present invention, the sidewall structure is located between the sidewalls of the gate structure and the first conductive structure, and the sidewall structure includes an air gap and a sealing layer located on top of the air gap, and the air gap can be used to form an "air sidewall". Since the dielectric constant of air is very small, the presence of the "air sidewall" is beneficial to reducing the overall dielectric constant of the dielectric between the gate structure and the first conductive structure. Thus, it is beneficial to reducing the parasitic capacitance generated between the gate structure and the first conductive structure. Furthermore, the delay and switching power consumption are reduced, and the performance of the semiconductor structure is improved.

[0045] In the method for forming a semiconductor structure provided by the technical solution of the present invention, a sidewall structure is formed between the sidewalls of the gate structure and the first conductive structure, and the sidewall structure includes an air gap and a sealing layer located on top of the air gap, and the air gap can be used to form an "air sidewall". Since the dielectric constant of air is very small, the presence of the "air sidewall" is beneficial to reducing the overall dielectric constant of the dielectric between the gate structure and the first conductive structure. Thus, it is beneficial to reducing the parasitic capacitance generated between the gate structure and the first conductive structure. Furthermore, the delay and switching power consumption are reduced, and the performance of the semiconductor structure is improved.

[0046] Further, the method for forming the air gap and the sealing layer includes: before forming the second sidewall, forming a sacrificial layer on the sidewall of the first conductive opening; after forming the first conductive structure, etching and removing part or all of the sacrificial layer to form an air groove, that is, forming the sacrificial layer after forming the first sidewall and before forming the first conductive structure, and etching the sacrificial layer after forming the second sidewall. Therefore, on the one hand, through the first sidewall, the gate structure can be protected during the process of forming the sacrificial layer and the process of etching the sacrificial layer, reducing the damage to the gate structure caused by the process of forming the air gap, so as to improve the performance of the semiconductor structure. On the other hand, through the second sidewall, the first conductive structure can be protected during the process of etching the sacrificial layer, reducing the damage to the first conductive structure caused by the process of forming the air gap, so as to improve the performance of the semiconductor structure. Moreover, since the sacrificial layer is formed before forming the first conductive structure, the damage to the first conductive structure caused by the process of forming the sacrificial layer is reduced, thereby improving the performance of the semiconductor structure. Brief Description of the Drawings

[0047] Figures 1 to 13 is a cross-sectional structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention. Detailed Description of the Embodiment

[0048] As described in the background art, currently, the materials of the sidewalls used in MOS transistors are usually silicon nitride, silicon oxide, etc. The dielectric constants of materials such as silicon nitride and silicon oxide are relatively large, resulting in relatively large parasitic capacitances of semiconductor devices, thereby affecting the electrical performance of semiconductor devices.

[0049] To solve the above problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same. Since the sidewall structure is located between the sidewalls of the gate structure and the first conductive structure, and the sidewall structure includes an air gap and a sealing layer located on the top of the air gap, the sealing layer is used to seal the air gap. Therefore, the air gap can be used to form an "air sidewall", which is beneficial to reducing the overall dielectric constant of the dielectric between the gate structure and the first conductive structure, thereby reducing the parasitic capacitance, reducing the delay and switching power consumption, and improving the performance of the semiconductor structure.

[0050] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0051] It should be noted that the "surface" in this specification is used to describe the relative positional relationship in space and is not limited to whether there is direct contact.

[0052] Figures 1 to 13It is a schematic cross-sectional structure diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0053] Please refer to Figure 1 , a substrate is provided.

[0054] In this embodiment, the substrate includes a base 100 and a plurality of fin structures 101 that are separately located on the base 100.

[0055] The material of the substrate includes semiconductor materials.

[0056] In this embodiment, the material of the substrate is silicon.

[0057] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon on insulator (SOI), or germanium on insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0058] In other embodiments, the fin structure includes: a plurality of layers of fin sacrificial layers arranged along a direction perpendicular to the surface of the base, and nanosheets located between adjacent fin sacrificial layers.

[0059] Next, a plurality of separately located gate structures, first conductive structures, and sidewall structures are formed on the substrate, and a plurality of source / drain structures are formed in the substrate on both sides of the gate structure. The first conductive structure is located on the surface of the source / drain structure, and the sidewall structure is located between the sidewalls of the gate structure and the first conductive structure. The sidewall structure includes an air gap and a sealing layer located on the top of the air gap, and the sealing layer is used to seal the air gap. For the detailed process of forming the gate structure, the first conductive structure, the sidewall structure, and the source / drain structure, please refer to Figures 2 to 12 .

[0060] Please refer to Figure 2 , a plurality of separately located dummy gate structures 110 are formed on the surface of the substrate; a first sidewall 111 is formed on the sidewalls of the dummy gate structures 110; and a plurality of source / drain structures 102 are formed in the substrate on both sides of the dummy gate structures 110.

[0061] In this embodiment, the method for forming the dummy gate structure 110 includes: forming a dummy gate material film (not shown) covering the surface of the fin structure 101 on the substrate 100; patterning the dummy gate material film until the surface of the substrate 100 is exposed, so as to form a plurality of discrete dummy gate structures 110 on the substrate 100, the dummy gate structures 110 straddling a plurality of the fin structures 101, and the top surface of the dummy gate structures 110 being higher than the top surface of the fin structures 101.

[0062] The formation process of the dummy gate material film includes: an epitaxial growth process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.

[0063] In this embodiment, the material of the dummy gate structure 110 includes polysilicon.

[0064] In this embodiment, the dummy gate structure 110 is also used to define the pattern of the gate structure during the subsequent formation of the gate structure.

[0065] In other embodiments, the dummy gate structure is directly used as the gate structure.

[0066] In this embodiment, the first sidewall 111 forms a part of the sidewall structure formed subsequently.

[0067] In this embodiment, the method for forming the first sidewall 111 on the sidewalls of the dummy gate structure 110 includes: depositing a first sidewall material film (not shown) on the surface of the substrate 100 and the surface of the dummy gate structure 110; using an anisotropic etching process to etch back the first sidewall material film until the first sidewall material film on the surface of the substrate 100 and the top surface of the dummy gate structure 110 is removed, and forming the first sidewall 111 on the sidewalls of the dummy gate structure 110.

[0068] The formation process of the first sidewall material film includes a deposition process. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.

[0069] In this embodiment, the material of the first sidewall 111 includes a low-k dielectric material (k less than 3.9), or a combination of multiple low-k dielectric materials. The low-k dielectric materials include SiOC, SiOCN, and SiBCN, etc.

[0070] In this embodiment, the method for forming a plurality of source / drain structures 102 in the substrate on both sides of the dummy gate structure 110 includes: after forming the first sidewall 111, forming source / drain openings (not shown) in the fin structures 101 on both sides of the dummy gate structure 110; using an epitaxial growth process to form the source / drain structures 102 in the source / drain openings.

[0071] Among them, during the formation of the source / drain structure 202, the first spacer 111 is used to define the formation position of the source / drain structure 102.

[0072] In this embodiment, before forming the dummy gate structure 110, a substrate dielectric layer (not shown) is further formed on the surface of the substrate 100, and the substrate dielectric layer is also located on partial sidewall surfaces of the fin structure 101. The function of the substrate dielectric layer is to electrically insulate adjacent fin structures 101 from each other and the semiconductor device from the substrate 100.

[0073] Please refer to Figure 3 , after forming the source / drain structure 102, a first dielectric layer 113 is formed on the substrate and the surface of the source / drain structure 102, and the first dielectric layer 113 is also located on the sidewall of the first spacer 112.

[0074] In this embodiment, the first dielectric layer 113 provides support for the subsequent formation of the gate structure and the first conductive structure.

[0075] In this embodiment, the material of the first dielectric layer 113 is silicon oxide.

[0076] In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH, and SiCN.

[0077] In this embodiment, the method for forming the first dielectric layer 113 includes: forming a first dielectric material layer (not shown) on the surface of the dummy gate structure 110 and the substrate, with the surface of the first dielectric material layer being higher than the top surface of the dummy gate structure 110; planarizing the first dielectric material layer until the top surface of the dummy gate structure 110 is exposed.

[0078] The formation process of the first dielectric material layer includes: a spin coating process or a deposition process, etc. The deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.

[0079] The process for planarizing the first dielectric material layer includes: a dry etching process, a wet etching process, or a chemical mechanical polishing process, etc.

[0080] In this embodiment, before subsequently etching the first dielectric layer 113 to form a first conductive opening, an initial etch stop layer 114 is formed on the surface of the substrate, the surface of the source / drain structure 102, and the sidewall of the first spacer 111.

[0081] The initial etch stop layer 114 provides materials for the subsequent formation of the etch stop layer.

[0082] In this embodiment, the etch stop layer forms part of the subsequent sidewall structure.

[0083] The material of the initial etch stop layer 114 includes one or a combination of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon boron carbonitride. Correspondingly, the material of the etch stop layer includes one or a combination of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon boron carbonitride.

[0084] In this embodiment, the materials of the initial etch stop layer 114 and the etch stop layer are silicon nitride.

[0085] In other embodiments, the initial etch stop layer and the etch stop layer may not be formed.

[0086] Specifically, in this embodiment, the method of forming the initial etch stop layer 114 includes: before forming the first dielectric layer 113, forming an etch stop material layer (not shown) on the surface of the substrate, the surface of the source / drain structure 102, the top surface of the dummy gate structure 110, and the surface of the first sidewall 111; while planarizing the first dielectric material layer, planarizing the etch stop material layer until the top surface of the dummy gate structure 110 is exposed.

[0087] Since the initial etch stop layer 114 is formed on the surface of the substrate, the surface of the source / drain structure 102, and the sidewalls of the first sidewall 111 before forming the subsequent first conductive opening, the initial etch stop layer 114 reduces the damage to the surface of the source / drain structure 102 and the surface of the first sidewall 111 during the process of etching the first dielectric layer 113 to form the first conductive opening. Thus, the performance of the semiconductor structure is better improved.

[0088] Please refer to Figure 4 , after forming the first dielectric layer 113, removing the dummy gate structure 110, and forming a gate opening 115 in the first dielectric layer 113, the gate opening 115 exposes the sidewall surface of the first sidewall 111.

[0089] The gate opening 115 provides space for forming the gate structure.

[0090] The process of removing the dummy gate structure 110 includes at least one of a dry etching process or a wet etching process.

[0091] Please refer to Figure 5 , forming a gate structure 120 in the gate opening 115, the gate structure 120 straddles several of the fin structures 101, the first sidewall 111 is located on the sidewalls of the gate structure 120, and several of the source / drain structures 102 are located in the substrate on both sides of the gate structure 120.

[0092] Specifically, in this embodiment, the gate structure 120 includes: a gate dielectric layer (not shown) on the inner wall surface of the gate opening 115, a work function layer (not shown) on the surface of the gate dielectric layer, and a gate electrode layer (not shown) on the surface of the work function layer.

[0093] The material of the gate dielectric layer includes a high-k material (dielectric constant greater than 3.9). The high-k materials include: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, etc.

[0094] The material of the gate electrode layer includes a metal material, such as: one or a combination of several of tungsten, copper, aluminum, titanium, and tantalum.

[0095] The material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

[0096] The method for forming the gate structure 120 includes: forming a gate dielectric material layer (not shown) on the surface of the first dielectric layer 113 and the inner wall surface of the gate opening; forming a work function material layer (not shown) on the surface of the gate dielectric material layer; forming a gate electrode material layer (not shown) on the surface of the work function material layer, and the gate electrode material layer fills the gate opening; planarizing the gate electrode material layer, the work function material layer, and the gate dielectric material layer until the surface of the first dielectric layer 113 is exposed to form the gate structure 120.

[0097] Please refer to Figure 6 , etch back the gate structure 120; after etching back the gate structure 120, form a gate protection structure 121 on the top surface of the gate structure 120, and the first sidewall 111 is also located on the sidewall of the gate protection structure 121.

[0098] Since the gate protection structure 121 is formed, therefore, through the gate protection structure 121, the gate structure 120 can be protected in subsequent etching and other processes, reducing the damage caused to the gate structure 120 by the etching and other processes, thereby improving the performance of the semiconductor structure.

[0099] In this embodiment, the material of the gate protection structure 121 includes silicon nitride.

[0100] In other embodiments, the material of the gate protection structure includes a combination of one or more of SiCON, SiCO, or SiBCN.

[0101] In this embodiment, the process of etching back the gate structure 120 includes at least one of a dry etching process or a wet etching process.

[0102] Specifically, the method for forming the gate protection structure 121 includes: performing a re-etch on the gate structure 120 to form a gate protection structure opening (not shown) in the first dielectric layer 113, where the gate protection structure opening exposes the top surface of the gate structure 120; forming a gate protection structure material layer (not shown) within the gate protection structure opening and on the surface of the first dielectric layer 113, where the gate protection structure material layer fills the gate protection structure opening; and planarizing the gate protection structure material layer until the surface of the first dielectric layer 113 is exposed, so as to form the gate protection structure 121 on the top surface of the gate structure 120.

[0103] It should be noted that since the first sidewall 111 is located on the sidewall of the gate protection structure 121, and the first sidewall 111 forms a part of the subsequently formed sidewall structure, the sidewall structure is also located on the sidewall of the gate protection structure 121.

[0104] In other embodiments, no gate protection structure is formed.

[0105] Please refer to Figure 7 , after forming the gate structure 120, etching the first dielectric layer 113 to form a first conductive opening 116 in the first dielectric layer 113, where the first conductive opening 116 exposes the surface of the source / drain structure 102.

[0106] In this embodiment, since the initial etch stop layer 114 is formed, the first conductive opening 116 exposes the etch stop layer 114 on the surface of the source / drain structure 102.

[0107] In this embodiment, the sidewall surface of the initial etch stop layer 114 is also exposed by the first conductive opening 116.

[0108] The first conductive opening 116 provides space for the subsequent formation of the first conductive structure.

[0109] In this embodiment, the process of etching the first dielectric layer 113 includes one of a dry etching process or a wet etching process.

[0110] Please refer to Figure 8 , forming a sacrificial layer 117 on the sidewall of the first conductive opening 116; after forming the sacrificial layer 117, forming a second sidewall 130 on the sidewall of the first conductive opening 116.

[0111] Generally, after forming the gate structure 120, in order to reduce the impact on the material of the gate structure 120, the temperature in subsequent processes is usually lower than the temperature of the process in forming the gate structure 120. In this embodiment, since the sacrificial layer 117 is formed after the gate structure 120 is formed, therefore, the impact of the high temperature in the process of forming the gate structure 120 on the material of the sacrificial layer 117 is avoided, and the risk that the material of the sacrificial layer 117 diffuses and affects the electrical characteristics of semiconductor structures such as the gate structure 120 and the first sidewall 111 after being affected by high temperature is reduced, improving the performance and reliability of the semiconductor structure. Moreover, in this embodiment, since the first sidewall 111 is formed before the sacrificial layer 117 is formed, therefore, through the first sidewall 111, the gate structure 120 can be protected during the process of forming the sacrificial layer 117 and the subsequent process of etching the sacrificial layer, reducing the damage caused to the gate structure 120 by the process of forming the air gap, so as to improve the performance of the semiconductor structure.

[0112] In this embodiment, the material of the sacrificial layer 117 includes silicon.

[0113] In other embodiments, the material of the sacrificial layer includes: silicon oxide, carbon or metal compound.

[0114] In this embodiment, in the direction perpendicular to the sidewall surface of the first conductive opening 116, the thickness range of the sacrificial layer 117 is 10 angstroms to 50 angstroms.

[0115] If the thickness of the sacrificial layer 117 is too small, the aspect ratio of the space occupied by the sacrificial layer 117 is too large, resulting in too great a difficulty in the etching process of removing the sacrificial layer 117, and it is difficult to completely remove or mostly remove the sacrificial layer 117 to form a larger air gap, which is not conducive to further reducing the parasitic capacitance and better improving the performance of the semiconductor structure. If the sacrificial layer 117 is too thick, the sacrificial layer 117 occupies too much space, increasing the aspect ratio of the first conductive opening 116 when filling the material of the first conductive structure subsequently, increasing the difficulty of filling the material of the first conductive structure, and easily resulting in defects such as voids in the formed first conductive structure, causing the performance of the semiconductor structure to deteriorate. Therefore, when selecting an appropriate thickness of the sacrificial layer 117, that is, when the thickness range of the sacrificial layer 117 is 10 angstroms to 50 angstroms, on the one hand, the etching difficulty of removing the sacrificial layer 117 subsequently can be reduced, forming a larger air gap, so as to be conducive to reducing the parasitic capacitance and better improving the performance of the semiconductor structure; on the other hand, the difficulty of filling the material of the first conductive structure is reduced, so as to be conducive to forming a first conductive structure with fewer defects and better quality, thereby improving the performance of the semiconductor structure.

[0116] In this embodiment, the method for forming the sacrificial layer 117 includes: depositing a sacrificial material film (not shown) on the inner wall surface of the first conductive opening 116, the top surface of the gate structure 120, and the top surface of the first sidewall 111; using an anisotropic etching process to etch back the sacrificial material film until the sacrificial material film on the bottom surface of the first conductive opening 116, the top surface of the gate structure 120, and the top surface of the first sidewall 111 is removed, so as to form the sacrificial layer 117 on the sidewall of the first conductive opening 116.

[0117] Specifically, in this embodiment, the second sidewall 130 is located on the sidewall surface of the sacrificial layer 117.

[0118] In this embodiment, the second sidewall 130 forms a part of the sidewall structure formed subsequently.

[0119] In other embodiments, the second sidewall 130 may not be formed, and the buffer layer formed subsequently is used as the second sidewall to form a part of the sidewall structure.

[0120] In this embodiment, the material of the second sidewall 130 includes a low-k dielectric material (k less than 3.9), or a combination of multiple low-k dielectric materials. The low-k dielectric materials include SiOC, SiOCN, SiBCN, etc.

[0121] Thus, by using the material with a low dielectric constant, on the basis of forming the sidewall structure with the air gap, the dielectric constant of the sidewall structure is further reduced to reduce the parasitic capacitance, decrease the delay and switching power consumption of the device, and improve the performance of the semiconductor structure.

[0122] In other embodiments, the buffer layer formed subsequently is used as the second sidewall, and the material of the second sidewall includes titanium nitride, or a combination of tantalum and tantalum nitride, that is, the material of the buffer layer includes titanium nitride, or a combination of tantalum and tantalum nitride.

[0123] The method for forming the second sidewall 130 includes: after forming the sacrificial layer 117, depositing a second sidewall material film (not shown) on the inner wall surface of the first conductive opening 116, the top surface of the gate protection structure 121, the top surface of the first sidewall 111, the top surface of the sacrificial layer 117, and the top surface of the initial etch stop layer 114; using an anisotropic etching process to etch back the second sidewall material film until the second sidewall material film on the bottom surface of the first conductive opening 116, the top surface of the gate protection structure 121, the top surface of the first sidewall 111, the top surface of the sacrificial layer 117, and the top surface of the initial etch stop layer 114 is removed, so as to form the second sidewall 130 on the sidewall surface of the sacrificial layer 117.

[0124] In this embodiment, after forming the second sidewall 130 and before forming the first conductive structure subsequently, the initial etch stop layer 114 on the source / drain structure 102 is etched until the surface of the source / drain structure 102 is exposed, thereby forming an etch stop layer 140.

[0125] On the one hand, since the initial etch stop layer 114 is etched after forming the second sidewall 130 and before forming the first conductive structure subsequently until the surface of the source / drain structure 102 is exposed, the damage to the surface of the source / drain structure 102 and the surface of the first sidewall 111 caused by the etching process during the etching of the sacrificial material film and the etching of the second sidewall material film is reduced through the initial etch stop layer 114. Thus, the performance of the semiconductor structure is better improved. On the other hand, through the etch stop layer 114, the loss of the sidewall surface of the first sidewall 111 during the subsequent etching process of removing the sacrificial layer 117 to form an air trench can also be reduced, thereby improving the performance of the semiconductor structure.

[0126] In this embodiment, in the process of etching the sacrificial material film, the etch selectivity between the sacrificial material film and the initial etch stop layer 114 is above 10:1. Thus, through the relatively large etch selectivity, the damage to the initial etch stop layer 114 during the etching of the sacrificial material film can be reduced, enabling the initial etch stop layer 114 to better protect the first sidewall 111, the gate structure 120, and the source / drain structure 102.

[0127] Please refer to Figure 9 , a first conductive structure 150 is formed on the substrate. The first conductive structure 150 is located on the surface of the source / drain structure 102, and the second sidewall 130 is located on the sidewall of the first conductive structure 150.

[0128] Since the first conductive structure 150 is formed before subsequently etching the sacrificial layer 117, and the second sidewall 130 is located on the sidewall of the first conductive structure 150, the first conductive structure 150 can be protected through the second sidewall 130 during the process of etching the sacrificial layer 117, and the damage to the first conductive structure 150 caused by the process of forming the air gap is reduced to improve the performance of the semiconductor structure. Moreover, since the sacrificial layer 117 is formed before forming the first conductive structure 150, the damage to the first conductive structure 150 caused by the process of forming the sacrificial layer 117 is also reduced, thereby improving the performance of the semiconductor structure.

[0129] Specifically, in this embodiment, the method for forming the first conductive structure 150 includes: after forming the second sidewall 130, forming a first conductive structure material layer (not shown) within the first conductive opening 116, as well as on the top surface of the gate protection structure 121, the top surface of the first sidewall 111, the top surface of the sacrificial layer 117, and the top surface of the second sidewall 130, and the first conductive material layer fills the first conductive opening 116; planarizing the first conductive material layer until the top surfaces of the gate protection structure 121, the first sidewall 111, the sacrificial layer 117, and the second sidewall 130 are exposed, and forming the first conductive structure 150 within the first conductive opening 116.

[0130] In this embodiment, the process for forming the first conductive structure material layer includes a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.

[0131] In other embodiments, the process for forming the material of the first conductive structure includes an electroless selective metal plating process, etc.

[0132] In this embodiment, the process for planarizing the first conductive structure material layer includes one of a dry etching process, a wet etching process, or a chemical mechanical polishing process.

[0133] In this embodiment, before forming the first conductive structure material layer, a contact layer (not shown) is formed on the surface of the exposed source / drain structure 102. Thus, through the contact layer, the contact resistance between the first conductive structure 150 and the source / drain structure 102 can be reduced, improving the performance of the semiconductor structure.

[0134] In other embodiments, the contact layer is not formed.

[0135] In this embodiment, the material of the contact layer includes metal silicide.

[0136] In this embodiment, after forming the contact layer and before forming the first conductive structure 150, a buffer layer 151 is formed on the sidewall of the second sidewall 130.

[0137] Thus, through the buffer layer 151, metal atoms or metal ions in the material of the formed first conductive structure 150 can be blocked from diffusing outwards, reducing the influence of the diffusion on the electrical characteristics of the devices in the semiconductor structure, and thus improving the performance and reliability of the semiconductor structure.

[0138] In this embodiment, the buffer layer 151 forms a part of the subsequent formed sidewall structure.

[0139] In this embodiment, the material of the buffer layer 151 includes titanium nitride, or a combination of tantalum and tantalum nitride.

[0140] In this embodiment, the method of forming the buffer layer 151 includes: forming a buffer material film (not shown) on the surface of the contact layer, the surface of the second sidewall 130, the top surface of the gate protection structure 121, the top surface of the first sidewall 111, and the top surface of the sacrificial layer 117; using an anisotropic etching process to etch the buffer material film until the buffer material film in the horizontal direction is removed, and forming the buffer layer 151 on the sidewall of the second sidewall 130.

[0141] In other embodiments, the buffer layer is not formed.

[0142] Please refer to Figure 10 , before forming the air gap subsequently, etch back the first conductive structure 150; after etching back the first conductive structure 150, form a conductive protection structure 152 on the top surface of the first conductive structure 150, and the second sidewall 130 is also located on the sidewall of the conductive protection structure 152.

[0143] Since the conductive protection structure 152 is formed, therefore, through the conductive protection structure 152, during the subsequent process of etching the sacrificial layer 117, the first conductive structure 150 can be protected, and the damage to the gate structure 120 caused by processes such as etching can be reduced, thereby improving the performance of the semiconductor structure.

[0144] In this embodiment, the process of etching back the first conductive structure 150 includes at least one of a dry etching process or a wet etching process.

[0145] Specifically, the method of forming the conductive protection structure 152 includes: etching back the first conductive structure 150 to form a conductive protection structure opening (not shown) in the first dielectric layer 113, and the conductive protection structure opening exposes the top surface of the first conductive structure 150; forming a conductive protection structure material layer (not shown) in the conductive protection structure opening and on the surface of the first dielectric layer 113, and the conductive protection structure material layer fills the conductive protection structure opening; planarizing the conductive protection structure material layer until the surface of the first dielectric layer 113 is exposed, so as to form the conductive protection structure 152 on the top surface of the first conductive structure 150.

[0146] It should be noted that since the second sidewall 130 is located on the sidewall of the conductive protection structure 152, and the second sidewall 130 forms a part of the sidewall structure formed subsequently, therefore, the sidewall structure is also located on the sidewall of the conductive protection structure 152.

[0147] In other embodiments, the conductive protection structure is not formed.

[0148] Please refer to Figure 11 , after forming the first conductive structure 150, etch and remove part or all of the sacrificial layer 117 to form an air groove 118.

[0149] Specifically, in this embodiment, the sacrificial layer 117 is completely removed.

[0150] In this embodiment, since the sacrificial layer 117 is completely removed, the space of the air groove 118 can be maximally increased. Thus, it is beneficial to form a larger air gap to more effectively reduce the dielectric constant of the sidewall structure and reduce the parasitic capacitance.

[0151] In other embodiments, when the dielectric constant of the part of the sidewall structure other than the air gap is below 4, part of the sacrificial layer is removed. On the one hand, since the dielectric constant of the part of the sidewall structure other than the air gap is below 4, that is, the dielectric constant of the part of the sidewall structure other than the air gap is small. Therefore, based on the small dielectric constant of the part of the sidewall structure other than the air gap, after increasing the air gap, the dielectric constant of the sidewall structure can be reduced and made to be within the preset dielectric constant range, thus meeting the design requirements for the size of the parasitic capacitance of the device.

[0152] In this embodiment, in the process of etching and removing part or all of the sacrificial layer, the etching selectivity between the sacrificial layer and the etch stop layer 140 is 10:1 or more. Thus, through the large etching selectivity, while etching the sacrificial layer, the damage to the etch stop layer 140 can be reduced. On the one hand, the etch stop layer 140 can better protect the gate structure 120 and the first sidewall 111, reducing the damage caused to the gate structure 120 and the first sidewall 111 during the etching process and improving the performance of the semiconductor structure; on the other hand, by reducing the damage to the etch stop layer 140 during the etching process, the influence of the etching process on the electrical characteristics of the semiconductor structure is reduced, improving the performance and reliability of the semiconductor structure.

[0153] In this embodiment, in the process of etching and removing part or all of the sacrificial layer 117, the etching selectivity between the sacrificial layer 117 and the second sidewall 130 is above 10:1. Thus, through the large etching selectivity, while etching the sacrificial layer 117, the damage to the second sidewall 130 can be reduced. Therefore, on the one hand, the second sidewall 130 can better protect the first conductive structure 150, reducing the damage to the first conductive structure 150 caused by the etching process, and improving the performance of the semiconductor structure; on the other hand, by reducing the damage to the second sidewall 130 during the etching process, the influence of the etching process on the electrical characteristics of the semiconductor structure is reduced, improving the performance and reliability of the semiconductor structure.

[0154] Similarly, in other embodiments, when the buffer layer is directly used as the second sidewall, in the process of etching and removing part or all of the sacrificial layer, the etching selectivity between the sacrificial layer and the buffer layer is above 10:1.

[0155] Similarly, in other embodiments, when the etch stop layer is not formed, in the process of etching and removing part or all of the sacrificial layer, the etching selectivity between the sacrificial layer and the first sidewall is above 10:1.

[0156] The process of etching the sacrificial layer 117 includes one of a dry etching process or a wet etching process, such as a reactive ion etching process (RIE), a vapor wet etching process (Vapor Wet), or a remote plasma etching process (Remote Plasma).

[0157] In this embodiment, the process of etching the sacrificial layer 117 includes a vapor wet etching process.

[0158] The parameters of the vapor wet etching process include: the pressure range is from 10 mTorr to 100 mTorr; the gases used include NH3 and HF; the reaction temperature range is from 35°C to 100°C; the post-heating temperature range is from 120°C to 300°C.

[0159] Specifically, in this embodiment, by making the pressure range of the vapor wet etching process from 10 mTorr to 100 mTorr, the accumulation rate of the etching by-products in the vapor wet etching process can be controlled. Therefore, the etching rate and etching uniformity of the sacrificial layer 117 can be better controlled to improve the surface roughness of the inner wall surface of the formed air trench 118 and the consistency between the depths of the air trenches 118 in the direction perpendicular to the substrate surface, thereby improving the performance and reliability of the semiconductor structure.

[0160] In this embodiment, by making the gas used include NH3 and HF and setting the reaction temperature range from 35°C to 100°C, the etching selectivity between the sacrificial layer 117 and the second sidewall 130 and the etching selectivity between the sacrificial layer 117 and the etch stop layer 140 are controlled, that is, the etching selectivity between the sacrificial layer 117 and the second sidewall 130 and the etching selectivity between the sacrificial layer 117 and the etch stop layer 140 are within a preset range.

[0161] In this embodiment, by setting the post-heating temperature range from 120°C to 300°C, the removal of etching by-products in the gas-phase wet etching process is achieved.

[0162] Please refer to Figure 12 , a sealing layer 161 is formed in the air groove 118 at the top, thereby forming the sidewall structure 200.

[0163] Specifically, the sidewall structure 200 is located between the sidewalls of the gate structure 120 and the first conductive structure 150. The sidewall structure 200 includes an air gap 160 and a sealing layer 161 located at the top of the air gap 160. The sealing layer 161 is used to seal the air gap 160.

[0164] Since the sidewall structure 200 is formed between the sidewalls of the gate structure 120 and the first conductive structure 150, and the sidewall structure 200 includes an air gap 160 and a sealing layer 161 located at the top of the air gap 160, the air gap can be used to form an "air sidewall". Since the dielectric constant of air is very small, the presence of the "air sidewall" is beneficial to reducing the overall dielectric constant of the dielectric between the gate structure 120 and the first conductive structure 150. Thus, it is beneficial to reducing the parasitic capacitance generated between the gate structure 120 and the first conductive structure 150. Furthermore, the delay and switching power consumption are reduced, and the performance of the semiconductor structure is improved.

[0165] Specifically, in this embodiment, the sidewall structure 200 further includes: the first sidewall 111, with the air gap 160 located between the first sidewall 111 and the sidewall of the first conductive structure 150; the second sidewall 130 located on the sidewall of the first conductive structure 150, with the air gap 160 located between the sidewalls of the first sidewall 111 and the second sidewall 130; the etch stop layer 140 located between the air gap 160 and the first sidewall 111; and the buffer layer 151 located between the sidewalls of the first conductive structure 150 and the second sidewall 130.

[0166] In this embodiment, the process of forming the sealing layer 161 includes a non-conformal deposition process.

[0167] The material of the sealing layer 161 includes silicon nitride, silicon oxide, or silicon carbide.

[0168] Please refer to Figure 13 , a second dielectric layer 210 is formed on the surface of the first conductive structure 150, the surface of the gate structure 120, and the sealing layer 161; a second conductive opening (not shown) is formed in the second dielectric layer 210, and the second conductive opening exposes the surface of the gate structure 120; a second conductive structure 220 is formed in the second conductive opening; a third conductive opening (not shown) is formed in the second dielectric layer 210, and the third conductive opening exposes the surface of the first conductive structure 150; a third conductive structure 230 is formed in the third conductive opening.

[0169] Specifically, the method of forming the second conductive opening includes: forming a second conductive opening mask layer on the surface of the second dielectric layer 210, and the second conductive opening mask layer exposes the surface of the second dielectric layer 210 on the gate structure 120; using the second conductive opening mask layer and the first sidewall 111 as masks, etching the second dielectric layer 210 and the gate protection structure 121 until the top surface of the gate structure 120 is exposed.

[0170] The method of forming the second conductive structure 220 includes: forming a second conductive structure material layer in the second conductive opening and on the surface of the second dielectric layer 210; planarizing the second conductive structure material layer until the surface of the second dielectric layer 210 is exposed to form the second conductive structure 220.

[0171] The method of forming the third conductive opening includes: forming a third conductive opening mask layer on the surface of the second dielectric layer 210, and the third conductive opening mask layer exposes the surface of the second dielectric layer 210 on the first conductive structure 150; using the third conductive opening mask layer and the second sidewall 130 as masks, etching the second dielectric layer 210 and the conductive protection structure 152 until the top surface of the first conductive structure 150 is exposed.

[0172] The method of forming the third conductive structure 230 includes: while forming the second conductive structure material layer in the second conductive opening, forming a second conductive structure material layer in the third conductive opening; planarizing the second conductive structure material layer until the surface of the second dielectric layer 210 is exposed to form the second conductive structure 220 and form the third conductive structure 230 at the same time.

[0173] Correspondingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method. Please continue to refer to Figure 12 , including: a substrate; a plurality of gate structures 120 that are discrete from each other and located on the substrate; a plurality of source / drain structures 102 located in the substrate on both sides of the gate structures 120; a first conductive structure 150 located on the surface of the source / drain structures 102; and a sidewall structure 200 located between the sidewalls of the gate structures 120 and the first conductive structure 150. The sidewall structure 200 includes an air gap 160 and a sealing layer 161 located on top of the air gap 160, and the sealing layer 161 is used to seal the air gap 160.

[0174] Since the sidewall structure 200 is located between the sidewalls of the gate structures 120 and the first conductive structure 150, and the sidewall structure 200 includes an air gap 160 and a sealing layer 161 located on top of the air gap 160, the air gap 160 can be used to form an "air sidewall". Since the dielectric constant of air is very small, the presence of the "air sidewall" is beneficial to reducing the overall dielectric constant of the dielectric between the gate structures 120 and the first conductive structure 150. Thus, it is beneficial to reducing the parasitic capacitance generated between the gate structures 120 and the first conductive structure 150, and further reducing the delay and switching power consumption, thereby improving the performance of the semiconductor structure.

[0175] In this embodiment, the substrate includes a base 100 and a plurality of fin structures 101 that are discrete from each other and located on the base 100.

[0176] The material of the substrate includes a semiconductor material.

[0177] In this embodiment, the material of the substrate is silicon.

[0178] In other embodiments, the material of the substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0179] In other embodiments, the fin structure includes: a plurality of fin sacrificial layers arranged in a direction perpendicular to the surface of the base, and nanosheets located between adjacent fin sacrificial layers.

[0180] In this embodiment, the gate structure 120 includes: located in the gate opening 115 (such as Figure 4The gate dielectric layer (not shown) on the inner wall surface as shown, the work function layer (not shown) on the surface of the gate dielectric layer, and the gate electrode layer (not shown) on the surface of the work function layer.

[0181] The material of the gate dielectric layer includes a high-k material (dielectric constant greater than 3.9). The high-k materials include: hafnium dioxide, hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, or aluminum oxide, etc.

[0182] The material of the gate electrode layer includes a metal material, such as: one or a combination of several of tungsten, copper, aluminum, titanium, and tantalum.

[0183] The material of the work function layer includes titanium nitride, tantalum nitride, or titanium aluminum.

[0184] In this embodiment, in the direction perpendicular to the extending direction of the gate structure 120, the width of the air gap 160 is below 50 angstroms.

[0185] In this embodiment, the material of the sealing layer 161 includes silicon nitride, silicon oxide, or silicon carbide.

[0186] In this embodiment, the sidewall structure 200 further includes: a first sidewall 111 on the sidewall of the gate structure 120, and the air gap 160 is located between the first sidewall 111 and the sidewall of the first conductive structure 150.

[0187] In this embodiment, the material of the first sidewall 111 includes a low-k material (k less than 3.9), or a combination of multiple low-k materials. The low-k materials include SiOC, SiOCN, and SiBCN, etc.

[0188] In this embodiment, the sidewall structure 200 further includes: an etch stop layer 140 located between the air gap 160 and the first sidewall 111.

[0189] The material of the etch stop layer 140 includes one or a combination of multiple of silicon nitride, silicon carbonitride, silicon oxycarbide, and silicon boron carbonitride.

[0190] In this embodiment, the material of the etch stop layer 140 is silicon nitride.

[0191] In other embodiments, the sidewall structure does not include the etch stop layer.

[0192] In this embodiment, the sidewall structure 200 further includes: a second sidewall 130 on the sidewall of the first conductive structure 150, and the air gap 160 is located between the sidewalls of the first sidewall 111 and the second sidewall 130.

[0193] In this embodiment, the material of the second sidewall 130 includes a low-k dielectric material (k less than 3.9), or a combination of multiple low-k dielectric materials. The low-k dielectric materials include SiOC, SiOCN, SiBCN, etc.

[0194] In other embodiments, the second sidewall 130 is not provided, and the buffer layer is used as the second sidewall to form a part of the sidewall structure 200. The material of the second sidewall includes titanium nitride, or a combination of tantalum and tantalum nitride, that is, the material of the buffer layer includes titanium nitride, or a combination of tantalum and tantalum nitride.

[0195] In this embodiment, the sidewall structure 200 further includes: a buffer layer 151 located between the sidewalls of the first conductive structure 150 and the second sidewall 130.

[0196] In this embodiment, the material of the buffer layer 151 includes titanium nitride, or a combination of tantalum and tantalum nitride. In other embodiments, the buffer layer is not provided.

[0197] In this embodiment, the top surface of the gate structure 120 is lower than the top surface of the sidewall structure 200; the semiconductor structure further includes: a gate protection structure 121 located on the top surface of the gate structure 120, and the sidewall structure 200 is also located on the sidewalls of the gate protection structure 121.

[0198] In this embodiment, the material of the gate protection structure 121 includes silicon nitride.

[0199] In other embodiments, the material of the gate protection structure includes one or a combination of SiCON, SiCO, or SiBCN.

[0200] In other embodiments, the gate protection structure is not provided.

[0201] In this embodiment, the top surface of the first conductive structure 150 is lower than the top surface of the sidewall structure 200; the semiconductor structure further includes: a conductive protection structure 152 located on the top surface of the first conductive structure 150, and the sidewall structure 200 is also located on the sidewalls of the conductive protection structure 152.

[0202] In other embodiments, the conductive protection structure is not provided.

[0203] In this embodiment, the semiconductor structure further includes: a contact layer (not shown) located between the source-drain structure 102 and the first conductive structure 150. Thus, through the contact layer, the contact resistance between the first conductive structure 150 and the source-drain structure 102 can be reduced, improving the performance of the semiconductor structure.

[0204] In other embodiments, the contact layer is not provided.

[0205] In this embodiment, the material of the contact layer includes metal silicide.

[0206] In this embodiment, the semiconductor structure further includes: a substrate dielectric layer (not shown) on the surface of the substrate 100, and the substrate dielectric layer also covers part of the sidewall surfaces of the fin structures 101.

[0207] In another embodiment, as Figure 13 shown, the semiconductor structure further includes: a second dielectric layer 200 on the surfaces of the first conductive structure 150, the gate structure 120, and the air gap 160. The second dielectric layer 200 has a second conductive opening (not shown) and a third conductive opening (not shown). The second conductive opening exposes the surface of the gate structure 120, and the third conductive opening exposes the surface of the first conductive structure 150; a second conductive structure 220 in the second conductive opening; and a third conductive structure 230 in the third conductive opening.

[0208] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A plurality of gate structures located on the substrate and separated from each other; A plurality of source / drain structures in the substrate on both sides of the gate structures; A first conductive structure on the surface of the source / drain structures; A sidewall structure located between the sidewalls of the gate structure and the first conductive structure, the sidewall structure comprising: a first sidewall on the sidewall of the gate structure, an air gap, a sealing layer on top of the air gap, an etch stop layer between the first sidewall and the air gap, and a second sidewall on the sidewall of the first conductive structure; the air gap is between the etch stop layer and the second sidewall, and the sealing layer is used to seal the air gap; Wherein, the surface of the source / drain structure is exposed through a first conductive opening; the etch stop layer exposes a part of the top surface of the source / drain structure and covers the sidewall of the first conductive opening, and the second sidewall exposes the etch stop layer on the bottom surface of the first conductive opening.

2. The semiconductor structure according to claim 1, wherein The sidewall structure further comprises: a buffer layer between the first conductive structure and the second sidewall.

3. The semiconductor structure according to claim 1, wherein In a direction perpendicular to the extending direction of the gate structure, the width of the air gap is below 50 angstroms.

4. The semiconductor structure according to claim 1, wherein The top surface of the gate structure is lower than the top surface of the sidewall structure; The semiconductor structure further comprises: a gate protection structure on the top surface of the gate structure, and the sidewall structure is also located on the sidewall of the gate protection structure.

5. The semiconductor structure according to claim 1, wherein, The top surface of the first conductive structure is lower than the top surface of the sidewall structure; the semiconductor structure further comprises: a conductive protection structure on the top surface of the first conductive structure, and the sidewall structure is also located on the sidewall of the conductive protection structure.

6. The semiconductor structure according to claim 1, wherein, Further comprising: A second dielectric layer on the surface of the first conductive structure, the surface of the gate structure and the air gap, the second dielectric layer having a second conductive opening and a third conductive opening, the second conductive opening exposing the surface of the gate structure, and the third conductive opening exposing the surface of the first conductive structure; A second conductive structure in the second conductive opening; A third conductive structure in the third conductive opening.

7. The semiconductor structure according to claim 1, characterized in that, The substrate comprises a substrate body, and a plurality of fin structures located on the substrate body and separated from each other, and the gate structure straddles a plurality of the fin structures.

8. The semiconductor structure according to claim 7, wherein The fin structure comprises: a plurality of fin sacrificial layers arranged in a direction perpendicular to the surface of the substrate, and nanosheets between adjacent fin sacrificial layers.

9. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate; Form a plurality of mutually discrete gate structures, first conductive structures, and sidewall structures on the substrate. Moreover, form a plurality of source / drain structures in the substrate on both sides of the gate structure. The first conductive structure is located on the surface of the source / drain structure. The sidewall structure is located between the sidewalls of the gate structure and the first conductive structure. The sidewall structure includes: a first sidewall on the sidewall of the gate structure, an air gap, a sealing layer on top of the air gap, an etch stop layer between the first sidewall and the air gap, and a second sidewall on the sidewall of the first conductive structure. The air gap is located between the etch stop layer and the second sidewall. The sealing layer is used to seal the air gap. The method for forming the air gap and the sealing layer includes: exposing the surface of the source / drain structure through a first conductive opening; depositing a sacrificial material film on the inner wall surface of the first conductive opening, the top surface of the gate structure, and the top surface of the first sidewall. The sacrificial material film covers the initial etch stop layer; back-etch the sacrificial material film to remove the sacrificial material film on the bottom surface of the first conductive opening, the top surface of the gate structure, and the top surface of the first sidewall to form a sacrificial layer; after forming the first conductive structure, etch and remove part or all of the sacrificial layer to form an air groove; form the sealing layer in the air groove at the top. After forming the sacrificial layer, form a second sidewall on the sidewall of the first conductive opening. The sacrificial layer and the second sidewall expose the initial etch stop layer on the top of the source / drain structure. The method for forming the etch stop layer includes: forming an initial etch stop layer on the surface of the substrate, the surface of the source / drain structure, and the sidewall of the first sidewall before the first conductive opening; after forming the second sidewall and before forming the first conductive structure, etch the initial etch stop layer on the source / drain structure until the surface of the source / drain structure is exposed.

10. The method for forming a semiconductor structure according to claim 9, wherein, The material of the first sidewall includes a low-k dielectric material.

11. The method for forming a semiconductor structure according to claim 9, wherein, The material of the second sidewall includes a low-k dielectric material, or the material of the second sidewall includes titanium nitride, or the material of the second sidewall includes a combination of tantalum and tantalum nitride.

12. The method for forming a semiconductor structure according to claim 9, wherein It further includes: After forming the source / drain structure and before forming the gate structure, form a first dielectric layer on the substrate and the surface of the source / drain structure. The first dielectric layer is also located on the sidewall of the first sidewall.

13. The method for forming a semiconductor structure according to claim 12, wherein, The method for forming the first sidewall includes: forming a plurality of mutually discrete dummy gate structures on the surface of the substrate before forming the source / drain structure; forming the first sidewall on the sidewall of the dummy gate structure; the method for forming the gate structure includes: after forming the first dielectric layer, removing the dummy gate structure, forming a gate opening in the first dielectric layer. The gate opening exposes the sidewall surface of the first sidewall; forming the gate structure in the gate opening.

14. The method for forming a semiconductor structure according to claim 12, wherein The method for forming the second sidewall includes: after forming the gate structure, etch the first dielectric layer to form a first conductive opening in the first dielectric layer; before forming the first conductive structure, form a second sidewall on the sidewall of the first conductive opening.

15. The method for forming a semiconductor structure according to claim 14, wherein, In the process of etching and removing part or all of the sacrificial layer, the etching selectivity of the sacrificial layer to the first sidewall is above 10:

1.

16. The method for forming a semiconductor structure according to claim 14, wherein, In the process of etching and removing part or all of the sacrificial layer, the etching selectivity of the sacrificial layer to the second sidewall is above 10:

1.

17. The method for forming a semiconductor structure as described in claim 14, characterized in that, The thickness range of the sacrificial layer is from 10 angstroms to 50 angstroms.

18. The method for forming a semiconductor structure according to claim 14, wherein, The material of the sacrificial layer includes silicon, or the material of the sacrificial layer includes silicon oxide, or the material of the sacrificial layer includes carbon, or the material of the sacrificial layer includes metal compounds.

19. The method for forming a semiconductor structure according to claim 14, wherein, In the process of etching and removing part or all of the sacrificial layer, the etching selectivity of the sacrificial layer to the etch stop layer is above 10:

1.

20. The method for forming a semiconductor structure according to claim 14, wherein The material of the etch stop layer includes one or a combination of more of silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride boron.

21. The method for forming a semiconductor structure according to claim 12, wherein, The sidewall structure further includes: a buffer layer located between the sidewalls of the first conductive structure and the second sidewall.

22. The method for forming a semiconductor structure according to claim 21, wherein, The material of the buffer layer includes titanium nitride, or a combination of tantalum and tantalum nitride.

23. The method for forming a semiconductor structure as claimed in claim 9, wherein, Further included: Before forming the air gap, re-etch the gate structure; after re-etching the gate structure, form a gate protection structure on the top surface of the gate structure, and the sidewall structure is also located on the sidewalls of the gate protection structure.

24. The method for forming a semiconductor structure according to claim 9, wherein, Further included: Before forming the air gap, re-etch the first conductive structure; After re-etching the first conductive structure, form a conductive protection structure on the top surface of the first conductive structure, and the sidewall structure is also located on the sidewalls of the conductive protection structure.

25. The method for forming a semiconductor structure as claimed in claim 9, wherein, Further included: Form a second dielectric layer on the surface of the first conductive structure, the surface of the gate structure, and the sealing layer; Form a second conductive opening in the second dielectric layer, and the second conductive opening exposes the surface of the gate structure; Form a second conductive structure in the second conductive opening; Form a third conductive opening in the second dielectric layer, and the third conductive opening exposes the surface of the first conductive structure; Form a third conductive structure in the third conductive opening.

26. The method for forming a semiconductor structure according to claim 9, wherein, The substrate includes a substrate and a plurality of fin structures located on the substrate and separated from each other, and the gate structure straddles a plurality of the fin structures.

27. The method for forming a semiconductor structure according to claim 9, wherein, The process of forming the sealing layer includes an uneven chemical vapor deposition process.

28. The method for forming a semiconductor structure as claimed in claim 9, wherein The material of the sealing layer includes silicon nitride, silicon oxide, or silicon carbide.

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