A novel anti-single event upset flip-flop circuit

Abstract

The application discloses a novel anti-single event upset flip-flop circuit, which comprises a logic input circuit, a first primary stage gate circuit, a second primary stage gate circuit, a third primary stage gate circuit, a fourth primary stage gate circuit, a first secondary stage gate circuit, a second secondary stage gate circuit, a third secondary stage gate circuit, a fourth secondary stage gate circuit, a primary stage latch, a secondary stage latch and at least one inverter in an existing circuit connection relationship. The application can solve the technical problem that the level of the prior art cannot be recovered when a particle is incident on the circuit in a radiation environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit, and particularly relates to a novel anti-single particle flip-flop circuit. BACKGROUND

[0002] In a radiation environment, the charged particles incident from outside of a digital circuit chip can cause ionizing radiation. A certain number of electron-hole pairs are generated around the trajectory of the particles. When the electron-hole pairs deposited along the incident direction of the particles are enough, the current caused by the electron-hole pairs collected by the depletion layer can cause the flip of the drain level, forming a single event upset.

[0003] The level occurring in the combinational logic unit is restored after the single event upset ends. When the particle upset occurs in the sequential logic unit (such as a flip-flop) or a memory array, the upset is locked due to the existence of the internal feedback structure, the level cannot be restored, and the level of the circuit changes. SUMMARY

[0004] The embodiment of the present application provides a novel anti-single particle flip-flop circuit, and solves the technical problem that the level is flipped and cannot be restored when the particle is incident on the circuit in the radiation environment in the prior art.

[0005] In one aspect, the embodiment of the present application provides a flip-flop circuit, which comprises a logic input circuit, a first main stage gate circuit, a second main stage gate circuit, a third main stage gate circuit, a fourth main stage gate circuit, a first slave stage gate circuit, a second slave stage gate circuit, a third slave stage gate circuit, a fourth slave stage gate circuit, a main stage latch, a slave stage latch and at least one inverter, wherein:

[0006] The logic input circuit, the first main stage gate circuit and the first slave stage gate circuit are connected in sequence, the logic input circuit, the third main stage gate circuit and the third slave stage gate circuit are connected in sequence, the logic input circuit, a first inverter in the at least one inverter, the second main stage gate circuit and the second slave stage gate circuit are connected in sequence, the logic input circuit, a first inverter in the at least one inverter, the fourth main stage gate circuit and the fourth slave stage gate circuit are connected in sequence, the output terminals of the first main stage gate circuit, the second main stage gate circuit, the third main stage gate circuit and the fourth main stage gate circuit are connected with the main stage latch, and the output terminals of the first slave stage gate circuit, the second slave stage gate circuit, the third slave stage gate circuit and the fourth slave stage gate circuit are connected with the slave stage latch.

[0007] Optionally, the logic input circuit, the first master stage gate circuit, the master stage latch, the first slave stage gate circuit and the slave stage latch form a first transmission channel, the logic input circuit, the third master stage gate circuit, the master stage latch, the third slave stage gate circuit and the slave stage latch form a third transmission channel, and the first transmission channel and the third transmission channel each correspond to the same signal transmission.

[0008] The logic input circuit, the first inverter, the second master stage gate circuit, the master stage latch, the second slave stage gate circuit and the slave stage latch form a second transmission channel, and the logic input circuit, the first inverter, the fourth master stage gate circuit, the master stage latch, the fourth slave stage gate circuit and the slave stage latch form a fourth transmission channel, and the second transmission channel and the fourth transmission channel each correspond to the same signal transmission.

[0009] The logic input circuit is configured to provide an input signal.

[0010] The first transmission channel, the second transmission channel, the third transmission channel and the fourth transmission channel are each configured to perform signal transmission on the input signal according to an input clock signal.

[0011] Optionally,

[0012] When the clock signal is a low-level signal, the first master stage gate circuit, the second master stage gate circuit, the third master stage gate circuit and the fourth master stage gate circuit are opened respectively, and the first slave stage gate circuit, the second slave stage gate circuit, the third slave stage gate circuit and the fourth slave stage gate circuit are closed respectively, and the first transmission channel, the second transmission channel, the third transmission channel and the fourth transmission channel are each configured to perform signal transmission on the input signal and output a result signal transmitted at a previous transmission time.

[0013] Optionally,

[0014] When the clock signal is a low-level signal converted into a high-level signal, i.e., a clock rising edge, the first slave stage gate circuit, the second slave stage gate circuit, the third slave stage gate circuit and the fourth slave stage gate circuit are opened respectively, and the first master stage gate circuit, the second master stage gate circuit, the third master stage gate circuit and the fourth master stage gate circuit are closed respectively, and the first transmission channel, the second transmission channel, the third transmission channel and the fourth transmission channel are each configured to perform signal transmission on the input signal and output a result signal after the signal transmission.

[0015] Optionally, the first transmission channel and the third transmission channel each correspond to the same resultant signal, the second transmission channel and the fourth transmission channel each correspond to the same resultant signal, and the first transmission channel and the second transmission channel each correspond to opposite resultant signal levels.

[0016] Optionally, the at least one inverter further comprises a second inverter and a third inverter, the second inverter being connected to an output terminal of the first slave stage gate circuit, and the third inverter being connected to an output terminal of the second slave stage gate circuit.

[0017] Optionally, the master stage latch or the slave stage latch is a latch with a hardened structure, which is used to prevent the flip-flop circuit from being locked (unable to recover) due to level inversion of a feedback structure when particles are incident in a radiation environment, thereby causing the output level of the flip-flop circuit to change.

[0018] Optionally, the hardened structure comprises four interlocking circuits, each of which comprises two series-connected transistors.

[0019] Optionally, the gate circuit comprises four series-connected transistors.

[0020] Optionally, the gate circuit comprises a first transistor, a second transistor, a third transistor, and a fourth transistor, the first transistor and the second transistor being connected in series, the third transistor and the fourth transistor being connected in parallel, and an interconnection terminal after the series connection being connected to a connection terminal after the parallel connection.

[0021] In another aspect, an embodiment of the present application provides a flip-flop, which comprises the flip-flop circuit as described above.

[0022] The one or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: the present application provides a flip-flop circuit, which comprises a logic input circuit, a first master stage gate circuit, a second master stage gate circuit, a third master stage gate circuit, a fourth master stage gate circuit, a first slave stage gate circuit, a second slave stage gate circuit, a third slave stage gate circuit, a fourth slave stage gate circuit, a master stage latch, a slave stage latch, and at least one inverter, which are connected in a circuit connection relationship. The master stage latch and the slave stage latch are used to harden the circuit against single event upset, thereby preventing single event effects from causing the output level of the circuit to change, i.e., resisting single event upset. Thus, the technical problem of level inversion and inability to recover when particles are incident in a radiation environment in the prior art is effectively solved. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0024] Figure 1 is a structural schematic diagram of a DICE hardened flip-flop circuit provided by the prior art.

[0025] Figure 2 is a structural schematic diagram of a latch in a DICE hardened flip-flop circuit provided by the prior art.

[0026] Figure 3 is a structural schematic diagram of a flip-flop circuit provided by the embodiments of the present application.

[0027] Figure 4 is a working principle diagram of a flip-flop circuit provided by the embodiments of the present application.

[0028] Figure 5 (a)- Figure 5 (c) is a structural schematic diagram of several gate circuits provided by the embodiments of the present application.

[0029] Figure 6 is a structural schematic diagram of a latch hardened structure provided by the embodiments of the present application.

[0030] Figure 7 (a)- Figure 7 (d) is a structural schematic diagram of the logic input of several flip-flops provided by the embodiments of the present application.

[0031] Reference signs:

[0032] 11 - logic input circuit; 131 - first main stage gate circuit; 132 - second main stage gate circuit; 133 - third main stage gate circuit; 134 - fourth main stage gate circuit; 141 - first slave stage gate circuit; 142 - second slave stage gate circuit; 143 - third slave stage gate circuit; 144 - fourth slave stage gate circuit; 151 - main stage latch; 152 - slave stage latch; 12 - inverter; 15 - latch structure; 13 - gate circuit; 1 - first transistor; 2 - second transistor; 3 - third transistor; 4 - fourth transistor. DETAILED DESCRIPTION

[0033] The applicant has also found in the process of filing the present application that, since a flip-flop is the most frequently used timing device in a digital circuit, the present application mainly performs a single event upset effect hardening design on the flip-flop.

[0034] Currently, a traditional trigger hardening scheme is the Dual Inter-locked Storage Cell (DICE), which is implemented by adding a transmission channel and storage nodes to the circuit and using an interlocking structure. A DICE is equivalent to a four-node storage cell; the input signal (also called data) is written to two of the nodes, and the level of the other two nodes is formed by feedback, ultimately forming a four-point interlocking structure. When the two inputs are different, the output has high impedance; therefore, if one of the two adjacent nodes of a node flips, its output remains unchanged.

[0035] Please see Figure 1 This is a schematic diagram of a DICE-hardened trigger circuit provided by existing technology. For example... Figure 1 The flip-flop circuit 100 shown includes a master-slave two-stage latch structure 15. Both latch structures are identical. Figure 2 The DICE latch shown uses time-division control of the gating circuit to latch the clock signal during its high and low phases. In the diagram, c and cn are connected to the non-inverting (c) and inverting (cn) terminals of the clock signal CK circuit, respectively. As a structure with storage and memory functions in the flip-flop circuit, the latch is the core of the single-event hardening design for flip-flops.

[0036] Please see also Figure 2 This is a schematic diagram of the latch structure in a DICE-hardened trigger circuit provided by existing technology. For example... Figure 2 The latch shown includes eight interlocked transistors and two clock switches, as indicated by the circuit switches marked cn and c in the figure.

[0037] The working principle of the traditional DICE hardened trigger circuit is as follows: First, the data is copied into two paths, which are controlled by the clock signal to be transmitted to the two input nodes of the latch, and then transmitted to the two output nodes of the master stage hardened latch via the master stage hardened latch feedback loop. Then, the data is controlled by the clock signal to be transmitted to the slave stage latch, and then transmitted to the output via the slave stage hardened latch feedback loop.

[0038] This shows that the traditional reinforcement method slows down data transmission speed due to the addition of interlocking structures.

[0039] To address the aforementioned problems, this application provides a flip-flop circuit with the following general concept: The flip-flop circuit includes: a logic input circuit, a first master-level gate circuit, a second master-level gate circuit, a third master-level gate circuit, a fourth master-level gate circuit, a first slave-level gate circuit, a second slave-level gate circuit, a third slave-level gate circuit, a fourth slave-level gate circuit, a master-level latch, a slave-level latch, and at least one inverter, wherein:

[0040] The logic input circuit, the first master-level gate circuit, and the first slave-level gate circuit are connected in sequence. The logic input circuit, the third master-level gate circuit, and the third slave-level gate circuit are connected in sequence. The logic input circuit, the first inverter in the at least one inverter, the second master-level gate circuit, and the second slave-level gate circuit are connected in sequence. The logic input circuit, the first inverter in the at least one inverter, the fourth master-level gate circuit, and the fourth slave-level gate circuit are connected in sequence. The output terminals of each of the first master-level gate circuit, the second master-level gate circuit, the third master-level gate circuit, and the fourth master-level gate circuit are connected to the master-level latch. The output terminals of each of the first slave-level gate circuit, the second slave-level gate circuit, the third slave-level gate circuit, and the fourth slave-level gate circuit are connected to the slave-level latch.

[0041] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0042] First, it should be clarified that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0043] Please see Figure 3 This is a schematic diagram of a trigger circuit provided in an embodiment of this application. Figure 3 The flip-flop circuit 300 shown includes: a logic input circuit 11, a first master-level gate circuit 131, a second master-level gate circuit 132, a third master-level gate circuit 133, a fourth master-level gate circuit 134, a first slave-level gate circuit 141, a second slave-level gate circuit 142, a third slave-level gate circuit 143, a fourth slave-level gate circuit 144, a master-level latch 151, a slave-level latch 152, and at least one inverter 12, wherein:

[0044] The logic input circuit 11, the first master stage gate circuit 131 and the first slave stage gate circuit 141 are connected in sequence, the logic input circuit 11, the third master stage gate circuit 133 and the third slave stage gate circuit 143 are connected in sequence, the logic input circuit 11, the first inverter 121 in the at least one inverter, the second master stage gate circuit 132 and the second slave stage gate circuit 142 are connected in sequence, the logic input circuit 11, the first inverter 121 in the at least one inverter, the fourth master stage gate circuit 134 and the fourth slave stage gate circuit 144 are connected in sequence, the output terminals of the first master stage gate circuit 131, the second master stage gate circuit 132, the third master stage gate circuit 134 and the fourth master stage gate circuit 134 are connected with the master stage latch 151 respectively, and the output terminals of the first slave stage gate circuit 141, the second slave stage gate circuit 142, the third slave stage gate circuit 143 and the fourth slave stage gate circuit 144 are connected with the slave stage latch 152 respectively.

[0045] As shown in the figure, the logic input circuit 11, the first master stage gate circuit 131, the master stage latch 151, the first slave stage gate circuit 141 and the slave stage latch 152 form a first transmission channel, also called a first transmission path, which is shown as transmission channel a1. The logic input circuit 11, the third master stage gate circuit 133, the master stage latch 151, the third slave stage gate circuit 143 and the slave stage latch 152 form a third transmission channel, also called a third transmission path, which is shown as transmission channel a2. Among them, the first transmission channel and the third transmission channel each correspond to the same signal transmission, in other words, the signals transmitted by the two transmission channels are exactly the same.

[0046] The logic input circuit 11, the first inverter 121, the second master stage gate circuit 132, the master stage latch 151, the second slave stage gate circuit 142 and the slave stage latch 152 form a second transmission channel, also called a second transmission path, which is shown as transmission channel b1. The logic input circuit 11, the first inverter 121, the fourth master stage gate circuit 134, the master stage latch 151, the fourth slave stage gate circuit 144 and the slave stage latch 152 form a fourth transmission channel, also called a fourth transmission path, which is shown as transmission channel b2. Among them, the second transmission channel and the fourth transmission channel each correspond to the same signal transmission, that is, the signals transmitted by the two transmission channels are exactly the same.

[0047] Among them, the c and cn terminals in the figure are respectively connected with clock signals, and cn represents the reverse signal corresponding to the input clock signal, which can be specifically referred to Figure 1The clock signal circuit CK is shown here and will not be described again. The logic input circuit is used to provide an input signal; the first transmission channel, the second transmission channel, the third transmission channel and the fourth transmission channel are all used to transmit the input signal according to the input clock signal.

[0048] The present application Figure 3 The reinforcement flip-flop circuit shown is an improved circuit of the conventional DICE reinforcement flip-flop circuit, which still consists of two levels of master and slave latches. Taking the master level latch as an example, first, the input signal (also called data) is processed into two-way inverted data "1" and "0", and then four-way data "1010" is obtained by copying. The four-way data is transmitted to the four nodes INOUT1, INOUT2, INOUT3 and INOUT4 (i.e. the input / output terminals of 151 in the figure) of the latch by the clock signal controlled gate inverter, and is controlled to be transmitted to the slave level latch in time. The transmission mode of the slave level latch is the same as that of the master level, which will not be described again here.

[0049] In actual application, taking the edge type (rising edge) D flip-flop reinforced by DICE as an example, please refer to Figure 4 A working principle diagram of a new type of DICE flip-flop circuit is shown. The diagram is divided into the following two working stages:

[0050] Stage one: when the input clock signal is a low level signal (the dotted line is the starting point and the solid line is the ending point in the figure), the first master level gate circuit 131, the second master level gate circuit 132, the third master level gate circuit 133 and the fourth master level gate circuit 134 are opened, at this time the master level latch 151 is in a data signal transmission state, the input signal (also called data) is transmitted into the master level output terminals INOUT31 and INOUT33 through the first transmission channel and the third transmission channel (the transmission channels a1 and a2 in the figure), and the input signal (also called data) is transmitted into the master level output terminals INOUT32 and INOUT34 through the second transmission channel and the fourth transmission channel (the transmission channels b1 and b2 in the figure). At the same time, the input signal is transmitted into the master level latch 151 (i.e. the master level DICE). At the same time, the first slave level gate circuit 141, the second slave level gate circuit 142, the third slave level gate circuit 143 and the fourth slave level gate circuit 144 are closed, and the slave level latch 152 (i.e. the slave level DICE) is in a data signal latching state (four-way interlocking), and the slave level output terminals INOUT41, INOUT42, INOUT43 and INOUT44 maintain the result signal output at the last stage / previous time.

[0051] Phase two: when the input clock signal is converted from low to high level signal, i.e. the clock rising edge (solid line in the figure), the first slave stage gate circuit 141, the second slave stage gate circuit 142, the third slave stage gate circuit 143 and the fourth slave stage gate circuit 144 are opened, the slave stage latch 152 is in the data signal transmission state, the result signals output from the master stage output terminals INOUT31 and INOUT33 are transmitted from the first transmission channel and the third transmission channel (transmission channels a1 and a2 in the figure) to the slave stage output terminals INOUT41 and INOUT43 respectively, and then transmitted into the slave stage latch 152 (i.e. the slave stage DICE). The result signals output from the master stage output terminals INOUT32 and INOUT34 are transmitted from the second transmission channel and the fourth transmission channel (transmission channels b1 and b2 in the figure) to the slave stage output terminals INOUT42 and INOUT44 respectively, and then transmitted into the slave stage latch 152 (i.e. the slave stage DICE). At this time, the first master stage gate circuit 131, the second master stage gate circuit 132, the third master stage gate circuit 133 and the fourth master stage gate circuit 134 are closed, the master stage latch 151 (i.e. the master stage DICE) is in the data signal latching state (four-way interlocking), and the master stage output terminals INOUT31, INOUT32, INOUT33 and INOUT34 maintain the result signals output at the previous stage / previous time.

[0052] It should be noted that the above two phases complete the data signal transmission process from the input end to the output end of the circuit. Among them, the data signals transmitted by the first transmission channel and the third transmission channel (i.e. transmission channels a1 and a2) are completely consistent. The data signals transmitted by the second transmission channel and the fourth transmission channel (i.e. transmission channels b1 and b2) are completely consistent. The working principles of the two groups of transmission channels are consistent, and only the levels of the output result signals are opposite. Among them, the "reverse" in the figure means that the levels are opposite.

[0053] In optional embodiments, the control ends of the master stage gate circuit and the slave stage gate circuit are reversed (c and cn are exchanged), i.e. can be transformed into falling edge D flip-flop.

[0054] In optional embodiments, the at least one inverter 12 further includes a second inverter 122 and a third inverter 123. One end of the second inverter 122 is connected with the output end of the first slave stage gate circuit 141, and the other end of the second inverter 122 is an output end Qn of the entire flip-flop circuit. One end of the third inverter 123 is connected with the output end of the second slave stage gate circuit 142, and the other end of the third inverter 123 is another output end Q of the entire flip-flop circuit.

[0055] In optional embodiments, please refer to Figure 5(a)- Figure 5 (c) shows the structure of several possible gating circuits. See Figure 5 (a) is a symbolic diagram of a gating circuit. In a specific embodiment, the gating circuit referred to in embodiments of the present application comprises four transistors, such as MOS transistors, in series, as shown in Figure 5 (b). Where IN represents the input of the gating circuit, OUT represents the output of the gating circuit. OEN and OE are connected to a pair of phase-opposed clock signals, OEN is connected to the inverted signal of the clock signal (also denoted as cn), and OE is connected to the non-inverted signal of the clock signal (also denoted as c); or OEN is connected to the non-inverted signal of the clock signal (c), and OE is connected to the inverted signal of the clock signal (cn).

[0056] In another specific embodiment, the gating circuit referred to in the present application comprises four transistors, namely a first transistor 1, a second transistor 2, a third transistor 3, and a fourth transistor 4. The first transistor 1 and the second transistor 2 are connected in series, and then connected in series with a combined device formed by the third transistor 3 and the fourth transistor 4 connected in parallel. In other words, an interconnection end after the series connection is connected to a connection end after the parallel connection, as shown in Figure 5 (c).

[0057] In an optional embodiment, the latch (specifically, the master latch 151 or the slave latch 152) referred to in the present application is a latch with a hardened structure, which is used to prevent the level of the feedback structure of the entire flip-flop circuit from being flipped and locked (unable to recover) when particles are incident in a radiation environment, resulting in a change in the output level of the flip-flop circuit.

[0058] In an optional embodiment, the latch (specifically, the hardened structure in the latch) comprises four interlocking circuits, and each interlocking circuit comprises two transistors connected in series. See Figure 6 shows a structure diagram of a DICE latch hardened structure provided in embodiments of the present application. As shown in Figure 6 The latch shown in comprises four interlocking paths, each interlocking path comprises two transistors connected in series, and there are a total of eight transistors, which are connected in an interlocking topology as shown in the figure. Compared with the two-input, two-output structure of the conventional DICE latch shown in Figure 2 The four storage nodes in the new DICE latch are both inputs and outputs, and data is directly transmitted simultaneously through the four channels of the flip-flop, without passing through the feedback structure of the master latch and the slave latch, which can accelerate the transmission speed of the data signal.

[0059] It should be noted that the trigger circuit provided by this invention is an improved DICE hardened trigger circuit. Its principle is similar to that of the traditional DICE structure. When a node in the feedback structure is flipped by a single particle incident, the two adjacent nodes restore the level of this node after the ionizing radiation ends through an interlocking function. Moreover, compared with the traditional DICE hardened trigger, the data in this invention is transmitted directly through four paths / channels simultaneously, without needing to go through the feedback loop of the master and slave latches, which can improve the circuit speed.

[0060] This application also provides a trigger, the trigger comprising the above-mentioned... Figures 3-6 The trigger circuit described in the embodiment includes, but is not limited to, edge-triggered D triggers, synchronous reset D triggers, D scan triggers, synchronous reset scan triggers, RS triggers, or other types of triggers.

[0061] For example, please see Figure 7 (a)- Figure 7 (d) shows the logic input structure diagrams of several possible flip-flops. Among them, Figure 7 (a) represents a D flip-flop. Figure 7 (b) indicates a synchronously reset D flip-flop. Figure 7 (c) represents a D-scan trigger. Figure 7 (d) indicates a synchronous reset scan D flip-flop.

[0062] This application is also applicable to single-event upset protection for other sequential circuits such as latch circuits.

[0063] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0064] This application provides a trigger circuit, including a logic input circuit with circuit connections, a first master-level gate circuit, a second master-level gate circuit, a third master-level gate circuit, a fourth master-level gate circuit, a first slave-level gate circuit, a second slave-level gate circuit, a third slave-level gate circuit, a fourth slave-level gate circuit, a master-level latch, a slave-level latch, and at least one inverter. The master-level latch and the slave-level latch are used to harden the circuit for single-event upsets (SEEs), preventing changes in the circuit's output level due to SEEs, i.e., SEE resistance. This effectively solves the technical problem in existing technologies where the circuit level flips and cannot be recovered when particles are incident on the circuit in a radiated environment.

[0065] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0066] It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

Claims

1. A single-event upset trigger circuit, characterized in that, The flip-flop circuit includes: a logic input circuit, a first master-level gate circuit, a second master-level gate circuit, a third master-level gate circuit, a fourth master-level gate circuit, a first slave-level gate circuit, a second slave-level gate circuit, a third slave-level gate circuit, a fourth slave-level gate circuit, a master-level latch, a slave-level latch, and at least one inverter, wherein: The logic input circuit, the first master-level gate circuit, and the first slave-level gate circuit are connected in sequence. The logic input circuit, the third master-level gate circuit, and the third slave-level gate circuit are connected in sequence. The logic input circuit, the first inverter in the at least one inverter, the second master-level gate circuit, and the second slave-level gate circuit are connected in sequence. The logic input circuit, the first inverter in the at least one inverter, the fourth master-level gate circuit, and the fourth slave-level gate circuit are connected in sequence. The output terminals of each of the first master-level gate circuit, the second master-level gate circuit, the third master-level gate circuit, and the fourth master-level gate circuit are connected to the master-level latch. The output terminals of each of the first slave-level gate circuit, the second slave-level gate circuit, the third slave-level gate circuit, and the fourth slave-level gate circuit are connected to the slave-level latch.

2. The circuit according to claim 1, characterized in that, The logic input circuit, the first master-level gate circuit, the master-level latch, the first slave-level gate circuit, and the slave-level latch form a first transmission channel. The logic input circuit, the third master-level gate circuit, the master-level latch, the third slave-level gate circuit, and the slave-level latch form a third transmission channel. The signal transmissions corresponding to the first transmission channel and the third transmission channel are the same. The logic input circuit, the first inverter, the second master-level gate circuit, the master-level latch, the second slave-level gate circuit, and the slave-level latch form a second transmission channel. The logic input circuit, the first inverter, the fourth master-level gate circuit, the master-level latch, the fourth slave-level gate circuit, and the slave-level latch form a fourth transmission channel. The signal transmissions corresponding to the second transmission channel and the fourth transmission channel are the same. The logic input circuit is used to provide input signals; The first transmission channel, the second transmission channel, the third transmission channel, and the fourth transmission channel are all used to transmit the input signal according to the input clock signal.

3. The circuit according to claim 2, characterized in that, When the clock signal is a low-level signal, the first master-level gate circuit, the second master-level gate circuit, the third master-level gate circuit, and the fourth master-level gate circuit are turned on respectively, and the first slave-level gate circuit, the second slave-level gate circuit, the third slave-level gate circuit, and the fourth slave-level gate circuit are turned off respectively. The first transmission channel, the second transmission channel, the third transmission channel, and the fourth transmission channel are used to transmit the input signal and output the result signal transmitted in the previous transmission time.

4. The circuit according to claim 2, characterized in that, When the clock signal changes from a low level to a high level, the first slave gate circuit, the second slave gate circuit, the third slave gate circuit, and the fourth slave gate circuit are turned on respectively, and the first master gate circuit, the second master gate circuit, the third master gate circuit, and the fourth master gate circuit are turned off respectively. The first transmission channel, the second transmission channel, the third transmission channel, and the fourth transmission channel are used to transmit the input signal and output the result signal after the signal transmission.

5. The circuit according to claim 3 or 4, characterized in that, The result signals corresponding to the first transmission channel and the third transmission channel are the same, the result signals corresponding to the second transmission channel and the fourth transmission channel are the same, and the result signal levels corresponding to the first transmission channel and the second transmission channel are opposite.

6. The circuit according to claim 1, characterized in that, The at least one inverter further includes a second inverter and a third inverter, wherein the second inverter is connected to the output terminal of the first slave gate circuit, and the third inverter is connected to the output terminal of the second slave gate circuit.

7. The circuit according to claim 1, characterized in that, The master latch or the slave latch is a latch with a reinforced structure to prevent the level of the trigger circuit from flipping and being locked when particles are incident in a radiation environment, which would cause the output level of the trigger circuit to change.

8. The circuit according to claim 7, characterized in that, The reinforcement structure includes four interlocking circuits, each of which includes two transistors connected in series.

9. The circuit according to claim 1, characterized in that, The gating circuit includes four transistors connected in series.

10. The circuit according to claim 1, characterized in that, The gated circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor and the second transistor are connected in series, and the third transistor and the fourth transistor are connected in parallel. The connection terminals of the first transistor and the second transistor are connected to the first connection terminals of the third transistor and the fourth transistor.

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