A method for preventing map offset errors

By statistically analyzing the actual test values ​​of the OPEN and SHORT items within the outer ring of wafer testing and setting control standards, the misjudgment problem caused by MAP offset error was solved, thus improving test accuracy.

CN114545205BActive Publication Date: 2026-04-17SHANGHAI LIYANGCHUANG CHIP TEST CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
SHANGHAI LIYANGCHUANG CHIP TEST CO LTD
Filing Date
2022-02-23
Publication Date
2026-04-17

AI Technical Summary

Technical Problem

Existing technologies are prone to MAP offset errors in wafer testing, leading to misjudgments and affecting testing accuracy.

Method used

By pre-setting the OPEN and SHORT items in the BIN settings of the MES system, the test results are statistically analyzed only within the outer ring range, the actual BIN item value is automatically determined, and settings are controlled to prevent MAP offset errors.

Benefits of technology

This reduces the false positive rate of MAP offset error and improves the accuracy of wafer testing.

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Abstract

This invention discloses a method for preventing MAP offset errors, comprising the following steps: S100, for the OPEN and SHORT items in the BIN settings of the CP settings of the MES system, pre-setting the flag settings for the OPEN and SHORT items corresponding to the BIN items; S200, after the flag settings are reviewed and submitted, for the test results of the MES system, automatically calculating the OPEN and SHORT items in the outer circle of the test results, and determining the actual BIN item values ​​corresponding to the OPEN and SHORT items; S300, based on the calculated OPEN and SHORT items in the outer circle of the test results, the actual BIN item values, and the pre-set flag settings, performing setting control of the OPEN and SHORT items to prevent MAP offset errors. This invention only performs statistics within the outer circle to prevent MAP offset errors.
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Description

Technical Field

[0001] This invention belongs to the field of wafer testing, and specifically relates to a method for preventing MAP offset errors. Background Technology

[0002] The primary purpose of wafer testing is to exclude defective chips from packaging, thereby reducing packaging costs. In the field of wafer testing, probe cards serve as the medium between the wafer and the testing equipment. Probe cards are typically placed directly on the probe station and connected to the testing equipment via wiring. The purpose of probe cards is to provide the connection between the chip and the testing equipment and to complete wafer testing. Figure 1 The diagram illustrates the relevant equipment and MAP diagram for wafer testing in the prior art.

[0003] However, with the continuous advancement of manufacturing technology, the number of DIEs on wafers is constantly increasing, while the size of DIEs is relatively shrinking. Under these circumstances, MAP SHIFT errors, a phenomenon that causes map shift, are increasingly prone to occur during wafer testing. This obviously affects the progress of wafer testing and inevitably impacts testing accuracy, leading to the inability to quickly and accurately detect problematic DIEs.

[0004] In existing technologies, MES systems prevent MAP SHIFT by statistically analyzing the ratio of open and shorted OS cells (open and short circuits) on the outer ring of the test die. The problem is that this method can lead to false MAP SHIFT detection. This is because MAP SHIFT targets anomalies at the test edge, but existing technologies cover the entire percentage of cells, thus resulting in misjudgments.

[0005] Therefore, there is an urgent need in this field for a technical solution to reduce misjudgment and prevent MAP offset errors. Summary of the Invention

[0006] In view of this, the present invention proposes a method for preventing MAP offset errors, the method comprising the following steps:

[0007] S100. For the OPEN and SHORT items in the BIN settings of the CP settings of the MES system, pre-set the flag settings of the OPEN and SHORT items corresponding to the BIN items.

[0008] S200. After the mark setting is reviewed and submitted, for the test results of the MES system, the OPEN and SHORT items in the outer ring of the test results are automatically counted, and the actual BIN item values ​​corresponding to the OPEN and SHORT items are determined.

[0009] S300: Based on the statistical test results, the values ​​of the OPEN and SHORT items and the actual BIN item in the outer ring, as well as the preset mark settings, the settings of the OPEN and SHORT items are controlled to prevent MAP offset errors.

[0010] Preferred,

[0011] Step S300 further includes: performing statistics on the OPEN and SHORT items in the outer ring of the test results.

[0012] Preferred,

[0013] In step S100, the BIN item includes mapping software and hardware BIN, namely SBIN and HBIN.

[0014] Preferred,

[0015] In step S100, the BIN item includes the BinName item, which is a character type.

[0016] Preferred,

[0017] In step S100, the BIN item includes the BinChar item, which is a numeric type.

[0018] Preferred,

[0019] In step S100, the BIN item includes a RawChar item, which is a numeric type.

[0020] Preferred,

[0021] In step S100, the BIN item includes an InkChar item, which is a character type.

[0022] The present invention has the following technical effects:

[0023] Compared to existing technologies, the above-mentioned solution is prone to misjudgment because it counts the number of OPEN and SHORT chips as a proportion of the total number of chips on the wafer. This invention, however, only counts the actual test values ​​of the outer ring within the outer ring range. This invention determines the number of OPEN and SHORT chips through its settings, enabling automatic control by the MES system and preventing MAP offset errors. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of the wafer testing process in existing technology;

[0026] Figure 2 This is a schematic diagram illustrating the marking setting method described in one embodiment of the present invention;

[0027] Figure 3 This is a schematic diagram illustrating the method for setting control standards in one embodiment of the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will be described in conjunction with the appendices in the embodiments of the present invention. Figures 1 to 3 The technical solutions in the embodiments of the present invention will be clearly and completely described herein. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0029] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0030] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0031] In the description of this invention, it should be noted that if terms such as "upper," "lower," "inner," or "outer" are used to indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship in which the product of this invention is usually placed, they are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention.

[0032] Furthermore, the terms "first" and "second" are used only to distinguish descriptions and should not be interpreted as indicating or implying relative importance.

[0033] It should be noted that, where there is no conflict, the features in the embodiments of the present invention can be combined with each other.

[0034] In one embodiment, the present invention discloses a method for preventing MAP offset errors, the method comprising the following steps:

[0035] S100. For the OPEN and SHORT items in the BIN settings of the CP settings of the MES system, pre-set the flag settings of the OPEN and SHORT items corresponding to the BIN items.

[0036] S200. After the mark setting is reviewed and submitted, for the test results of the MES system, the OPEN and SHORT items in the outer ring of the test results are automatically counted, and the actual BIN item values ​​corresponding to the OPEN and SHORT items are determined.

[0037] S300: Based on the statistical test results, the values ​​of the OPEN and SHORT items and the actual BIN item in the outer ring, as well as the preset mark settings, the settings of the OPEN and SHORT items are controlled to prevent MAP offset errors.

[0038] In this embodiment, the invention determines the number of open and short chips by statistically analyzing the actual test values ​​of the outer ring only within the outer ring area. This allows for automatic control of the MES system and prevention of MAP offset errors. In contrast, existing technologies calculate the number of open and short chips as a proportion of the total number of chips on the wafer, which is inherently prone to misjudgment.

[0039] More preferably,

[0040] In step S200, only the OPEN and SHORT items in the outermost ring are counted.

[0041] This is to fully utilize the fact that MAP SHIFT is an abnormal situation targeting the edge of the test. Thus, the test results are statistically calculated based on the relevant OS items (i.e., OPEN and SHORT items) in the outer ring. The MES system uses this invention to determine the OS settings in the BIN settings, and further controls the OS settings based on which BIN value corresponds to the OS item, thereby preventing MAP SHIFT situations.

[0042] Preferred,

[0043] In step S100, the BIN item includes mapping software and hardware BIN, namely SBIN and HBIN.

[0044] Preferred,

[0045] In step S100, the BIN item includes the BinName item, which is a character type.

[0046] Preferred,

[0047] In step S100, the BIN item includes the BinChar item, which is a numeric type.

[0048] Preferred,

[0049] In step S100, the BIN item includes a RawChar item, which is a numeric type.

[0050] Preferred,

[0051] In step S100, the BIN item includes an InkChar item, which is a character type.

[0052] See Figure 2 This illustrates an example of step S100, where the value of the InkChar item corresponds to the BinName.

[0053] Preferred,

[0054] In step S300, when setting and controlling the OPEN and SHORT items, the control standards are set, including:

[0055] Features include project formulas, calculation formulas, baseline values, single-piece hold, batch hold, QDN generation, cumulative statistics, and activation.

[0056] The calculation formula describes how to calculate the values ​​of the OPEN and SHORT items after statistical analysis. This calculation formula corresponds to the calculation formula for the specific item. The calculation formula can be determined based on experience from multiple tests, such as summing the OPEN and SHORT items (note: summing is feasible because, for a specific wafer size and under a certain process, the number of dies in the outer ring is fixed), or the ratio of the total number of OPEN and SHORT items to the total number of dies in the outer ring. The baseline value is also related to the calculation formula. For example, in the case of summation, the baseline value is assumed to be 16. The item formula describes and expresses a specific item. See also... Figure 3 This illustrates the setting and control of the OPEN and SHORT items in step S300, and implements the setting and control in a standard manner.

[0057] In summary, the method disclosed in this invention provides a technical solution to reduce misjudgments and prevent MAP offset errors. Compared with the prior art, this invention improves test accuracy.

[0058] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for preventing MAP offset errors, the method comprising the following steps: S100. For the OPEN and SHORT items in the BIN settings of the CP settings of the MES system, pre-set the flag settings of the OPEN and SHORT items corresponding to the BIN items. S200. After the mark setting is reviewed and submitted, for the test results of the MES system, the OPEN and SHORT items in the outer ring of the test results are automatically counted, and the actual BIN item values ​​corresponding to the OPEN and SHORT items are determined. S300. Based on the statistical test results, the values ​​of OPEN and SHORT items and the actual BIN item in the outer ring, as well as the preset mark settings, the settings of OPEN and SHORT items are controlled to prevent MAP offset errors. In step S200, only the OPEN and SHORT items in the outer ring are counted; MAP SHIFT is fully utilized as an abnormal situation for the test edge; the test results are calculated by statistically analyzing the relevant OS items in the outer ring, namely OPEN and SHORT items. The MES system determines the OS setting in the BIN setting and further controls the OS setting based on which BIN value the OS item corresponds to, thereby preventing MAP SHIFT. In step S300, when setting and controlling the OPEN and SHORT items, the control standards are set, including: Project formulas, calculation formulas, baseline values, single-piece hold, batch hold, QDN generation, cumulative statistics, and activation functions; in, In step S100, the BIN item includes mapping software and hardware BIN, namely SBIN and HBIN; The BIN field includes the BinName field, which is a character type; The BIN item includes the BinChar item, which is a numeric type; The BIN item includes a RawChar item, which is a numeric type; The BIN item includes an InkChar item, which is a character type.

Citation Information

Patent Citations

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