A modeling verification and code generation method for integrated circuit design

Abstract

The present invention discloses a modeling verification and code generation method for integrated circuit design, including: dividing the functions in the requirement design document into different VerilogHDL statement modules, the VerilogHDL statement modules include top-level modules and bottom-level modules; filling the top-level module code, bottom-level module code, top-level module port number and bottom-level module port number into the corresponding module table respectively according to the internal functions and ports of the top-level module and the bottom-level module; verifying whether the code in the module table conforms to the principle of synthesizable model; verifying the syntax structure and logical structure of the code in the module table; filling in the functions required to be implemented by the code in the module table, and functionally verifying the principle of synthesizable model; converting the code that conforms to the principle of synthesizable model, syntax structure, logical structure and functional verification into usable VerilogHDL code. The present invention ensures that the code implementation stage conforms to the principle of synthesizable model, and reduces code implementation errors and functional logic errors.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit verification, and in particular to a modeling verification and code generation method for integrated circuit design. Background Art

[0002] With the continuous development of integrated circuit technology and the continuous innovation of processor architecture, the complexity and scale of high-performance processors are constantly increasing. The problem that comes with it is that reliability is difficult to guarantee. Therefore, correctness verification has become one of the important bottlenecks in the development of high-performance processor chips. The verification process usually accounts for more than 70% of the entire chip development cycle. At present, FPGA development is often used to verify the design of digital integrated circuits, especially in aerospace, military industry and other national defense fields, which have put forward higher requirements for the functional realization, security and reliability of FPGA design. Therefore, the verification of FPGA design becomes more important.

[0003] At present, verification technology faces two problems: complexity and comprehensiveness. Complexity means that as the scale of the system continues to expand, the complexity of the corresponding verification rules increases, it is difficult to take into account the verification work of each functional module, and the proportion of time occupied in the development cycle is also increasing, resulting in the verification cycle often being longer than the development cycle; comprehensiveness means that most of the current verification work is concentrated after the system design and development is completed, ignoring the verification of the demand analysis stage before actual development, resulting in the verification process not covering the entire system development cycle, and due to omissions or unreasonable problems in the early design, it is easy to cause large-scale rework in the development stage, reducing the efficiency of system development. Summary of the invention

[0004] The purpose of the present invention is to provide a modeling verification and code generation method for integrated circuit design, which ensures that the code implementation stage complies with the principle of a synthesizable model and reduces code implementation errors and functional logic errors.

[0005] To achieve the above objectives, the present application proposes a modeling verification and code generation method for integrated circuit design, comprising:

[0006] Analyze the demand design document in detail, and divide the functions in the demand design document into different Verilog HDL statement modules, wherein the Verilog HDL statement module includes a top-level module and a bottom-level module, and the top-level module mainly realizes the instantiation of the bottom-level module;

[0007] According to the internal functions and ports of the top-level module and the bottom-level module, the top-level module code, the bottom-level module code, the top-level module port number and the bottom-level module port number are respectively filled into the corresponding module table;

[0008] Verify whether the code in the module table complies with the principle of synthesizable model;

[0009] Verify the syntax and logic structure of the code in the module table;

[0010] Fill in the functions required to implement the code in the module table and perform functional verification on the synthesizable model principle;

[0011] Convert the code that complies with the synthesizable model principles, syntax structure, logical structure, and functional verification into usable Verilog HDL code.

[0012] Furthermore, Verilog HDL statements other than instantiation functions are divided into multiple sub-functions according to functions, each of the sub-functions is a bottom-level module, and the top-level module instantiates different bottom-level modules, thereby realizing all required functions.

[0013] Further, according to the internal functions and ports of the top-level module and the bottom-level module, the top-level module code, the bottom-level module code, the top-level module port number and the bottom-level module port number are respectively filled into the corresponding module table, specifically:

[0014] Determine the top-level module variables, and use the current value and the previous value as the way to determine the rising and falling edges;

[0015] Determine the underlying module variables, using the current value and previous value as a way to determine the rising and falling edges;

[0016] Designing a bottom-level module table according to the bottom-level module variables;

[0017] The top-level module selects to instantiate different bottom-level modules, defines the instantiation relationship between top-level module variables and bottom-level module variables, and creates an instantiated top-level module table.

[0018] Furthermore, verify whether the code in the module table complies with the principle of the synthesizable model, specifically: based on the rules of the synthesizable statements, determine whether the variables and statements defined in the top-level module table and the bottom-level module table comply with the rules, and output the definitions that do not comply with the rules.

[0019] Furthermore, the grammatical structure and logical structure of the code in the module table are verified, specifically: the top-level module table and the bottom-level module table are displayed, and jumps are performed according to the fill-in codes in the respective module tables. When jumping to a table that cannot be reached as specified or the fill-in code in the table to be jumped to does not meet the grammatical standards, the specific cells in the module table are highlighted.

[0020] Furthermore, the functions required to be implemented are filled in the code in the module table, and the functional verification of the synthesizable model principle is performed, specifically: the codes in the top-level module table and the bottom-level module table are converted into codes under the Promela syntax, and the Promela code is input into the Spin software to perform functional verification of the code.

[0021] Furthermore, the codes in the top-level module table and the bottom-level module table are converted into codes under the Promela syntax, and the Promela codes are input into the Spin software to perform functional verification on the codes, specifically:

[0022] According to the Promela syntax standard, convert the top-level module table and the bottom-level module table into Promela statements supported by the Spin software;

[0023] The Promela statement and the filled-in functional requirements are input into the Spin software, and the verification function of Spin is applied to determine whether the code in the corresponding module table meets the functional requirements.

[0024] Furthermore, the code that complies with the synthesizable model principles, syntax structure, logical structure, and functional verification is converted into usable Verilog HDL code. Specifically, according to the Verilog HDL syntax standard, the top-level module table and the bottom-level module table are converted into Verilog HDL statements that meet the requirements analysis and are executable.

[0025] Compared with the prior art, the above technical solution adopted by the present invention has the following advantages: the code design method of the front end of the present invention is a visual modeling method. After the code design is completed, the code running process can be simulated in a visual way, so that code errors can be effectively found, and the error path can be found, which provides assistance for the modification work. The front end also judges whether the design of the code conforms to the synthesizable statements, reduces the code structure that cannot be converted into circuits, and provides a basis for the subsequent conversion into circuits. After the code design is completed, it is converted into Promela statements supported by Spin, and the Spin tool is used to verify the function of the code, which can find design errors in the early stage of design, greatly reduce rework time, and improve design efficiency. Through the above method, when generating Verilog HDL statements, it is guaranteed that the statements are available and valid. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A flow chart of a modeling verification and code generation method for integrated circuit design;

[0027] Figure 2 It is the port diagram of the top-level module or the bottom-level module;

[0028] Figure 3 A structural diagram of a top-level module module table or a bottom-level module module table;

[0029] Figure 4 It can be used to verify the synthesizable statements, the syntax and logic structures, and the functional verification flow chart;

[0030] Figure 5 This is a comparison chart between Verilog HDL language and Promela language. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application, that is, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0032] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0033] Example 1

[0034] like Figure 1 As shown, this embodiment provides a modeling verification and code generation method for integrated circuit design, which specifically includes:

[0035] S1, analyzing the demand design document in detail, dividing the functions in the demand design document into different Verilog HDL statement modules, wherein the Verilog HDL statement modules include a top-level module and a bottom-level module, and the top-level module mainly realizes the instantiation of the bottom-level module;

[0036] It should be noted that the top-level module is divided into functions that only instantiate the bottom-level modules, and the specific functions are implemented by the bottom-level modules.

[0037] S2, according to the internal functions and ports of the top-level module and the bottom-level module, fill the top-level module code, the bottom-level module code, the top-level module port number and the bottom-level module port number into the corresponding module table respectively;

[0038] Specifically, Figure 2 As shown in the figure, when determining the top-level module variables, they are divided into two types of table storage: input and output. The variables include seven attributes: port name, Verilog HDL data type, Verilog HDL variable size, Promela data type, Promela variable size, initial value and last value. The initial last value is equal to the initial value by default. The initial value and last value can indicate the rising edge and falling edge. Determining the bottom-level module variables is similar to the above method.

[0039] Fill in the functions of the bottom-level modules first; the top-level modules are filled after the bottom-level modules are designed. When filling, you only need to select the bottom-level modules that need to be instantiated, such as Figure 3 As shown, the input and output variables are matched to complete the instantiation.

[0040] S3, verifying whether the code in the module table complies with the principle of a synthesizable model;

[0041] Specifically, Figure 4 The synthesizable statement rules shown include:

[0042] You cannot assign a value to the same variable in more than one always procedure block. You cannot use both blocking and non-blocking assignments for the same assignment object.

[0043] Avoid mixing rising-edge and falling-edge triggered flip-flops.

[0044] The assignment of the same variable cannot be controlled by multiple clocks, nor can it be controlled by two different clock conditions (or different clock edges).

[0045] Avoid using x-values ​​or z-values ​​in case statements.

[0046] Only statements that meet the synthesizable statement rules can proceed to the next step.

[0047] S4, verifying the grammatical structure and logical structure of the code in the module table.

[0048] Specifically, Figure 4 The syntax structure verification shown is: checking the bit width of the top-level module and the bottom-level module variables to prevent truncation, and checking the integrity of the If statement or Case statement to check whether there is an incomplete branch. At the same time, since the selected variables can only be defined variables when defining the module, undefined variables can be avoided.

[0049] like Figure 4 The logic function verification shown in the figure is realized by jumping within the table. The table may include ignored cells and unreachable cells, and jumps are performed according to the data (code) filled in the table, such as Figure 3 As shown, the events and states in the table will be marked with values, and each processing cell (except event and state cells) will be divided into two parts. One part is the number of events to be jumped to. The table jumps according to the value of the event. When jumping to an unreachable cell, it means that an error has occurred in the code and an error will be reported. The specific cell where the error occurs in the module is highlighted, indicating that an error has occurred in the current cell. At the same time, the path where the error cell appears, that is, the error path, is recorded. The error path can be replayed to facilitate the discovery of the cause of the error.

[0050] S5, filling in the functions required to be implemented by the code in the module table, and performing functional verification on the synthesizable model principle;

[0051] Specifically, Figure 5 As shown, both Promela and Verilog HDL support parallel systems. It is feasible and effective to convert the designed VerilogHDL code into Promela code. When defining the module, the properties required to generate Promela code are defined. Then, according to the defined bottom-level modules and top-level modules and the instantiation relationship between them, Promela code is generated according to Promela syntax rules. The Promela code and the defined functional description are input into the Spin tool to verify whether the function is realized.

[0052] S6, converting the code that complies with the synthesizable model principle, syntax structure, logic structure, and functional verification into a usable Verilog HDL code;

[0053] Specifically, when the code passes the above verifications and is guaranteed to be in compliance with the requirements, the code generation begins. When defining the bottom-level modules and top-level modules, the properties required to generate the Verilog HDL code are defined. Based on the defined bottom-level modules and top-level modules and the instantiation relationship between them, the Verilog HDL statements that meet the requirements analysis and are executable are generated according to the Verilog HDL syntax standard.

[0054] The above method of this application requires an operating system with more than 8G memory and more than 4 CPU cores.

[0055] The foregoing description of specific exemplary embodiments of the present invention is for the purpose of illustration and demonstration. These descriptions are not intended to limit the present invention to the precise form disclosed, and it is clear that many changes and variations can be made based on the above teachings. The purpose of selecting and describing the exemplary embodiments is to explain the specific principles of the present invention and its practical application, so that those skilled in the art can realize and utilize various different exemplary embodiments of the present invention and various different selections and changes. The scope of the present invention is intended to be limited by the claims and their equivalents.

Claims

1. A modeling verification and code generation method for integrated circuit design, characterized in that: include: Analyze the demand design document in detail, and divide the functions in the demand design document into different Verilog HDL statement modules, wherein the Verilog HDL statement modules include top-level modules and bottom-level modules; According to the internal functions and ports of the top-level module and the bottom-level module, the top-level module code, the bottom-level module code, the top-level module port number and the bottom-level module port number are respectively filled into the corresponding module table; Verify whether the code in the module table complies with the principle of synthesizable model; Verify the syntax and logic structure of the code in the module table; Fill in the functions required to implement the code in the module table and perform functional verification on the synthesizable model principle; Convert the code that complies with the principles of synthesizable models, syntax structure, logic structure, and functional verification into usable Verilog HDL code; The Verilog HDL statements other than the instantiation function are divided into a plurality of sub-functions according to the functions, each of the sub-functions is a bottom-level module, and the top-level module instantiates different bottom-level modules; According to the internal functions and ports of the top-level module and the bottom-level module, the top-level module code, the bottom-level module code, the top-level module port number and the bottom-level module port number are respectively filled into the corresponding module table, specifically: Determine the top-level module variables, and use the current value and the previous value as the way to determine the rising and falling edges; Determine the underlying module variables, using the current value and previous value as a way to determine the rising and falling edges; Designing a bottom-level module table according to the bottom-level module variables; The top-level module selects to instantiate different bottom-level modules, defines the instantiation relationship between top-level module variables and bottom-level module variables, and creates an instantiated top-level module table; Fill in the functions required by the code in the module table and perform functional verification on the synthesizable model principle, specifically: convert the codes in the top-level module table and the bottom-level module table into codes under Promela syntax, and input the Promela code into the Spin software to perform functional verification on the code.

2. A modeling verification and code generation method for integrated circuit design according to claim 1, characterized in that: Verify whether the code in the module table complies with the principle of the synthesizable model, specifically: based on the rules of the synthesizable statements, determine whether the variables and statements defined in the top-level module table and the bottom-level module table comply with the rules, and output definitions that do not comply with the rules.

3. A modeling verification and code generation method for integrated circuit design according to claim 1, characterized in that: Verify the grammatical structure and logical structure of the code in the module table, specifically: display the top-level module table and the bottom-level module table, jump according to the fill-in code in each module table, and highlight the specific cells in the module table when jumping to a table that cannot be reached as specified or the fill-in code in the table does not meet the grammatical standards.

4. A modeling verification and code generation method for integrated circuit design according to claim 1, characterized in that: The codes in the top-level module table and the bottom-level module table are converted into codes under the Promela syntax, and the Promela codes are input into the Spin software to perform functional verification on the codes, specifically: According to the Promela syntax standard, convert the top-level module table and the bottom-level module table into Promela statements supported by the Spin software; The Promela statement and the filled-in functional requirements are input into the Spin software, and the verification function of Spin is applied to determine whether the code in the corresponding module table meets the functional requirements.

5. The modeling verification and code generation method for integrated circuit design according to claim 1, characterized in that: Convert the code that complies with the principles of synthesizable models, syntax structure, logical structure, and functional verification into usable VerilogHDL code. Specifically, according to the Verilog HDL syntax standard, convert the top-level module table and the bottom-level module table into Verilog HDL statements that meet the requirements analysis and are executable.

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