A Fast FPGA Delay Evaluation Method Based on Delay Database

Abstract

The present invention provides a fast FPGA delay evaluation method based on a delay database. The method includes: obtaining the path information of the line segments covered by the nets between units and the resistance-capacitance information of the line segments; obtaining the net configuration information based on the path information and the resistance-capacitance information; obtaining the relative coordinates (x, y) of the starting unit and the ending unit at both ends of the net; establishing a number of delay tables according to the net configuration information and the relative coordinates, including: a clock table, a differential table, a path table, an additional delay table, a basic delay table, and a pin table; and calculating the delays at both ends of the net by looking up the tables according to the net type and the relative coordinates of the units at both ends of the net. The present invention can quickly evaluate the net delay, the evaluation result is accurate and reliable, and it does not require a large amount of computing resources.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and particularly relates to a fast FPGA delay evaluation method based on a delay database. Background Art

[0002] FPGA is a product further developed on the basis of programmable devices such as PAL (Programable Logic Device) and CPLD (Complex Programable Logic Device). The circuit unit modules included inside it are: configurable logic modules (LB Logic Block), input / output modules (IOB, Input Output Block), and internal connections (INT, Interconnect), etc. The FPGA chip is a two-dimensional structure, each point corresponds to a Tile, each Tile contains a slice structure SLICE, and SLICE contains a gate-level table (GATE).

[0003] FPGA is a programmable device and allows unlimited programming. Compared with traditional logic circuits and gate arrays (such as PAL, GAL, and CPLD devices), FPGA has a different structure. FPGA uses a small lookup table (such as 16×1RAM) to implement combinational logic. Each lookup table is connected to the input end of a D flip-flop, and the D flip-flop then drives other logic circuits or drives I / O, thus constituting a basic logic unit module (hereinafter simply referred to as a module) that can implement both combinational logic functions and sequential logic functions. These modules are interconnected with each other or connected to the I / O module using metal wires. The logic of FPGA is realized by loading programming data into internal static storage units. The values stored in the static memory units determine the logic functions of the modules and the connection methods between the modules and between the modules and I / O, and ultimately determine the functions that FPGA can achieve.

[0004] The typical FPGA development process generally includes main steps such as function definition, device selection, design input, functional simulation, synthesis optimization, post-synthesis simulation, technology mapping, placement, routing, post-simulation, board-level simulation, and chip programming and debugging.

[0005] In the entire development process, timing constraints are the most basic constraints specified by users, which can specify the operating frequency of the designed circuit and stipulate the operating speed of the chip. In order to meet the timing constraints of users, the FPGA software needs to be considered at every step of the entire physical implementation. Especially in the later stage of the design, different delay evaluation methods and different delay optimization strategies have a great impact on the function of the entire circuit. The most important of these include placement and routing, which is also a time-consuming step in the entire process.

[0006] Among them, layout specifically refers to placing circuit elements at legal positions on the chip without violating physical constraints. Wiring specifically refers to connecting the nets between circuit elements without violating physical constraints such as short circuits or open circuits. In an FPGA, it is a process of reasonably configuring the hardware primitives and underlying cells in the logic netlist onto the inherent hardware structure inside the chip. In the layout and wiring process in the FPGA field, how to quickly and effectively evaluate the delay of nets before actual wiring plays a crucial role in the layout design.

[0007] The commonly used delay evaluation method in the industry is to calculate a most likely path between modules through a fast router, and then evaluate this path based on the Elmore Delay Model (delay model) of the Resistance Capacitance (RC) chain to obtain the delay result. However, the calculation speed of this method is relatively slow, so it cannot be frequently called during optimization processes such as layout, and correspondingly, it will also cause a decrease in the accuracy of delay evaluation.

[0008] Some also store the delay data between common modules in a delay query table for local acceleration during delay evaluation. However, creating a delay query table still takes a lot of time, the storage space occupied by the created delay query table is relatively large, and it cannot completely cover all wiring scenarios.

[0009] Even by creating more delay query tables to increase the coverage rate for different wiring scenarios, when the number of delay query tables is increased a lot, the storage space and query time of the FPGA memory are both very large. Eventually, when multiple delay query tables are added to the memory, due to frequent cache swapping caused by calling the delay query tables, it cannot achieve the effect of quickly evaluating the delay between modules. Summary of the Invention

[0010] The object of the present invention is to provide a fast FPGA delay evaluation method based on a delay database, which can obtain multiple configuration information of a net by loading the wiring information of the chip and the resistance capacitance information of the segments covered by the net from the circuit netlist, and according to the obtained configuration information and the relative coordinates at both ends of the net, quickly and effectively evaluate the delay of the net before actual wiring of the chip. The evaluated net delay can be used to improve the layout design of the FPGA, which is beneficial to improving the design performance of the FPGA chip.

[0011] To achieve the above object, the present invention provides a fast FPGA delay evaluation method based on a delay database. The FPGA chip includes a number of cells arranged in an array, and any two cells are connected by a net. The method includes:

[0012] Obtain the path information of the segments covered by the nets between units and the resistance-capacitance information of the segments; obtain the net configuration information based on the path information and the resistance-capacitance information;

[0013] Obtain the relative coordinates (x, y) of the starting unit and the ending unit at both ends of the net; establish several delay tables according to the net configuration information and the relative coordinates, including: clock table, differential table, path table, additional delay table, basic delay table, pin table;

[0014] Calculate the delay Delay at both ends of the net by looking up the table according to the net type and the relative coordinates of the units at both ends of the net net 。

[0015] Preferably, the configuration information includes the net type, and the net type includes: clock net, non-clock net.

[0016] Preferably, when the net is a clock net, the configuration information includes: the clock type Clock corresponding to the clock net type 、delay value Delay clock ;

[0017] The clock table includes several key-value pairs, and the key-value pair includes the clock type Clock type and the corresponding delay value Delay clock ;

[0018] Look up the clock table according to the clock type Clock of the clock net type to obtain the delay Delay at both ends of the net net =Delay clock 。

[0019] Preferably, the configuration information of the non-clock net includes: the source pin flag ID of the starting unit of the net source 、the type Type of the starting unit of the net source 、the delay value Delay of the source pin of the starting unit of the net itself source intrinc pin 、the delay value Delay from the source pin of the starting unit of the net to the adjacent routing Tile of the starting unit clb to int ;

[0020] The pin table includes several first quadruples, and one first quadruple corresponds to one net; the first quadruple includes: the source pin flag ID of the starting unit of the net source 、the type Type of the starting unit of the net source 、the delay value Delay of the source pin of the starting unit of the net itself source intrinc pin 、the delay value Delay from the source pin of the starting unit of the net to the adjacent routing Tile of the starting unit clb to int ;

[0021] The configuration information of the non-clock net also includes: the leakage pin flag ID of the net end unit sink , the type Type of the net end unit sink , the delay value Delay of the leakage pin of the net end unit itself sink intrinc pin , the delay value Delay from the leakage pin of the net end unit to the adjacent routing Tile of the end unit int to clb ;

[0022] The pin table contains several second quadruples, and one second quadruple corresponds to one net; the second quadruple includes: the leakage pin flag ID of the net end unit sink , the type Type of the net end unit sink , the delay value Delay of the leakage pin of the net end unit itself sink intrinc pin , the delay value Delay from the adjacent routing Tile of the net end unit to the leakage pin of the end unit int to clb .

[0023] Preferably, the configuration information of the non-clock net also includes: the additional delay value Delay of the net add , Delay add = Delay x_dir_add + Delay y_dir_add ; Let x base , y base be the preset line length thresholds in the X and Y axis directions respectively, and x and y are the abscissa and ordinate of the relative coordinate (x, y); Let Delay x_base be the delay value in the X axis direction of the line segment with a line length of x base , and Delay y_base be the delay value in the Y axis direction of the line segment with a line length of y base ; Delay x_dir_add = Delay x_base * numx, Delay y_dir_add = Delay y_base * numy;

[0024] The additional delay table contains several third quadruples, and one third quadruple corresponds to one net;

[0025] The third quadruple includes: the source pin flag ID of the net start unit source , the leakage pin flag ID of the net end unit sink , the relative coordinate (x, y) of the start unit and the end unit at both ends of the net, and the additional delay value Delay add .

[0026] Preferably, the configuration information of the non-clock net also includes: the basic delay value Delay of the net base , Delay base = Delay x_dir_base + Delay y_dir_base ; lenx ≡ x mod x base , leny ≡ y mod y base , Delay x_dir_base , Delay y_dir_base respectively represent the delay values of the line segments with lengths lenx and leny on the X and Y axes;

[0027] The basic delay table contains several fourth quadruples, and one fourth quadruple corresponds to one net; the fourth quadruple includes: the source pin flag ID of the starting unit of the net source , the drain pin flag ID of the ending unit of the net sink , the relative coordinates (x, y) of the starting unit and the ending unit at both ends of the net, and the basic delay value Delay base .

[0028] Preferably, the configuration information of the non-clock net also includes: the path information of the net, and the path information includes the Tile type Tile of the Tile spanned by different positions of the net path type ; several groups of path information are stored in the path table, and one group of path information corresponds to one net.

[0029] Preferably, the Tiles spanned by the net path are divided into a first group and a second group according to the Tile type; the delay generated by the net spanning any Tile in the first group exceeds the set reference delay value Time base , and the delay exceeding the reference delay value is recorded as the differential delay value of the Tile;

[0030] The configuration information of the non-clock net also includes: the reference delay value Time base , the Tile type Tile type , the position information of the Tile in the net, and the differential delay value Delay corresponding to the Tile type Tile type and the position information; diff ;

[0031] The differential table contains several fifth quadruples, and one fifth quadruple corresponds to one Tile, and the Tile is the Tile in the first group; the fifth quadruple includes: the reference delay value Time base , the Tile type Tile type , the position information of the Tile in the net, and the differential delay value corresponding to the Tile type Tile type, the differential delay value Delay corresponding to the location information of the Tile online network diff .

[0032] Preferably, calculating the delay of a non-clock net includes the steps of:

[0033] S1. Based on the source pin flag ID source of the net starting cell, the type Type source of the net starting cell, look up the pin table to obtain the delay value Delay source intrinc pin of the source pin of the net starting cell itself, and the delay value Delay clb to int from the source pin of the net starting cell to the adjacent routing Tile of this starting cell; calculate the delay value Delay source pin of the source pin of the net starting cell = Delay source intrinc pin + Delay clb to int ;

[0034] Based on the drain pin flag ID sink of the net ending cell, the type Type sink of the net ending cell, look up the table to obtain the delay value Delay sink intrinc pin of the drain pin of the net ending cell itself, and the delay value Delay int to clb from the adjacent routing Tile of the net ending cell to the drain pin of this ending cell; calculate the delay value Delay sink pin of the drain pin of the net ending cell = Delay sink intrinc pin + Delay int to clb ; calculate the delay values Delay pin of the pins at both ends of the net = Delay source pin + Delay sink pin ;

[0035] S2. Based on the source pin flag ID source of the net starting cell, the drain pin flag ID sink of the net ending cell, and the relative coordinates (x, y) of the starting cell and the ending cell at both ends of the net, look up the additional delay table to obtain the additional delay value Delay add of the net;

[0036] S3. Based on the source pin flag ID source of the net starting cell, the drain pin flag ID sink of the net ending cell, and the relative coordinates (x, y) of the starting cell and the ending cell at both ends of the net, look up the basic delay table to obtain the basic delay value Delay base of the net;

[0037] S4. Look up the path table to obtain the net path, and the Tile type Tile spanned by different positions of the net pathtype If the Tile type belongs to the first group, based on the type of the Tile across which the wire network spans, the Tile type , and the position of the Tile in the wire network, look up the difference table to obtain the differential delay value Delay of the Tile diff ; Repeat step S4 until the differential delay values of all the Tiles belonging to the first group across which the wire network spans are obtained and summed to obtain the differential delay value Delay of the wire network net diff = ∑Delay diff ;

[0038] S5. Calculate the delays Delay at both ends of the wire network net = Delay pin + Delay base + Delay add + Delay net diff .

[0039] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0040] 1) The delay evaluation method of the present invention can greatly accelerate the evaluation speed of the delays at both ends of the wire network;

[0041] 2) The delay evaluation method of the present invention can greatly improve the evaluation accuracy of the delays at both ends of the wire network, and the evaluation results are accurate and reliable;

[0042] 3) In the prior art, a lookup table is established by corresponding a module of the chip to a delay data. Not only is the table lookup time long, but the established lookup table occupies too much memory and the lookup speed is slow. Moreover, in the case of a complex chip layout, the actual delay result of the wire network after routing is quite different from the lookup table evaluation result; in the present invention, by establishing six basic lookup tables (clock table, differential table, path table, additional delay table, basic delay table, pin table) and delay calculation rules, the fast calculation of the delays at both ends of the wire network is realized by means of table lookup and accumulation under the condition of reasonable memory consumption;

[0043] 4) The present invention can be applied to the wire networks in all routing scenarios. For different routers, the deviation between the wire network delay evaluation result before wire network routing and the actual wire network delay after routing is reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solution of the present invention, the drawings required for description will be briefly introduced below. Obviously, the drawings in the following description are an embodiment of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts:

[0045] Figure 1Schematic diagram of the FPGA chip array structure and the internal logic resource structure of the Tile;

[0046] Figure 2 In the embodiment of the present invention, flowchart of the fast FPGA delay evaluation method based on the delay database;

[0047] Figure 2A In the embodiment of the present invention, flowchart of calculating the delays at both ends of the net by looking up the table in step S103;

[0048] Figure 3 In the embodiment of the present invention, a schematic diagram of a net of the FPGA chip;

[0049] Figure 4 In the embodiment of the present invention, schematic diagrams of two nets with the same relative coordinates at both ends; Detailed implementation manners

[0050] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0051] First, definitions of some special terms in the present invention are given:

[0052] Tile (array): A component that realizes specific physical functions, such as LUT (Look-Up-Table), DFF (Data Flip-Flop), SLICE, DSP (Digital Signal Processor), etc.; among them, the delay value generated when the net crosses units of types such as DSP, IOB (Programmable Input / Output Unit), and RAM is relatively long;

[0053] segment (line segment): Each segment of metal trace in the net after routing;

[0054] net (net): A signal line connecting between units;

[0055] pin (pin): The intersection point between a unit and a net;

[0056] place (placement): Placing a unit at a legal position in the circuit;

[0057] route (routing): Mapping a signal line onto a layout;

[0058] path (path): A complete line from the source pin of the starting unit of the net to the drain pin of the ending unit of the net;

[0059] table: A set of regular storage units;

[0060] timing: A standard for optimizing each path to meet specific delay requirements during the physical implementation process;

[0061] FPGA is a regular array structure based on TILE. The routing resource map of the FPGA chip (which can be obtained from the circuit netlist of the FPGA chip) mainly describes the connection information of the segments between any two units inside the chip. At the same time, the circuit netlist also contains the capacitance and resistance information of each segment. According to the capacitance and resistance information, the delay of the corresponding segment can be known (this is the prior art and will not be described in detail in the present invention).

[0062] As Figure 1 shown, the FPGA chip is designed with a regular array structure. The types of Tiles are mainly divided into two categories. One is the Logic type of Tile for placing insts (units, designed by users; Tiles are arrays, designed by chip manufacturers. Insts are placed into Tiles to implement user functions), and the other is the Interconnect (routing, simply referred to as Inter) type of Tile for connecting logic units.

[0063] Except for some special functional requirements on the FPGA chip, such as GTX (Gigabit Transceiver) and XADC (Xilinx Analog-to-Digital Converter), etc., the type of Tile in each column on the FPGA chip is the same (for example, a column of Tiles can be any one of INTER, IOB, LB, DSP, RAM). And to make the routing resources rich, the Logic type of Tile and the Inter type of Tile appear in pairs to facilitate the smooth routing of the signal lines of the logic units.

[0064] As Figure 1 shown by the two long dashed boxes in the vertical direction, the distribution of Tiles on the FPGA chip is the same in type for each column. Figure 1 The internal logics of the Inter type of Tile and the Logic type of Tile are also enlarged and shown.

[0065] The following is the configuration information of the path corresponding to the net between pin AQ and pin D4 in the routing resource map: Figure 3 net "net_name",

[0066] net "net_name",

[0067] outpin "source_inst" AQ,

[0068] inpin "sink_inst" D4,

[0069] pip LB2_X31Y117 LB_PIN_AQ -> OMUX4,

[0070] pip LB1_X38Y137 IMUX37 -> LB_PIN_D4,

[0071] pip INT1_X38Y137 ALTER1 -> BOUNCE1,

[0072] pip INT1_X38Y137 BOUNCE1 -> IMUX137,

[0073] pip INT1_X38Y137 S1TOEN DO -> ALTER1,

[0074] pip INT1_X38Y138 S2T1END0 -> S1T0BEG0,

[0075] pip INT2_X31Y117 OMUX4 -> S6TOBEG0,

[0076] pip INT2_X33Y121 S6TOENDO -> S6T1BEGO,

[0077] pip INT2_X33Y127 S6T1ENDO -> S6T1BEGO,

[0078] pip INT2_X33Y133 S6T1END0 -> S6T0BEG0,

[0079] pip INT2_X35Y137 S6T0END0 -> S2T0BEG0,

[0080] pip INT2_X37Y137 S2T0END0 -> S2T1BEG0,;

[0081] In the circuit designed by the user, after synthesis, a circuit netlist is generated first, and then through physical implementation, the functions designed by the user are configured and implemented on the FPGA. The signals in the netlist first pass through the input pins (Output Pin), and then through the configuration unit, they are connected to zero or multiple groups of Paths through PIP (programmable interconnection point), and finally output through the output pins (Input Pin).

[0082] In the above path information, AQ represents the source pin (i.e., Output Pin) of the starting unit of the net, and D4 represents the drain pin (i.e., Input Pin) of the ending unit of the net. Tiles of the same type have the same Source Pin and Sink Pin.

[0083] As Figure 3 shown, a successfully configured two - end net (the net between AQ and D4) describes how the signal is transmitted from AQ (Source Pin) to D4 (Sink Pin), and it can conveniently show the used Path and PIP (in the above path configuration information, "→" represents a pip, and several pips form a path). Taking the last line in the above path information as an example, INT2_X37Y137 represents a Tile of INT type, and S2TOEND0 and S2T1BEG0 represent line segments.

[0084] Due to the regular storage of the FPGA chip, given the Source Pin, Sink Pin, and the relative offset between the Source Pin and Sink Pin, no matter where the starting position of the net Source Pin is, the path between the Source Pin and the corresponding Sink Pin is the same, and the types of the Segments and PIPs it passes through are exactly the same.

[0085] In the embodiment of the present invention, as Figure 4 shown, in the FPGA chip, it is necessary to connect the AB pin of the unit in the first row and the first column (at the position X01Y01 in the chip) to the CD pin of the unit in the first row and the second column (at the position X01Y20 in the chip), and it is also necessary to connect the AB pin of the unit in the second row and the first column to the CD pin of the unit in the second row and the second column. The relative position between the AB pin and the CD pin in the first row, and the relative coordinates between the AB pin and the CD pin in the second row are both (0, 19). The path for connecting the AB pin in the first row to the CD pin in the first row is path1, and the path for connecting the AB pin in the second row to the CD pin in the second row is path2. The chip resources spanned by path1 and path2 are the same, so the delay values are also the same.

[0086] The present invention provides a fast FPGA delay evaluation method based on a delay database. The FPGA chip includes a number of units arranged in an array, and any two units are connected by a net. The method includes:

[0087] S101. Load the circuit netlist, obtain the path information of the segments covered by the nets between cells and the resistance-capacitance information of the segments; obtain the net configuration information based on the path information and the resistance-capacitance information (how to obtain the configuration information from the circuit netlist is prior art and not the focus of this invention, so it will not be elaborated here).

[0088] In an embodiment of the present invention, the configuration information includes the net type, and the net type includes: clock net and non-clock net. The net type can be determined according to the pin types at both ends of the net.

[0089] In an embodiment of the present invention, the configuration information of the clock net includes: the clock type Clock corresponding to the clock net type , the delay value Delay clock . Among them, Clock type includes: global clock and local clock.

[0090] In an embodiment of the present invention, the configuration information of the non-clock net includes: the source pin flag ID of the starting cell of the net source , the type Type of the starting cell of the net source , the delay value Delay of the source pin of the starting cell of the net itself source intrinc pin , the delay value Delay from the source pin of the starting cell of the net to the adjacent routing (INT) Tile of the starting cell clb to int .

[0091] In an embodiment of the present invention, the configuration information of the non-clock net further includes: the drain pin flag ID of the ending cell of the net sink , the type Type of the ending cell of the net sink , the delay value Delay of the drain pin of the ending cell of the net itself sink intrinc pin , the delay value Delay from the drain pin of the ending cell of the net to the adjacent routing (INT) Tile of the ending cell int to clb .

[0092] In an embodiment of the present invention, the configuration information of the non-clock net further includes: the basic delay value Delay of the net base , Delay base =Delay x_dir_base +Delay y_dir_base ; x base , y base are the wire length thresholds in the X and Y axis directions from the starting cell of the net respectively, and Delay x_dir_base , Delay y_dir_base respectively represent the delay values in the X and Y axis directions when the distance from the starting cell of the net is less than the wire length thresholds x base , y baseWithin the range, it is the sum of the time delays of all line segments covered by the wire network in the X and Y axis directions.

[0093] In an embodiment of the present invention, the configuration information of the non-clock wire network further includes: the additional time delay value Delay of the wire network add , Delay add = Delay x_dir_add + Delay y_dir_add ; Let x base , y base be the preset line length thresholds in the X and Y axis directions respectively, and x and y are the abscissa and ordinate of the relative coordinate (x, y); Let Delay x_base be the time delay value of the line segment with a line length of x base in the X axis direction, and Delay y_base be the time delay value of the line segment with a line length of y base in the Y axis direction, Delay x_dir_add = Delay x_base *numx, Delay y_dir_add = Delay y_base *numy. In an embodiment of the present invention, the configuration information of the non-clock wire network further includes: the basic time delay value Delay of the wire network base , Delay base = Delay x_dir_base + Delay y_dir_base ; lenx ≡ x mod x base , leny ≡ y mod y base , Delay x_dir_base , Delay y_dir_base respectively represent the time delay values of the line segments with lengths of lenx and leny in the X and Y axis directions;

[0094] In an embodiment of the present invention, the configuration information of the non-clock wire network further includes: the path information of the wire network, the Tile types of the Tiles spanned by different positions of the wire network path information; there are several groups of path information stored in the path table, and a group of path information corresponds to a wire network.

[0095] In an embodiment of the present invention, several Tiles spanned by the wire network are divided into a first group and a second group according to the Tile type; the time delay generated by the wire network spanning any Tile in the first group exceeds the set reference time delay value Time base , and the time delay exceeding the reference time delay value is recorded as the differential time delay value of the Tile; the first group of units includes Tiles of types such as DSP, IOB, and RAM.

[0096] The configuration information of the non-clock wire network further includes: the reference time delay value Time base, Tile type Tile type , the location information of Tile in the online network, and Tile type Tile type and the differential delay value Delay corresponding to the location information of Tile in the online network diff ;

[0097] S102. Obtain the relative coordinates (x, y) of the starting unit and the ending unit at both ends of the network; establish several delay tables according to the network configuration information and the relative coordinates, including: Clock Table, Diff Table, Path Table, Long Table, base Table, Pin Table;

[0098] In an embodiment of the present invention, the Clock Table includes several key-value pairs, and the key-value pair includes the clock type Clock type and the corresponding delay value Delay clock ; the delay Delay at both ends of the clock network net = Delay clock .

[0099] In an embodiment of the present invention, the Pin Table includes several first quadruples, and one first quadruple corresponds to one network; the first quadruple includes: the source pin flag ID of the starting unit of the network source , the type Type of the starting unit of the network source , the delay value Delay of the source pin of the starting unit of the network itself source intrinc pin , the delay value Delay from the source pin of the starting unit of the network to the starting unit clb to int .

[0100] In an embodiment of the present invention, the Pin Table further includes several second quadruples, and one second quadruple corresponds to one network; the second quadruple includes: the drain pin flag ID of the ending unit of the network sink , the type Type of the ending unit of the network sink , the delay value Delay of the drain pin of the ending unit of the network itself sink intrinc pin , the delay value Delay from the ending unit of the network to the drain pin of the ending unit int to clb .

[0101] The base Table includes several third quadruples, and one third quadruple corresponds to one network; the third quadruple includes: the source pin flag ID of the starting unit of the network source , the drain pin flag ID of the ending unit of the network sink , the relative coordinates (x, y) of the starting unit and the ending unit at both ends of the network, the basic delay value Delaybase 。

[0102] The additional delay table contains several fourth quadruples, and one fourth quadruple corresponds to one wire network;

[0103] The fourth quadruple includes: the source pin flag ID of the starting unit of the wire network source , the drain pin flag ID of the ending unit of the wire network sink , the relative coordinates (x, y) of the starting unit and the ending unit at both ends of the wire network, and the additional delay value Delay add 。

[0104] The difference table contains several fifth quadruples, and one fifth quadruple corresponds to one unit, and this unit is the unit of the first group; the fifth quadruple includes: the reference delay value Time of the unit base , the unit type Tile type , the position information of the unit on the wire network, and the differential delay value Delay corresponding to the unit type Tile type diff 。

[0105] S103. Calculate the delay Delay at both ends of the wire network by looking up the table according to the wire network type and the relative coordinates of the units at both ends of the wire network net , as Figure 2A shown, specifically including the steps:

[0106] S1031. When the wire network is a clock wire network, look up the clock table based on the clock type Clock of the clock wire network, and the delay Delay at both ends of the clock wire network type = Delay net ; when the wire network is a non-clock wire network, go to S1032; clock

[0107] S1032. Based on the source pin flag ID of the starting unit of the wire network source , the type Type of the starting unit of the wire network source look up the pin table to obtain the delay value Delay of the source pin of the starting unit of the wire network itself source intrinc pin , the delay value Delay from the source pin of the starting unit of the wire network to the adjacent routing Tile of this starting unit clb to int ; calculate to obtain the delay value Delay of the source pin of the starting unit of the wire network source pin = Delay source intrinc pin + Delay clb to int ;

[0108] Based on the drain pin flag ID of the ending unit of the wire network sink , the type Type of the ending unit of the wire network sink look up the table to obtain the delay value Delay of the drain pin of the ending unit of the wire network itselfsink intrinc pin The delay value Delay from the wiring Tile adjacent to the end unit of the wire network to the drain pin of the end unit int to clb ; Calculate the delay value Delay of the drain pin of the end unit of the wire network sink pin = Delay sink intrinc pin + Delay int to clb ; Calculate the delay values Delay of the pins at both ends of the wire network pin = Delay source pin + Delay sink pin ; Enter S1033;

[0109] S1033. Based on the source pin flag ID of the start unit of the wire network source , the drain pin flag ID of the end unit of the wire network sink , and the relative coordinates (x, y) of the start unit and the end unit at both ends of the wire network, look up the additional delay table to obtain the additional delay value Delay of the wire network add ;

[0110] S1034. Based on the source pin flag ID of the start unit of the wire network source , the drain pin flag ID of the end unit of the wire network sink , and the relative coordinates (x, y) of the start unit and the end unit at both ends of the wire network, look up the basic delay table to obtain the basic delay value Delay of the wire network base ; Enter S1035;

[0111] S1035. Look up the path table to obtain the type Tile of the Tile spanned by the wire network type and the position of the Tile in the wire network; If Tile type belongs to the first group, look up the differential table based on the Tile type Tile type to obtain the differential delay value Delay of the Tile diff ; Repeat step S1035 until the differential delay values of all Tiles belonging to the first group spanned by the wire network are obtained and summed to obtain the differential delay value Delay of the wire network net diff = ∑Delay diff ; Enter S1036;

[0112] S1036. Calculate the delays at both ends of the wire network:

[0113] Delay net = Delay pin + Delay base + Delay add + Delay net diff .

[0114] Example 1

[0115] As shown Figure 4 , AQ is used as the source pin flag of the starting unit of the wire network, and D4 is used as the drain pin flag of the ending unit of the wire network. Calculate the delay of the wire network between pin AQ and pin D4. This wire network is a non-clock wire network. The length of this wire network in the X-axis direction is 8, and the length in the Y-axis direction is 21. In this embodiment, x base = 15, y base = 22. That is, in this embodiment, Delay add = 0. By looking up the path table, it is found that a set of Paths corresponding to this wire network sequentially includes: the Segment connected to pin AQ, 4 consecutive Segments of type X6 with a length of 6, 2 Segments of type X2, 1 Segment of type X1, and the Segment corresponding to pin D4 (equivalent to a wire length of 8 in the X-axis direction and 21 in the Y-axis direction), and a total of 2 RAMs and 1 DSP are passed through (that is, 3 units of the first group are passed through).

[0116] The delay values of the pins at both ends of the wire network are 170 ns. Among them, the sum of the self-delay of pin AQ and the delay from pin AQ to its adjacent unit is 103 ns; the sum of the self-delay of pin D4 and the delay from the adjacent unit of pin D4 to pin D4 is 67 ns;

[0117] Delay source pin = 103 ns; Delay sink pin = 67 ns;

[0118] The delay value of the pins at both ends of the wire network Delay pin = Delay source pin + Delay sink pin = 170 ns;

[0119] The third and fourth tuples corresponding to it in the basic delay table are: AQ, D4, (8, 21), 1350. Through the first three values in this third tuple, the basic delay value corresponding to the wire network can be found:

[0120] Delay base = 1350 ns.

[0121] The additional value for the wire network crossing the DSP is 20 ns, and the additional values for crossing two RAMs are 30 ns and 32 ns respectively. The differential delay value of the wire network Delay net diff = 30 + 32 + 20 = 82 ns.

[0122] Therefore, the delay Delay net at both ends of the wire network = Delay pin + Delay base + Delay net diff = 1602 ns.

[0123] Embodiment 2

[0124] In this embodiment, the relative coordinates at both ends of the wire grid are (43, 35), and both x base and y base are 18. The wire grid is regarded as being composed of a line segment with a length of 7 (X7) and two line segments with a length of x base = 18 spliced in the X-axis direction. The wire grid is spliced by a X18 line segment and a X7 line segment in the Y-axis direction. Since the chip has different structures in the X-axis direction and the Y-axis direction, line segments of the same length can have different delay values in the X-axis direction and the Y-axis direction.

[0125] The delay value of the line segment with a length of 18 in the X-axis direction is 230 ns, and the delay value of the line segment with a length of 18 in the Y-axis direction is 180 ns. Delay add = 230 * 2 + 180 = 640.

[0126] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A fast FPGA delay evaluation method based on a delay database. The FPGA chip includes several units arranged in an array, and any two units are connected by a net. Characterized in that, The method includes: Obtain the path information of the line segments covered by the nets between the units and the resistance-capacitance information of the line segments; obtain the net configuration information based on the path information and the resistance-capacitance information; Obtain the relative coordinates (x, y) of the starting unit and the ending unit at both ends of the net; establish several delay tables according to the net configuration information and the relative coordinates, including: a clock table, a differential table, a path table, an additional delay table, a basic delay table, and a pin table; According to the network type and the relative coordinates of the two end units of the network, the time delay Delay at both ends of the network is calculated by looking up a table. net ; The configuration information includes a wire network type, and the wire network type includes: a clock wire network, a non-clock wire network; when the wire network is a clock wire network, the configuration information includes: a clock type Clock corresponding to the clock wire network type , a delay value Delay clock ; The clock table contains a number of key-value pairs, and the key-value pairs include the clock type Clock type and the corresponding delay value Delay clock ; According to the clock type Clock of the clock wire network type Search the clock table to obtain the delay Delay at both ends of the wire network net = Delay clock ; The configuration information of the non-clock net includes: the source pin flag ID of the starting unit of the net source , the type Type of the starting unit of the net source , the delay value Delay of the source pin of the starting unit of the net itself source intrinc pin , the delay value Delay from the source pin of the starting unit of the net to the adjacent routing Tile of the starting unit clb to int ; The pin table contains a number of first quadruples, and one first quadruple corresponds to one net; the first quadruple includes: the source pin flag ID of the net starting unit source , the type Type of the net starting unit source , the delay value Delay of the source pin of the net starting unit itself source intrinc pin , the delay value Delay from the source pin of the net starting unit to the adjacent routing Tile of the starting unit clb to int ; The configuration information of the non-clock net also includes: the leakage pin flag ID of the net end unit sink , the type Type of the net end unit sink , the delay value Delay of the leakage pin of the net end unit itself sink intrinc pin , the delay value Delay from the leakage pin of the net end unit to the adjacent routing Tile of the end unit int to clb ; The pin list contains several second quadruples, and one second quadruple corresponds to one net; the second quadruple includes: the ID of the leakage pin of the net end unit sink , the type Type of the net end unit sink , the delay value Delay of the leakage pin of the net end unit itself sink intrinc pin , the delay value Delay from the adjacent routing Tile of the net end unit to the leakage pin of this end unit int to clb ; The configuration information of the non-clock wire network further includes: the additional delay value Delay of the wire network add , Delay add = Delay x_dir_add + Delay y_dir_add ; Let x base , y base be the preset wire length thresholds in the X and Y axis directions respectively, and x and y be the abscissa and ordinate of the relative coordinate (x, y); Let Delay x_base be the delay value of the line segment with a wire length of x base in the X axis direction, and Delay y_base be the delay value of the line segment with a wire length of y base in the Y axis direction, Delay x_dir_add = Delay x_base * numx, Delay y_dir_add = Delay y_base * numy; The additional delay table includes several third quadruples, and one third quadruple corresponds to one net; The third quadruple includes: the source pin flag ID of the starting unit of the wire network source , the drain pin flag ID of the ending unit of the wire network sink , the relative coordinates (x, y) of the starting unit and the ending unit at both ends of the wire network, and the additional delay value Delay add ; The configuration information of the non-clock wire network further includes: the basic delay value Delay of the wire network base , Delay base = Delay x_dir_base + Delay y_dir_base ; lenx ≡ x mod x base , leny ≡ y mod y base , Delay x_dir_base , Delay y_dir_base respectively represent the delay values of the line segments with lengths lenx and leny on the X and Y axes; The basic delay table contains several fourth quadruples, and one fourth quadruple corresponds to one wire network; the fourth quadruple includes: the source pin flag ID of the starting unit of the wire network source , the drain pin flag ID of the ending unit of the wire network sink , the relative coordinates (x, y) of the starting unit and the ending unit at both ends of the wire network, and the basic delay value Delay base ; The configuration information of the non-clock wire network further includes: the path information of the wire network, and the path information includes the Tile type Tile of the Tile crossed at different positions of the wire network path type ; There are several groups of path information stored in the path table, and one group of path information corresponds to one wire network; The Tiles crossed by the wire network path are divided into a first group and a second group according to the Tile type; the time delay generated by the wire network crossing any Tile in the first group exceeds the set reference time delay value Time base , and the time delay exceeding the reference time delay value is recorded as the differential time delay value of the Tile; The configuration information of the non-clock wire network further includes: the reference delay value Time base , the Tile type Tile type , the position information of the Tile in the wire network, and the differential delay value Delay corresponding to the Tile type Tile type ; diff ; The differential table contains a number of fifth quadruples, with one fifth quadruple corresponding to one Tile, and the Tile being a Tile of the first group; the fifth quadruple includes: a reference delay value Time base , a Tile type Tile type , the location information of the Tile in the online network, and the differential delay value Delay corresponding to the Tile type Tile type , diff ; Calculating the delay of a non-clock net includes the steps: S1. Based on the source pin flag ID of the net starting point unit source , the type Type of the net starting point unit source Search the pin table to obtain the delay value Delay of the source pin of the net starting point unit itself source intrinc pin , the delay value Delay from the source pin of the net starting point unit to the adjacent routing Tile of this starting point unit clb t o int ; Calculate to obtain the delay value Delay of the source pin of the net starting point unit source pin = Delay source intrinc pin + Delay clb to int ; Based on the ID of the missing pin of the net end unit sink , the type Type of the net end unit sink Look up the table to obtain the delay value Delay of the missing pin of the net end unit itself sink intrinc pin , the delay value Delay from the adjacent routing Tile of the net end unit to the missing pin of this end unit int to clb ; Calculate the delay value Delay of the missing pin of the net end unit sink pin = Delay sink intrinc pin + Delay int to clb ; Calculate the delay values Delay of the pins at both ends of the net pin = Delay source pin + Delay sink pin ; S2. Based on the source pin flag ID of the starting unit of the wire network source , the drain pin flag ID of the ending unit of the wire network sink , look up the additional delay table according to the relative coordinates (x, y) of the starting unit and the ending unit at both ends of the wire network to obtain the additional delay value Delay of the wire network add ; S3. Based on the source pin flag ID of the starting unit of the wire network source , the drain pin flag ID of the ending unit of the wire network sink , and the relative coordinates (x, y) of the starting unit and the ending unit at both ends of the wire network, search the basic delay table to obtain the basic delay value Delay of the wire network base ; S4. Search the path table to obtain the net path, and obtain the Tile types of the Tiles crossed by different positions of the net path type , if the Tile type belongs to the first group, based on the type of the Tile crossed by the net type , and the position of the Tile in the net, search the difference table to obtain the differential delay value Delay of the Tile diff ; Repeat step S4 until the differential delay values of all the Tiles belonging to the first group crossed by the net are obtained and summed up to obtain the differential delay value Delay of the net net diff = ∑Delay diff ; S5. Calculate the delay Delay at both ends of the wire network net = Delay pin + Delay base + Delay add + Delay net diff .

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