Interface of a Memory Circuit and Its Memory System

Abstract

The interface of the memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that can vary between a first high voltage and a low voltage and is used to enable the memory circuit. At least one data terminal receives at least one first data signal that can vary between a second high voltage and the low voltage. The data strobe terminal receives a first data strobe signal that can vary periodically between the second high voltage and the low voltage. The first data strobe signal is synchronized with at least one first data signal and is configured to latch and sample at least one first data signal. The first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

Description

Technical Field

[0001] The present disclosure relates to an interface of a memory circuit; in particular, an interface of a memory circuit capable of operating with signals of low voltage swing. Background Art

[0002] A system on chip (SoC) can integrate most or all components of a computer on a single chip, thus providing an efficient solution in a smaller size. Due to the above advantages, SoCs have been used in various applications, such as display driver integrated circuits (DDICs), microcontroller units (MCUs), true wireless stereo Bluetooth, and edge artificial intelligence (Edge-AI).

[0003] To improve computing efficiency, static random access memory (SRAM) circuits are often embedded in SoCs. However, integrating SRAM into the same die as the SoC not only increases the cost and complexity of the SoC but also reduces the yield of the die. Although external dynamic random access memory (DRAM) or pseudo SRAM (PSRAM) can provide a more cost-effective solution, the high-speed, high-swing signals used to control external DRAM or PSRAM result in increased power consumption and cause problems of high electromagnetic interference (EMI).

[0004] The discussion of the prior art is provided only for background information. Statements in the prior art do not admit that the subject matter disclosed therein constitutes the prior art of the present disclosure, and no part of the prior art should be regarded as the prior art admitted by any part of this application (including the discussion of the prior art). Summary of the Invention

[0005] An embodiment of the present disclosure provides an interface of a memory circuit. The interface of the memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal is used to receive a chip enable signal that varies between a first high voltage and a low voltage and is used to enable the memory circuit. The at least one data terminal is used to receive at least one first data signal that varies between a second high voltage and the low voltage. The data strobe terminal is used to receive a first data strobe signal that periodically varies between the second high voltage and the low voltage. Wherein, the first data strobe signal is synchronized with the at least one first data signal, the first data strobe signal is configured to latch and sample the at least one first data signal, and the first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

[0006] Another embodiment of the present disclosure provides a memory system. The memory system includes a memory circuit and a host circuit. The memory circuit includes a first interface. The first interface includes a first chip enable terminal, at least one first data terminal, and a first data strobe terminal. The first chip enable terminal is used to receive a chip enable signal that varies between a first high voltage and a low voltage. The at least one first data terminal is used to receive at least one first data signal that varies between a second high voltage and the low voltage. The first data strobe terminal is used to receive a first data strobe signal that periodically varies between the second high voltage and the low voltage, and the first data strobe signal is configured to latch and sample the at least one first data signal. The host circuit includes a second interface, and the second interface includes a second chip enable terminal, at least one second data terminal, and a second data strobe terminal. The second chip enable terminal is coupled to the first chip enable terminal and is used to transmit the chip enable signal for enabling the memory circuit. The at least one second data terminal is coupled to the at least one first data terminal and is used to transmit the at least one first data signal. The second data strobe terminal is coupled to the first data strobe terminal and is used to transmit the first data strobe signal that is synchronized with the at least one first data signal. Wherein the first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage. Brief Description of the Drawings

[0007] With reference to the embodiments and the claims, and together with the accompanying drawings, a more complete understanding of the present disclosure can be obtained, wherein like reference numerals refer to like elements in all the drawings.

[0008] Figure 1 Shows a memory system according to an embodiment of the present disclosure.

[0009] Figure 2 Shows when performing a write operation, Figure 1 of the memory system.

[0010] Figure 3 A timing diagram showing signals transmitted between a memory circuit and a host circuit during a write operation.

[0011] Figure 4 A schematic diagram showing some components of a first interface when a write operation is performed.

[0012] Figure 5 Showing when a read operation is performed, Figure 1 the memory system.

[0013] Figure 6 A timing diagram showing signals transmitted between a memory circuit and a host circuit during a read operation.

[0014] Figure 7 A schematic diagram showing some components of a first interface when a read operation is performed.

[0015] Figure 8 Showing a memory system according to another embodiment of the present disclosure. Detailed Embodiments

[0016] The following description of the present disclosure, together with the accompanying drawings (which are incorporated in and constitute a part of this specification), illustrates embodiments of the present disclosure, but the present disclosure is not limited to these embodiments. In addition, the following embodiments can be appropriately combined to implement another embodiment.

[0017] As used herein, "one embodiment", "an embodiment", "exemplary embodiment", "other embodiments", "another embodiment", etc. mean that an embodiment of the present disclosure described herein may include a particular feature, structure, or characteristic, but not every embodiment must include the particular feature, structure, or characteristic. In addition, repeated use of "in the embodiment" does not necessarily refer to the same embodiment, although it may.

[0018] To make the present disclosure easier to understand, the following provides detailed steps and structures. Obviously, the implementation manner of the present disclosure does not limit the specific details known to those of ordinary skill in the art to which the present invention pertains. Furthermore, well-known structures and steps are not described in detail to avoid unnecessary limitations to the present disclosure. The preferred embodiments of the present disclosure will be described in detail below. However, in addition to these embodiments, the present disclosure can also be widely implemented in other embodiments. The scope of the present disclosure is not limited to the embodiments below, but is defined by the scope of the patent application.

[0019] Figure 1FIG. 100 shows a memory system 100 according to an embodiment of the present disclosure. The memory system 100 includes a memory circuit 110 and a host circuit 120. In some embodiments, the host circuit 120 can be designed as a SoC, which includes a controller and can be used to process accesses to the memory circuit 110.

[0020] The memory circuit 110 may include a memory array 114, which is composed of a plurality of memory cells, and the host circuit 120 can control the memory circuit 110 to access the memory space provided by the memory array 114. In some embodiments, the memory cells MC1 of the memory array 114 can be dynamic random access memory (DRAM) cells or static random access memory (SRAM) cells. In addition, in the present disclosure, communication between the memory circuit 110 and the host circuit 120 can be performed without using a constant oscillating clock signal by utilizing a novel mechanism of low voltage-swing signals; in this way, the power consumption of the host circuit 120 during accessing the memory circuit 110 can be effectively reduced.

[0021] As Figure 1 shown, the memory circuit 110 further includes a first interface 112. The first interface 112 includes a first chip enable terminal TCEA, N first data terminals TDQA0 to TDQA(N - 1), and a first data strobe terminal TDQSA, where N is a positive integer. Correspondingly, the host circuit 120 may include a second interface 122. The second interface 122 also includes a second chip enable terminal TCEB, N second data terminals TDQB0 to TDQB(N - 1), and a second data strobe terminal TDQSB. In addition, the second chip enable terminal TCEB is coupled to the first chip enable terminal TCEA, the second data terminals TDQB0 to TDQB(N - 1) are coupled to the first data terminals TDQA0 to TDQA(N - 1), and the second data strobe terminal TDQSB is coupled to the first data strobe terminal TDQSA. In this embodiment, N is greater than 1. However, in some other embodiments, N can be 1. In this case, the first interface 112 has a first data terminal TDQA0, and the second interface 122 has a second data terminal TDQB0.

[0022] In some embodiments, the memory circuit 110 and the host circuit 120 may be formed in two different dies, and the memory system 100 may further include a plurality of interconnect structures CTE, CTQ0 to CTQ(N-1), and CTS to couple the terminals of the memory circuit 110 and the host circuit 120 in different dies. The interconnect structure CTE may be coupled between the first chip enable terminal TCEA and the second chip enable terminal TCEB, the interconnect structures CTQ0 to CTQ(N-1) may be coupled between the first data terminals TDQA0 to TDQA(N-1) and the second data terminals TDQB0 to TDQB(N-1), and the interconnect structure CTS may be coupled between the first data strobe terminal TDQSA and the second data strobe terminal TDQSB. In some embodiments, the two dies of the memory circuit 110 and the host circuit 120 may be stacked in a 3D package, so that the interconnect structures CTE, CTQ0 to CTQ(N-1), and CTS may be formed in the process of 3D packaging technology. The interconnect structures CTE, CTQ0 to CTQ(N-1), and CTS may be any form of vertical die-to-die interconnect structure provided by 3D packaging technology. For example, the interconnect structures CTE, CTQ0 to CTQ(N-1), and CTS may be wafer-to-wafer connection pads, chip-to-wafer connection pads, microbumps formed during a chip-to-wafer stacking process, microbumps formed during a chip-to-chip stacking process, etc. However, the present disclosure is not limited thereto. For example, in some other embodiments, in a 2.5D package, the two dies of the memory circuit 110 and the host circuit 120 may be arranged laterally adjacent to each other on the same substrate. In this case, the interconnect structures CTE, CTQ0 to CTQ(N-1), and CTS may include conductive traces formed in the substrate. Since the memory circuit 110 and the host circuit 120 may be formed in different dies through different suitable processes, the yield of the memory system 100 can be improved.

[0023] In addition, in some embodiments, the memory system 100 may further include more memory circuits in addition to or adjacent to the memory circuit 110, and the host circuit 120 must control all the memory circuits in the memory system 100. In this case, the host circuit 120 may generate a chip enable signal to notify the corresponding memory circuit (e.g., 110) to select the memory circuit 110 for performing read operations and write operations. Figure 2 Illustrates the memory system 100 when performing a write operation.

[0024] As Figure 2As shown, the second chip enable terminal TCEB of the host circuit 120 can transmit a chip enable signal SIGCE to the memory circuit 110, and the first chip enable terminal TCEA of the memory circuit 110 can receive the chip enable signal SIGCE through the first interconnect structure CTE. In some embodiments, the voltage level of the chip enable signal SIGCE can be controlled to vary between a first high voltage VH1 and a low voltage VL, and when the received chip enable signal SIGCE has a specific waveform or is at a specific voltage, the memory circuit 110 can be enabled. For example, when the chip enable signal SIGCE changes from the first high voltage VH1 to the low voltage VL, the memory circuit 110 can be enabled. In some embodiments, the first high voltage VH1 can be the supply voltage of the memory system 100, and the low voltage VL can be the ground voltage of the memory system 100. In this embodiment, the first interface 112 of the memory circuit 110 can further include a voltage terminal TLA, and the second interface 122 of the host circuit 120 can further include a voltage terminal TLB. The voltage terminal TLA can be coupled to the voltage terminal TLB through the interconnect structure CTL, so that the voltage terminals TLA and TLB can be coupled to ground to receive the same low voltage VL.

[0025] In addition, the host circuit 120 can generate N first data signals SIGDQA0 to SIGDQA(N - 1) according to the information to be transmitted to the memory circuit 110. As Figure 2 shown, the second data terminals TDQB0 to TDQB(N - 1) of the host circuit 120 can transmit the first data signals SIGDQA0 to SIGDQA(N - 1) to the memory circuit 110, and the first data terminals TDQA0 to TDQA(N - 1) of the memory circuit 110 can receive the first data signals SIGDQA0 to SIGDQA(N - 1) through the interconnect structures CTQ0 to CTQ(N - 1). In this embodiment, the voltage level of each of the first data signals SIGDQA0 to SIGDQA(N - 1) can vary between a second high voltage VH2 and the low voltage VL to indicate the corresponding bit value.

[0026] In some embodiments, in order to reduce the power consumption required to generate the first data signals SIGDQA0 to SIGDQA(N - 1), the second high voltage VH2 can be less than the first high voltage VH1. In this embodiment, the host circuit 120 can generate the second high voltage VH2 according to the first high voltage VH1. As Figure 2 shown, a voltage terminal TH2B of the second interface 122 can transmit the second high voltage VH2 to the memory circuit 110, and a voltage terminal TH2A of the first interface 112 can receive the second high voltage VH2 through the interconnect structure CTH2 coupled between the voltage terminals TH2A and TH2B.

[0027] Since the second highest voltage VH2 may be quite small, it is not easy to identify the bit values based on the voltages of the first data signals SIGDQA0 to SIGDQA(N - 1). Therefore, in this embodiment, the host circuit 120 can further generate a reference voltage VREF, which is higher than the low voltage VL and lower than the second highest voltage VH2. The reference voltage VREF can be used to assist the memory circuit 110 in determining the value of the received bit. In this embodiment, the difference between the second highest voltage VH2 and the low voltage VL can be twice the difference between the reference voltage VREF and the low voltage VL. In this case, the memory circuit 110 can identify the bit value by comparing the voltages of the first data signals SIGDQA0 to SIGDQA(N - 1) with the reference voltage VREF. For example, if the voltage of the first data signal SIGDQA0 is higher than the reference voltage VREF, it can be determined that the bit of the first data signal SIGDQA0 has a logical value of "1". Furthermore, if the voltage of the first data signal SIGDQA0 is less than the reference voltage VREF, it can be determined that the bit value of the first data signal SIGDQA0 has a logical value of "0". By using the reference voltage VREF, the memory circuit 110 can identify the bit values of the first data signals SIGDQA0 to SIGDQA(N - 1) more quickly and accurately.

[0028] In this embodiment, the host circuit 120 can generate the reference voltage VREF by dividing the second highest voltage VH2 in half. As Figure 2 shown, the voltage terminal TREFB of the second interface 122 can transmit the reference voltage VREF to the memory circuit 110, and the voltage terminal TREFA of the first interface 112 can receive the reference voltage VREF through the interconnection structure CTR coupled between the voltage terminals TREFA and TREFB.

[0029] Furthermore, in order to assist the memory circuit 110 in distinguishing the bits carried by the first data signals SIGDQA0 to SIGDQA(N - 1) respectively, the host circuit 120 can further generate the first data strobe signals SIGDQSA accompanying the first data signals SIGDQA0 to SIGDQA(N - 1) to the memory circuit 110. As Figure 2 shown, the second data strobe terminal TDQSB of the host circuit 120 can transmit the first data strobe signal SIGDQSA to the memory circuit 110, and the first data strobe terminal TDQSA of the memory circuit 110 can receive the first data strobe signal SIGDQSA through the third interconnection structure CTS. In this embodiment, the first data strobe signal SIGDQSA can be within a specific time interval (such as Figure 3PW1 and PW2) periodically vary between a second high voltage VH2 and a low voltage VL, and can be synchronized with the first data signals SIGDQA0 to SIGDQA(N-1) within the specific time interval, so that the first data strobe signal SIGDQSA can be used to latch and sample the first data signals SIGDQA0 to SIGDQA(N-1).

[0030] Figure 3 Shows a timing diagram of signals transmitted between the memory circuit 110 and the host circuit 120 during a write operation. As Figure 3 shown, the write operation can be performed in two stages: an instruction stage PW1 and a data stage PW2. In the instruction stage PW1, the first data signals SIGDQA0 to SIGDQA(N-1) corresponding to or carrying the write instruction and the write address will be transmitted. Since the write instruction and the write address are usually presented in a predetermined format and thus have a fixed data length, in the instruction stage PW1, the write instruction and the write address can be transmitted to the first data terminals TDQA0 to TDQA(N-1) within a predetermined number of clock cycles of the first data strobe signal SIGDQSA.

[0031] In the present embodiment, in the instruction stage PW1, each of the first data signals SIGDQA0 to SIGDQA(N-1) can be transmitted at a single data rate (SDR). That is, in the instruction stage PW1, for each clock cycle of the first data strobe signal SIGDQSA, the voltage of each of the first data signals SIGDQA0 to SIGDQA(N-1) will change at most once. In this way, in each clock cycle of the first data strobe signal SIGDQSA, the memory circuit 110 can identify a single data from each of the first data signals SIGDQA0 to SIGDQA(N-1). In the present embodiment, the single data rate architecture adopted in the instruction stage PW1 provides a wider latch window for the memory circuit 110 to sample the first data signals SIGDQA0 to SIGDQA(N-1).

[0032] As Figure 3 shown, the signal edge EA1 of the first data strobe signal SIGDQSA leads the signal edges EA2 of the first data signals SIGDQA0 to SIGDQA(N-1) by a first time interval T1, and a latch signal SIGL1 can be derived from the first data strobe signal SIGDQSA used to sample the first data signals SIGDQA0 to SIGDQA(N-1). In some embodiments, a delay element in the interface 112 can be used to generate the latch signal SIGL1. Figure 4 Shows a schematic diagram of some components of the first interface 112 when performing a write operation.

[0033] As shown Figure 4 in FIG. 1, the first interface 112 may include a logic circuit LCA, an input strobe comparator CPS, a delay unit DU1, and N input data comparators CP0 to CP(N-1). The input strobe comparator CPS is coupled to the first data strobe terminal TDQSA to receive the first data strobe signal SIGDQSA, and the input data comparators CP0 to CP(N-1) are respectively coupled to the first data terminals TDQA0 to TDQA(N-1) to correspondingly receive the first data signals SIGDQA0 to SIGDQA(N-1). The input strobe comparator CPS can compare the first data strobe signal SIGDQSA with the reference voltage VREF and output a comparison signal SIGCP to the delay unit DU1. The delay unit DU1 can thus generate a latch signal SIGL1 by delaying the comparison signal SIGCP for a predetermined time. In this way, the latch signal SIGL1 can trigger the input data comparators CP0 to CP(N-1) to compare the first data signals SIGDQA0 to SIGDQA(N-1) with the reference voltage VREF, so that the logic circuit LCA can further correspondingly identify the bit values of the first data signals SIGDQA0 to SIGDQA(N-1).

[0034] In this embodiment, by appropriately adjusting the delay time provided by the delay unit DU1, the signal edge EA3 of the latch signal SIGL1 can be aligned with the window interval between the rising edge REA1 and the falling edge FEA1 of the first data signals SIGDQA0 to SIGDQA(N-1), so that the input data comparators CP0 to CP(N-1) can sample the first data signals SIGDQA0 to SIGDQA(N-1) when the first data signals SIGDQA0 to SIGDQA(N-1) are stably at the desired voltage.

[0035] In addition, in this embodiment, since the host circuit 120 attempts to control the memory circuit 110 to perform a write operation, when in the instruction stage PW1, after the first data signals SIGDQA0 to SIGDQA(N-1) corresponding to the write instruction and the write address are transmitted, the host circuit 120 will start to generate the first data signals SIGDQA0 to SIGDQA(N-1) corresponding to the write data to be written into the memory circuit 110. As shown Figure 3As shown, after the instruction phase PW1, in the data phase PW2, the first data signals SIGDQA0 to SIGDQA(N - 1) corresponding to the write data can be transmitted together with the first data strobe signal SIGDQSA. That is, in the data phase PW2, the data terminals TDQA0 to TDQA(N - 1) receive the first data signals SIGDQA0 to SIGDQA(N - 1), and the data strobe terminal TDQSA receives the first data strobe signal SIGDQSA.

[0036] Furthermore, in the data phase PW2, the first data signals SIGDQA0 to SIGDQA(N - 1) corresponding to the write data can be transmitted using double data rate (DDR). That is, within each clock cycle of the first data strobe signal SIGDQSA in the data phase PW2, each of the first data signals SIGDQA0 to SIGDQA(N - 1) can change its voltage up to two times. In this way, in the data phase PW2, for each clock cycle of the first data strobe signal SIGDQSA, the memory circuit 110 recognizes two bits of data from each of the first data signals SIGDQA0 to SIGDQA(N - 1).

[0037] In the present embodiment, since the voltages of the first data signals SIGDQA0 to SIGDQA(N - 1) and the first data strobe signal SIGDQSA can often swing, that is, they can include high-speed voltage swings, a relatively small second high voltage VH2 can be deliberately selected to reduce the overall power consumption of the memory system 100, especially the power consumption of the host circuit 120. In addition, by reducing the level of the second high voltage VH2, the electromagnetic interference (EMI) problem caused by the high-speed voltage swings can also be improved.

[0038] Furthermore, in order to further reduce power consumption and improve the EMI problem, when the first data signals SIGDQA0 to SIGDQA(N - 1) stop being transmitted, the first data strobe signal SIGDQSA can stop swinging. For example, before and after the write operation, the first data strobe signal SIGDQSA can remain at the low voltage VL, as Figure 3 shown. In addition, in some embodiments, during the transition period between the instruction phase PW1 and the data phase PW2, if no valid bits are transmitted through the first data signals SIGDQA0 to SIGDQA(N - 1), the first data strobe signal SIGDQSA can also stop swinging. Thus, the EMI problem can be further improved.

[0039] However, detecting such a small voltage swing may require dedicated components to be provided in the memory circuit 110, and may thus require more power. In the present embodiment, in order to reduce the unnecessary power consumption of the memory circuit 110, the voltage swing of the chip enable signal SIGCE can be relatively large, such that the memory circuit 110 can detect the enable status without the need to use low-voltage detection components, and the memory circuit 110 can detect and process the first data signals SIGDQA0 to SIGDQA(N-1) only when the memory circuit 110 is enabled. Since the chip enable signal SIGCE will remain at the same voltage (e.g., low voltage VL) throughout the operation to keep the memory circuit 110 enabled, the swing frequency of the chip enable signal SIGCE is relatively low. Therefore, the power consumption and EMI problems of the host circuit 120 caused by the relatively high voltage swing of the chip enable signal SIGCE are relatively acceptable.

[0040] Therefore, in the present embodiment, the first high voltage VH1 is higher than the second high voltage VH2, such that the memory circuit 110 can easily detect the chip enable signal SIGCE, and the second high voltage VH2 can be higher than the low voltage VL. In some embodiments, the first high voltage VH1 can be higher than 0.8V and the second high voltage VH2 can be less than 0.6V. For example, the first high voltage VH1 can be 1.8V and the second high voltage VH2 can be 0.3V, but the present disclosure is not limited thereto.

[0041] Figure 5 Illustrates the memory system 100 when performing a read operation. Figure 6 Illustrates a timing diagram of signals transmitted between the memory circuit 110 and the host circuit 120 during the read operation. As Figure 6 shown, the read operation includes an instruction phase PR1 and a data phase PR2. In the instruction phase PR1, the first data signals SIGDQA0 to SIGDQA(N-1) corresponding to or carrying a read instruction and a read address can be transmitted using single data rate. After transmitting the first data signals SIGDQA0 to SIGDQA(N-1), the host circuit 120 will hand over the channels between the data strobes TDQSA and TDQSB and the channels between the data terminals TDQA0 to TDQA(N-1) and TDQB0 to TDQB(N-1) to the memory circuit 110, such that the memory circuit 110 can transmit the read data to the host circuit 120 correspondingly. Furthermore, in the instruction phase PR1, after transmitting the first data signals SIGDQA0 to SIGDQA(N-1), the host circuit 120 can control the first data terminals TDQA0 to TDQA(N-1) to remain in a high impedance state (i.e., Figure 6for a predetermined time in the Hi-Z state, enabling the memory circuit 110 to have sufficient time to take over the channel. When the host circuit 120 is ready to sample the signal transmitted by the memory circuit 110, the voltage levels of the first data terminals TDQA0 to TDQA(N-1) can be changed to a predetermined voltage level (such as a low voltage VL), as Figure 6 shown. In some embodiments, during the handover period, the host circuit 120 can keep the data strobe terminals TDQSA and TDQSB at the low voltage VL, thus being able to prevent surges before the memory circuit 110 takes over.

[0042] In this embodiment, after the memory circuit 110 reads the first data signals SIGDQA0 to SIGDQA(N-1), the memory circuit 110 can generate second data signals SIGDQB0 to SIGDQB(N-1) corresponding to the data in a memory cell of the memory array 114 according to the read address. Then, the first data terminals TDQA0 to TDQA(N-1) of the memory circuit 110 can transmit the second data signals SIGDQB0 to SIGDQB(N-1) to the second data terminals TDQB0 to TDQB(N-1) of the host circuit 120.

[0043] In addition, to assist the host circuit 120 in differentiating each bit of the second data signals SIGDQB0 to SIGDQB(N-1), the memory circuit 110 can transmit the second data strobe signal SIGDQSB together with the second data signals SIGDQB0 to SIGDQB(N-1) through the first data strobe terminal TDQSA. The second data strobe signal SIGDQSB is synchronized with the second data signals SIGDQB0 to SIGDQB(N-1), enabling the host circuit 120 to latch and sample the second data signals SIGDQB0 to SIGDQB(N-1) according to the second data strobe signal SIGDQSB. In this embodiment, as Figure 5 shown, the memory circuit 110 can further include an oscillator 116, such as a ring oscillator, for generating the second data strobe signal SIGDQSB.

[0044] As Figure 6 shown, the signal edge EB1 of the second data strobe signal SIGDQSB leads the signal edge EB2 of the second data signals SIGDQB0 to SIGDQB(N-1) by a second time interval T2. In addition, a latch signal SIGL2 can be derived from the second data strobe signal SIGDQSB for sampling the second data signals SIGDQB0 to SIGDQB(N-1). Figure 7 Schematic diagram showing some components of the first interface 112 when performing a read operation.

[0045] AsFigure 7 As shown, in addition to Figure 4 the logic circuit LCA, the input strobe comparator CPS, the delay unit DU1, and the input data comparators CP0 to CP(N-1) described above, the first interface 112 further includes an output strobe buffer BSO, a delay unit DU2, and N output data buffers BDO0 to BDO(N-1). The output strobe buffer BSO is coupled to the first data strobe terminal TDQSA to transmit the second data strobe signal SIGDQSB, and the output data buffers BDO0 to BDO(N-1) are respectively coupled to the first data terminals TDQA0 to TDQA(N-1) to transmit the second data signals SIGDQB0 to SIGDQB(N-1) correspondingly. In this case, the logic circuit LCA can output the second data signals SIGDQB0 to SIGDQB(N-1) to the delay unit DU2, and the delay unit DU2 can delay the second data signals SIGDQB0 to SIGDQB(N-1) by a predetermined time according to the second data strobe signal SIGDQSB to ensure that the signal edge EB1 of the second data strobe signal SIGDQSB can lead the signal edges EB2 of the second data signals SIGDQB0 to SIGDQB(N-1).

[0046] In some embodiments, the second interface 122 of the host circuit 120 and the first interface 112 of the memory circuit 110 may have a symmetric structure. In this case, the second interface 122 can derive a latch signal SIGL2 from the second data strobe signal SIGDQSB, and the second data strobe signal SIGDQSB has a signal edge EB3 that is aligned with a window interval between a rising edge REB2 and a falling edge FEB2 of the second data signals SIGDQB0 to SIGDQB(N-1), as Figure 6 shown. In this way, the host circuit 120 can use the latch signal SIGL2 to latch and sample the second data signals SIGDQA0 to SIGDQA(N-1) when the second data signals SIGDQA0 to SIGDQA(N-1) are stably at the desired voltage.

[0047] In addition, as Figure 6As shown, in data phase PR2, the second data signals SIGDQB0 to SIGDQB(N-1) corresponding to the read data can be transmitted at double data rate. That is, in data phase PR2, within each clock cycle of the second data strobe signal SIGDQSB, each of the second data signals SIGDQB0 to SIGDQB(N-1) can change its voltage up to two times. In this way, for each clock cycle of the second data strobe signal SIGDQSB, the memory circuit 110 can transmit two bits of data through each of the second data signals SIGDQB0 to SIGDQB(N-1) in data phase PR2.

[0048] In addition, as Figure 6 shown, since the second data strobe signal SIGDQSB and the second data signals SIGDQB0 to SIGDQB(N-1) change between the second high voltage VH2 and the low voltage VL, the second data strobe signal SIGDQSB and the second data signals SIGDQB0 to SIGDQB(N-1) can have a smaller voltage swing. In this way, the power consumption of the memory circuit 110 can be reduced and the EMI problem caused by the high-speed voltage swing can be alleviated.

[0049] Although in the memory system 100, the second high voltage VH2 and the reference voltage VREF are generated by the host circuit 120, the present disclosure is not limited thereto. In some other embodiments, the memory circuit 110 can generate the second high voltage VH2 and the reference voltage VREF, and can transmit the second high voltage VH2 and the reference voltage VREF to the host circuit 120.

[0050] Figure 8 FIG. shows a memory system 200 according to another embodiment of the present disclosure. The memory system 200 and the memory system 100 have a similar structure and can operate according to similar principles. However, the memory circuit 210 can internally generate the second high voltage VH2 and the reference voltage VREF according to the first high voltage VH1, and transmit the second high voltage VH2 and the reference voltage VREF to the host circuit 220.

[0051] As Figure 8As shown, the memory circuit 210 may further include a switched-capacitor voltage regulator 217 to generate a second high voltage VH2 according to a first high voltage VH1 provided externally. In some embodiments, the memory array 214 may be composed of a plurality of DRAM cells MC1 and is fabricated using a process capable of forming high-quality and high-density capacitors required for the DRAM cells MC1. In this case, the switched-capacitor voltage regulator 217 can be fabricated using the same process as that used for forming the DRAM cells MC1, so that the switched-capacitor voltage regulator 217 can have better power efficiency due to these higher-quality capacitors. Furthermore, a voltage divider 218 can be used to generate a reference voltage VREF according to the second high voltage VH2. That is, the voltage terminals TH2A and TREFA of the first interface 212 can transmit the second high voltage VH2 and the reference voltage VREF to the host circuit 220.

[0052] In addition, the host circuit 220 can generate a first complementary data strobe signal SIGDQSAC, which is complementary to the first data strobe signal SIGDQSA. Since the voltage swing of the first data strobe signal SIGDQSA is very small, the complementary data strobe signals SIGDQSA and SIGDQSAC can be sensed as a differential pair, thereby increasing the overall voltage swing that can be sensed by the memory circuit 210. In some embodiments, an input strobe comparator of the memory circuit 210 can compare the first data strobe signal SIGDQSA and the first complementary data strobe signal SIGDQSAC to obtain a latch signal to latch and sample the first data signals SIGDQA0 to SIGDQA(N - 1), which is different from Figure 4 And Figure 7 the method of comparing the first data strobe signal SIGDQSA with the reference voltage VREF as shown. Similarly, when transmitting the second data signals SIGDQB0 to SIGDQB(N - 1), the memory circuit 210 can also generate and transmit a second data strobe signal SIGDQSB and a second complementary data strobe signal SIGDQSBC, thus helping the host circuit 220 to correspondingly derive a latch signal for latching and sampling the second data signals SIGDQB0 to SIGDQB(N - 1).

[0053] As Figure 8As shown, the first interface 212 of the memory circuit 210 may further include a first complementary data strobe terminal TDQSCA, and the second interface 222 of the host circuit 220 may further include a second complementary data strobe terminal TDQSCB, which is coupled to the first complementary data strobe terminal TDQSCA through an interconnect structure CTSC. In this configuration, the first complementary data strobe terminal TDQSCA may receive the first complementary data strobe signal SIGDQSAC and transmit the second complementary data strobe signal SIGDQSBC. Furthermore, the second complementary data strobe terminal TDQSCB may transmit the first complementary data strobe signal SIGDQSAC and receive the second complementary data strobe signal SIGDQSBC.

[0054] In addition, in some embodiments, data masking may be employed during a burst read operation or a burst write operation because burst read and burst write operations may have requirements for a fixed data length and may need to add redundant bits to meet such requirements. Therefore, data masking can be used to indicate valid bits so that the receiver can ignore the redundant bits.

[0055] As Figure 8 shown, the first interface 212 of the memory circuit 210 may further include a voltage terminal TDMA, and the second interface 222 of the host circuit 220 may further include a voltage terminal TDMB, which is coupled to the voltage terminal TDMA through an interconnect structure CTM. The host circuit 220 may generate a first data mask signal SIGDMA and transmit the first data mask signal SIGDMA through the voltage terminal TDMB, and the voltage terminal TDMA may receive the first data mask signal SIGDMA. In this case, when reading the first data signals SIGDQA0 to SIGDQA(N - 1), the memory circuit 210 may obtain valid bits from the bits of the first data signals SIGDQA0 to SIGDQA(N - 1) according to the first data mask signal SIGDMA. Similarly, the memory circuit 210 may also generate and transmit a second data mask signal SIGDMB through the voltage terminal TDMA to indicate the valid bits in the second data signals SIGDQB0 to SIGDQB(N - 1).

[0056] In summary, the interfaces of the memory system and the memory circuit provided by the embodiments of the present disclosure can operate with low voltage swing signals; thus, it is possible to significantly reduce the power consumption associated with controlling an external memory and can alleviate related EMI problems. In addition, since the host circuit and the memory circuit can be fabricated in different dies according to different processes, the yield of the memory system can also be improved.

[0057] Although the present disclosure has described the disclosure and its advantages in detail, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of the present disclosure as defined by the appended patent claims. For example, many of the processes described above can be implemented in different ways and replaced by other processes, or combinations thereof.

[0058] In addition, the scope of the present application is not limited to the specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. As can be easily understood and applied by those of ordinary skill in the art, processes, machines, manufactures, compositions of matter, means, methods, or steps that currently exist or will be developed in the future and perform substantially the same functions or achieve substantially the same results also fall within the scope of protection of the appended patent claims.

[0059]

Symbol Description

[0060] 100, 200: Memory system

[0061] 110, 210: Memory circuit

[0062] 120, 220: Host circuit

[0063] 112, 212: First interface

[0064] 114, 214: Memory array

[0065] 116, 216: Oscillator

[0066] MC1: Memory cell

[0067] 122, 222: Second interface

[0068] VH1: First high voltage

[0069] VL: Low voltage

[0070] TCEA: First chip enable

[0071] TDQA0 to TDQA(N - 1): First data terminal

[0072] TDQSA: First data strobe

[0073] TH2A, TREFA, TLA, TH2B, TREFB, TLB: Voltage terminal

[0074] TCEB: Second chip enable

[0075] TDQB0 to TDQB(N - 1): Second data terminal

[0076] TDQSB: Second data strobe

[0077] CTE, CTQ0 to CTQ(N-1), CTS, CTH2, CTR, CTL: Interconnection structure

[0078] SIGCE: Chip enable signal

[0079] SIGDQA0 to SIGDQA(N-1): First data signal

[0080] SIGDQSA: First data strobe signal

[0081] VH2: Second high voltage

[0082] VREF: Reference voltage

[0083] EA1, EA2, EA3, EB1, EB2, EB3: Signal edges

[0084] REA1, REB1: Rising edges

[0085] FEA1, FEB1: Falling edges

[0086] PW1: Instruction phase

[0087] PW2: Data phase

[0088] SIGL1, SIGL2: Latch signals

[0089] T1: First time interval

[0090] LCA: Logic circuit

[0091] BSO: Output strobe buffer

[0092] BDO0 to BDO(N-1): Output data buffer

[0093] CPS: Input strobe comparator

[0094] CP0 to CP(N-1): Input data comparator

[0095] DU1, DU2: Delay units

[0096] SIGCP: Comparison signal

[0097] SIGDQB0 to SIGDQB(N-1): Second data signal

[0098] SIGDQSB: Second data strobe signal

[0099] T2: Second time interval

[0100] 217: Switching capacitor voltage regulator

[0101] 218: Voltage divider

[0102] TDMA, TDMB: Voltage terminal

[0103] TDQSCA: First complementary data strobe terminal

[0104] TDQSCB: Second complementary data strobe terminal

[0105] SIGDMA: First data mask signal

[0106] SIGDMB: Second data mask signal

[0107] SIGDQSAC: First complementary data strobe signal

[0108] SIGDQSBC: Second complementary data strobe signal

Claims

1. An interface of a memory circuit, comprising: A chip enable terminal for receiving a chip enable signal that varies between a first high voltage and a low voltage and for enabling the memory circuit; At least one data terminal for receiving at least one first data signal that varies between a second high voltage and the low voltage; and A data strobe terminal for receiving a first data strobe signal that periodically varies between the second high voltage and the low voltage; Among them, The first data strobe signal is synchronized with the at least one first data signal, the first data strobe signal is configured to latch and sample the at least one first data signal, and the first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

2. The interface according to claim 1, wherein when the memory circuit operates in an instruction phase, a data rate of the at least one first data signal is a single data rate (SDR) to transmit a single data per clock cycle of the first data strobe signal.

3. The interface according to claim 2, wherein the at least one first data signal corresponds to instruction and address information, and in the instruction phase, the instruction and address information is transmitted to the at least one data terminal in a first predetermined number of clock cycles of the first data strobe signal.

4. The interface according to claim 1, wherein when the memory circuit operates in a data phase of a write operation, a data rate of the at least one first data signal is a double data rate (DDR) to transmit two data per clock cycle of the first data strobe signal.

5. The interface according to claim 1, wherein the at least one data terminal is further configured to transmit at least one second data signal that varies between the second high voltage and the low voltage, and the data strobe terminal is further configured to transmit a second data strobe signal that periodically varies between the second high voltage and the low voltage, and wherein the second data strobe signal is synchronized with the at least one second data signal.

6. The interface according to claim 5, wherein when the memory circuit operates in a data phase of a read operation, a data rate of the at least one second data signal is a double data rate (DDR) to transmit two data per clock cycle of the second data strobe signal.

7. The interface according to claim 5, wherein a signal edge of the first data strobe signal leads a signal edge of the at least one first data signal by a first time interval, and a signal edge of the second data strobe signal leads a signal edge of the at least one second data signal by a second time interval.

8. The interface according to claim 7, wherein a latch signal is derived from the first data strobe signal for sampling the at least one first data signal, and a window interval between a signal edge of the latch signal and a rising edge and a falling edge of the at least one first data signal is aligned.

9. The interface according to claim 5, wherein in an instruction phase, when the at least one first data signal corresponds to a read instruction and a read address, the at least one data terminal is further configured to transmit the at least one second data signal, the at least one second data signal corresponding to a read data read by the memory circuit in a data phase after the instruction phase, and the data strobe terminal is configured to transmit the second data strobe signal in the data phase.

10. The interface according to claim 5, wherein: the memory circuit further includes an oscillator for generating the second data strobe signal.

11. The interface according to claim 5, wherein in an instruction phase, when the at least one first data signal corresponds to a write instruction and a write address, the at least one data terminal is further configured to receive the at least one first data signal, the at least one first data signal corresponding to a write data to be written into the memory circuit in a data phase after the instruction phase, and the data strobe terminal is configured to receive the first data strobe signal in the data phase.

12. The interface according to claim 1, wherein: the memory circuit is further configured to provide the second high voltage and a reference voltage; a difference between the second high voltage and the low voltage is twice a difference between the reference voltage and the low voltage; and a bit value of the at least one first data signal is obtained by comparing a voltage of the at least one first data signal with the reference voltage.

13. The interface according to claim 12, wherein: the memory circuit further includes a plurality of dynamic random access memory (DRAM) cells and a switched capacitor voltage regulator for generating the second high voltage based on the first high voltage.

14. The interface according to claim 1, wherein: the memory circuit is enabled when the chip enable signal transitions from the first high voltage to the low voltage.

15. A memory system, comprising: a memory circuit including a first interface, wherein the first interface includes: a first chip enable terminal for receiving a chip enable signal that varies between a first high voltage and a low voltage; At least one first data terminal for receiving at least one first data signal that varies between a second high voltage and the low voltage; and a first data strobe terminal for receiving a first data strobe signal that periodically varies between the second high voltage and the low voltage, and the first data strobe signal is configured to latch and sample the at least one first data signal; and a host circuit including a second interface, wherein the second interface includes: a second chip enable terminal coupled to the first chip enable terminal and configured to transmit the chip enable signal for enabling the memory circuit; at least one second data terminal coupled to the at least one first data terminal and configured to transmit the at least one first data signal; and a second data strobe terminal coupled to the first data strobe terminal and configured to transmit the first data strobe signal synchronized with the at least one first data signal; wherein the first high voltage is higher than the second high voltage, and the second high voltage is higher than the low voltage.

16. The memory system according to claim 15, further comprising: A first interconnection structure, coupled between the first chip enable terminal and the second chip enable terminal, for transmitting the chip enable signal; At least one second interconnection structure, coupled between the at least one first data terminal and the at least one second data terminal, for transmitting the at least one first data signal; and A third interconnection structure, coupled between the first data strobe terminal and the second data strobe terminal, for transmitting the first data strobe signal.

17. The memory system according to claim 16, wherein the at least one first data terminal is further configured to transmit at least one second data signal varying between the second high voltage and the low voltage to the at least one second data terminal through the at least one second interconnection structure, and the first data strobe terminal is further configured to transmit a second data strobe signal periodically varying between the second high voltage and the low voltage to the second data strobe terminal through the third interconnection structure, and wherein the second data strobe signal is synchronized with the at least one second data signal.

18. The memory system according to claim 17, wherein: The memory circuit includes an oscillator for generating the second data strobe signal.

19. The memory system according to claim 17, wherein: The first interface further includes: A first voltage terminal for outputting / inputting the second high voltage; and A second voltage terminal for outputting / inputting a reference voltage, a difference between the second high voltage and the low voltage is twice a difference between the reference voltage and the low voltage, and a bit value of the at least one first data signal is obtained by comparing a voltage of the at least one first data signal with a voltage of the reference voltage; and The second interface further includes: A third voltage terminal for inputting / outputting the second high voltage; and A fourth voltage terminal for inputting / outputting the reference voltage; and A bit value of the at least one second data signal is obtained by comparing a voltage of the at least one second data signal with a voltage of the reference voltage.

20. The memory system according to claim 19, further including: A fourth interconnection structure, coupled between the first voltage terminal and the third voltage terminal, for transmitting the second high voltage; and A fifth interconnection structure, coupled between the second voltage terminal and the fourth voltage terminal, for transmitting the reference voltage.

21. The memory system according to claim 20, wherein: The first interface further includes a fifth voltage terminal for receiving a data mask signal; The second interface further includes a sixth voltage terminal for transmitting the data mask signal; And The memory circuit is further configured to obtain valid bits from the at least one first data signal according to the data mask signal when reading the at least one first data signal.

22. The memory system according to claim 21, further including: A sixth interconnection structure, coupled between the fifth voltage terminal and the sixth voltage terminal, for transmitting the data mask signal.

23. The memory system according to claim 15, wherein: The memory circuit further includes a plurality of dynamic random access memory (DRAM) cells and a switched-capacitor voltage regulator for generating the second high voltage according to the first high voltage.

24. The memory system as claimed in claim 15, wherein the first high voltage is higher than 0.8V and the second high voltage is lower than 0.6V.

25. The memory system as claimed in claim 15, wherein the first high voltage is 1.8V and the second high voltage is 0.3V.

26. The memory system as claimed in claim 15, wherein the memory circuit comprises a plurality of dynamic random access memory (DRAM) cells or a plurality of static random access memory (SRAM) cells.

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