Memory detection method, detection system, readable medium and electronic device

Abstract

The present disclosure provides a memory detection method, detection system, computer-readable medium and electronic device, the detection method comprising: writing a first voltage into a memory cell connected to a target word line, and writing a second voltage into a memory cell connected to at least one other adjacent word line; or, writing a second voltage into a memory cell connected to a target word line, and writing a first voltage into a memory cell connected to at least one other adjacent word line; the first voltage is greater than the second voltage; repeatedly writing the first voltage or the second voltage into other word lines; reading the memory cells connected to the target word line, and judging whether the reading result of each memory cell is equal to the first voltage or the second voltage written therein; if the reading result of the memory cell is not equal to the first voltage or the second voltage written therein, judging that the memory cell is leaking. The chips with potential double-bit failure can be screened out in advance.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a memory detection method, a memory detection system, a computer-readable medium and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) includes a plurality of memory cells for storing data. Each memory cell may include a transistor and a capacitor. The transistor is used as a gate for the flow of data to and from the memory cell. The capacitor is used to store data in the form of electric charge.

[0003] Because the structure of DRAM is too delicate and the mass production process is complicated and cumbersome, in the capacitor process of DRAM, the capacitor columns that form the capacitor are prone to tilt against each other, causing adjacent capacitor units to easily malfunction.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a memory detection method, a memory detection system, a computer-readable medium and an electronic device, which can screen out chips with potential double-bit failures in advance.

[0006] According to one aspect of an embodiment of the present disclosure, for testing a memory to be tested, the detection method includes:

[0007] Writing a first voltage into a memory cell connected to a target word line, and writing a second voltage into a memory cell connected to at least one other adjacent word line; or writing a second voltage into a memory cell connected to a target word line, and writing a first voltage into a memory cell connected to at least one other adjacent word line; the first voltage is greater than the second voltage;

[0008] repeatedly writing the first voltage or the second voltage to the other word lines;

[0009] Reading the storage cells connected to the target word line, and determining whether the reading result of each storage cell is equal to the first voltage or the second voltage written therein;

[0010] If the reading result of the memory cell is not equal to the first voltage or the second voltage written therein, it is determined that the memory cell is leaking.

[0011] In an exemplary embodiment of the present disclosure, writing a first voltage into the storage unit includes:

[0012] Controlling a target charge pump connected to a sense amplifier to turn on to generate a first voltage, and controlling a target switch element connected to the first voltage and the sense amplifier to turn on to input the first voltage to the sense amplifier;

[0013] The first voltage is written into the memory cell through the sense amplifier.

[0014] In an exemplary embodiment of the present disclosure, writing a second voltage into the storage unit includes:

[0015] Controlling a target charge pump connected to a sense amplifier to turn on to generate a second voltage, and controlling a target switch element connected to the second voltage and the sense amplifier to turn on to input the second voltage to the sense amplifier;

[0016] The second voltage is written into the memory cell through the sense amplifier.

[0017] In an exemplary embodiment of the present disclosure, the first voltage is higher than a power supply voltage of the memory to be detected.

[0018] In an exemplary embodiment of the present disclosure, the second voltage is zero voltage or negative voltage.

[0019] In an exemplary embodiment of the present disclosure, a first voltage is written into a memory cell connected to a target word line, and a second voltage is written into a memory cell connected to 1 to 10 other adjacent word lines; or, a second voltage is written into a memory cell connected to a target word line, and a first voltage is written into a memory cell connected to 1 to 10 other adjacent word lines.

[0020] In an exemplary embodiment of the present disclosure, the detection method further includes:

[0021] The plurality of word lines are successively set as the target word lines for testing.

[0022] In an exemplary embodiment of the present disclosure, the first voltage or the second voltage is repeatedly written to the other word lines in a strobe mode.

[0023] In an exemplary embodiment of the present disclosure, writing a first voltage or a second voltage into a memory cell connected to a target word line includes:

[0024] A target word line is turned on, the first voltage or the second voltage is written into a preset number of consecutive memory cells connected to the target word line, and the target word line is turned off.

[0025] In an exemplary embodiment of the present disclosure, the preset number is equal to the burst length of the memory array of the memory; or, the preset number is equal to the number of all memory cells connected to the word line; and writing the first voltage or the second voltage into the memory cell connected to a target word line includes:

[0026] After the target word line is turned off, the other word lines adjacent to the target word line are turned on to write the first voltage or the second voltage into a preset number of consecutive memory cells connected to a next word line.

[0027] In an exemplary embodiment of the present disclosure, the preset number is equal to the burst length of the memory array of the memory; and the step of writing the first voltage or the second voltage into a memory cell connected to a target word line includes:

[0028] After closing the target word line, opening the target word line to write the first voltage or the second voltage into a preset number of consecutive memory cells connected to the target word line and not subjected to a write operation, and closing the target word line;

[0029] The above steps are repeated until all the memory cells connected to the target word line are written with the first voltage or the second voltage.

[0030] In an exemplary embodiment of the present disclosure, reading the memory cell connected to the target word line includes:

[0031] The target word line is turned on to read a preset number of continuous storage cells connected to the target word line; and the target word line is turned off, the preset number being equal to a burst length of a storage array of the memory.

[0032] In an exemplary embodiment of the present disclosure, reading the storage unit connected to the target word line further includes:

[0033] After closing the target word line, opening the target word line to read the preset number of consecutive memory cells connected to the target word line and not read;

[0034] The above steps are repeated until all the memory cells connected to the target word line are read.

[0035] According to another aspect of the embodiments of the present disclosure, a memory detection system is provided for testing a memory to be tested, the detection system comprising:

[0036] A data writing module is configured to write a first voltage into a memory cell connected to a target word line, and write a second voltage into a memory cell connected to at least one other adjacent word line; or write a second voltage into a memory cell connected to a target word line, and write a first voltage into a memory cell connected to at least one other adjacent word line; the first voltage is greater than the second voltage;

[0037] A word line switch module, configured to repeatedly write the first voltage or the second voltage to the other word lines;

[0038] a data reading module, configured to read the storage unit connected to the target word line;

[0039] The data judgment module is configured to judge whether the reading result of each storage unit is equal to the first voltage or the second voltage written thereto; if the reading result of the storage unit is not equal to the first voltage or the second voltage written thereto, the storage unit is judged to be leaking.

[0040] According to another aspect of the embodiments of the present disclosure, a computer-readable medium is provided, on which a computer program is stored. When the program is executed by a processor, the detection method as described in the first aspect of the above embodiments is implemented.

[0041] According to another aspect of the embodiments of the present disclosure, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the detection method as described in the above embodiments.

[0042] The memory detection method provided by the present disclosure is implemented by writing a first voltage into a memory cell connected to a target word line, and writing a second voltage into a memory cell connected to at least one other adjacent word line; or, writing a second voltage into a memory cell connected to a target word line, and writing a first voltage into a memory cell connected to at least one other adjacent word line, and making the first voltage greater than the second voltage; then repeatedly writing the first voltage or the second voltage into other word lines; then reading the memory cells connected to the target word line, and judging whether the reading result of each memory cell is equal to the first voltage or the second voltage written therein; if the reading result of the memory cell is not equal to the first voltage or the second voltage written therein, judging that the memory cell is leaking; the chips with potential double-bit failures are screened out in advance, and the detection method is applied to the pre-burn-in engineering mass production process, so as to improve the detection capability of partial double-bit defects of the memory array, and help improve product reliability and yield.

[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings herein are incorporated into and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0045] Figure 1 A schematic diagram of a storage array of a memory provided by the present disclosure;

[0046] Figure 2 A schematic diagram of the position relationship between word lines and bits in a memory array provided by the present disclosure;

[0047] Figure 3 A schematic diagram of a double bit failure in a storage array provided by the present disclosure;

[0048] Figure 4 A schematic diagram of a double bit failure in a storage array provided by the present disclosure;

[0049] Figure 5 A flowchart of a memory detection method provided by an embodiment of the present disclosure;

[0050] Figure 6 A schematic diagram of the failure of excitation "1" provided for an embodiment of the present disclosure;

[0051] Figure 7 A schematic diagram of the failure of the excitation "0" provided for an embodiment of the present disclosure;

[0052] Figure 8 A schematic diagram of a reading circuit of a storage unit provided in accordance with an embodiment of the present disclosure;

[0053] Fig. 9 An embodiment of the present disclosure provides Figure 4 The circuit shown is a schematic diagram of the process of reading the state of the storage unit;

[0054] Fig.10 A schematic diagram of a process for reading a target word line storage cell state provided by an embodiment of the present disclosure;

[0055] Fig.11 A schematic diagram of a process for reading states of other word line storage cells provided by an embodiment of the present disclosure;

[0056] Fig.12 A schematic diagram of a memory detection system provided by an embodiment of the present disclosure;

[0057] Fig.13 A schematic diagram of the structure of a computer system suitable for implementing an electronic device of an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0058] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present invention will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0059] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present invention. However, those skilled in the art will appreciate that the technical solution of the present invention can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring various aspects of the present invention.

[0060] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0061] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0062] like Figure 1 As shown, the memory includes multiple memory cells Cell, multiple independent bit lines BL and multiple independent word lines WL, each bit line BL connects multiple memory cells Cell, each word line WL connects multiple memory cells Cell, and each memory cell Cell is connected to a corresponding bit line BL and a word line WL.

[0063] like Figure 1 and Figure 2As shown in the figure, there are seven types of positional relationships between word lines WL and bits. Dual bits refer to Cell to Cell (capacitor to capacitor), i.e., two storage cells, where coaxial WL dual bits refer to one word line WL controlling two storage cells, i.e., the RDB type marked in the figure; except for the RDB type, all others are heteroaxial WL dual bits, including HDB type, ICDB type, CDB type, VDB type, GDB type, and DDB type.

[0064] like Figure 3 and Figure 4 As shown, in the DRAM capacitor process, the capacitor columns tend to tilt relative to each other ( Figure 3 The area with the explosion pattern is shown in the figure. Figure 4 The present invention aims to provide a detection method for detecting HDB type and ICDB type double-bit failures in a memory, so as to solve the product yield loss caused by capacitor column defects.

[0065] In view of the above technical problems, the embodiments of the present disclosure first provide a method for detecting a memory, such as Figure 5 As shown, the detection method includes:

[0066] Step S100, writing a first voltage into a memory cell connected to a target word line, and writing a second voltage into a memory cell connected to at least one other adjacent word line; or, writing a second voltage into a memory cell connected to a target word line, and writing a first voltage into a memory cell connected to at least one other adjacent word line; the first voltage is greater than the second voltage;

[0067] Step S200, repeatedly writing the first voltage or the second voltage to other word lines;

[0068] Step S300, reading the memory cells connected to the target word line, and determining whether the read result of each memory cell is equal to the first voltage or the second voltage written therein;

[0069] Step S400: If the read result of the memory cell is not equal to the first voltage or the second voltage written therein, it is determined that the memory cell is leaking.

[0070] The memory detection method provided by the present disclosure is implemented by writing a first voltage into a memory cell connected to a target word line, and writing a second voltage into a memory cell connected to at least one other adjacent word line; or, writing a second voltage into a memory cell connected to a target word line, and writing a first voltage into a memory cell connected to at least one other adjacent word line, and making the first voltage greater than the second voltage; then repeatedly writing the first voltage or the second voltage into other word lines; then reading the memory cells connected to the target word line, and judging whether the reading result of each memory cell is equal to the first voltage or the second voltage written therein; if the reading result of the memory cell is not equal to the first voltage or the second voltage written therein, judging that the memory cell is leaking; the chips with potential double-bit failures are screened out in advance, and the detection method is applied to the pre-burn-in engineering mass production process, so as to improve the detection capability of partial double-bit defects of the memory array, and help improve product reliability and yield.

[0071] Specifically, the present disclosure may implement excitation failure in two ways: excitation "1" failure or excitation "0" failure.

[0072] In one embodiment of the present disclosure, the method of excitation "1" failure is adopted, such as Figure 6 As shown, a first voltage is written into a memory cell connected to a target word line, and a second voltage is written into a memory cell connected to at least one other adjacent word line, the first voltage corresponds to data "1", and the second voltage corresponds to data "0".

[0073] In step S100, data "1" is written into all memory cells connected to the target word line, and data "0" is written into all other adjacent word lines. The number of other word lines may be 1 to 10. Figure 6 As shown, the number of other word lines can be 3. After the target word line is detected, the next target word line is detected, and the next target word line is the Yth column, Y=X+K, X is the Xth column of the current target word line, and K is the number of columns of other word lines in the current detection process. Since different voltages are written to adjacent storage cells, there is a voltage difference between the capacitors. If there is capacitor leakage between the two storage cells, the data stored in the storage cells will change.

[0074] In order to improve the detection efficiency and make the possible capacitor leakage more obvious, the first voltage is set to be higher than the power supply voltage (VDD) of the memory array of the memory. For example, if the power supply voltage of the memory array of the memory is equal to 1.0V, the first voltage can be set to 1.2V. The difference between the first voltage and the power supply voltage can be set by those skilled in the art according to the actual operating parameters of the memory array to be tested, and the present disclosure does not limit it.

[0075] For example, the method of generating the first voltage may be, for example, through a charge pump or a short circuit. For example, before writing the first voltage to the memory cell connected to the target word line in the memory array, the target charge pump connected to the sense amplifier is controlled to be turned on to generate the first voltage, the target switch element connected to the first voltage and the sense amplifier is controlled to be turned on, the first voltage is input to the sense amplifier, and then written into the memory cell through the sense amplifier, and the upper plate voltage of the memory cell increases by △V PLT After that, the voltage of the lower plate of the storage unit also increases △V PLT , so that the plate voltage under the storage unit is VDD + △V PLT There are many methods for writing into a memory cell through a sense amplifier, and the present disclosure does not impose any particular limitation thereto.

[0076] For example, the second voltage (VSS) may be a zero voltage or a negative voltage, further increasing the voltage difference between the two bits of the different-axis word lines.

[0077] The first voltage is pulled to a higher potential VDD+△V through a charge pump or a short circuit. PLT , the memory cell corresponding to the sense amplifier connected to the target word line writes data "1", and the memory cell corresponding to the even-bit sense amplifier connected to other word lines writes data "0". The memory cell corresponding to the sense amplifier connected to the target word line has a higher voltage difference VDD+△V than the memory cell corresponding to the sense amplifier connected to other word lines. PLT -Vss; after the first voltage or the second voltage is written to the storage unit, capacitor leakage begins to occur due to the large voltage difference between adjacent storage units.

[0078] Next, in step S200, the second voltage is repeatedly written to other word lines. The second voltage can be repeatedly written to other word lines in a stroboscopic (Multi WL) mode to stimulate capacitor leakage. The number of repetitions can be 1-200 times. The more times the rewriting is repeated, the more the capacitor leakage can be stimulated; however, the more times the test takes longer; the present application adopts a rewriting number of 1-200 times, which shortens the time required for the test as much as possible while ensuring the stimulation of capacitor leakage. Of course, the number of rewriting can also be greater than 200 times, and the present disclosure does not limit this.

[0079] Next, in step S300, the memory cells connected to the target word line are read, and it is determined whether the read result of each memory cell is equal to the first voltage written therein. By reading the state of the memory cell, it is possible to determine whether there is a capacitance leakage between the two bits of the different-axis word lines by determining whether the state of the memory cell changes.

[0080] For example, the sense amplifier connected to the bit line is controlled to be turned on to read the memory cell connected to the target word line, and the memory cell written with "1" is read to determine whether it is still "1". If leakage occurs, the amount of charge in the capacitor of the memory cell will decrease and will not be "1", such as Figure 6 As shown, it will become "0".

[0081] For example, Figure 8 As shown, the memory cell 510 includes M1 and a capacitor C. M1 can be, for example, an N-type transistor, with a source connected to the capacitor C, a drain connected to a bit line BL, and a gate connected to a word line WL. A column selection unit, a balance unit, and a sense amplifier are sequentially arranged on the bit line BL.

[0082] The column selection unit 520 includes a second switch element M2 . The second switch element M2 is an N-type transistor, with a source connected to a local input / output signal line LIO (Local Input / Output), a drain connected to a bit line BL, and a gate connected to a column selection signal line YS (Y Select).

[0083] The balancing unit 530 includes a third switch element M3, a fourth switch element M4 and a fifth switch element M5. The third switch element M3, the fourth switch element M4 and the fifth switch element M5 are all N-type transistors. The gates of the third switch element M3, the fourth switch element M4 and the fifth switch element M5 are all connected to a voltage equalizer VEQ (Voltage Equalizer). The source of the third switch element M3 and the drain of the fourth switch element M4 are both connected to the bit line precharge voltage V BLP (Voltage of Bit Line Precharge), the drain of the third switch element M3 is connected to the bit line BL, and the source of the fourth switch element M4 is connected to the complementary bit line / BL.

[0084] The sense amplifier (SA) 510 is a differential amplifier, and its two input terminals are respectively connected to the bit line BL and the complementary bit line / BL, and are used to amplify the voltage difference between the bit line BL and the complementary bit line / BL. The sense amplifier includes a sixth switch element M6, a seventh switch element M7, an eighth switch element M8, and a ninth switch element M9. Among them, the sixth switch element M6 and the seventh switch element M7 are both N-type transistors, and the eighth switch element M8 and the ninth switch element M9 are both P-type transistors. One end of the sixth switch element M6 is connected to the bit line BL through the first node N1, and the other end is connected to the low potential node NCS, and the low potential node NCS is connected to the low voltage Vss, and the control end of the sixth switch element M6 is connected to the complementary bit line / BL. One end of the seventh switch element M7 is connected to the complementary bit line / BL through the second node N2, and the other end is connected to the low potential node NCS, and the control end of the seventh switch element M7 is connected to the bit line BL. One end of the eighth switch element M8 is connected to the bit line BL through the first node N1, and the other end is connected to the high potential node PCS, the high potential node PCS is connected to the high voltage Vary, and the control end of the eighth switch element M8 is connected to the complementary bit line / BL. One end of the ninth switch element M9 is connected to the complementary bit line / BL through the second node N2, and the other end is connected to the high potential node PCS, and the control end of the ninth switch element M9 is connected to the bit line BL.

[0085] Before reading, the voltage equalizer VEQ turns on the three switch elements in the balance unit, and the bit line BL and the complementary bit line / BL are equal to the bit line precharge voltage V BLP After the activation signal ACT arrives, the voltage equalizer VEQ is turned off, allowing a voltage difference to exist between the bit line BL and the complementary bit line / BL. Next, the control word line WL is turned on, and M1 in the memory cell is turned on.

[0086] like Fig. 9 As shown, after the sense amplifier pulls the voltage of the bit line BL to the high voltage Vary or the low voltage Vss, the column selection signal YS is used to control the column selection unit to turn on (YS ON), and the voltage of the bit line BL is read onto the local signal line LIO. If the potential of the bit line BL is the high voltage Vary, the read result is "1"; if the potential of the bit line BL is the low voltage Vss, the read result is "0". After turning off the column selection signal YS (YS OFF), the sense amplifier is controlled to enter the preparation stage (PRE) for the next read. The word line WL (WL OFF) and the sense amplifier (SA OFF) are turned off, and the voltage equalizer VEQ is controlled to turn on (VEQ ON), so that the bit line BL and the complementary bit line / BL are equal to the bit line precharge voltage V BLP , until the activation signal ACT is received again. This period of time is called the row precharge time t RP (Row Precharge Time).

[0087] If after turning on the word line WL and the sense amplifier corresponding to the target memory cell reads a target memory cell, it is found that the target memory cell written with data "1" is read as 0, it means that the target word line WL has leaked to the adjacent memory cell. At this time, it can be determined that the off-axis dual-bit capacitor leakage phenomenon exists.

[0088] For example, when there is no leakage between capacitors, Figure 8 As shown, when the capacitor C in the storage unit is written with the first voltage, there is no leakage between the capacitors, the word line WL is turned on, and the charge sharing stage is entered. The potential of the bit line BL is raised by the capacitor C, and the potential of the first node N1 is higher than the potential of the second node N2. After the control sense amplifier is turned on, the first node N1 controls the seventh switch element M7 to turn on, and the second node N2 controls the eighth switch element M8 to turn on. The opening degree of the seventh switch element M7 is greater than the opening degree of the sixth switch element M6, and the potential of the bit line BL and the complementary bit line / BL both drop to a certain extent. However, then, the second node N2 is first pulled to the low voltage Vss through the seventh switch element M7 with a larger opening degree, the eighth switch element M8 is turned on, and the sixth switch element M6 is turned off. The potential of the first node N1 quickly rises to the high voltage Vary, the ninth switch element M9 is turned off, the seventh switch element M7 is turned on, and the potential of the second node N2 is fixed to the low voltage Vss. So far, when the voltage of the bit line BL is read through the column selection signal YS, the high voltage Vary can be read, that is, the reading result is "1".

[0089] For example, in step S400, when there is leakage between capacitors, Figure 8 As shown, the leaked capacitor C shares the charge with the bit line BL, causing the potential of the bit line BL to drop, and the potential of the bit line BL is lower than the voltage V of the complementary bit line / BL. BLP After the control sense amplifier is turned on, the voltage of the first node N1 is less than the voltage of the second node N2, the opening degree of the sixth switch element M6 is greater than the opening degree of the seventh switch element M7, the voltage of the first node N1 reaches the low voltage Vss faster than the voltage of the second node N2, the ninth switch element M9 controlled by the first node N1 is turned on first, the voltage of the second node N2 is quickly pulled to the high voltage Vary, the eighth switch element M8 controlled by the second node N2 is turned off, and the voltage of the bit line BL is pulled to the low voltage Vss. Therefore, in this case, the voltage of the bit line BL read by the column selection signal YS is "0", that is, it is detected that the memory cell has a capacitor leakage phenomenon.

[0090] Among them, Fig.11As shown, when there is leakage between capacitors, the voltage of capacitor C of other word lines affected by leakage becomes relatively high, and the charge sharing of capacitor C to bit line BL is reduced, so that the potential drop △V of bit line BL is smaller than the potential drop △V of capacitor C without leakage.

[0091] In one embodiment of the present disclosure, a method of excitation "0" failure is adopted, such as Figure 7 As shown, a second voltage is written into a memory cell connected to a target word line, and a first voltage is written into a memory cell connected to at least one other adjacent word line, the first voltage corresponds to data "1", and the second voltage corresponds to data "0".

[0092] In step S100, data "0" is written into all memory cells connected to the target word line, and data "1" is written into all other adjacent word lines. The number of other word lines may be 1 to 10. Figure 7 As shown, the number of other word lines can be 3. After the target word line is detected, the next target word line is detected, and the next target word line is the Yth column, Y=X+K, X is the Xth column of the current target word line, and K is the number of columns of other word lines in the current detection process. Since two adjacent storage cells are written with different voltages, there is a voltage difference between the capacitors. If there is capacitor leakage between the two storage cells, the data stored in the storage cells will change.

[0093] In order to improve the detection efficiency and make the possible capacitor leakage more obvious, the first voltage is set to be higher than the power supply voltage (VDD) of the memory array of the memory. For example, if the power supply voltage of the memory array of the memory is equal to 1.0V, the first voltage can be set to 1.2V. The difference between the first voltage and the power supply voltage can be set by those skilled in the art according to the actual operating parameters of the memory array to be tested, and the present disclosure does not limit it.

[0094] For example, the method of generating the first voltage may be, for example, through a charge pump or a short circuit. For example, before writing the first voltage to the storage unit, the target charge pump connected to the sense amplifier is controlled to be turned on to generate the first voltage, the target switch element connected to the first voltage and the sense amplifier is controlled to be turned on, the first voltage is input to the sense amplifier, and then written into the storage unit through the sense amplifier, and the upper plate voltage of the storage unit increases by △V PLT After that, the voltage of the lower plate of the storage unit also increases △V PLT , so that the plate voltage under the storage unit is VDD + △V PLT There are many methods for writing into a memory cell through a sense amplifier, and the present disclosure does not impose any particular limitation thereto.

[0095] For example, the second voltage (VSS) may be a zero voltage or a negative voltage, further increasing the voltage difference between the two bits of the different-axis word lines.

[0096] The first voltage is pulled to a higher potential VDD+△V through a charge pump or a short circuit. PLT , the memory cells corresponding to the even-bit sense amplifiers connected to other word lines write data "1", and the memory cells corresponding to the sense amplifiers connected to the target word line write data "0". The memory cells corresponding to the sense amplifiers connected to other word lines have a higher voltage difference VDD+△V than the memory cells corresponding to the sense amplifiers connected to the target word line. PLT -Vss; after the first voltage or the second voltage is written to the storage unit, capacitor leakage begins to occur due to the large voltage difference between adjacent storage units.

[0097] Next, in step S200, the first voltage is repeatedly written to other word lines. The first voltage may be repeatedly written to other word lines in a strobe (Multi WL) mode to stimulate capacitor leakage.

[0098] Next, in step S300, the memory cells connected to the target word line are read, and it is determined whether the read result of each memory cell is equal to the second voltage written therein. By reading the state of the memory cell, it is possible to determine whether there is a capacitance leakage between the two bits of the different-axis word lines by determining whether the state of the memory cell changes.

[0099] For example, the sense amplifier connected to the bit line is controlled to turn on to read the memory cell connected to the target word line, and the memory cell written with "0" is read to determine whether it is still "0". If leakage occurs, the charge in the capacitor of the memory cell will not be "0", such as Figure 7 As shown, it will become "1".

[0100] like Figure 8 As shown, the memory unit 510 , the column selection unit 520 , the balancing unit 530 and the sense amplifier 540 have been discussed in detail in the above embodiments and will not be described again.

[0101] If after turning on the word line WL and the sense amplifier corresponding to the target memory cell reads a target memory cell, it is found that the target memory cell written with data "0" is read as 1, it means that the memory cell adjacent to the target word line WL has leaked to the target memory cell. At this time, it can be determined that the off-axis dual-bit capacitor leakage phenomenon exists.

[0102] For example, when there is no leakage between capacitors, Figure 8As shown, when the capacitor C in the storage unit is written with the second voltage, the opening degree of the sixth switch element M6 is greater than the opening degree of the seventh switch element M7, the voltage of the first node N1 reaches the low voltage Vss faster than the voltage of the second node N2, the ninth switch element M9 controlled by the first node N1 is turned on first, the voltage of the second node N2 is quickly pulled to the high voltage Vary, and the eighth switch element M8 controlled by the second node N2 is turned off. At this time, the first node N1 is connected to the low voltage Vss through the opened sixth switch element M6, that is, the voltage of the bit line BL is equal to the low voltage Vss, the seventh switch element M7 is turned off, and the second node N2 is connected to the high voltage Vary through the opened ninth switch element M9, that is, the voltage of the complementary bit line / BL is pulled to the high voltage Vary. At this point, the voltage difference ΔV caused by the leakage of the bit line BL to the capacitor C is amplified by the sense amplifier, the potential of the bit line BL is equal to the low voltage Vss, and the potential of the complementary bit line / BL is equal to the high voltage Vary. When the voltage of the bit line BL is read through the column selection signal YS, a low voltage Vss can be read, that is, the read result is "0", that is, there is no capacitance leakage phenomenon in the off-axis dual bit.

[0103] For example, in step S400, Figure 8 and Fig.10 As shown, when the capacitor C in the storage unit is written with the second voltage, the control word line WL is turned on, the M1 in the storage unit is turned on, and the capacitor C shares the charge with the bit line BL, causing the potential of the bit line BL to drop; the opening degree of the sixth switch element M6 is greater than the opening degree of the seventh switch element M7, and the voltage of the first node N1 reaches the bottom voltage Vss faster than the voltage of the second node N2, and the ninth switch element M9 controlled by the first node N1 is turned on first, and the voltage of the second node N2 is quickly pulled to the high voltage Vary, and the eighth switch element M8 controlled by the second node N2 is turned off. At this time, the first node N1 is connected to the low voltage Vss through the opened sixth switch element M6, that is, the voltage of the bit line BL is equal to the low voltage Vss, the seventh switch element M7 is turned off, and the second node N2 is connected to the high voltage Vary through the opened ninth switch element M9, that is, the voltage of the complementary bit line / BL is pulled to the high voltage Vary. When leakage occurs between capacitors, the capacitor C that is leaked shares the charge with the bit line BL. Due to the high voltage V DD is greater than the high voltage Vary, the voltage of the bit line BL is equal to the high voltage V DD, resulting in the voltage of the first node N1 gradually becoming greater than the second node N2, the opening degree of the sixth switch element M6 being less than the opening degree of the seventh switch element M7, the ninth switch element M9 controlled by the first node N1 being turned off, the seventh switch element M7 controlled by the first node N1 being turned on, and the voltage of the second node N2 reaching the bottom voltage Vss, that is, the voltage of the complementary bit line / BL is pulled to the bottom voltage Vss. So far, when the voltage of the bit line BL is read through the column selection signal YS, the high voltage Vary can be read, that is, the reading result is "1", that is, there is a capacitance leakage phenomenon in the off-axis dual bit.

[0104] Specifically, in the above two embodiments, when the memory array is tested, the order of writing data can be preset to write the first voltage or the second voltage to the memory cell.

[0105] By way of example, the data writing process may include: turning on a target word line, writing a first voltage and a second voltage into a preset number of consecutive memory cells connected to the target word line, and turning off the target word line.

[0106] The preset number is equal to the burst length (BL) of the memory array to be tested; or the preset number is equal to the number of all memory cells connected to the target word line. At this time, after closing the target word line, the next word line of the target word line can be opened to write the first voltage or the second voltage to the continuous preset number of memory cells connected to the next word line.

[0107] When the preset number is equal to the burst length of the memory array to be tested, the process of turning on the next word line of the target word line to write the first voltage or the second voltage to the continuous burst length memory cells connected to the next word line can be called X-Fast writing mode, that is, fast writing is achieved in the X direction.

[0108] When the preset number is equal to the number of all memory cells connected to the word line, after closing the target word line, the method of opening the next word line of the target word line to write the first voltage or the second voltage to a continuous preset number of memory cells connected to the next word line is called the Y-Page writing method, that is, realizing full-page writing in the Y direction.

[0109] The preset number is equal to the burst length of the memory array to be tested. After closing the target word line, the target word line can be opened to write the first voltage or the second voltage to the continuous burst length memory cells connected to the target word line that have not been written, and then close the target word line; repeat the above steps until all memory cells connected to the target word line are written with the first voltage or the second voltage. This writing method can be called a Y-Fast writing method, that is, fast writing is achieved in the Y direction.

[0110] Similarly, the reading process can also pre-set the reading order.

[0111] The reading process may include: turning on the target word line, reading a preset number of consecutive memory cells connected to the target word line; turning off the target word line, the preset number is equal to the burst length of the memory array of the memory. The burst length is the number of bit lines corresponding to the memory array that can be read simultaneously. For example, the burst length supported by DDR4 is 8 bits, and the maximum burst length supported by DDR5 is 16 bits.

[0112] After closing the target word line, the next word line of the target word line can be opened to read a preset number of continuous storage cells connected to the next word line. This reading method is called X-Fast reading method, which can achieve fast reading in the X direction.

[0113] In another embodiment, after the target word line is turned off, the target word line can be turned on to read a preset number of unread consecutive memory cells connected to the target word line; the above steps are repeated until all memory cells connected to the target word line are read. This reading method is called a Y-Fast reading method, which can achieve fast reading in the Y direction.

[0114] The embodiment of the present disclosure also provides a memory detection system, such as Fig.12 As shown, the detection system 1000 includes: a data writing module 1010, a word line switch module 1020, a data reading module 1030 and a data judgment module 1040. The data writing module 1010 is configured to write a first voltage into a storage cell connected to a target word line, and write a second voltage into a storage cell connected to at least one other adjacent word line; or, write a second voltage into a storage cell connected to a target word line, and write a first voltage into a storage cell connected to at least one other adjacent word line; the first voltage is greater than the second voltage; the word line switch module 1020 is configured to repeatedly write the first voltage or the second voltage into other word lines; the data reading module 1030 is configured to read the storage cell connected to the target word line; the data judgment module 1040 is configured to judge whether the reading result of each storage cell is equal to the first voltage or the second voltage written therein; if the reading result of the storage cell is not equal to the first voltage or the second voltage written therein, the storage cell is judged to be leaking. The detailed functions and principles of each module refer to the above discussion on the detection method.

[0115] The memory detection system provided by the present disclosure has a data writing module that writes a first voltage into a memory cell connected to a target word line and writes a second voltage into a memory cell connected to at least one other adjacent word line; or, writes a second voltage into a memory cell connected to a target word line and writes a first voltage into a memory cell connected to at least one other adjacent word line, and makes the first voltage greater than the second voltage; then the word line switch module repeatedly writes the first voltage or the second voltage into other word lines; then the data reading module reads the memory cells connected to the target word line and determines whether the reading result of each memory cell is equal to the first voltage or the second voltage written therein; if the reading result of the memory cell is not equal to the first voltage or the second voltage written therein, the data judgment module determines that the memory cell is leaking; the chips with potential double-bit failures are screened out in advance, and the detection method is applied to the pre-burn-in engineering mass production process, which can improve the detection capability of partial double-bit defects of the memory array, and help improve product reliability and yield.

[0116] Since the various functional modules of the memory detection system device of the example embodiment of the present disclosure correspond to the steps of the example embodiment of the memory detection method described above, for details not disclosed in the device embodiment of the present disclosure, please refer to the embodiment of the memory detection method described above in the present disclosure.

[0117] Reference below Fig.13 , which shows a schematic diagram of the structure of a computer system 1200 suitable for implementing an electronic device of an embodiment of the present disclosure. Fig.13 The computer system 1200 of the electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0118] like Fig.13 As shown, the computer system 1200 includes a central processing unit (CPU) 1201, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1202 or a program loaded from a storage part 1208 into a random access memory (RAM) 1203. Various programs and data required for system operation are also stored in the RAM 1203. The CPU 1201, the ROM 1202, and the RAM 1203 are connected to each other via a bus 1204. An input / output (I / O) interface 1205 is also connected to the bus 1204.

[0119] The following components are connected to the I / O interface 1205: an input section 1206 including a keyboard, a mouse, etc.; an output section 1207 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 1208 including a hard disk, etc.; and a communication section 1209 including a network interface card such as a LAN card, a modem, etc. The communication section 1209 performs communication processing via a network such as the Internet. A drive 1210 is also connected to the I / O interface 1205 as needed. A removable medium 1211, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1210 as needed, so that a computer program read therefrom is installed into the storage section 1208 as needed.

[0120] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication part 1209, and / or installed from a removable medium 1211. When the computer program is executed by a central processing unit (CPU) 1201, the above-mentioned functions defined in the system of the present application are executed.

[0121] It should be noted that the computer-readable medium shown in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0122] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0123] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, constitute limitations on the units themselves.

[0124] As another aspect, the present application also provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the detection method described in the above embodiment.

[0125] For example, the electronic device can implement Figure 5 As shown in: Step S100, write a first voltage into a memory cell connected to a target word line, and write a second voltage into a memory cell connected to at least one other adjacent word line; or, write a second voltage into a memory cell connected to a target word line, and write a first voltage into a memory cell connected to at least one other adjacent word line; the first voltage is greater than the second voltage; Step S200, repeatedly write the first voltage or the second voltage to other word lines; Step S300, read the memory cells connected to the target word line, and determine whether the read result of each memory cell is equal to the first voltage or the second voltage written thereto; Step S400, if the read result of the memory cell is not equal to the first voltage or the second voltage written thereto, determine that the memory cell is leaking.

[0126] For example, the electronic device can achieve Figure 5 The steps shown.

[0127] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0128] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a touch terminal, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0129] Those skilled in the art will readily appreciate other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present invention and include common knowledge or customary techniques in the art that are not disclosed by the present invention. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present invention are indicated by the following claims.

[0130] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A memory detection method for testing a memory to be tested, characterized in that: The detection method comprises: Writing a first voltage into a memory cell connected to a target word line, and writing a second voltage into a memory cell connected to at least one other adjacent word line; or writing a second voltage into a memory cell connected to a target word line, and writing a first voltage into a memory cell connected to at least one other adjacent word line; the first voltage is greater than the second voltage; Repeating writing the first voltage or the second voltage to the other word lines; Reading the storage cells connected to the target word line, and determining whether the reading result of each storage cell is equal to the first voltage or the second voltage written therein; If the reading result of the storage unit is not equal to the first voltage or the second voltage written therein, it is determined that the storage unit is leaking; Wherein, reading the storage unit connected to the target word line includes: The target word line is turned on to read a preset number of continuous storage cells connected to the target word line; and the target word line is turned off, the preset number being equal to a burst length of a storage array of the memory.

2. The detection method according to claim 1, characterized in that: Writing a first voltage into the storage unit includes: Controlling a target charge pump connected to a sense amplifier to turn on to generate a first voltage, and controlling a target switch element connected to the first voltage and the sense amplifier to turn on to input the first voltage to the sense amplifier; The first voltage is written into the memory cell through the sense amplifier.

3. The detection method according to claim 1, characterized in that: Writing a second voltage into the storage unit comprises: Controlling a target charge pump connected to a sense amplifier to turn on to generate a second voltage, and controlling a target switch element connected to the second voltage and the sense amplifier to turn on to input the second voltage to the sense amplifier; The second voltage is written into the memory cell through the sense amplifier.

4. The detection method according to claim 1, characterized in that: The first voltage is higher than the power supply voltage of the memory to be detected.

5. The detection method according to claim 1, characterized in that: The second voltage is zero voltage or negative voltage.

6. The detection method according to claim 1, characterized in that: A first voltage is written into a memory cell connected to a target word line, and a second voltage is written into a memory cell connected to 1 to 10 other adjacent word lines; or a second voltage is written into a memory cell connected to a target word line, and a first voltage is written into a memory cell connected to 1 to 10 other adjacent word lines.

7. The detection method according to claim 1, characterized in that: The detection method further comprises: The plurality of word lines are successively set as the target word lines for testing.

8. The detection method according to claim 1, characterized in that: The first voltage or the second voltage is repeatedly written to the other word lines in a strobe mode.

9. The detection method according to claim 1, characterized in that: Writing a first voltage or a second voltage into a memory cell connected to a target word line comprises: A target word line is turned on, the first voltage or the second voltage is written into a preset number of consecutive memory cells connected to the target word line, and the target word line is turned off.

10. The detection method according to claim 9, characterized in that: The preset number is equal to the burst length of the memory array of the memory; or, the preset number is equal to the number of all memory cells connected to the word line; The step of writing a first voltage or a second voltage into a memory cell connected to a target word line comprises: After the target word line is turned off, the other word lines adjacent to the target word line are turned on to write the first voltage or the second voltage into a preset number of consecutive memory cells connected to a next word line.

11. The detection method according to claim 9, characterized in that: The preset number is equal to the burst length of the memory array of the memory; and writing the first voltage or the second voltage into a memory cell connected to a target word line comprises: After closing the target word line, opening the target word line to write the first voltage or the second voltage into a preset number of consecutive memory cells connected to the target word line and not subjected to a write operation, and closing the target word line; The above steps are repeated until all the memory cells connected to the target word line are written with the first voltage or the second voltage.

12. The detection method according to claim 1, characterized in that: Reading the storage unit connected to the target word line also includes: After closing the target word line, opening the target word line to read the preset number of consecutive memory cells connected to the target word line and not read; The above steps are repeated until all the memory cells connected to the target word line are read.

13. A memory detection system for testing a memory to be tested, characterized in that: The detection system comprises: A data writing module is configured to write a first voltage into a memory cell connected to a target word line, and write a second voltage into a memory cell connected to at least one other adjacent word line; or write a second voltage into a memory cell connected to a target word line, and write a first voltage into a memory cell connected to at least one other adjacent word line; the first voltage is greater than the second voltage; A word line switch module, configured to repeatedly write the first voltage or the second voltage to the other word lines; A data reading module is configured to read the storage unit connected to the target word line; reading the storage unit connected to the target word line includes: turning on the target word line and reading a preset number of consecutive storage units connected to the target word line; turning off the target word line, the preset number being equal to the burst length of the storage array of the memory; The data judgment module is configured to judge whether the reading result of each storage unit is equal to the first voltage or the second voltage written thereto; if the reading result of the storage unit is not equal to the first voltage or the second voltage written thereto, the storage unit is judged to be leaking.

14. A computer readable medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the detection method according to any one of claims 1 to 12 is implemented.

15. An electronic device, characterized in that: include: one or more processors; A storage device, used to store one or more programs, when the one or more programs are executed by the one or more processors, enables the one or more processors to implement the detection method according to any one of claims 1-12.

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