Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a first region having a plurality of first fins arranged parallel to each other along a first direction; forming a plurality of dummy gate structures on the substrate, the dummy gate structures spanning the first fins along a second direction perpendicular to the second direction; forming a sacrificial layer on the first region, the sacrificial layer having a first opening, the first opening exposing the first fins located between adjacent dummy gate structures; forming first source / drain openings on both sides of the dummy gate structures and within the first fins exposed by the first opening; and forming first source / drain doped layers in and within the first source / drain openings. The sacrificial layer provides a barrier, resulting in a smaller volume difference between the various first source / drain doped layers formed in the first source / drain openings and within the first openings, thereby improving the performance of the finally formed semiconductor structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] MOS (Metal-Oxide-Semiconductor) transistors are among the most important components in modern integrated circuits. The basic structure of a MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, the gate structure comprising: a gate dielectric layer on the surface of the semiconductor substrate and a gate electrode layer on the surface of the gate dielectric layer; and source / drain doped regions located in the semiconductor substrate on both sides of the gate structure.

[0003] With the development of semiconductor technology, the traditional planar MOS transistor has become less able to control the channel current, resulting in severe leakage current. Fin field-effect transistors (Fin FETs) are a new type of multi-gate device. They generally include fins protruding from the surface of a semiconductor substrate, a gate structure covering part of the top surface and sidewalls of the fins, and source / drain doped regions located in the fins on both sides of the gate structure.

[0004] However, the performance of semiconductor devices composed of fin field-effect transistors in the existing technology still needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a method for forming a semiconductor structure, which can effectively improve the performance of the final semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a first region having a plurality of first fins arranged in parallel along a first direction; forming a plurality of dummy gate structures on the substrate, the dummy gate structures spanning the first fins along a second direction perpendicular to the second direction; forming a sacrificial layer on the first region, the sacrificial layer having a first opening, the first opening exposing the first fins located between adjacent dummy gate structures; forming first source / drain openings on both sides of the dummy gate structures and within the first fins exposed by the first opening; and forming a first source / drain doped layer within the first source / drain openings and the first openings.

[0007] Optionally, after forming the first source / drain doped layer, the method further includes: planarizing the top surface of the first source / drain doped layer.

[0008] Optionally, the first source / drain doped layer contains first source / drain ions, and the first source / drain doped layers are interconnected.

[0009] Optionally, the substrate further includes a second region, the first region and the second region are arranged along the first direction, the second region has a plurality of second fins arranged in parallel along the first direction, and the pseudo-gate structure also spans across the second fins along the second direction.

[0010] Optionally, in the process of forming the first source drain opening, the method further includes: forming a second source drain opening in the second fins on both sides of the pseudo-gate structure.

[0011] Optionally, the process of forming the first source / drain doped layer further includes: forming a second source / drain doped layer within the second source / drain opening.

[0012] Optionally, the second source / drain doped layer contains second source / drain ions, and each of the second source / drain doped layers is discrete from each other.

[0013] Optionally, the first source / drain ion is a P-type ion, and the P-type ion includes boron or indium.

[0014] Optionally, the second source / drain ion is an N-type ion, which includes phosphorus or arsenic.

[0015] Optionally, the method for forming the first source-drain opening includes: etching the first fin using the pseudo-gate structure and the sacrificial layer as a mask to form the first source-drain opening within the first fin.

[0016] Optionally, the method for forming the second source-drain opening includes: etching the second fin using the pseudo-gate structure as a mask to form the second source-drain opening within the second fin.

[0017] Optionally, the method for forming the first source / drain doped layer includes: forming a first epitaxial layer in the first source / drain opening using an epitaxial growth process; and during the epitaxial growth process, in-situ doping of the first source / drain ions into the first epitaxial layer using an in-situ doping process to form the first source / drain doped layer.

[0018] Optionally, the method for forming the second source / drain doped layer includes: forming a second epitaxial layer in the second source / drain opening using an epitaxial growth process; and, during the epitaxial growth process, incorporating the second source / drain ions into the second epitaxial layer using an in-situ doping process to form the second source / drain doped layer.

[0019] Optionally, the method for forming the sacrificial layer includes: forming an initial sacrificial layer on the first region, the initial sacrificial layer covering the first fin and the pseudo-gate structure located on the first region; forming a patterned layer on the initial sacrificial layer, the patterned layer exposing a portion of the top surface of the initial sacrificial layer; etching the initial sacrificial layer using the patterned layer as a mask to form the sacrificial layer; and removing the patterned layer after forming the sacrificial layer.

[0020] Optionally, the material of the initial sacrificial layer is different from the material of the first fin.

[0021] Optionally, the material of the initial sacrificial layer includes: hydrogen silsesquioxane.

[0022] Optionally, the process for planarizing the top surface of the first source / drain doped layer includes: wet etching or dry etching.

[0023] Optionally, before forming the pseudo-gate structure, the method further includes: forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewalls of the first fin and the second fin, and the top surface of the isolation layer being lower than the top surfaces of the first fin and the second fin.

[0024] Optionally, the pseudo-gate structure includes: a pseudo-gate dielectric layer, a pseudo-gate layer located on the pseudo-gate dielectric layer, and sidewalls located on the sidewalls of the pseudo-gate dielectric layer and the pseudo-gate layer.

[0025] Optionally, after planarizing the top surface of the first source / drain doped layer, the method further includes: removing the sacrificial layer; forming a dielectric layer on the substrate, the dielectric layer covering the first source / drain doped layer, the second source / drain doped layer, the first fin, the second fin, and the dummy gate structure, and the dielectric layer exposing the top surface of the dummy gate structure.

[0026] Optionally, the method for forming the dielectric layer includes: forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first source / drain doped layer, the first fin, and the dummy gate structure; and planarizing the initial dielectric layer until the top surface of the dummy gate structure is exposed, thereby forming the dielectric layer.

[0027] Optionally, after forming the dielectric layer, the method further includes: removing the dummy gate structure, forming a gate opening within the dielectric layer, and forming a gate structure within the gate opening.

[0028] Optionally, the gate structure includes: a gate dielectric layer and a gate layer located on the gate dielectric layer.

[0029] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0030] In the method for forming the technical solution of the present invention, a sacrificial layer is formed on the first region, the sacrificial layer having a first opening, the first opening exposing a first fin located between adjacent dummy gate structures; first source / drain openings are formed in the first fins on both sides of the dummy gate structures; and first source / drain doped layers are formed in the first source / drain openings and within the first openings. By providing a barrier through the sacrificial layer, the volume difference of each of the first source / drain doped layers formed in the first source / drain openings and within the first openings is minimized, thereby improving the performance of the finally formed semiconductor structure.

[0031] Furthermore, after forming the first source / drain doped layer, the method further includes: planarizing the top surface of the first source / drain doped layer. By planarizing the first source / drain doped layer, the contact between the subsequently formed conductive layer and the first source / drain doped layer is improved, thereby enhancing the performance of the final semiconductor structure.

[0032] Furthermore, the material of the initial sacrificial layer is different from the material of the first fin. By setting the materials of the initial sacrificial layer and the first fin to be different, the etching selectivity between the initial sacrificial layer and the first fin is increased during the etching of the initial sacrificial layer, thereby reducing the damage to the first fin during the etching of the initial sacrificial layer.

[0033] Furthermore, the initial sacrificial layer is made of a hydrogen silsesquioxane. This material has a certain degree of fluidity, facilitating deposition and subsequent removal. Attached Figure Description

[0034] Figure 1 and Figure 2 This is a schematic diagram of a semiconductor structure.

[0035] Figures 3 to 19 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0036] As described in the background section, the performance of semiconductor devices constructed from fin field-effect transistors in the prior art still needs improvement. The following will provide a detailed explanation in conjunction with the accompanying drawings.

[0037] Please refer to Figure 1 and Figure 2 , Figure 1 This is a top view of the semiconductor structure. Figure 2 yes Figure 1A cross-sectional view along line AA shows a substrate 100, which includes a first region I. A plurality of first fins 101 are formed on the substrate 100, the first fins 101 being located on the first region I. A plurality of dummy gate structures 102 are formed on the substrate 100, the dummy gate structures 102 spanning the first fins 101. The first fins 101 are etched using the dummy gate structures 102 as a mask, forming first source / drain openings (not shown) within the first fins 101. A first source / drain doped layer 103 is formed within the first source / drain openings, the first source / drain doped layer 103 containing first source / drain ions.

[0038] In this embodiment, the first source / drain ions are P-type ions, and the first source / drain doped layer 103 is used to form a PMOS transistor structure. In semiconductor electrical design requirements, the first source / drain doped layers 103 of each PMOS transistor structure in the first region I need to be interconnected. However, in actual manufacturing processes, when forming the first source / drain doped layers 103 using epitaxial growth, the different surrounding environments of each of the first fins 101 result in significant differences in the morphology and volume of the formed first source / drain doped layers 103, leading to poor performance of the final semiconductor structure.

[0039] Based on this, the present invention provides a method for forming a semiconductor structure, wherein a sacrificial layer is formed on a first region, the sacrificial layer having a first opening, the first opening exposing a first fin located between adjacent dummy gate structures; first source / drain openings are formed within the first fins on both sides of the dummy gate structures; and first source / drain doped layers are formed within the first source / drain openings and the first opening. By providing a barrier through the sacrificial layer, the volume difference of each of the first source / drain doped layers formed within the first source / drain openings and the first opening is minimized, thereby improving the performance of the finally formed semiconductor structure.

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0041] Figures 3 to 19 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0042] Please refer to Figures 3 to 5 , Figure 3 This is a top view of the semiconductor structure. Figure 4 yes Figure 3 Schematic diagram of the cross section along line AA. Figure 5 yes Figure 3 A cross-sectional view along the BB line shows a substrate 200, which includes a first region I and has a plurality of first fins 201 arranged in parallel along a first direction X.

[0043] In this embodiment, the substrate 200 further includes a second region II, the first region I and the second region II are arranged along the first direction X, and the second region II has a plurality of second fins 202 arranged in parallel along the first direction X.

[0044] In this embodiment, the method for forming the substrate 200, the first fin 101, and the second fin 202 includes: providing an initial substrate (not shown); forming a first patterned layer (not shown) on the initial substrate, the first patterned layer exposing a portion of the top surface of the initial substrate; and etching the initial substrate using the first patterned layer as a mask to form the substrate 200, the first fin 201, and the second fin 202.

[0045] In this embodiment, the substrate 200 is made of silicon; in other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0046] In this embodiment, the first fin 201 and the second fin 202 are made of silicon; in other embodiments, the first fin and the second fin may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium.

[0047] Please refer to Figure 6 and Figure 7 , Figure 6 and Figure 4 The view orientation is consistent. Figure 7 and Figure 5 With the view orientation consistent, an isolation layer 203 is formed on the substrate 200. The isolation layer 203 covers part of the sidewalls of the first fin 201 and the second fin 202, and the top surface of the isolation layer 203 is lower than the top surfaces of the first fin 201 and the second fin 202.

[0048] In this embodiment, the method for forming the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200; etching away a portion of the initial isolation layer to form the isolation layer 204, wherein the top surface of the isolation layer 203 is lower than the top surfaces of the first fin and the second fin.

[0049] The insulating layer 203 is made of an insulating material, including silicon oxide or silicon oxynitride; in this embodiment, the insulating layer 203 is made of silicon oxide.

[0050] Please refer to Figure 8 and Figure 9After the isolation layer 203 is formed, a plurality of pseudo-gate structures 204 are formed on the substrate 200. The pseudo-gate structures 204 span the first fin 201 along the second direction Y, and the first direction X is perpendicular to the second direction Y.

[0051] In this embodiment, the pseudo-gate structure 204 also spans across the second fin 202 along the second direction Y.

[0052] In this embodiment, the method for forming the pseudo-gate structure 204 includes: forming a pseudo-gate dielectric layer (not shown) on the isolation layer 203; forming a pseudo-gate layer (not shown) on the pseudo-gate dielectric layer; and forming a first sidewall (not shown) on the sidewalls of the pseudo-gate layer and the pseudo-gate dielectric layer.

[0053] In this embodiment, the dummy gate dielectric layer is made of silicon oxide; in other embodiments, the dummy gate dielectric layer may also be made of silicon oxynitride.

[0054] In this embodiment, the pseudo-gate layer is made of polycrystalline silicon.

[0055] In this embodiment, the sidewall is made of silicon nitride.

[0056] Please refer to Figures 10 to 12 , Figure 10 This is a top view of the semiconductor structure. Figure 11 yes Figure 10 Schematic diagram of the cross section along the CC line. Figure 12 yes Figure 10 A cross-sectional view along the DD line shows a sacrificial layer 205 formed on the first region I. The sacrificial layer 205 has a first opening 206, which exposes a first fin 201 located between adjacent pseudo-gate structures 204.

[0057] In this embodiment, the method for forming the sacrificial layer 205 includes: forming an initial sacrificial layer (not shown) on the first region I, the initial sacrificial layer covering the first fin 201 and the pseudo-gate structure 204 located on the first region I; forming a patterned layer (not shown) on the initial sacrificial layer, the patterned layer exposing a portion of the top surface of the initial sacrificial layer; etching the initial sacrificial layer using the patterned layer as a mask to form the sacrificial layer 205; and removing the patterned layer after forming the sacrificial layer 205.

[0058] In this embodiment, the material of the initial sacrificial layer is different from the material of the first fin 201. By setting the materials of the initial sacrificial layer and the first fin 201 to be different, the etching selectivity ratio between the initial sacrificial layer and the first fin 201 is increased during the etching of the initial sacrificial layer, thereby reducing the damage to the first fin 201 during the etching of the initial sacrificial layer.

[0059] In this embodiment, the initial sacrificial layer is made of hydrogen silsesquioxane (HSQ). This material has a certain degree of fluidity, which facilitates deposition and subsequent removal.

[0060] Please refer to Figure 13 and Figure 14 , Figure 13 and Figure 11 The view orientation is consistent. Figure 14 and Figure 12 With consistent view orientation, a first source / drain opening 207 is formed on both sides of the pseudo-gate structure 204 and within the first fin 201 exposed by the first opening 206.

[0061] In this embodiment, the method for forming the first source-drain opening 207 includes: etching the first fin portion 201 using the pseudo-gate structure 204 and the sacrificial layer 205 as a mask, and forming the first source-drain opening 207 in the first fin portion 201.

[0062] In this embodiment, during the process of forming the first source drain opening 207, the method further includes forming a second source drain opening 208 in the second fin portion 202 on both sides of the pseudo gate structure 204.

[0063] In this embodiment, the method for forming the second source-drain opening 208 includes: etching the second fin portion 202 using the pseudo-gate structure 204 as a mask, and forming the second source-drain opening 208 within the second fin portion 202.

[0064] Please refer to Figure 15 and Figure 16 , Figure 15 This is a top view of the semiconductor structure. Figure 16 yes Figure 15 A schematic diagram of the cross-section along the EE line shows that a first source / drain doped layer 209 is formed within the first source / drain opening 207 and the first opening 206.

[0065] In this embodiment, a sacrificial layer 205 is formed on the first region I. The sacrificial layer 205 has a first opening 206, which exposes a first fin 201 located between adjacent dummy gate structures 204. First source / drain openings 207 are formed within the first fins 201 on both sides of the dummy gate structure 204. First source / drain doped layers 209 are formed within the first source / drain openings 207 and 206. By providing a barrier through the sacrificial layer 205, the volume difference of the various first source / drain doped layers 209 formed within the first source / drain openings 207 and 206 is minimized, thereby improving the performance of the final semiconductor structure.

[0066] In this embodiment, the first source / drain doped layer 209 contains first source / drain ions, and the first source / drain doped layers 209 are interconnected.

[0067] In this embodiment, the first source / drain ion is a P-type ion, which includes boron or indium.

[0068] In this embodiment, the method for forming the first source / drain doped layer 209 includes: forming a first epitaxial layer (not shown) in the first source / drain opening 207 using an epitaxial growth process; and during the epitaxial growth process, in-situ doping is used to incorporate the first source / drain ions into the first epitaxial layer to form the first source / drain doped layer 209.

[0069] In this embodiment, the process of forming the first source / drain doped layer 209 further includes: forming a second source / drain doped layer 210 within the second source / drain opening 208.

[0070] In this embodiment, the second source / drain doped layer 210 contains second source / drain ions, and each of the second source / drain doped layers 210 is discrete from each other.

[0071] In this embodiment, the second source / drain ion is an N-type ion, which includes phosphorus or arsenic.

[0072] In this embodiment, the method for forming the second source / drain doped layer 210 includes: forming a second epitaxial layer (not shown) in the second source / drain opening 208 using an epitaxial growth process; and during the epitaxial growth process, in-situ doping is used to incorporate the second source / drain ions into the second epitaxial layer to form the second source / drain doped layer 210.

[0073] Please refer to Figure 17 , Figure 17 and Figure 16 With the view direction consistent, after the first source / drain doped layer 209 is formed, the top surface of the first source / drain doped layer 209 is planarized.

[0074] By planarizing the first source / drain doped layer 209, the contact between the subsequently formed conductive layer and the first source / drain doped layer 209 is improved, thereby enhancing the performance of the final semiconductor structure.

[0075] The process for planarizing the top surface of the first source / drain doped layer 209 includes a wet etching process or a dry etching process; in this embodiment, the process for planarizing the top surface of the first source / drain doped layer 209 is a dry etching process.

[0076] Please refer to Figure 18 After planarizing the top surface of the first source / drain doped layer 209, the sacrificial layer 205 is removed; a dielectric layer 211 is formed on the substrate 200, the dielectric layer 211 covering the first source / drain doped layer 209, the second source / drain doped layer 210, the first fin 201, the second fin 202 and the dummy gate structure 204, and the dielectric layer 211 exposing the top surface of the dummy gate structure 204.

[0077] In this embodiment, the method for forming the dielectric layer 211 includes: forming an initial dielectric layer (not shown) on the substrate 200, the initial dielectric layer covering the first source / drain doped layer 209, the first fin 201, and the dummy gate structure 204; planarizing the initial dielectric layer until the top surface of the dummy gate structure 204 is exposed, thereby forming the dielectric layer 211.

[0078] In this embodiment, the dielectric layer 211 is made of silicon oxide; in other embodiments, the dielectric layer may also be made of low-K dielectric material (low-K dielectric material refers to dielectric material with a relative permittivity of less than 3.9) or ultra-low-K dielectric material (ultra-low-K dielectric material refers to dielectric material with a relative permittivity of less than 2.5).

[0079] Please refer to Figure 19 After forming the dielectric layer 211, the dummy gate structure 204 is removed, and a gate opening is formed in the dielectric layer 211; a gate structure 212 is formed in the gate opening.

[0080] In this embodiment, the pseudo-gate dielectric layer and pseudo-gate layer of the pseudo-gate structure 204 are specifically removed.

[0081] In this embodiment, the gate structure 212 includes: a gate dielectric layer (not shown) and a gate layer (not shown) located on the gate dielectric layer.

[0082] In this embodiment, the gate dielectric layer material includes a high-k dielectric material.

[0083] The gate layer is made of a metal, including tungsten, aluminum, copper, titanium, silver, gold, lead, or nickel. In this embodiment, the gate layer is made of tungsten.

[0084] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a first region having a plurality of first fins arranged in parallel along a first direction; A plurality of dummy gate structures are formed on the substrate, the dummy gate structures spanning the first fin along a second direction, the first direction being perpendicular to the second direction; A sacrificial layer is formed on the first region, the sacrificial layer having a first opening that exposes a first fin located between adjacent pseudo-gate structures; A first source / drain opening is formed on both sides of the pseudo-gate structure and within the first fin exposed by the first opening; A first source / drain doped layer is formed in the first source / drain opening and within the first opening; wherein... The method for forming the sacrificial layer includes: forming an initial sacrificial layer on a first region, the initial sacrificial layer covering the first fin and a pseudo-gate structure located on the first region; forming a patterned layer on the initial sacrificial layer, the patterned layer exposing a portion of the top surface of the initial sacrificial layer; etching the initial sacrificial layer using the patterned layer as a mask to form the sacrificial layer; and removing the patterned layer after forming the sacrificial layer. The sacrificial layer is used to provide a barrier to the process of forming the first source / drain doped layer using an epitaxial growth process, so as to reduce the volume difference of the various first source / drain doped layers formed in the first source / drain opening and the first opening.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, After forming the first source / drain doped layer, the method further includes: planarizing the top surface of the first source / drain doped layer.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first source / drain doped layer contains first source / drain ions, and the first source / drain doped layers are interconnected.

4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The substrate further includes a second region, the first region and the second region are arranged along the first direction, the second region has a plurality of second fins arranged in parallel along the first direction, and the pseudo-gate structure also spans across the second fins along the second direction.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The process of forming the first source drain opening also includes: forming a second source drain opening in the second fins on both sides of the pseudo-gate structure.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The process of forming the first source / drain doped layer also includes: forming a second source / drain doped layer within the second source / drain opening.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The second source / drain doped layer contains second source / drain ions, and each of the second source / drain doped layers is independent of the others.

8. The method for forming a semiconductor structure as described in claim 3, characterized in that, The first source / drain ion is a P-type ion, and the P-type ion includes boron or indium.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The second source / drain ion is an N-type ion, which includes phosphorus or arsenic.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the first source drain opening includes: etching the first fin using the pseudo-gate structure and the sacrificial layer as a mask, and forming the first source drain opening within the first fin.

11. The method for forming a semiconductor structure as described in claim 5, characterized in that, The method for forming the second source-drain opening includes: etching the second fin using the pseudo-gate structure as a mask, and forming the second source-drain opening within the second fin.

12. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method for forming the first source / drain doped layer includes: forming a first epitaxial layer in the first source / drain opening using an epitaxial growth process; and, during the epitaxial growth process, incorporating the first source / drain ions into the first epitaxial layer using an in-situ doping process to form the first source / drain doped layer.

13. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the second source / drain doped layer includes: forming a second epitaxial layer in the second source / drain opening using an epitaxial growth process; and, during the epitaxial growth process, incorporating the second source / drain ions into the second epitaxial layer using an in-situ doping process to form the second source / drain doped layer.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the initial sacrificial layer is different from the material of the first fin.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The material of the initial sacrificial layer includes: hydrogen silsesquioxane.

16. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for planarizing the top surface of the first source / drain doped layer includes: wet etching or dry etching.

17. The method for forming a semiconductor structure as described in claim 4, characterized in that, Before forming the pseudo-gate structure, the method further includes: forming an isolation layer on the substrate, the isolation layer covering a portion of the sidewalls of the first fin and the second fin, and the top surface of the isolation layer being lower than the top surfaces of the first fin and the second fin.

18. The method for forming a semiconductor structure as described in claim 1, characterized in that, The pseudo-gate structure includes: a pseudo-gate dielectric layer, a pseudo-gate layer located on the pseudo-gate dielectric layer, and sidewalls located on the sidewalls of the pseudo-gate dielectric layer and the pseudo-gate layer.

19. The method for forming a semiconductor structure as described in claim 6, characterized in that, After planarizing the top surface of the first source / drain doped layer, the method further includes: removing the sacrificial layer; forming a dielectric layer on the substrate, the dielectric layer covering the first source / drain doped layer, the second source / drain doped layer, the first fin, the second fin, and the dummy gate structure, and the dielectric layer exposing the top surface of the dummy gate structure.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The method for forming the dielectric layer includes: forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first source / drain doped layer, the first fin, and the dummy gate structure; and planarizing the initial dielectric layer until the top surface of the dummy gate structure is exposed, thereby forming the dielectric layer.

21. The method for forming a semiconductor structure as described in claim 19, characterized in that, After forming the dielectric layer, the method further includes: removing the dummy gate structure, forming a gate opening within the dielectric layer, and forming a gate structure within the gate opening.

22. The method for forming a semiconductor structure as described in claim 21, characterized in that, The gate structure includes: a gate dielectric layer and a gate layer located on the gate dielectric layer.

Images