Semiconductor structure manufacturing method

Abstract

A semiconductor structure manufacturing method includes the following processes. A semiconductor substrate is provided. A first via is formed on the semiconductor substrate, wherein the via extends from a surface of the semiconductor substrate to an interior of the semiconductor substrate. A first conductive material is filled in the first via. The semiconductor substrate and the first conductive material are ground differently so that the first conductive material protrudes from the semiconductor substrate. The first conductive material and the surface of the semiconductor substrate are planarized so that a top surface of the first conductive material is flush with the surface of the semiconductor substrate. In this way, the exposed surface of the conductive material for interconnection is uniform, which is conducive to subsequent bonding.

Description

TECHNICAL FIELD

[0001] The present invention relates to a semiconductor structure manufacturing method. BACKGROUND

[0002] In semiconductor processes, after active elements are formed on a semiconductor wafer, a redistribution layer of conductive material and lines for interconnection is formed.

[0003] For example, the conductive material for interconnection extends from the surface of the semiconductor wafer to the interior. However, in some existing processes, after the conductive material is formed and polished by a chemical mechanical planarization process, there are non-uniform recesses in the exposed surface of the conductive material corresponding to different locations on the semiconductor wafer. In some existing examples, the exposed surface of the conductive material in the center of the semiconductor wafer is recessed differently from the exposed surface of the conductive material near the periphery, which affects the effectiveness of subsequent hybrid bonding. SUMMARY

[0004] An object of the present invention is to provide a semiconductor structure manufacturing method, in which the exposed surface of the conductive material for interconnection is uniform, which is beneficial for subsequent bonding.

[0005] According to an embodiment of the present invention, a semiconductor structure manufacturing method includes the following steps. A semiconductor substrate is provided. A first via is formed on the semiconductor substrate, wherein the via extends from a surface of the semiconductor substrate to an interior of the semiconductor substrate. A first conductive material is filled in the first via. The semiconductor substrate and the first conductive material are polished differently, so that the first conductive material protrudes from the semiconductor substrate. The surface of the semiconductor substrate and the first conductive material are planarized, so that the top surface of the first conductive material is flush with the surface of the semiconductor substrate.

[0006] In one or more embodiments of the present invention, the aforementioned semiconductor structure manufacturing method further includes the following steps. A second via is formed on the semiconductor substrate, wherein the second via extends from the surface of the semiconductor substrate to the interior of the semiconductor substrate, and the second via is farther from the center of the semiconductor substrate than the first via. A second conductive material is filled in the second via. The semiconductor substrate and the second conductive material are polished differently, so that the second conductive material protrudes from the semiconductor substrate.

[0007] In some embodiments of the present invention, in the step of planarizing the surface of the semiconductor substrate and the first conductive material, the first conductive material, the second conductive material, and the semiconductor substrate are simultaneously planarized, so that the top surface of the first conductive material, the top surface of the second conductive material, and the surface of the semiconductor substrate are flush.

[0008] In some embodiments of the present application, the width of the first channel is equal to the width of the second channel, and the second conductive material is the same as the first conductive material.

[0009] In some embodiments of the present application, the top surface of the first conductive material, the top surface of the second conductive material, and the surface of the semiconductor substrate are flush, defined as the top surface of the first conductive material has a first height difference relative to the surface of the semiconductor substrate, and the top surface of the second conductive material has a second height difference relative to the surface of the semiconductor substrate, the first height difference and the second height difference are less than and the error between the first height difference and the second height difference is less than

[0010] In one or more embodiments of the present application, the process of differentially polishing the semiconductor substrate and the first conductive material is performed by a polishing liquid, and the composition of the polishing liquid includes cerium oxide.

[0011] In some embodiments of the present application, the aforementioned semiconductor structure manufacturing method further includes the following process. The polishing selectivity of the polishing liquid to the first conductive material and the semiconductor substrate is regulated.

[0012] In some embodiments of the present application, the semiconductor substrate includes an oxide layer, the first conductive material includes copper, the first channel extends from the oxide layer to the interior of the semiconductor substrate, and the polishing selectivity is a copper-to-oxide polishing selectivity.

[0013] In one or more embodiments of the present application, in the process of differentially polishing the semiconductor substrate and the first conductive material to make the first conductive material protrude from the semiconductor substrate, there is a height difference between the top surface of the first conductive material and the surface of the semiconductor substrate, and the height difference is in the range of to .

[0014] In one or more embodiments of the present application, the process of planarizing the protruding first conductive material and the surface of the semiconductor substrate is achieved by a chemical mechanical planarization process.

[0015] In summary, by the semiconductor structure manufacturing method of the present application, the exposed surface of the interconnection conductive material formed on the semiconductor wafer can be uniform, thereby facilitating the subsequent bonding process.

[0016] It should be understood that the above general description and the following detailed description are further illustrated by examples and are intended to provide further explanation of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0017] The advantages of the present application will be better understood by the following embodiments, with reference to the attached drawings. The embodiments illustrated in the drawings are merely exemplary, and therefore should not be considered as limiting the individual embodiments, or limiting the scope of the claims.

[0018] Figure 1 A flow chart of a semiconductor structure manufacturing method according to an embodiment of the present application;

[0019] Figures 2 to 6 Cross-sectional views of different flows of a semiconductor structure manufacturing method according to an embodiment of the present application;

[0020] Figure 7 A summary table of height differences between top surfaces of conductive materials of different line widths and surfaces of semiconductor substrates according to an embodiment of the present application;

[0021] Figure 8 A summary table of height differences between top surfaces of conductive materials of different line widths and surfaces of semiconductor substrates after forming semiconductor structures according to an embodiment of the present application.

[0022] Explanation of main reference numerals:

[0023] 100 - semiconductor structure manufacturing method; 110-150 - flow; 210 - semiconductor substrate; 215 - active layer; 215S - surface; 220 - oxide layer; 220S - surface; 231 - first channel; 232 - second channel; 233 - third channel; 241 - first conductive material; 241S - top surface; 242 - second conductive material; 242S - top surface; 243 - third conductive material; 243S - top surface; H - height difference; d1, d2, d3 - height difference; W1, W2, W3 - width. DETAILED DESCRIPTION

[0024] The following embodiments are described in detail with reference to the attached drawings, but the embodiments provided are not intended to limit the scope of the present application, and the description of the structure and operation is not intended to limit the order of execution. Any structure recombined by elements, resulting in a device with equivalent efficiency, is within the scope of the present application. In addition, the drawings are for illustration purposes only and are not drawn to scale. For ease of understanding, the same or similar elements will be described using the same reference numerals in the following description.

[0025] Unless otherwise defined, all terms used herein (including technical and scientific terms) have their ordinary meanings, meanings that are understandable to those skilled in the art. Furthermore, the definitions of the foregoing terms in commonly used dictionaries should be interpreted in the context of this specification as having the meaning consistent with the relevant field of this invention. Unless specifically defined, these terms will not be construed as having idealized or overly formal meanings.

[0026] The terms “first,” “second,” etc., used in this document do not specifically refer to any order or sequence, nor are they intended to limit the invention. They are merely used to distinguish elements or operations described using the same technical terms.

[0027] Secondly, the terms “contains,” “includes,” “has,” “contains,” etc., used in this article are all open-ended terms, meaning that they include but are not limited to.

[0028] Furthermore, in this document, unless otherwise specified in the text, “a” and “the” can refer to one or more. It will be further understood that the terms “comprising,” “including,” “having,” and similar words as used herein specify the features, regions, integers, steps, operations, elements, and / or components described herein, but do not exclude one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof described or additionally described herein.

[0029] The semiconductor structure manufacturing method provided by this invention can improve the uneven height of multiple exposed top surfaces of conductive materials used for interconnection on a semiconductor wafer / semiconductor substrate from the center to the edge.

[0030] Please refer to Figure 1 and refer to them respectively. Figures 2 to 6 . Figure 1 A flowchart illustrating a semiconductor structure manufacturing method 100 according to an embodiment of the present invention. Figures 2 to 6 Cross-sectional views of different processes in a semiconductor structure manufacturing method 100 according to an embodiment of the present invention.

[0031] Please refer to the following at the same time Figure 1 and Figure 2 In process 110, a semiconductor substrate 210 is provided. Figure 2 An embodiment of the semiconductor substrate 210 provided by the present invention is illustrated, but it is not intended to limit the purpose of the semiconductor substrate 210 used in the present invention. In this embodiment, the semiconductor substrate 210 includes an active layer 215 and an oxide layer 220.

[0032] In some embodiments, the active layer 215 can include different active components and integrated circuits, such as transistors or integrated DRAM memory cells. For the purpose of simplicity, only one active component 215A is shown in the active layer 215. Figure 2 and subsequent Figures 3 to 6 The active component 215A inside the active layer 215 is not shown.

[0033] An oxide layer 220 is formed on the active layer 215. In some embodiments, the semiconductor substrate 210 includes silicon. The oxide layer 220 includes silicon oxide as a dielectric to block unintended electrical connections. Thus, by forming conductive vias through the oxide layer 220 to the active layer 215 inside the semiconductor substrate 210, electrical connections to the active components or integrated circuits inside the active layer 215 can be achieved.

[0034] It should be noted that, Figure 2 Only a portion of the semiconductor substrate 210 from the center to the edge is shown schematically, and the direction Dl represents a direction from the center to the edge of the semiconductor substrate 210.

[0035] Referring to Figure 1 and Figure 3 to flow 120, vias are formed on the semiconductor substrate 210. In this embodiment, a first via 231, a second via 232, and a third via 233 are formed on the semiconductor substrate 210. The first via 231, the second via 232, and the third via 233 extend from the surface 220S of the semiconductor substrate 210 to the active layer 215 inside the semiconductor substrate 210. As shown in Figure 3 In this embodiment, the first via 231, the second via 232, and the third via 233 all extend through the surface 215S of the active layer 215 to ensure that the first via 231, the second via 232, and the third via 233 can connect to the components inside the active layer 215.

[0036] As mentioned previously, the direction Dl corresponds to a direction from the center to the edge of the semiconductor substrate 210. As shown in Figure 3 The first via 231 is closest to the center of the semiconductor substrate 210, the second via 232 is farther from the center of the semiconductor substrate 210 than the first via 231, and the third via 233 is farthest from the center of the semiconductor substrate 210 than the first via 231 and the second via 232.

[0037] As Figure 3As shown, the first channel 231 has a width W1, the second channel 232 has a width W2, and the third channel 233 has a width W3. The different widths W1, W2, and W3 of the first channel 231, the second channel 232, and the third channel 233 correspond to the line width widths of the subsequently formed conductive vias. In the present embodiment, the width W1, the width W2, and the width W3 are the same as each other. This corresponds to the embodiment in which the multiple channels of the same line width width are at different distances from the center of the semiconductor substrate 210. By the semiconductor structure manufacturing method 100 of the present application, after the conductive channels are formed by filling the first channel 231, the second channel 232, and the third channel 233 with the conductive material, the conductive materials of the different first channel 231, the second channel 232, and the third channel 233 can be leveled, and no excessive unevenness can occur. Details are discussed later.

[0038] Please also refer to Figure 1 and Figure 3 . Enter the flow 130, fill the first channel 231, the second channel 232, and the third channel 233 with the conductive material 240. In Figure 3 , the conductive material 240 fills the first channel 231, the second channel 232, and the third channel 233, and the conductive material 240 covers the surface 220S of the semiconductor substrate 210.

[0039] In the present embodiment, the conductive material 240 is, for example, copper, but the conductive material used is not limited thereto.

[0040] Please refer to Figure 1 , and in order Figure 4 and Figure 5 . In flow 140, grind the semiconductor substrate 210 and the conductive material 240.

[0041] Figure 4 The intermediate flow of flow 140 is schematically shown. In Figure 4 , the semiconductor substrate 210 and the conductive material 240 are first planarized. The conductive material 240 includes a first conductive material 241, a second conductive material 242, and a third conductive material 243, which are filled in the first channel 231, the second channel 232, and the third channel 233, respectively. In other words, in the present embodiment, the conductive materials filled in the first channel 231, the second channel 232, and the third channel 233 are the same.

[0042] However, the first conductive material 241, the second conductive material 242, and the third conductive material 243 filling the respective first channel 231, second channel 232, and third channel 233 will not be completely flush, but may have some dishing. Furthermore, because the distances of the respective first channel 231, second channel 232, and third channel 233 relative to the center of the semiconductor substrate 210 are different, the first conductive material 241, second conductive material 242, and third conductive material 243 will exhibit differences.

[0043] like Figure 4 As shown, the top surface 241S of the first conductive material 241 filled in the first channel 231 has a height difference d1 relative to the surface 220S of the oxide layer 220 of the semiconductor substrate 210; the top surface 242S of the second conductive material 242 filled in the second channel 232 has a height difference d2 relative to the surface 220S; and the top surface 243S of the third conductive material 243 filled in the third channel 233 has a height difference d3 relative to the surface 220S. In some embodiments, the differences in height difference d1, height difference d2, and height difference d3 are approximately within the range of...

[0044] Continued Figure 4 In process 140 and Figure 5 In the process, the semiconductor substrate 210 and the first conductive material 241, the second conductive material 242 and the third conductive material 243 are ground differently, so that the first conductive material 241, the second conductive material 242 and the third conductive material 243 protrude from the surface 220S of the semiconductor substrate 210 respectively.

[0045] As previously described, the formation of the first channel 231, the second channel 232, and the third channel 233 respectively penetrates the oxide layer 220 of the semiconductor substrate 210. In this embodiment, the semiconductor substrate 210 is made of silicon, and the corresponding oxide layer 220 is made of, for example, silicon oxide. Furthermore, in this embodiment, the conductive material 240 (including the first conductive material 241, the second conductive material 242, and the third conductive material 243 respectively filling the first channel 231, the second channel 232, and the third channel 233) is made of copper. Therefore, in this embodiment, process 140 involves differentially etching copper and silicon oxide.

[0046] In one or more embodiments of the present invention, process 140, which involves differentially polishing the semiconductor substrate 210 and the first conductive material 241, the second conductive material 242, and the third conductive material 243, is performed using a polishing slurry. Specifically, by adjusting the polishing selectivity ratio of the polishing slurry to the first conductive material 241, the second conductive material 242, the third conductive material 243, and the semiconductor substrate 210, the polishing rate of the first conductive material 241, the second conductive material 242, and the third conductive material 243 can be different from the polishing rate of the semiconductor substrate 210 during the polishing process.

[0047] Specifically, in this embodiment, the first conductive material 241, the second conductive material 242, and the third conductive material 243 are made of copper, and the oxide layer 220 on the semiconductor substrate 210 is polished together with the first conductive material 241, the second conductive material 242, and the third conductive material 243. Therefore, in this embodiment, process 140 essentially corresponds to differential polishing of copper / oxide layer 220 (Cu / Oxide). By adjusting the polishing selectivity ratio of the polishing slurry to the copper / oxide layer 220, it is possible to make the polishing rate of copper less than the polishing rate of oxide layer 220 during the polishing process, thereby causing the first conductive material 241, the second conductive material 242, and the third conductive material 243 of copper to protrude from the surface 220S of the oxide layer 220 of the semiconductor substrate 210.

[0048] In some embodiments, the polishing slurry comprises cerium oxide (CeO2). In some embodiments, the polishing slurry is mixed with a cerium oxide-containing polishing slurry (e.g., Hitachi HS8800-C2T CeO2 slurry) and a surfactant (e.g., STI2910) to control the polishing selectivity ratio between the copper / oxide layer 220.

[0049] After grinding in process 140, as Figure 5 As shown, the first conductive material 241, the second conductive material 242, and the third conductive material 243 protrude from the surface 220S. The top surfaces 241S of the first conductive material 241, 242S of the second conductive material 242, and 243S of the third conductive material 243 become flat after grinding, and it is possible to design that the three surfaces 241S, 242S, and 243S are approximately flush after grinding. There is a height difference H between the top surfaces 241S, 242S, and 243S and the surface 220S, which has been lowered in height after grinding.

[0050] In some implementations, the height difference H is greater than... This ensures that there is enough time to adjust the height of the top surface 241S, top surface 242S, and top surface 243S during the subsequent grinding process.

[0051] In this way, compared to Figure 4 ,exist Figure 5 In this process, the height relationship between the surface 220S of the semiconductor substrate 210 and the first conductive material 241, the second conductive material 242, and the third conductive material 243 is reversed. The first conductive material 241, the second conductive material 242, and the third conductive material 243 protrude from the surface, which facilitates the control of the flatness of the top surfaces 241S, 242S, and 243S respectively. In this way, even if the distances of the first conductive material 241, the second conductive material 242, and the third conductive material 243 relative to the center of the semiconductor substrate 210 are different, it can be ensured that the top surfaces 241S, 242S, and 243S are controllable during the subsequent planarization process, thereby ensuring that the three are flush.

[0052] Please refer to the following first. Figure 7 . Figure 7 A summary table illustrating the height differences of the top surfaces 241S, 242S, and 243S of the first conductive material 241, the second conductive material 242, and the third conductive material 243 with different line widths relative to the surface 220S of the semiconductor substrate 210 under process 140, according to an embodiment of the present invention.

[0053] like Figure 3 As shown, the first channel 231, the second channel 232, and the third channel 233 each have a width W1, a width W2, and a width W3, respectively. In this embodiment, the widths W1, W2, and W3 are equal to each other. This corresponds to an embodiment where multiple channels of the same width are at different distances from the center of the semiconductor substrate 210.

[0054] The first channel 231, the second channel 232, and the third channel 233 have widths W1, W2, and W3, respectively, corresponding to the different linewidths of the formed conductive vias. Figure 7 The table provides three embodiments with line widths of 12μm, 16μm, and 30μm, meaning that widths W1, W2, and W3 are the same, while the three embodiments with widths W1, W2, and W3 of 12μm, 16μm, or 30μm are all grouped together. Figure 7 In the table.

[0055] The first channel 231 is closest to the center of the semiconductor substrate 210, corresponding to Figure 7 The table shows the center; the second channel 232 is located between the center and the edge of the semiconductor substrate 210, corresponding to... Figure 7 In the table, the middle; the third channel 233 is close to the edge of the semiconductor substrate 210, corresponding to Figure 7 The edge in the table.

[0056] As Figure 7 shown, since the first conductive material 241, the second conductive material 242 and the third conductive material 243 are protruded from the semiconductor substrate 210, it is easier to set the same height difference H. In the embodiment with line width width of 12 μιη, the top surface 241S, the top surface 242S and the top surface 243S of the first conductive material 241, the second conductive material 242 and the third conductive material 243 are set to have the same height difference H of 0.5 μιη. greater than Similarly, for the embodiment with line width width of 16 μιη, the height difference H is 0.5 μιη. For the embodiment with line width width of 30 μιη, the height difference H is 0.5 μιη. The larger the line width width, the longer height difference H can be reserved for easy control during polishing. In some embodiments of the present application, the height difference H reserved is in the range of 0.5 μιη to 1.5 μιη. to .

[0057] Please refer to Figure 1 and Figure 6 . At the process 150, the first conductive material 241, the second conductive material 242 and the third conductive material 243 are planarized with the surface 220S of the semiconductor substrate 210, so that the top surface 241S, the top surface 242S and the top surface 243S of the first conductive material 241, the second conductive material 242 and the third conductive material 243 are planarized with the surface 220S of the semiconductor substrate 210.

[0058] The planarization process 150 can be achieved by chemical mechanical planarization (CMP) (e.g. Cu CMP barrier slurry polishing). For the protruded first conductive material 241, the second conductive material 242 and the third conductive material 243, they can be treated by mechanical polishing. The reduction of the height of the top surface 241S, the top surface 242S and the top surface 243S of the first conductive material 241, the second conductive material 242 and the third conductive material 243 can be controlled by adjusting the overall time of polishing. For example, the more the polishing time, the more the protruded part of the conductive material will be removed. Since the first conductive material 241, the second conductive material 242 and the third conductive material 243 are protruded from the semiconductor substrate 210, it is easier to polish and thus more accurate to control the height of the top surface 241S, the top surface 242S and the top surface 243S.

[0059] In Figure 6In this case, the heights of the first conductive material 241, the second conductive material 242, and the third conductive material 243, and the thickness of the oxide layer 220 are further reduced. Since the first conductive material 241, the second conductive material 242, and the third conductive material 243 are planarized in a state of protruding from the semiconductor substrate 210, the heights of the top surface 241S, the top surface 242S, and the top surface 243S can be preferably controlled. Thus, in the semiconductor structure 200 formed, the first conductive material 241, the second conductive material 242, and the third conductive material 243 are flush with the surface 220S.

[0060] Figure 8 According to an embodiment of the present application, a table of the height differences of the respective top surfaces 241S, 242S, and 243S of the first conductive material 241, the second conductive material 242, and the third conductive material 243 with different line width widths relative to the surface 220S of the semiconductor substrate 210 is shown after the semiconductor structure 200 is formed. Figure 8 Subsequently Figure 7 , the height differences of the respective top surfaces 241S, 242S, and 243S relative to the surface 220S are improved after planarization.

[0061] Similarly Figure 7 to the table shown in Figure 8 , three embodiments with line width widths of 12 μm, 16 μm, and 30 μm are provided, and the first channel 231, the second channel 232, and the third channel 233 have widths W1, W2, and W3 of 12 μm, 16 μm, and 30 μm, respectively. The first channel 231 is closest to the center of the semiconductor substrate 210, corresponding to the center in the table; the second channel 232 is between the center and the edge of the semiconductor substrate 210, corresponding to the middle in the table; and the third channel 233 is closest to the edge of the semiconductor substrate 210, corresponding to the edge in the table. Figure 8 Figure 8 Figure 8

[0062] As shown in Figure 8 , for the embodiment with a line width width of 12 μm, the height differences of the top surface 241S, the top surface 242S, and the top surface 243S relative to the surface 220S after planarization are respectively and That is, the maximum difference between the top surface 241S, the top surface 242S, and the top surface 243S is only

[0063] ​​​For the embodiment with a linewidth of 16μm, after planarization, the height differences between the top surface 241S, top surface 242S, and top surface 243S and the surface 220S can be ensured as follows: as well as That is to say, the greatest difference between top surface 241S, top surface 242S, and top surface 243S is only

[0064] For the embodiment with a linewidth of 30μm, after planarization, the height differences between the top surface 241S, top surface 242S, and top surface 243S and the surface 220S can be ensured to be respectively as well as That is to say, the greatest difference between top surface 241S, top surface 242S, and top surface 243S is only

[0065] As can be seen from the above embodiments, after the semiconductor structure 200 is formed through the semiconductor structure manufacturing method 100, the top surfaces 241S, 242S, and 243S of the first conductive material 241, the second conductive material 242, and the third conductive material 243 at different locations from the center of the semiconductor substrate 210 can be planarized to make them flush with the surface 220S of the semiconductor substrate 210. In this embodiment, the flushness of the top surfaces 241S, 242S, and 243S with the surface 220S of the semiconductor substrate 210 can be defined as the height difference between the top surfaces 241S, 242S, and 243S and the surface 220S being less than 1 / 3 of the height difference between the top surfaces 241S, 242S, and 243S and the surface 220S. Furthermore, the error between top surface 241S, top surface 242S, and top surface 243S is less than [missing value].

[0066] Therefore, as Figure 8 As shown in the consolidated table, regardless of the line widths of 12μm, 16μm, and 30μm, all embodiments meet the requirement that the height difference between top surface 241S, top surface 242S, and top surface 243S and surface 220S is less than [missing information]. Furthermore, the error between top surface 241S, top surface 242S, and top surface 243S is less than [missing information]. Due to the limitations, the top surfaces 241S, 242S, and 243S are flush with the surface 220S of the semiconductor substrate 210.

[0067] In this way, after ensuring that the top surfaces 241S, 242S, 243S of the first, second and third conductive materials 241, 242, 243 and the surface 220S of the semiconductor substrate 210 are flush, the first, second and third conductive materials 241, 242, 243 form conductive vias in the first, second and third channels 231, 232, 233, respectively.

[0068] In summary, by the semiconductor structure manufacturing method 100 of the present application, the semiconductor structure 200 formed has flush exposed top surfaces 241S, 242S, 243S, and the height or recess degree of these exposed top surfaces can be uniform from the center to the edge of the semiconductor substrate 210, which is beneficial for subsequent bonding processes. The bonding process can be, for example, hybrid bonding. For example, in some embodiments, the semiconductor structure 200 formed by the present application is a plurality of conductive vias with flush top surfaces. In some embodiments, two conductive vias of the semiconductor structure 200 formed can be aligned with each other, and the exposed conductive materials of the uniform top surfaces are in contact and bonded together, thereby realizing via-to-via hybrid bonding. Since the height of the exposed top surfaces of the conductive materials can be uniform from the center to the edge, it is beneficial for the consistency of bonding at different positions on the semiconductor substrate / wafer, and the electrical properties will not be defective due to different bonding positions. In some embodiments, the semiconductor structure 200 formed by the present application can also be used for pad-to-via hybrid bonding.

[0069] Although the present application has been disclosed with reference to examples as above, it is not intended to limit the present application, and any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present application, and therefore the scope of protection of the present application is defined by the claims.

[0070] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the embodiments of the present application without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present application cover modifications and variations of this application provided they come within the scope of the appended claims.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, Comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises an active layer and an oxide layer on the active layer; forming a first via on the semiconductor substrate, wherein the first via extends from a surface of the semiconductor substrate to an interior of the semiconductor substrate, the first via extending through the oxide layer into the active layer; filling the first via with a first conductive material; differentially grinding the semiconductor substrate and the first conductive material such that the first conductive material protrudes from the semiconductor substrate; and planarizing the protruding first conductive material and the surface of the semiconductor substrate such that a top surface of the first conductive material is flush with the surface of the semiconductor substrate.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein Further comprising: forming a second via on the semiconductor substrate, wherein the second via extends from the surface of the semiconductor substrate to an interior of the semiconductor substrate, the second via being further from a center of the semiconductor substrate than the first via; filling the second via with a second conductive material; and differentially grinding the semiconductor substrate and the second conductive material such that the second conductive material protrudes from the semiconductor substrate, wherein in the process of planarizing the first conductive material and the surface of the semiconductor substrate, the first conductive material, the second conductive material, and the semiconductor substrate are simultaneously planarized such that the top surface of the first conductive material, a top surface of the second conductive material, and the surface of the semiconductor substrate are flush.

3. The method of manufacturing a semiconductor structure according to claim 2, wherein The top surface of the first conductive material is disposed flush with the top surface of the second conductive material after the differential grinding of the first conductive material and the second conductive material from the semiconductor substrate.

4. The method of fabricating a semiconductor structure of claim 2, wherein The first via has a width equal to a width of the second via, and the second conductive material is the same as the first conductive material.

5. The method of manufacturing a semiconductor structure according to claim 4, wherein the top surface of the first conductive material, the top surface of the second conductive material, and the surface of the semiconductor substrate are flush, defined as the top surface of the first conductive material has a first height difference relative to the surface of the semiconductor substrate, the top surface of the second conductive material has a second height difference relative to the surface of the semiconductor substrate, the first height difference and the second height difference are less than and the error between the first height difference and the second height difference is less than 6. The method of fabricating a semiconductor structure of claim 1, wherein, The process of differentially grinding the semiconductor substrate and the first conductive material is performed with a grinding solution, the composition of the grinding solution comprising cerium oxide.

7. The method of manufacturing a semiconductor structure according to claim 6, wherein Further comprising: regulating a grinding selectivity ratio of the grinding solution for the first conductive material and the semiconductor substrate.

8. The method of manufacturing a semiconductor structure according to claim 7, wherein The semiconductor substrate comprises an oxide layer, the first conductive material comprises copper, the first via extends from the oxide layer to an interior of the semiconductor substrate, and the grinding selectivity ratio is a copper-to-oxide grinding selectivity ratio.

9. The method of fabricating a semiconductor structure of claim 1, wherein, In a process of differentially grinding the semiconductor substrate and the first conductive material to cause the first conductive material to protrude from the semiconductor substrate, a height difference between the top surface of the first conductive material and the surface of the semiconductor substrate ranges from to .

10. The method of fabricating a semiconductor structure of claim 1, wherein, The process of planarizing the protruding first conductive material and the surface of the semiconductor substrate is performed by a chemical mechanical planarization process.

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