Current-mode transconductance-capacitor filter within a radio frequency digital-to-analog converter

Abstract

A filter stage system comprising a continuous-time baseband filter comprising a feedback loop employing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current, and a mirror component mirrors the filtered current to an output.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an integrated radio frequency digital-to-analog converter (RF DAC), and more particularly, utilizing a current-mode transconductance-capacitor filter to generate filtered current and provide a path to reuse current between a filter and an adjacent stage in a signal chain. BACKGROUND

[0002] Quantum computing generally uses quantum mechanical phenomena to perform computing and information processing functions. Quantum computing can be viewed as the opposite of classical computing, which generally operates on binary values with transistors. That is, while a classical computer can run on two basic states of 0 or 1, a quantum computer runs on qubits that include superpositions of both 0 and 1, can entangle multiple qubits, and uses interference. Quantum computing is emerging as a new paradigm to solve a large number of problems that show adverse scaling on regular classical high-performance computers. Arbitrary waveform generation capability with variable amplitude and low distortion is desirable in multiple contexts, including in the control of qubits in the field of quantum computing. In particular, radio frequency digital-to-analog converters (RF DACs) are valuable in a variety of applications, including wireless transmitters and implementing control pulses for qubits. Filter implementation and the interface between a filter and other elements of a signal chain are significant in such designs. Continuous-time filters are well suited for high dynamic range, low power active filter implementations. Current-mode signal processing is well suited for low distortion applications because it reduces voltage swings at nodes of interest. However, conventional current-mode input filters using operational amplifiers consume a large amount of power and have limitations for high frequency applications. SUMMARY

[0003] The following presents a summary to provide a basic understanding of one or more embodiments of the application. This summary is not intended to identify key or critical elements, thereby delineating the scope of particular embodiments or the scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later. In one or more embodiments described herein, a system, computer-implemented method, apparatus, and / or computer program product facilitates an integrated radio frequency digital-to-analog converter (RF DAC), more particularly, utilizing a current-mode transconductance-capacitor filter to generate filtered current and provide a path to reuse current between a filter and an adjacent stage in a signal chain.

[0004] According to an embodiment, a system comprises a processor that executes the following system-executable components stored in a memory: a radio frequency digital-to-analog converter (RF DAC) that operates in a current mode; and a continuous-time baseband filter that comprises a feedback loop that employs at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and wherein the continuous-time baseband filter generates a filtered current.

[0005] In an optional aspect, a mirror component operating in the current mode mirrors the filtered current to an output.

[0006] According to an embodiment, a system implementation method comprises a radio frequency digital-to-analog converter (RF DAC) to execute system-executable components to perform the following acts: operating in a current mode with a baseband filter, wherein inputs and outputs of the system block are represented as currents.

[0007] In an optional aspect, the system implementation method further comprises mirroring, by the system, a mirror component operating in the current mode, the filtered current to an output, wherein the mirror component selectively changes a mirror ratio to achieve a variable gain with respect to a fine base-line step. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A block diagram showing an example system implementation to implement an integrated digital-to-analog converter (DAC) with a current-mode signal path is shown.

[0009] Figure 2 An example flow diagram showing an integrated radio frequency digital-to-analog converter with a current-mode transconductance capacitor filter is shown.

[0010] Figure 3 An example architecture of a radio frequency digital-to-analog converter (RF DAC) signal chain is shown.

[0011] Figure 4 An example block-level view architecture of a feedback-based transconductance capacitor baseband filter is shown.

[0012] Figure 5 An example transistor-level schematic diagram of a single-ended implementation of a filter is shown.

[0013] Figure 6 An example transistor-level implementation of a baseband filter is shown.

[0014] Figure 7 Another example transistor-level diagram of an alternative filter arrangement of an embodiment is shown.

[0015] Figure 8 Another example transistor-level diagram showing an alternative filter arrangement of embodiments.

[0016] Figure 9 Another example transistor-level diagram showing an alternative filter arrangement of embodiments.

[0017] Figure 10 An example transistor-level diagram showing a differential filter transfer function of embodiments.

[0018] Figure 11 An example showing simulation results for a current-mode transconductance capacitor filter.

[0019] Figure 12 An example showing a schematic extension of an array-based system.

[0020] Figure 13 An example schematic diagram showing a cascaded extension of complementary stages.

[0021] Figure 14 A block diagram showing an example non-limiting operating environment in which one or more embodiments described herein can be facilitated.

[0022] Figure 15 A block diagram showing an example non-limiting cloud computing environment in accordance with one or more embodiments of the subject disclosure.

[0023] Figure 16 A block diagram showing example non-limiting abstraction model layers in accordance with one or more embodiments of the subject disclosure. DETAILED DESCRIPTION

[0024] The following detailed description is merely illustrative and is not intended to limit embodiments and / or the application or uses of embodiments. Furthermore, there is no intention to be bound by any expressed or implied information presented in the preceding Background or Summary sections, or in the Detailed Description. One or more embodiments are now described with reference to the drawings, where like reference numerals are used to refer to like elements throughout. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a more thorough understanding of one or more embodiments. It is evident, however, that one or more embodiments can be practiced without these specific details.

[0025] The present invention relates generally to systems and methods that implement a current-mode end-to-end path through an output from a radio frequency digital-to-analog converter (RF DAC) that enables advantageous tradeoffs regarding power consumption and distortion to be achieved. The elements of the signal path are the RF DAC, a baseband filter, a mirror, and an output stage. Benefits can be achieved by implementing the entire chain in current mode or by implementing sub-elements of the chain in current mode.

[0026] Embodiments integrate a radio frequency digital-to-analog converter that utilizes a current-mode transconductance capacitor filter to generate a filtered current and provide a path for current reuse between the filter and an adjacent stage in a signal chain. Current-mode signal processing is well suited for low-distortion applications because it reduces voltage swings at various nodes of interest. However, traditional current-mode input filters that use operational amplifiers consume a large amount of power and have limitations for high-frequency applications. Embodiments disclosed and claimed herein present a promising solution to this problem by introducing a current-mode signal path design in the implementation of an integrated digital-to-analog converter. Implementing an efficient current-mode filter stage provides multiple benefits in the context of the proposed end-to-end current-mode analog signal path RF DAC architecture that has been developed for low-power, low-distortion arbitrary waveform generation applications. It provides a path for current reuse between filter stages and adjacent stages in a signal chain. It also avoids introducing additional current-to-voltage conversion in the signal path (such conversion can be included in a feedback path), which helps limit undesirable distortion products and aligns well with low output amplitude requirements.

[0027] Quantum computing uses qubits instead of classical computing bits as its basic unit. A qubit (e.g., a quantum binary digit) is a quantum mechanical analog of a classical bit. Whereas a classical bit can use only one of two basic states (e.g., 0 or 1), a qubit can use a superposition of these basic states (e.g., a|0> + |b|1>, where a and b are complex scalars, such that |a|2 + |b|2 = 1). A quantum computer can use a superposition of qubits to perform many calculations simultaneously. 2 + |b| 2= 1), thus allowing multiple qubits to theoretically hold exponentially more information than the same number of classical bits. As such, theoretically, a quantum computer (e.g., a computer that employs qubits instead of just classical bits) can quickly solve problems that are extremely difficult for classical computers. A classical computer's bit is just a binary digit, with a value of 0 or 1. Almost any device with two different states can be used to represent a classical bit: a switch, a valve, a magnet, a coin, or similar binary-type state measurement. A qubit, which participates in the quantum mystery, can occupy a superposition of 0 and 1 states. Not that the qubit can have an intermediate value (such as 0.63); when the state of the qubit is measured, the result is 0 or 1. But during computation, the qubit can act as if it is a mixture of states - for example: 63 percent 0 and 37 percent 1. A general quantum program needs to coordinate the quantum and classical parts of the computation. One way to consider a general quantum program is to identify the processes and abstractions involved in specifying a quantum algorithm, transforming the algorithm into executable form, running experiments or simulations, and analyzing the results. The concept that runs through these processes is the intermediate representation. The intermediate representation (IR) of a computation is neither its source language description nor its target machine instructions, but something in between. A compiler can use multiple IRs during the process of translating and optimizing a program. The input is the source code that describes the quantum algorithm and the compilation time parameter(s). The output is the combined quantum / classical program expressed using a high-level IR. The difference between quantum and classical computers is that quantum computers are probabilistic, so the measurement of the algorithm output provides a proper solution within an algorithm-specific confidence interval. The computation is then repeated until a satisfactory, possible solution certainty can be achieved.

[0028] By using quantum mechanical laws to process information, quantum computers provide novel ways to perform computational tasks such as molecular computation, optical photons, optimization, and more. A number of algorithms have been introduced to efficiently perform such computational tasks. In particular, radio frequency digital-to-analog converters are valuable in a variety of applications, including wireless transmitters and implementing control pulses for qubits. There are challenges with designs that use a voltage-mode representation for signal paths, including high dynamic range requirements at block interfaces, resulting in non-linear behavior and creating higher amplitude distortion products and independent power per block, without opportunities for power efficiency from current reuse. As such, embodiments herein present an efficient current-mode filter design in implementing an integrated RF DAC solution to develop low-power-distortion arbitrary waveform generation applications. This provides reusing current between filters and adjacent stages in the signal chain and avoids introducing additional current-to-voltage conversion in the signal path (e.g., such conversion can be included in the feedback path), which helps limit undesirable distortion products; and it also aligns well with low output amplitude requirements.

[0029] Figure 1 A block diagram of an example system 100 depicting a variable computing component depicted in accordance with one or more embodiments described herein to access data and process the data is shown. The system 100 can facilitate a process of evaluating and identifying a large number of different forms of data using machine learning and training neural networks or other types of models. The system 100 can also generate predictive recommendations at individual levels with context in accordance with one or more embodiments described herein. Aspects of the systems (e.g., system 100, etc.), apparatuses, or processes explained in this disclosure can constitute machine-executable component(s) embodied within machine(s), e.g., embodied in one or more computer readable mediums (or media) associated with one or more machines. Such component(s), when executed by the one or more machines, e.g., computer(s), computing device(s), virtual machine(s), etc. can cause the machine(s) to perform the operations described herein. Repetitive description of like elements employed in one or more embodiments described herein is omitted for sake of brevity.

[0030] The system 100 facilitates an integrated radio frequency digital-to-analog converter (RFDAC) that utilizes a current mode signal path. Embodiments relate to elements of the hold signal path, the RFDAC, the baseband filter, the mirror, and the output stage. Benefits can be achieved by implementing the entire chain in current mode or implementing sub-elements of the chain in current mode.

[0031] The system 100 can optionally include a server device, one or more networks, and one or more devices (not shown). The system 100 can also include or otherwise be associated with a radio frequency digital-to-analog converter 102 operating in current mode, which includes a continuous-time baseband filter 104 operating in current mode, where the inputs and outputs of the system blocks are represented as currents. A mirror component 106 mirrors the filtered current to an output 108 operating in current mode.

[0032] In implementations, the current mode end-to-end path from the radio frequency digital-to-analog converter through the output 108 enables low-power, low-distortion arbitrary waveform generation applications. The continuous-time baseband filter 104 includes a feedback loop that employs at least one first impedance node and at least one second impedance node, where the at least one first impedance node has a higher impedance than the at least one second impedance node, and where the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, and where the continuous-time baseband filter generates a filtered current. The mirror component 106 mirrors the filtered current to the output 108, where it selectively changes the mirror ratio to achieve variable gain with respect to a fine baseline step size.

[0033] The system 100 can be any suitable computing device or set of computing devices that can be communicably coupled to a device, non-limiting examples of which can include, but are not limited to, a server computer, a computer, a mobile computer, a mainframe computer, an automated testing system, a network storage device, a communication device, a web server device, a network switch device, a network routing device, a gateway device, a network hub device, a network bridge device, a control system, or any other suitable computing device. A device can be any device capable of communicating information with the system 100 and / or any other suitable device capable of employing information provided by the system 100. It should be appreciated that the system 100, components, models, or devices can be equipped with communication components (not shown) that enable communication between systems, components, models, devices, etc. over one or more networks.

[0034] The different components of the system 100 can be connected directly or via one or more networks. Such networks can include wired and wireless networks, including but not limited to a cellular network, a wide area network (WAN) (e.g., the Internet), or a local area network (LAN), non-limiting examples of which include cellular, WAN, wireless fidelity (Wi-Fi), Wi-Max, WLAN, radio communication, microwave communication, satellite communication, optical communication, sonic communication, or any other suitable communication technology. Moreover, the above-described systems and / or devices have been described with respect to interactions between multiple components. It can be appreciated that such systems and components can include the components or subcomponents specified therein, some of the specified components or subcomponents, and / or additional components. Subcomponents can also be implemented as components communicatively coupled to other components rather than included within parent components. Further, one or more components and / or subcomponents can be combined into a single component to provide aggregate functionality. These components can also interact with one or more other components not specifically described herein for the sake of brevity but known by those of skill in the art.

[0035] The subject computer processing systems, methods apparatus, and / or computer program products can be used to address new problems that have arisen with advances in technology, computer networks, the Internet, and the like.

[0036] One of the largest growth areas in electronics in today's digital world has been in the application of wireless communications. Modern radio frequency systems such as superconducting qubit controllers are based on wideband multi-channel architectures. Due to the calibration complexity and cost of RF signals, the use of vector signal generators with IQ modulators and analog synthesizers poses a limitation. As such, digital-to-analog conversion is valuable to enable signal processing, modulation, and signal generation. Furthermore, radio frequency digital-to-analog converters (RF DACs) are valuable in a variety of applications, including wireless transmitters and implementing control pulses and addressing signal-to-noise ratios for qubits. In particular, RF DACs ideally enable targeting low distortion and simultaneously minimizing power consumption. Often, these goals form a trade space that can be navigated in the design process. Implementations of RF DAC signal paths can involve voltage-mode signals, current-mode signals, or a combination of both. Embodiments thus present a promising solution by introducing a current-mode signal path design in an integrated digital-to-analog converter. A high-efficiency current-mode filter provides multiple benefits in the context of an end-to-end current-mode analog signal path RF DAC architecture developed for low-power low-distortion arbitrary waveform generation applications. It provides a path to reuse the current between filters and adjacent stages in the signal chain. It also avoids introducing additional current-to-voltage conversion in the signal path (such conversions can be included in feedback paths, for example), which mitigates undesirable distortion products and aligns well with low output amplitude requirements.

[0037] Figure 2An example flow diagram of an integrated radio frequency digital to analog converter utilizing a current mode trans-impedance capacitance filter is shown. As described in flow diagram 200, the system includes a radio frequency digital to analog converter (RFDAC) in which a current mode baseband filter is used. At 202, the continuous time baseband filter includes a feedback loop that employs at least one first impedance node and at least one second impedance node, where the at least one first impedance node has a higher impedance than the at least one second impedance node, and where the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole. At 204, the continuous time baseband filter generates a filtered current. At 206, a mirror component selectively changes a mirror ratio to achieve variable gain with respect to a fine baseline step size. At 208, a scaling component scales an input current of the feedback loop to facilitate coarse gain control. At 210, a monitor component monitors a scaled version of the input current to mitigate distortion interference on the monitoring. An additional set of poles is placed between the continuous time baseband filter and the mirror component to facilitate high order filtering and mitigate impairments to the stability of the continuous time baseband filter. At 212, a subset of a plurality of cascaded continuous time baseband filters provide low pass, band pass, or high pass characteristics with a corner frequency, a quality factor, or a gain control set by digital control. The output from this continuous time filter is a current, and multiple such filters can be easily cascaded to achieve higher order current mode filters. The filters can provide low pass, band pass, or high pass characteristics with the corner frequency, quality factor, and gain step size set by digital control.

[0038] Wireless communication applications are challenging due to the speed and frequency domain performance requirements of modern data converters. High speed digital to analog converters require fewer mixing and filtering stages to produce an effective output. Today's technology advancements face many challenges to meet the ever growing demand for bandwidth in congested spectrum. This increases the complexity of the signal chain as frequency planning compromises size, power, and performance requirements. The ability to utilize spectrum creates enhanced user experiences and enables new system capabilities. Radio frequency converters are used to convert microwave signals to lower or higher frequency ranges for a wide range of processing options. Reducing the size and cost of telecommunication and military systems is driving the evolution of modern digital to analog converters to integrate more functionality into a single chip. Certain high speed digital to analog converters contain digital signal processing and conditioning functions such as filters, complex modulation, and digitally controlled oscillators. This enables efficient and compact direct generation of complex RF signals. In traditional RFDAC architectures, information is processed from one frequency and converted to another. Embodiments disclosed herein perform general signal processing at low frequencies and reduced power consumption.

[0039] Figure 3An example architecture of a radio frequency digital-to-analog converter (RFDAC) signal chain is shown. One method of generating a composite signal is to modulate a carrier signal frequency by a local oscillator using a vector modulator. In RF applications, baseband digital I and Q signals are generated using an arbitrary waveform generator (AWG) that includes two or more synchronized digital-to-analog converters. The RFDAC chain architecture 300 has baseband digital BBI 302 and BBQ 304 signals. Multi-bit baseband digital-to-analog converters (DACs) 306 and 308 take digital bits and convert the digital bits to analog signals depending on the bandwidth of the signal and the sampling clock frequency. This enables the output of a current and provides a filtered and amplified current to a mixer. The signal is processed through low pass filters 306 and 308 to reject out-of-band noise components generated by the digital-to-analog converters 300. The filtered signals are mixed and thus upconverted by mixers 310 and 312 using two carriers (LO-Q and LO-I) with quadrature phases of 0 and 90 degrees for I and Q. The resulting signals are combined by creating a single sideband signal representation using a signal combiner 311. For example, if a (x*y) function needs to be performed in a single sideband representation, variable x can be represented as a combination of 0 and 90 degrees and variable y can be represented as a combination of 0 and 90 degrees. Similar to a scalar multiplication of two vectors, the two variables can then be multiplied and added. The output of the function is processed by a driver DRV 314. A matching network MN 316 is a component that is typically composed of passive elements that do not provide distortion. The matching network 316 transmits a resistance 318 (e.g., 50 ohms) to the impedance needed by the driver to maximize power transfer. The outputs 320 of these DACs are filtered, upconverted using I and Q channel mixers, and the resulting signals are combined and fed through a driver and matching network to a nominal load (e.g., 50 ohms) at the output 320. Filter implementation and the interface between the filter and other elements of the signal chain are important in this design. Continuous time filters are well suited for high dynamic range, low power active filter implementations. Current mode signal processing is well suited for low distortion applications as it reduces voltage swings at various nodes of interest. However, traditional current mode input filters using operational amplifiers consume a lot of power and have limitations in high frequency applications. Continuous time gm-C filters typically provide high input impedance, which leads to higher distortion products. gm-C type filters are well suited for high frequency applications but are very limited in terms of the dynamic range they support as the input is typically a voltage.

[0040] Figure 4 An example block level view architecture of a feedback-based transconductance capacitor baseband filter is shown. The circuit architecture 400 has a DC power supply V DD402. The circuit 400 comprises a buffer BUF 403 and a high impedance Z 404 providing the output impedance from the load transistor. There are two transconductance blocks g m1 410 and g m2 412. The two capacitors with arrows C1 406 and C2 408 show that C1 and C2 can be controlled together or independently. The ratio of transconductance and capacitors determines the quality factor of the filter. The current bleeder IBLD 416 is providing different bias so that the current taken by g m1 410 and the buffer BUF 403 can be different current helpers. The feedback loop will be through Z, BUF, and it takes the following equation:

[0041]

[0042] where Q is the quality factor and it is the ratio of similar quantities, almost constant over process (P), temperature (T) variations. The Q factor can be varied by programming g m1 , g m2 , C1, C2 using digital control. The feedback loop gain reduces distortion and the bandwidth BW can be derived by taking the following equation:

[0043]

[0044] The biasing strategy can be a sub-declaration of optimizing performance, where the biasing strategy is from constant g mThe bias block biases and offsets from 1 / R bias (e.g., hold filter pole tracking). The continuous-time baseband filter uses an input current and provides an output current, and the internal feedback mechanism is performed as a combination of current to voltage and voltage to current conversion. The feedback loop uses at least one high impedance node and at least one low impedance node, where the high impedance node provides the dominant pole and the low impedance node provides the non-dominant pole. Pole splitting ensures stability, and the bias provides a substantially constant separation between the dominant and non-dominant poles to maintain sufficient phase margin. The loop uses a mirror device to mirror the filtered current to the output, and by varying the mirror ratio, variable gain to fine baseline steps can be achieved. Coarse gain control can be achieved by scaling the input current inside the feedback loop, and the auxiliary path can also serve as a path to monitor a scaled version of the input current without additional distortion. Additional poles can be placed between the filter core stage and the mirror stage to achieve higher order filtering without compromising the stability of the filter. The additional poles do not consume current and do not create distortion, and can be implemented using resistors and capacitors. The output of the continuous-time filter is a current, multiple such filters can be cascaded easily to achieve a high order current mode filter. The filter can provide low pass, band pass, or high pass characteristics, with corner frequency, quality factor, and gain step set by digital control.

[0045] Figure 5 An example transistor level drawing of a single ended implementation of filter 500 is shown. The example embodiment is one of a method of construction of a filter. Transistors M PB 502 or M N1 504 can implement a DC offset compensation DAC. Filter 500 has a current mode input / output gm-C filter. The common mode of input current 506 is set and output current 508 is programmed via M NMX 502 and M NC1 504 using drain / gate / source switching elements. This is done by M N2 510 and M N1 512. M PB 502 and M NB514 are PMOS and NMOS bias transistors, respectively. The baseband filter has a current mode input as well as a negative feedback loop. The feedback loop consists of two capacitors CI 516 and C2 518. CI 516 is associated with the dominant pole, where node CI is connected and C2 518 is associated with the non-dominant pole. The feedback loop is connected to one dominant pole and one non-dominant pole. In this way, it provides an optimized space for phase margin and stability purposes. The dominant pole is formed by the output conductance of the transistors and the non-dominant pole is formed by the transconductance of the transistors. The third pole has the input capacitance of the device M NMX522 520 and a resistor R 522. This provides three poles and the third pole can be achieved without any additional current consumption. The output is also a current out 508 and it provides a filter function and a gain function, where the gain is represented by i out / i in . This filter 500 provides the possibility of both low pass or band pass transfer functions. By using a current waveform associated with i out / i in , the transfer function can be derived, where it is a low pass response. Otherwise, the transfer function of the current can be derived by i(M NC1 ) / i in , where it will be a band pass response. Thus, this filter 500 provides both responses simultaneously; it has two poles that are complex conjugates of each other and the real pole formed outside the loop is given by the resistance of M NMX and the input capacitance. II 524 and I2 526, which can use a current mirror, are digitally programmable via V P 530 and V N2 532 networks. M NC2 528 is used as an attenuator to handle the input dynamic range. This is one representation of the example structure. If the NMOS becomes PMOS, then this can be another example representation.

[0046] Figure 6 Another example transistor level diagram showing a single ended implementation of a filter architecture 600 with a DC power supply V DD 602. The filter 600 consists of two transistors M P1 604 and M P2 608. Zl 606 and Z2 610 represent capacitors associated with the dominant pole and the non-dominant pole. Zl 606 and Z2 610 can be represented using series and parallel combinations of at least one reactive element (e.g., capacitor, inductor). The feedback loop provides negative feedback using transistors M PC1 612, M P2 604, M P1608. The composition of the low pass and high pass filters H LP and H HP The transfer function of the variable Gm / C can be represented by the following equation:

[0047]

[0048] where g m1 and g m2 represent the transconductance of the transistors M P1 604 and M P2 608. I in , i out represent the input and output currents, and the capacitances are represented as C1 and C2. HP and LP represent the low pass filter and high pass filter. a represents the ratio between the two transistors M PMY 614 and M P1 604, respectively. The pole is formed by the ratio of G m m and the capacitance, and can be biased so that G m can be constant, where G m m and C can be calibrated independently, or can also be biased where it itself tracks Gm / C. The bias also holds a unique position with the filter 600. The transistors M PMY 614 and M P1 604 can be biased in sub-threshold or strong impulse, where one transistor can be sub-threshold and the other transistor can get a strong impulse. Similar substitutions and combinations can be made with transistors as described in the above examples.

[0049] Figure 7 Another example transistor level diagram of an alternative filter arrangement of embodiments is shown. There are multiple implementation combinations of baseband filters, and these embodiments present one of the implementation methods. As shown in diagram 700A, g m m represents the transconductance of the transistors, and C represents the capacitors. The architecture 700A has a DC power supply V DD 702. In this configuration, impedance Z2 706 is associated with the dominant pole, and Z1 704 is associated with the non-dominant pole. Further, this configuration uses positive feedback, which uses current mode signaling. Another example of embodiments is shown in diagram 700B. In this configuration, impedance Z2 708 is coupled between the gate and drain terminals of M P1 710. This results in a smaller size pole, and Z1 712 is associated with the non-dominant pole. This configuration also uses positive feedback of current mode signaling.

[0050] Figure 8Another example transistor-level diagram showing alternative filter placement for sample embodiments. There are many combinations of baseband filter implementations, and these embodiments present one of the implementation methods. As shown in diagram 800A, impedance Z2 804 is associated with a dominant pole and Z1 802 is associated with a non-dominant pole. This configuration uses negative feedback that uses current-mode signaling. Similarly, the architecture shown in 800B demonstrates the introduction of additional current-mode signaling branches within the feedback loop (M N1 Depending on the signal scaling and polarity, the filter order can be increased.

[0051] Figure 9 Another example transistor-level diagram showing alternative filter placement for sample embodiments. There are many combinations of baseband filter implementations, and these embodiments present one of the implementation methods. As shown in diagram 900A, this configuration has impedance Z2 902 associated with a dominant pole and Z1 904 associated with a non-dominant pole. This configuration uses negative feedback that uses current-mode signaling. Impedance Z3 906 is inserted in the loop to implement a higher order filter and is comprised of at least one passive element and can be placed at the gate of M N2 904. Similarly, the diagram shown in 900B has additional impedances where impedance Z2 908 is associated with a dominant pole and Z1 910 is associated with a non-dominant pole. This configuration uses positive feedback that uses current-mode signaling.

[0052] Figure 10 Another example transistor-level diagram showing alternative filter placement for sample embodiments. There are many combinations of baseband filter implementations, and these embodiments present one of the implementation methods. As shown in diagram 1000A, this configuration has impedance Z2 1002 associated with a dominant pole and Z1 1004 associated with a non-dominant pole. This diagram is a differential filter where the transistors are transposed to the differential side 1006. Additionally, the diagram shown in 1000B is configured where impedance Z2 1008 is associated with a dominant pole and Z1 1010 is associated with a non-dominant pole. The additional series impedance at the input results in neutralization and can reduce the load on the driver circuit. The neutralization network is comprised of at least one passive element.

[0053] The novelty of these embodiments is the use of a current mode gm-C continuous time filter. This approach can implement two poles within the feedback loop. The feedback loop can implement complex pole pairs. This feedback provides linearization that results in low distortion. Real poles are implemented outside the loop. In addition, variable gain is implemented by using multiple current mirror elements and enabling M out of N elements to achieve the desired output current. This current can be shared between the mixer and the baseband filter output stage, which reduces power. Three poles can be implemented while causing distortion of only one conductor stage. The concept can be extended by seamless cascading of multiple current mode filters with common mode compatibility. The input stage can be shared with the previous stage output to further reduce power consumption. The output stage can be shared with the next stage input to further reduce power consumption. Delayed signals from I and Q can be used to implement complex filter implementations.

[0054] Figure 11 An example of simulation results for the current mode transconductance capacitance filter is shown. The simulation shows the frequency response 1102 at the 3dB cutoff frequency. The intermodulation results 1104 show the results varying based on the spectrum on the x-axis. The loop stability is based on the varying spectrum 1106 and the resulting output noise of the baseband filter 1108. These simulations determine that this type of current mode baseband filter is necessary for the overall requirements of the right controller block in quantum applications. This can also be used in a general sense for any transmitter, such as a radio transmitter. The output results and intermodulation results show that the filter provides a path to current reuse between the filter and any adjacent stage in the signal chain. It avoids introducing additional current-voltage conversion in the signal path, which helps to limit undesirable distortion products. It also aligns well with low output amplitude requirements.

[0055] Figure 12 An example of a schematic extension of an array-based system is shown. As shown in the illustration 1200, the input is fed baseband signals I and Q represented by BBI1 1202 and BBQ1 1204. This can also be extended to n signals BBI N 1206 and BBQ N1208. In this flow, the filter element is shared between multiple channels. In the case of input and output as current, current is taken from one filter to another filter 1210 and 1212. Addition or subtraction 1214 can also be performed in any of these interfaces in the simplest way to produce an output 1216 with 50 ohm resistance. Another set of applications can also be performed where one filter in the array, one filter in a low pass configuration, and another filter with a band pass response can be used. In this way, it provides different types of signals to different sensors or qubits. Higher order filtering can be achieved by cascading multiple filters with common mode compatibility. Furthermore, low distortion polyphase filtering can be achieved by cross-coupled quadrature phase filters.

[0056] Figure 13 An example schematic showing a cascaded extension of complementary stages is shown. The illustration in block 1300 shows how the cascading can be done where filter 1302 is a 3rd order filter, but it can only consume current for a 2nd order filter. This can put it in a loop. The output of the NMOS stage is coupled 1304 directly to the input of the PMOS stage 1306. The filter shown in this illustration is a 3rd order filter, and the cascading is resulting in a 6th order that uses minimum power consumption and low distortion. The illustration shows a single stage system, but the loop configuration can also be made differential. Filter 1306 is also a 3rd order filter, and two similar filters can be used to construct a high order filter without losing dynamic range, and thus it makes it simple to cascade the two filters. In previous embodiments, OTA-based transimpedance filters are typically used in wireless systems. The filter typically uses shunt-shunt feedback, however the gain-bandwidth requirement results in high power consumption. Both low and band pass transfer functions can be implemented. For a 4th order function, this proposed structure can work in a feedback loop with only one high impedance node. It is compact due to the lack of resistors. In some cases, an open loop cascaded structure is used with a common gate input, and typically with a current to voltage converter. The proposed structure uses feedback to implement two complex poles, resulting in two real poles. This limits the reliability of the filter transfer function.

[0057] This current mode solution provides a path of reusing current and low distortion that is well tuned to the requirements of low temperature waveform generation. The novelty of these embodiments is the use of a transconductance capacitor filter (gm-C). The main contribution is the implementation of a gm-C filter that provides low input impedance. Traditional gm-C filters have high input impedance, and typically provide an input voltage to an output voltage transfer function. The implementation in commercially available CMOS technology is fully feasible. This circuit approach is valuable for implementing CMOS controlled pulse generation analog circuits to enable enhanced scalability of future quantum computing systems.

[0058] To provide context for aspects of the disclosed subject matter, Figure 14 and the following discussion is intended to provide a general description of a suitable environment in which aspects of the disclosed subject matter can be implemented. Figure 14 A block diagram of an example, non-limiting operating environment in which one or more embodiments described herein can be facilitated is shown. Repetitive description of like elements employed in other embodiments described herein is omitted for sake of brevity.

[0059] Referring to Figure 14 A suitable operating environment 1400 for implementing various aspects of the disclosure can also include the computer 1412. The computer 1412 can also include a processing unit 1414, a system memory 1416, and a system bus 1418. The system bus 1418 couples system components including, but not limited to, the system memory 1416 to the processing unit 1414. The processing unit 1414 can be any of various available processors. Dual microprocessors and other multiprocessor architectures can also be employed as the processing unit 1414. The system bus 1418 can be any of several types of bus structures including, but not limited to, memory buses or memory controllers, peripheral buses or external buses, and / or a local bus using any of a variety of bus architectures including, but not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Universal Serial Bus (USB), Advanced Graphics Port (AGP), Firewire (IEEE 1394), and Small Computer Systems Interface (SCSI).

[0060] The system memory 1416 can also include volatile memory 1420 and nonvolatile memory 1422. The non-volatile memory 1422 can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or a different type of nonvolatile memory used for storage of instructions or data structures. The volatile memory 1420 can include registers, cache memory, and / or buffer storage. Figure 14 Exemplary, non-exhaustive, list of R / W storage devices suitable for embodying memory 1420 include the following: disk drives, floppy disks, hard disk drives, or optical discs, tape drives, zip drives, LS-100 drives, flash memory cards, and / or memory sticks. To facilitate connection of the disk drives 1424 to the system bus 1418, a removable or non-removable interface is typically used, such as interface 1426. Figure 14Software is also depicted as being used in mediating between the user and the basic computer resources described in the suitable operating environment 1400. Such software can also include, for example, an operating system 1428. The operating system 1428, which can be stored on disk storage 1424, acts to control and allocate resources of the computer 1412.

[0061] System applications 1430 take advantage of the management of resources by the operating system 1428 through program modules 1432 and program data 1434, such as stored on system memory 1416 or disk storage 1424. It is to be appreciated that this disclosure can be implemented with both different operating systems or combinations of operating systems. A user enters commands or information into the computer 1412 through input device(s) 1436. Input devices 1436 include, but are not limited to, a pointing device such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, game pad, satellite dish, scanner, TV tuner card, digital camera, digital video camera, web camera, and the like. These and other input devices connect to the processing unit 1414 through the system bus 1418 via interface port(s) 1438. Interface port(s) 1438 include, for example, a serial port, a parallel port, a game port, and a universal serial bus (USB). Output device(s) 1440 use some of the same type of ports as input device(s) 1436. Thus, for example, a USB port can be used to provide input to computer 1412, and to output information from computer 1412 to an output device 1440. Output adapter 1442 is provided to illustrate that there are some output devices 1440 like monitors, speakers, and printers, among other output devices 1440, that require special adapters. The output adapters 1442 include, by way of illustration and not limitation, video and sound cards that provide a connection between the output device 1440 and system bus 1418. It should be noted that other devices and / or systems of devices provide both input and output capabilities such as remote computer(s) 1444.

[0062] The computer 1412 can operate in a networked environment using logical connections to one or more remote computers, such as a remote computer 1444. The remote computer 1444 can be a computer, a server, a router, a network PC, a workstation, a microprocessor-based appliance, a peer device, or other common network node, and typically includes many or all of the elements described relative to the computer 1412. For purposes of brevity, only a memory storage device 1446 is illustrated with the remote computer 1444. The remote computer 1444 is logically connected to the computer 1412 through a network interface 1448 and then physically connected via a communication connection 1450. The network interface 1448 encompasses wire and / or wireless communication networks such as local-area networks (LAN), wide-area networks (WAN), cellular networks, etc. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring and others. WAN technologies include, but are not limited to, point-to-point links, circuit-switching networks like Integrated Services Digital Networks (ISDN) and variations thereon, packet-switching networks, and Digital Subscriber Lines (DSL). The communication connection 1450 refers to the hardware / software employed to connect the network interface 1448 to the system bus 1418. While the communication connection 1450 is shown for illustrative clarity inside the computer 1412, it can also be external to the computer 1412. The hardware / software for connecting the network interface 1448 to the system bus 1418 can also include, for exemplary purposes only, internal and external technologies such as modems including regular telephone grade modems, cable modems and DSL modems, ISDN adapters, and Ethernet cards.

[0063] Referring now to the Figure 15 , an illustrative cloud computing environment 1550 is depicted. As shown, cloud computing environment 1550 includes one or more cloud computing nodes 1510 with which a cloud consumer can engage with to use the cloud computing nodes 1510. Although Figure 15 is shown with cloud computing nodes 1510 being single machines, cloud computing nodes 1510 can also include a plurality of machines (not shown), virtual organizations network computing resources, network storage available virtual machines (not shown), or a combination of machines, virtual organizations network computing resources, network storage available virtual machines (not shown). Cloud computing environment 1550 can include, or be implemented by, one or more quantum platforms (e.g., quantum computers, quantum hardware, quantum software, etc.) with which a cloud consumer can engage with to use the quantum platforms. Cloud computing nodes 1510 can be communicably coupled to each other by various networking and / or communication means, such as a network 1520 (e.g., the Internet or a private, proprietary network) and / or a storage area network (SAN) 1522 (e.g., a Fibre Channel SAN). Cloud computing nodes 1510 can be grouped (not shown) physically or virtually, in one or more networks, such as Private, Community, Public, or Hybrid clouds as described hereinabove, or a combination thereof. This allows cloud computing environment 1550 to offer infrastructure, platforms and / or software as services with Figure 15The types of computing devices 1554A-N shown in FIG. 15 are intended to be illustrative only and computing nodes 1510 and cloud computing environment 1550 can communicate with any type of computerized device over any type of network and / or network addressable connection (e.g., using a web browser).

[0064] Referring now to Figure 16 , a set of functional abstraction layers provided by cloud computing environment 1550 Figure 15 ) is shown. It should be understood that Figure 16 the components, layers, and functions shown in FIG. 15 are intended to be illustrative only and embodiments of the application are not limited thereto. As depicted, the following layers and respective functions are provided:

[0065] Hardware and software layer 1660 includes hardware and software components. Examples of hardware components include: mainframes 1661; RISC (Reduced Instruction Set Computer) architecture based servers 1662; servers 1663; blade servers 1664; storage devices 1665; and networks and networking components 1666. In some embodiments, software components include network application server software 1667, quantum platform routing software 1668, and / or quantum software Figure 16 (not shown in FIG. 15).

[0066] Virtualization layer 1670 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual servers 1671; virtual storage 1672; virtual networks 1673, including virtual private networks; virtual applications and operating systems 1674; and virtual clients 1675.

[0067] In one example, management layer 1680 can provide the functions described below. Resource provisioning 1681 provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. Metering and Pricing 1682 provide cost tracking as resources are utilized within the cloud computing environment, and billing or invoicing for consumption of these resources. In one example, these resources can include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal 1683 provides access to the cloud computing environment for consumers and system administrators. Service level management 1684 provides cloud computing resource allocation and management such that required service levels are met. Service Level Agreement (SLA) planning and fulfillment 1685 provide pre-arrangement for, and procurement of, cloud computing resources for which a future requirement is anticipated in accordance with an SLA.

[0068] Workload layer 1690 provides examples of functionality that can be utilized by the cloud computing environment. Non-limiting examples of what can be provided from this layer include: map and navigation 1691; software development and lifecycle management 1692; virtual classroom education delivery 1693; data analytics processing 1694; transaction processing 1695; and quantum state preparation software 1696.

[0069] The present application can be a system, a method, an apparatus and / or a computer program product at any possible technical detail level of integration. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application. The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium can also include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in grooves of a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0070] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in a computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions to a computer readable storage medium within the respective computing / processing device for storage. Computer readable program instructions for carrying out operations of the present application can be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computing / processing device, partly on the user's computing / processing device, as a stand-alone software package, partly on the user's computing / processing device and partly on a remote computing / processing device or entirely on the remote computing / processing device. In the latter scenario, the remote computing / processing device can be connected to the user's computing / processing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspect(s) of the present application.

[0071] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational acts to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0072] The flow diagrams and block diagrams in the drawings are described with reference to methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer readable program instructions. These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flow diagrams and / or block diagrams block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including

[0073] While the subject matter has been described above in the general context of computer-executable instructions of a computer program product that runs on a computer and / or computers, those skilled in the art will recognize that the disclosure also can or can not be implemented in conjunction with other program modules. Generally, program modules include routines, programs, components, data structures, etc. that perform particular tasks and / or implement particular abstract data types. Moreover, those skilled in the art will appreciate that the inventive computer-implemented methods can be practiced with other computer system configurations, including single-processor or multiprocessor computer systems, minicomputers, mainframe computers, as well as computers, hand-held computing devices (e.g., PDA, phone), microprocessor-based or programmable consumer or industrial electronics, etc. The illustrated aspects can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. However, some, if not all, aspects of this disclosure can be practiced on stand-alone computers. In a distributed computing environment, program modules can be located in both local and remote memory storage devices.

[0074] As used in this application, the terms "component," "system," "platform," "interface," and the like can refer to and / or can include a computer-related entity or an entity that is related to an operational machine with one or more specific functionalities. The entities disclosed herein can be either hardware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a server and the server can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, co-resident, and / or distributed amongst one computer and / or across multiple computers. In another example, a component can execute from various computer readable media having various data structures stored thereon. The components can communicate via local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal). As another example, a component can be an apparatus with specific functionality provided by mechanical parts operated by electric or electronic circuitry, which is operated by a software or firmware application executed by a processor. In such a case, the processor can be internal or external to the apparatus and can execute at least a part of the software or firmware application. As yet another example, a component can be an apparatus that provides specific functionality through electronic components without mechanical parts, wherein an electronic component can include a processor or other portion that executes software or firmware that conveys at least a part of the functionality of the electronic component. In an aspect, a component can emulate an electronic component via a virtual machine, for example, within a cloud computing system.

[0075] Furthermore, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless specified otherwise, or clear from context, "X employs A or B" is intended to mean any of the natural inclusive permutations. That is, if X employs A; X employs B; or X employs both A and B, then "X employs A or B" is satisfied under any of the foregoing instances. Moreover, articles "a" and "an" as used in the subject specification and annexed drawings should generally be construed to mean "one or more" unless specified otherwise or clear from context to be directed to a singular form. As used herein, the terms "example" and / or "exemplary" are utilized to mean serving as an example, instance, or illustration. For the avoidance of doubt, the subject matter disclosed herein is not limited by such examples. In addition, any aspect or design described herein as an "example" and / or "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects or designs, nor is it meant to preclude equivalent exemplary structures and techniques known to those of ordinary skill in the art.

[0076] As employed in this specification, the term "processor" can refer to substantially any computing processing unit or device comprising single-core processors; single-processors with software multithread execution capability; multi- core processors; multi-core processors with software multithread execution capability; multi-core processors with hardware multithread technology; parallel platforms; and parallel platforms with distributed shared memory. Additionally, a processor can refer to an integrated circuit, an application specific integrated circuit (ASIC), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic controller (PLC), a complex programmable logic device (CPLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Further, processors can utilize nano- scale architectures such as, but not limited to, molecular and quantum-dot based transistors, switches and gates, in order to optimize space usage or enhance performance of user equipment. A processor can also be implemented as a combination of computing processing units. In this disclosure, terms such as "store," "storage," "data store," data storage," "database," and substantially any other information storage component relevant to operation and functionality of a component are utilized to refer to "memory components," entities embodied in a "memory," or components comprising a memory. It is appreciated that memory and / or memory components described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of illustration, and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, or nonvolatile random access memory (RAM) (e.g., ferroelectric RAM (FeRAM)). Volatile memory can include RAM, which, as

[0077] The foregoing description includes only examples of systems and computer-implemented methods. Of course, for the purposes of describing this disclosure, it is impossible to describe every conceivable combination of components or computer-implemented method; however, those skilled in the art will recognize that many further combinations and arrangements of this disclosure are possible. Furthermore, with regard to the use of terms such as “comprising,” “having,” “possessing,” etc., in the detailed description, claims, appendices, and drawings, such terms are intended to be inclusive in a manner similar to the term “comprising,” as “comprising” is interpreted when used as a transitional word in the claims.

[0078] Various embodiments have been described for illustrative purposes, but the description is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A filter stage system, comprising: a continuous-time baseband filter including a feedback loop employing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, wherein the feedback loop includes the at least one first impedance node, the at least one second impedance node, a buffer, a first transconductance block, and a second transconductance block, and wherein the continuous-time baseband filter generates a filtered current; and a mirroring component that mirrors the filtered current to an output.

2. The filter stage system of claim 1, wherein, The mirroring component selectively changes a mirroring ratio to achieve a variable gain.

3. The filter stage system of claim 1, further comprising a scaling component that scales an input current of the feedback loop to facilitate coarse gain control.

4. The filter stage system of claim 3, further comprising a monitoring component that monitors a scaled version of the input current to mitigate distortion interference.

5. The filter stage system of claim 1, further comprising a set of poles interposed between the continuous-time baseband filter and the mirroring component to facilitate high order filtering and mitigate impairments to stability of the continuous-time baseband filter.

6. The filter stage system of claim 1, further comprising a plurality of continuous-time baseband filters cascaded in series.

7. The filter stage system of claim 6, wherein, A subset of the plurality of continuous-time baseband filters provides a low pass, band pass, or high pass characteristic having a corner frequency, a quality factor, or a gain control set by digital control.

8. The filter stage system of claim 1, wherein, The feedback loop employs the following equation: where C1 and C2 are capacitors, g m1 is the first transconductance block, g m2 is the second transconductance block, Q is the quality factor, and BW is the bandwidth.

9. The filter stage system of claim 1, wherein, The continuous-time baseband filter is single-ended.

10. The filter stage system of claim 1, wherein, The continuous-time baseband filter is differential.

11. The filter stage system of claim 4, wherein, At least one of the continuous-time baseband filter, the mirroring component, the scaling component, or the monitoring component is a cryogenic electronic component.

12. A method for quantum computing, comprising: using a continuous-time baseband filter including a feedback loop employing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, wherein the feedback loop includes the at least one first impedance node, the at least one second impedance node, a buffer, a first transconductance block, and a second transconductance block, and wherein the continuous-time baseband filter generates a filtered current; and using a mirroring component that mirrors the filtered current to an output.

13. The method of claim 12, further comprising: using the mirroring component to selectively change a mirroring ratio to achieve a variable gain.

14. The method of claim 12, further comprising: using a scaling component to scale an input current of the feedback loop to facilitate coarse gain control.

15. The method of claim 14, further comprising: using a monitoring component to monitor a scaled version of the input current to mitigate distortion interference.

16. The method of claim 12, further comprising: using an additional set of poles placed between the continuous-time baseband filter and the mirror component to facilitate high order filtering and mitigate compromising stability of the continuous-time baseband filter.

17. The method of claim 12, further comprising: using a plurality of continuous-time baseband filters cascaded in series.

18. The method of claim 17, further comprising: using a subset of the plurality of continuous-time baseband filters cascaded in series to provide low pass, band pass or high pass characteristics with a corner frequency, a quality factor, or a gain control set by digital control.

19. The method of claim 12, further comprising: the feedback loop employs the following equation: where C1 and C2 are capacitors, g m1 is the first transconductance block, g m2 is the second transconductance block, Q is the quality factor, and BW is the bandwidth.

20. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to: A continuous-time baseband filter using a feedback loop employing at least one first impedance node and at least one second impedance node, wherein the at least one first impedance node has a higher impedance than the at least one second impedance node, and wherein the at least one first impedance node provides a dominant pole and the at least one second impedance node provides a non-dominant pole, wherein the feedback loop comprises the at least one first impedance node, the at least one second impedance node, a buffer, a first transconductance block and a second transconductance block, and wherein the continuous-time baseband filter generates a filtered current; and using a mirror component to mirror the filtered current to an output.

21. The computer program product of claim 20, the program instructions executable by the processor to further cause the processor to: selectively vary a mirror ratio using the mirror component to achieve variable gain.

22. The computer program product of claim 20, the program instructions executable by the processor to: scale an input current of the feedback loop using a scaling component to facilitate coarse gain control.

23. The computer program product of claim 22, the program instructions executable by the processor to further cause the processor to: monitor a scaled version of the input current using a monitoring component to mitigate distortion interference.

24. A system for quantum computing comprising means for performing the steps of the method of any of claims 12-19, respectively.

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