A driving circuit and chip for power semiconductor switching device

Abstract

The present application discloses a driving circuit and chip for a power semiconductor switching device, wherein the power semiconductor switching device includes a first power switching device and a second power switching device arranged between an operating voltage and a reference voltage, a first node between the first power switching device and the second power switching device is used to connect a load, and the driving circuit includes: a driving unit, which is used to generate a driving signal at the output end of the driving circuit, the output end is used to connect the control end of the first power switching device, the driving unit includes a first leakage branch and a second leakage branch connected in parallel; a detection unit, which connects the first node and the driving unit, the detection unit is used to detect the first node voltage of the first node, and control the conduction or disconnection of the second leakage branch according to the first node voltage, thereby controlling the leakage speed of the driving signal. The present application controls the disconnection of the second leakage branch when the detection unit detects that the voltage of the first node is abnormal, thereby reducing the leakage speed of the driving signal.

Description

Technical Field

[0001] The present application relates to the field of high-voltage drive switch devices, and in particular to a drive circuit and chip for power semiconductor switch devices. Background Art

[0002] The bus voltage of the working system of the high-voltage gate driver chip is very high, which can reach hundreds of volts or even thousands of volts. In the system where the power device is used as the switching device, especially when the switching frequency is very fast, the high-amplitude voltage or current change in a short time will produce serious electrical stress. For example, the rapid change of the injection current can cause a serious VS negative voltage shock, which can induce the latch effect of the driver tube. Summary of the invention

[0003] The present application at least provides a driving circuit and chip for a power semiconductor switching device.

[0004] In a first aspect, the present application provides a driving circuit for a power semiconductor switching device, wherein the power semiconductor switching device includes a first power switching device and a second power switching device arranged between an operating voltage and a reference voltage, and a first node between the first power switching device and the second power switching device is used to connect a load, and the driving circuit includes:

[0005] A driving unit, used to generate a driving signal at an output end of the driving circuit, wherein the output end is used to connect to a control end of the first power switch device, and the driving unit includes a first leakage branch and a second leakage branch connected in parallel;

[0006] The detection unit is connected to the first node and the driving unit, wherein the detection unit is used to detect a first node voltage of the first node, and control the conduction or disconnection of the second leakage branch according to the first node voltage, thereby controlling the leakage speed of the driving signal.

[0007] A second aspect of the present application provides a chip, comprising the driving circuit as described above.

[0008] The beneficial effect of the present application is: different from the prior art, the present application detects the first node voltage of the first node through a detection unit, and when the first node voltage is detected to be abnormal, the second leakage branch is controlled to be disconnected, thereby reducing the leakage speed of the driving signal and preventing the latch effect caused by the excessive leakage speed of the driving signal.

[0009] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 It is a structural schematic diagram of a high voltage gate drive switch circuit in the prior art;

[0012] Figure 2 is a schematic structural diagram of an embodiment of a driving circuit of the present application;

[0013] Figure 3 yes Figure 2 The structural diagram of the detection unit;

[0014] Figure 4 yes Figure 2 A schematic diagram of the structure of the first inverter group;

[0015] Figure 5 yes Figure 2 A schematic diagram of the structure of the second inverter group;

[0016] Figure 6 It is a schematic diagram of the structure of a chip embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solution of the present application, the driving circuit and chip provided by the present application are further described in detail below in conjunction with the accompanying drawings and specific implementation methods. It is understandable that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0018] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0019] See also Figure 1 , Figure 1 Schematic diagram of the structure of the high voltage gate drive switch circuit in the prior art. Figure 1As shown, the high-voltage gate drive switch circuit includes a gate drive circuit and a working circuit.

[0020] The input terminal IN of the gate drive circuit inputs a control signal, and the control signal is transmitted to the control terminal of the PMOS tube and the NMOS tube through a multi-stage inverter, that is, transmitted to the gate of the PMOS tube and the NMOS tube to control the conduction and disconnection of the PMOS tube and the NMOS tube. The source of the PMOS tube receives the working voltage VB, the drain of the PMOS tube is connected to the drain of the NMOS tube, and the signal output terminal HO is formed between the drain of the NMOS tube and the drain of the PMOS tube.

[0021] The working circuit includes a first power switch device Q1, a second power switch device Q2 and a load L load The control end of the first power switch device Q1 is connected to the signal output end HO for receiving a control signal, the first path end of the first power switch device Q1 receives the bus voltage VP, the second path end of the first power switch device Q1 is connected to the first path end of the second power switch device Q2, and the second path end of the second power switch device Q2 is connected to the ground voltage VCOM. A node VS is formed between the second path end of the first power switch device Q1 and the first path end of the second power switch device Q2 for connecting a load L load .

[0022] In this embodiment, the first power switch device Q1 and the second power switch device Q2 are both IGBTs (Insulated Gate Bipolar Transistor), and the control end, the first path end and the second path end of the first power switch device Q1 and the second power switch device Q2 are the gate, collector and emitter of the IGBT respectively.

[0023] In other embodiments, the first power switch device Q1 and the second power switch device Q2 may be power devices such as power MOS tubes or IGCTs (Integrated Gate Commutated Thyristors).

[0024] When the first power switch device Q1 and the second power switch device Q2 are power MOS tubes, the control end, the first path end and the second path end of the first power switch device Q1 and the second power switch device Q2 are respectively the gate, source and drain of a PMOS tube; or, the control end, the first path end and the second path end of the first power switch device Q1 and the second power switch device Q2 are respectively the gate, drain and source of an NMOS tube.

[0025] When the gate of the PMOS tube receives a high-level control signal and the gate of the NMOS tube receives a low-level control signal, the PMOS tube is turned on and the NMOS tube is turned off. The working voltage VB is output to the first power switch device Q1 through the PMOS tube, that is, the control terminal of the first power switch device Q1 receives the control signal output by the signal output terminal HO as a high-level signal, the first power switch device Q1 is turned on, and the bus voltage VP generates a working current through the first power switch device Q1 and flows to the load L load At this time, the working current flows from the bus voltage VP to the parasitic inductance L1 of the first power switch device Q1, and then to the load L load .

[0026] When the gate of the PMOS tube receives a low-level control signal and the gate of the NMOS tube receives a high-level control signal, the NMOS tube is turned on and the PMOS tube is turned off. At this time, the control signal output by the signal output terminal HO received by the control terminal of the first power switch device Q1 is a low-level signal, the first power switch device Q1 is turned off, and the gate charge of the first power switch device Q1 is released through the NMOS tube, that is, the signal output terminal HO generates a sink current.

[0027] Since the load L load is a large inductor, flowing through the load L load The working current cannot change suddenly, so it flows through the diode D2 of the second power switch device Q2. At this time, the working current flows from the ground voltage VCOM to the parasitic inductance L2 of the second power switch device Q2, and then flows to the load L load The parasitic inductance L2 generates an induced electromotive force due to the working current, so that the potential of the VS point is lower than the ground voltage VCOM, that is, a negative voltage is generated at the VS point.

[0028] When the turn-off frequency of the first power switch device Q1 is faster, the sinking current generated by the signal output terminal HO changes faster, and the current value of the sinking current is larger, and the probability of generating a latch effect is higher.

[0029] In order to solve the problem in the prior art that the rapid change of the injection current causes a serious VS negative pressure shock and induces a latching effect on the driver tube, the present application provides a driving circuit for a power semiconductor switch device. Figure 2-Figure 5 , Figure 2 is a schematic structural diagram of an embodiment of a driving circuit of the present application; Figure 3 yes Figure 2 The structural diagram of the detection unit; Figure 4 yes Figure 2 A schematic diagram of the structure of the first inverter group; Figure 5 yes Figure 2 Schematic diagram of the structure of the second inverter group.

[0030] like Figure 2As shown, the driving circuit 1 includes a driving unit 11 and a detecting unit 12. The driving circuit 1 is connected to the working circuit 2 and drives the working circuit 2 to work. Figure 1 The working circuit is not described in detail here. A first node a is formed between the first power switch device Q1 and the second power switch device Q2 for connecting a load L load and the detection unit 12.

[0031] The driving unit 11 is connected between the first working voltage VB and the second working voltage VS', and is used to receive the control signal input from the input terminal IN of the driving circuit 1, and generate a driving signal HO at the output terminal of the driving circuit 1, wherein the output terminal of the driving circuit 1 is connected to the control terminal of the first power switch device Q1. Optionally, in other embodiments, the second working voltage may be a reference ground voltage VCOM.

[0032] The driving unit 11 includes a first leakage branch 111 , a second leakage branch 112 , a pull-up circuit 113 , a first inverter group 114 and a second inverter group 115 , wherein the first leakage branch 111 and the second leakage branch 112 are arranged in parallel.

[0033] The first leakage branch 111 includes a first semiconductor device 1111 connected between the output end of the driving circuit 1 and the second working voltage VS', the control end of the first semiconductor device 1111 is connected to the input end IN of the driving circuit 1, the first channel end of the first semiconductor device 1111 is connected to the output end of the driving circuit 1, and the second channel end of the first semiconductor device 1111 is connected to the second working voltage VS'. Specifically, the first semiconductor device 1111 is an NMOS transistor, and the control end, the first channel end, and the second channel end of the first semiconductor device 1111 are the gate, the drain, and the source of the NMOS transistor, respectively.

[0034] The second leakage branch 112 includes a first switch 1121 and a second semiconductor device 1122 connected in series between the output end of the driving circuit 1 and the second working voltage VS', wherein the control end of the first switch 1121 is connected to the detection unit 12 to be turned on or off according to the first node voltage VS of the first node a detected by the detection unit 12, thereby controlling the second leakage branch 112 to be turned on or off.

[0035] Specifically, the first channel end of the first switch 1121 is connected to the output end of the driving circuit 1, the second channel end of the first switch 1121 is connected to the first channel end of the second semiconductor device 1122, the second channel end of the second semiconductor device 1122 is connected to the second working voltage VS', and the control end of the second semiconductor device 1122 is connected to the input end IN of the driving circuit 1. The first switch 1121 and the second semiconductor device 1122 are both NMOS transistors, and the control end, the first channel end, and the second channel end of the first switch 1121 and the second semiconductor device 1122 are the gate, drain, and source of the NMOS transistor, respectively.

[0036] The pull-up circuit 113 includes a third semiconductor device 1131 , which is connected between the output terminal of the driving circuit 1 and the first working voltage VB to pull up the driving signal so that the first power switch device Q1 receives a high level signal.

[0037] The control end of the third semiconductor device 1131 is connected to the input end IN of the driving circuit 1, the first channel end of the third semiconductor device 1131 is connected to the first working voltage VB, and the second channel end of the third semiconductor device 1131 is connected to the output end of the driving circuit 1. Specifically, the third semiconductor device 1131 is a PMOS transistor, and the control end, the first channel end, and the second channel end of the third semiconductor device 1131 are the gate, source, and drain of the PMOS transistor, respectively.

[0038] The first inverter group 114 is connected between the first operating voltage VB and the second operating voltage VS', and is connected between the pull-up circuit 113 and the input terminal IN of the driving circuit 1, and is used to output a third control signal to the third semiconductor device 1131 to control the conduction or disconnection of the third semiconductor device 1131, thereby controlling the conduction or disconnection of the pull-up circuit 113.

[0039] Specifically, Figure 4 As shown, the first inverter group 114 includes a first inverter 1141 , a second inverter 1142 and a third inverter 1143 .

[0040] The first end of the first inverter 1141 is connected to the input terminal IN of the driving circuit 1, the second end is connected to the first voltage VB, the third end is connected to the second voltage VS', and the fourth end is connected to the first end of the second inverter 1142; the second end of the second inverter 1142 is connected to the first voltage VB, the third end is connected to the second voltage VS', and the fourth end is connected to the first end of the third inverter 1143; the second end of the third inverter 1143 is connected to the first voltage VB, the third end is connected to the second voltage VS', and the fourth end is connected to the control end of the third semiconductor device 1131, and outputs a third control signal to the third semiconductor device 1131 to control the conduction or disconnection of the third semiconductor device 1131. Among them, the first end and the fourth end of the first inverter 1141, the second inverter 1142 and the third inverter 1143 are the signal input end and the output end of the first inverter 1141, the second inverter 1142 and the third inverter 1143 respectively.

[0041] Among them, the first inverter 1141, the second inverter 1142 and the third inverter 1143 are all composed of a PMOS tube and an NMOS tube connected in series, and the second end and the third end of the first inverter 1141, the second inverter 1142 and the third inverter 1143 are the source of the PMOS tube and the source of the NMOS tube respectively.

[0042] The second inverter group 115 is connected between the first operating voltage VB and the second operating voltage VS', and is connected between the first leakage branch 111 and the second leakage branch 112 and the input terminal IN of the driving circuit 1, and is used to output a fourth control signal to the first semiconductor device 1111 and the second semiconductor device 1122 to control the conduction or disconnection of the first semiconductor device 1111 and the second semiconductor device 1122, thereby controlling the conduction or disconnection of the first leakage branch 111 and the second leakage branch 112.

[0043] Specifically, Figure 5 As shown, the second inverter group 115 includes a fourth inverter 1151 , a fifth inverter 1152 , a sixth inverter 1153 and a third resistor 1154 .

[0044] The first end of the fourth inverter 1151 is connected to the input terminal IN of the driving circuit 1, the second end is connected to the first voltage VB, the third end is connected to the second voltage VS', and the fourth end is connected to the first end of the fifth inverter 1152; the second end of the fifth inverter 1152 is connected to the first voltage VB, the third end is connected to the second voltage VS', and the fourth end is connected to the first end of the sixth inverter 1153; the second end of the sixth inverter 1153 is connected to the first voltage VB, the third end is connected to the second voltage VS', and the fourth end is connected to the control end of the first semiconductor device 1111 and the second semiconductor device 1122. The first end and the fourth end of the fourth inverter 1151, the fifth inverter 1152 and the sixth inverter 1153 are the signal input end and the output end of the fourth inverter 1151, the fifth inverter 1152 and the sixth inverter 1153 respectively.

[0045] One end of the third resistor 1154 is connected to the first voltage VB, and the other end of the third resistor 1154 is connected to a sixth node f formed between the fourth end of the sixth inverter 1153 and the control end of the first semiconductor device 1111 and the second semiconductor device 1122. The sixth node f is used to output a fourth control signal to the first semiconductor device 1111 and the second semiconductor device 1122 to control the conduction or disconnection of the first semiconductor device 1111 and the second semiconductor device 1122.

[0046] Among them, the fourth inverter 1151, the fifth inverter 1152 and the sixth inverter 1153 are all composed of a PMOS tube and an NMOS tube connected in series, and the second end and the third end of the fourth inverter 1151, the fifth inverter 1152 and the sixth inverter 1153 are the source of the PMOS tube and the source of the NMOS tube respectively.

[0047] The detection unit 12 includes a comparison clamp circuit 121 and a control signal generating circuit 122. The detection unit 12 is preset to be floating ground, and the floating ground voltage is VS'.

[0048] The comparison clamp circuit 121 connects the first node a and the floating ground to receive the first node voltage VS and the floating ground voltage VS′, and generates a first control signal according to the first node voltage VS and the floating ground voltage VS′.

[0049] The control signal generating circuit 122 is connected to the comparison clamping circuit 121 to generate a second control signal according to the first control signal, and output the second control signal to the first switch 1121 to control the on / off of the first switch 1121 and further control the on / off of the second leakage branch 112 .

[0050] like Figure 3 As shown, the comparison clamp circuit 121 includes a first resistor 1211 , a second switch 1212 , a third switch 1213 and a diode 1214 .

[0051] Specifically, one end of the first resistor 1211 is connected to the first working voltage VB, the other end of the first resistor 1211 is connected to the first path end of the second switch 1212, and the second path end of the second switch 1212 is connected to the first node a; the first path end of the third switch 1213 is connected to the floating ground, and the second path end of the third switch 1213 is connected to the first node a; wherein the control end of the second switch 1212 and the control end of the third switch 1213 are connected together and connected to the second node b between the first resistor 1211 and the first path end of the second switch 1212. The anode of the diode 1214 is connected to the first node a, and the cathode of the diode 1214 is connected to the floating ground.

[0052] The first resistor 1211 , the second switch 1212 and the third switch 1213 form a bias circuit for applying voltage to the third switch 1213 to enable the third switch 1213 to work normally.

[0053] Among them, a parasitic PNP tube 1215 is formed between the first working voltage VB and the floating ground, the base of the parasitic PNP tube 1215 is connected to the first working voltage VB, the emitter of the parasitic PNP tube 1215 is connected to the floating ground, and the collector of the parasitic PNP tube 1215 is connected to the first channel end of the third switch 1213 and the cathode of the diode 1214.

[0054] Optionally, the second switch 1212 and the third switch 1213 are both NMOS transistors, and the control end, the first channel end and the second channel end of the second switch 1212 and the third switch 1213 are respectively the gate, the drain and the source of the NMOS transistor.

[0055] The control signal generating circuit 122 includes a fourth switch 1221 , a fifth switch 1222 , a sixth switch 1223 , a seventh switch 1224 , a second resistor 1225 , and an eighth switch 1226 .

[0056] Specifically, the first channel end of the fourth switch 1221 is connected to the first working voltage VB, the control end of the fourth switch 1221 is connected to the second channel end of the fourth switch 1221; the first channel end of the fifth switch 1222 is connected to the second channel end of the fourth switch 1221, the second channel end of the fifth switch 1222 is connected to the first node a, and the control end of the fifth switch 1222 is connected to the floating ground. The diode 1214 is a clamping diode, which is used to maintain the voltage difference between the control end and the second channel end of the fifth switch 1222 at 5V or 7V.

[0057] The first passage end of the sixth switch 1223 is connected to the first working voltage VB, wherein the control end of the sixth switch 1223 and the control end of the fourth switch 1221 are connected together and connected to a third node c between the second passage end of the fourth switch 1221 and the first passage end of the fifth switch 1222; the first passage end of the seventh switch 1224 is connected to the second passage end of the sixth switch 1223, the second passage end of the seventh switch 1224 is connected to the first node a, and the control end of the seventh switch 1224 is connected to the first passage end of the seventh switch 1224.

[0058] One end of the second resistor 1225 is connected to the first working voltage VB; the first path end of the eighth switch 1226 is connected to the other end of the second resistor 1225, and the second path end of the eighth switch 1226 is connected to the first node a, wherein the control end of the eighth switch 1226 and the control end of the seventh switch 1224 are connected together and connected to a fourth node d between the first path end of the seventh switch 1224 and the second path end of the sixth switch 1223.

[0059] Optionally, the fourth switch 1221 and the sixth switch 1223 are both PMOS transistors, and the control terminals, the first channel terminals and the second channel terminals of the fourth switch 1221 and the sixth switch 1223 are respectively the gate, the source and the drain of the PMOS transistor. The fifth switch 1222, the seventh switch 1224 and the eighth switch 1226 are all NMOS transistors, and the control terminals, the first channel terminals and the second channel terminals of the fifth switch 1222, the seventh switch 1224 and the eighth switch 1226 are respectively the gate, the drain and the source of the NMOS transistor.

[0060] The second resistor 1225 and the first channel end of the eighth switch 1226 form a fifth node e for outputting a second control signal to the first switch 1121 to control the on or off state of the first switch 1121 .

[0061] When the first node voltage VS of the first node a is normal, the first node voltage VS is equal to the floating ground voltage VS', the control end of the fifth switch 1222 receives the first control signal at a low level, that is, the fifth switch 1222 is not turned on, and the fourth switch 1221, the fifth switch 1222, the sixth switch 1223, the seventh switch 1224 and the eighth switch 1226 are all not turned on, and the second control signal output by the fifth node e is the first voltage VB. Since the first voltage VB is at a high level, the first switch 1121 is turned on, and the gate charge of the first power switch device Q1 is released through the NMOS tube to cause the sink current generated by the signal output terminal HO to be discharged through the first leakage branch 111 and the second leakage branch 112.

[0062] When the first node voltage VS of the first node a is abnormal, that is, the first node voltage VS drops to a negative voltage quickly, a voltage difference is formed between the control end of the fifth switch 1222 and the second path end, that is, the control end of the fifth switch 1222 receives the first control signal as a high level, and the fifth switch 1222 is turned on to generate current. Since the fourth switch 1221, the fifth switch 1222, the sixth switch 1223, the seventh switch 1224, the second resistor 1125 and the eighth switch 1226 form a mirror circuit, the fourth switch 1221, the fifth switch 1222, the sixth switch 1223, the seventh switch 1224 and the eighth switch 1226 are all turned on, and at this time, the second control signal output by the fifth node e is the first node voltage VS. Since the first node voltage VS is a negative voltage, i.e., a low-level signal, the first switch 1121 is disconnected, so that the second leakage branch 112 is disconnected, and the gate charge of the first power switch device Q1 is released through the NMOS tube so that the injection current generated by the signal output terminal HO can only be discharged through the first leakage branch 111, thereby reducing the leakage rate compared to when the first node voltage VS is normal.

[0063] The present application detects the first node voltage VS of the first node a through the detection unit 12. When the first node voltage VS is detected to be abnormal, the second leakage branch 112 is controlled to be disconnected, thereby reducing the leakage speed of the driving signal, that is, the leakage rate of the injection current, and effectively preventing the latch effect caused by the excessive leakage speed of the driving signal.

[0064] This application also provides a chip 6, see Figure 6 , Figure 6 1 is a schematic diagram of the structure of an embodiment of the chip of the present application. The chip 6 includes a driving circuit 61, and the driving circuit 61 is the driving circuit 1 disclosed in the above embodiment, which will not be described in detail here.

[0065] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A driving circuit for a power semiconductor switching device, in, The power semiconductor switch device comprises a first power switch device and a second power switch device arranged between an operating voltage and a reference voltage, a first node between the first power switch device and the second power switch device is used to connect a load, and is characterized in that the drive circuit comprises: A driving unit, used for generating a driving signal at an output end of the driving circuit, wherein the output end is used to connect to a control end of a first power switch device, the driving unit comprises a first leakage branch and a second leakage branch connected in parallel, and the driving unit is connected between a first working voltage and a second working voltage; the first leakage branch comprises a first semiconductor device connected between the output end and the second working voltage; the second leakage branch comprises a first switch and a second semiconductor device connected in series between the output end and the second working voltage, wherein the control end of the first switch is connected to a detection unit to be turned on or off according to the first node voltage detected by the detection unit, thereby controlling the second leakage branch to be turned on or off; A detection unit is connected to the first node and the driving unit, wherein the detection unit is used to detect a first node voltage of the first node, and control the conduction or disconnection of the second leakage branch according to the first node voltage, thereby controlling the leakage speed of the driving signal.

2. The driving circuit according to claim 1, It is characterized in that The detection unit presets a floating ground, including: a comparison clamp circuit connected to the first node and the floating ground to receive the first node voltage and the floating ground voltage and generate a first control signal according to the first node voltage and the floating ground voltage; The control signal generating circuit is connected to the comparison clamp circuit to generate a second control signal according to the first control signal, and outputs the second control signal to the first switch to control the on or off state of the first switch.

3. The driving circuit according to claim 2, It is characterized in that The comparison clamping circuit comprises: a first resistor, one end of which is connected to the first working voltage; a second switch, a first path end of which is connected to the other end of the first resistor, and a second path end of which is connected to the first node; a third switch, a first channel end of which is connected to the floating ground, and a second channel end of which is connected to the first node, wherein a control end of the second switch and a control end of the third switch are connected together and connected to a second node between the first resistor and the first channel end of the second switch; A diode has an anode connected to the first node and a cathode connected to the floating ground.

4. The driving circuit according to claim 2, It is characterized in that The control signal generating circuit comprises: a fourth switch, a first channel end of which is connected to the first working voltage, and a control end of which is connected to a second channel end; a fifth switch, wherein a first channel end thereof is connected to the second channel end of the fourth switch, a second channel end thereof is connected to the first node, and a control end thereof is connected to the floating ground; a sixth switch, a first channel end of which is connected to the first working voltage, wherein a control end of the sixth switch and a control end of the fourth switch are connected together and connected to a third node between the second channel end of the fourth switch and the first channel end of the fifth switch; a seventh switch, wherein a first path end of the seventh switch is connected to the second path end of the sixth switch, a second path end of the seventh switch is connected to the first node, and a control end of the seventh switch is connected to the first path end; a second resistor, one end of which is connected to the first operating voltage; an eighth switch, a first path end of which is connected to the other end of the second resistor, and a second path end of which is connected to the first node, wherein a control end of the eighth switch and a control end of the seventh switch are connected together and connected to a fourth node between the first path end of the seventh switch and the second path end of the sixth switch; A fifth node is formed between the second resistor and the first path end of the eighth switch, and is used to output the second control signal to the first switch to control the on or off state of the first switch.

5. The driving circuit according to claim 1, It is characterized in that The driving unit further comprises: The pull-up circuit comprises a third semiconductor device, wherein the third semiconductor device is connected between the output terminal and the first operating voltage to pull up the driving signal.

6. The driving circuit according to claim 5, It is characterized in that The driving unit further comprises: a first inverter group, connected between the first operating voltage and the second operating voltage, and used to output a third control signal to the third semiconductor device to control the conduction or disconnection of the third semiconductor device, thereby controlling the conduction or disconnection of the pull-up circuit; A second inverter group is connected between the first operating voltage and the second operating voltage, and is used to output a fourth control signal to the first semiconductor device and the second semiconductor device to control the conduction or disconnection of the first semiconductor device and the second semiconductor device, thereby controlling the conduction or disconnection of the first leakage branch and the second leakage branch.

7. The driving circuit according to claim 6, It is characterized in that The first inverter group comprises: A first inverter, an input end of which is connected to an input end of the driving circuit; A second inverter, an input end of which is connected to the output end of the first inverter; The third inverter has an input end connected to the output end of the second inverter, an output end connected to the control end of the third semiconductor device, and outputs the third control signal to the third semiconductor device to control the conduction or disconnection of the third semiconductor device.

8. The driving circuit according to claim 6, It is characterized in that The second inverter group comprises: a fourth inverter, an input end of which is connected to the input end of the driving circuit; a fifth inverter, an input end of which is connected to the output end of the fourth inverter; a sixth inverter, whose input end is connected to the output end of the fifth inverter, and whose output end is connected to the control ends of the first semiconductor device and the second semiconductor device; a third resistor, one end of which is connected to the first operating voltage, and the other end of which is connected to a sixth node formed between the output end of the sixth inverter and the control end of the first semiconductor device and the second semiconductor device; The sixth node is used to output the fourth control signal to the first semiconductor device and the second semiconductor device to control the on or off of the first semiconductor device and the second semiconductor device.

9. A chip, It is characterized in that The invention comprises a driving circuit as claimed in any one of claims 1 to 8.

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