Modern GNSS receivers

Abstract

GNSS receivers and systems within such receivers utilize improvements to reduce memory usage while providing sufficient processing resources to directly receive and acquire and track E5 band GNSS signals (without attempting to receive L1 GNSS signals, in one embodiment). Other aspects are also described.

Description

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 915,510, filed on October 15, 2019, and U.S. Non-Provisional Patent Application No. 17 / 068,659, filed on October 12, 2020, which are incorporated herein by reference. Background Art

[0002] The present disclosure relates to the field of global navigation satellite systems (GNSS), and in particular, in one embodiment, to a GNSS receiver that uses modern L5 signals in the L5 band. There are many available GNSS systems, including the United States' GPS (Global Positioning System), GLONASS, Galileo, BeiDou, and regional systems that already exist or may be deployed in the future. The United States' GPS system was initially only available in the L1 band. Currently, the United States' GPS system includes GNSS signals in the L5 band, and the Galileo system includes modernized GNSS signals (such as E5A and E5B) in the L5 band centered at 1191.79 MHz. Modernized GNSS signals in the L5 band offer certain advantages over GNSS signals in the L1 band, and some of these advantages are discussed below. However, direct acquisition of L5-band GNSS signals in a GNSS receiver is considered too difficult without prior acquisition of L1 GNSS signals. Therefore, conventional GNSS receivers employ techniques that first acquire L1 GNSS signals. This acquisition provides information, such as time information and Doppler estimates, for acquiring GNSS signals in the E5 band. Consequently, conventional GNSS receivers that support GNSS L5 signals use a radio frequency front-end that receives both L5 and L1 signals, meaning that these GNSS receivers have duplicate RF components. Furthermore, conventional receivers must store and use pseudorandom noise (PRN) codes for both L1 and L5 GNSS signals. Summary of the Invention

[0003] Various aspects described herein provide improvements that can allow a GNSS receiver to directly receive, acquire, process, and use only L5 band GNSS signals in the GNSS receiver with greater sensitivity and reliability than through acquisition at the narrowband L1, although in some embodiments these improvements can be used with conventional receivers that receive and process L5 band GNSS signals as well as one or more additional GNSS bands (such as the L1 GPS band). These aspects can be implemented in various embodiments that can include a GNSS receiver or a portion of a GNSS receiver, or a data processing system (such as a smartphone) that includes such a receiver or a portion of such a receiver, and can include methods performed by such a device (e.g., a GNSS receiver, etc.), and can include a non-transitory machine-readable medium storing computer program instructions that, when executed by a data processing system, cause the data processing system to perform one or more of the methods described herein.

[0004] One aspect of the present disclosure relates to direct acquisition of L5-band GNSS signals. In other words, in this aspect, a GNSS receiver directly acquires L5-band GNSS signals without attempting to acquire time and frequency information from the L1-band GNSS signals. The terms "direct acquisition" and "directly acquiring" are intended to mean that a GNSS receiver receives L5-band GNSS signals and acquires these L5-band GNSS signals to obtain time and frequency information derived from these signals without acquiring time and frequency information from the L1-band GNSS signals. While cellular assistance data (as described in the prior Snaptrack patent for time or phase lock of frequency) can be used in a GNSS receiver, L1-band GNSS signals are not acquired and are not used by a GNSS receiver that directly acquires L5-band GNSS signals. Therefore, when a GNSS receiver directly acquires L5-band GNSS signals, it acquires the L5-band GNSS signals to obtain time and frequency information from these signals without having the benefit of previously acquiring L1-band GNSS signals or acquiring time or frequency information from the L1-band GNSS signals.

[0005] Another aspect of the present disclosure relates to sharing cache memory between a set of one or more application processors (APs) and a GNSS processing system (or sharing other memory between the GNSS processing system and other processors on a SOC or integrated circuit). This aspect provides a solution to the typically excessive memory requirements for capturing L5 GNSS signals, particularly for methods using discrete Fourier transform (DFT) calculations. The one or more application processors (or other processors) and the GNSS processing system can be implemented together in a single monolithic integrated circuit (IC) on a single semiconductor substrate, which can be referred to as a system on a chip (SOC), and the cache memory can also be on the same IC. In this aspect, the application processor (or other processor) shares the cache memory (or other memory) of the application processor (or other processor) with at least an acquisition engine (AE) of the GNSS processing system. In one embodiment, this sharing can be limited to those instances in which the acquisition engine initially acquires GNSS signals (e.g., startup with or without assistance data from a cellular telephone network). In response to a request for location data (such as latitude and longitude) from an application (such as a map application or other application), a portion of cache memory (which can be the L1 (level 1) or L2 (level 2) SRAM cache of one or more application processors, or other memory used by other processing systems) can be allocated to the capture engine for the capture phase. Depending on the location request, this allocation can be prioritized or de-prioritized by the system's operating system (OS) or firmware on the IC; if the request for location comes from a low-priority background daemon application, the allocation can be temporarily deferred until sufficient free memory is available in the cache memory. On the other hand, if the location request comes from the map application that is the foreground application (and therefore the device's display is displaying the map application's user interface to the user), the allocation is prioritized. In one embodiment, the portion to be allocated can be identified by determining which pages in the cache memory are not dirty and are stored in a backing store such as main DRAM or, better yet, non-volatile memory (such as flash memory). Such pages (e.g., not dirty and stored in backing storage) can be immediately flushed / deleted from the cache memory (or other memory) and then allocated to the AE for storing, for example, one or more of: hypothesis data or generated GNSS PRN codes and / or their code spectrum from DFT.

[0006] According to its shared aspects, the method may include the following operations implemented in a GNSS receiver: receiving a request from one or more application processors on the integrated circuit to generate position data using a GNSS processing system on the integrated circuit, the GNSS processing system including an acquisition engine (AE) configured to acquire a plurality of GNSS signals, each of which is transmitted from one of a GNSS space vehicle (SV) constellation; identifying a portion of a cache memory (or other memory) on the integrated circuit and, in response to the request to generate position data, allocating the portion for use by the acquisition engine, while the one or more application processors (or other processor(s)) are allocated a remaining portion of the cache memory (or other memory), the allocation being performed by an operating system executing on the one or more application processors or by firmware on the IC; and storing, by the acquisition engine or the one or more application processors, data related to GNSS signal acquisition processing in the allocated portion. In one embodiment, the method may use static random access memory (SRAM) as a cache memory (or other memory) on an integrated circuit, and the acquisition engine may include ASIC (application-specific integrated circuit) hardware logic for performing a fast Fourier transform (FFT) operation (such as a discrete Fourier transform (DFT) operation using a time decimation method and also using a frequency decimation method). In one embodiment, the method may also include an operation of deallocating the allocated portion after the GNSS processing system begins tracking GNSS signals that have been acquired from at least three (3) GNSS SVs, the deallocation occurring in response to acquiring GNSS signals from at least three GNSS SVs before the tracking phase. In one embodiment, the GNSS processing system includes a dedicated memory separate from the cache memory (or other memory) and dedicated for use by the GNSS processing system. In one embodiment, a memory controller coupled to the cache memory (or other memory) may include a first port controller that controls access to the allocated portion of the acquisition engine and a second port controller that controls access to the remaining portion of the cache memory (or other memory). In one embodiment, an acquisition engine performs acquisition of a GNSS signal from a GNSS SV, and the acquisition includes determining a primary code phase and frequency of the received GNSS signal including a pseudorandom noise (PRN) code to enable tracking of the GNSS signal to generate a pseudorange to the GNSS SV (as a result of the tracking). In one embodiment of the method, the allocated portion stores one or more of: (1) the pseudorandom noise code of the GNSS SV or (2) a hypothesis of an identifier of a potentially acquired GNSS signal and a hypothesis of its frequency.In one embodiment of this method, one or more application processors may generate GNSS PRN codes and / or their DFT-derived code spectra for at least the GNSS SVs in view of the system before the acquisition phase begins; in one implementation of this embodiment, these PRN codes and / or their DFT-derived code spectra may be generated and used immediately without storing these codes, or alternatively, these PRN codes and / or their DFT-derived code spectra may be temporarily generated and stored while being used during the acquisition and tracking phases. In an alternative embodiment, one or more application processors may generate GNSS PRN codes (or their code spectra, or both) and then copy these codes to a cache memory (or other memory) before the acquisition phase begins or in response to a request for position. In one embodiment, to save memory, the system may generate GNSS PRN codes and / or their DFT-derived code spectra only for healthy GNSS SVs in view.

[0007] In one embodiment, a system according to this shared aspect may include the following components: a set of one or more application processors configured to execute an operating system (OS) and one or more applications, the set of one or more application processors being implemented in an integrated circuit; a set of one or more buses coupled to the set of one or more application processors, the one or more buses being on the integrated circuit; a cache memory (or other memory) on the integrated circuit and coupled to the set of one or more buses and to the set of one or more application processors to store data for use by the operating system or for use by one or more applications and other memory (such as high-bandwidth modem memory or other memory used by one or more processors not in the set of one or more application processors) that may also be on the IC and coupled to the one or more buses; The integrated circuit includes a processor (CPU) and a bus interface coupled to the set of one or more buses, the bus interface coupling the set of one or more application processors to dynamic random access memory (DRAM) external to the integrated circuit; a GNSS processing system implemented on the integrated circuit, the GNSS processing system including an acquisition engine (AE) and a tracking engine (TE), the GNSS processing system coupled to a cache memory (or other memory) via one or more buses; and a memory controller coupled to the cache memory (or other memory) and to the set of one or more application processors and to the GNSS processing system, the memory controller configured to allocate a portion of the cache memory (or other memory) for use by the AE in response to one or more instructions from an operating system (or other software component) to enable GNSS signal acquisition. In one embodiment, the cache memory may include static random access memory (SRAM), and the AE may include ASIC hardware logic configured to perform discrete Fourier transform operations using both decimation-in-time and decimation-in-frequency methods. In one embodiment, the memory controller may include a first port controller configured to control reads and writes to a portion of the cache memory (or other memory) for use by the AE, and a second port controller configured to control reads and writes to a remaining portion of the cache memory (or other memory). In one embodiment, after the GNSS processing system begins tracking GNSS signals that have been acquired from at least three GNSS SVs (but before position data such as latitude and longitude is determined), the memory controller may deallocate the portion of cache memory (or other memory) used by the AE.

[0008] Another aspect that can help reduce memory usage in L5 band GNSS receivers is the on-demand generation of GNSS PRN codes and / or their DFT-derived spectrum, which are used to correlate with received GNSS signals during the acquisition phase. In one embodiment, this on-demand generation can generate GNSS PRN codes and / or their DFT-derived spectrum during both the acquisition and tracking phases. For example, in one embodiment, these codes can be generated but not stored during both the acquisition and tracking phases; in an alternative embodiment, the codes can be generated and stored on-the-fly and on-demand during both the acquisition and tracking phases, and not stored once the position is determined. In one embodiment, the codes and spectrum are generated before each correlation operation, once every 1 ms per channel, and then the memory is overwritten for the next channel. There is no code or spectrum storage, only temporary reuse of memory. For example, if 24 signals are acquired, the codes for these 24 signals are regenerated 24 times every 1 ms. It is temporarily stored in memory for use in the first stage of the DFT performed during the frequency domain correlation algorithm.

[0009] Another aspect of the present disclosure relates to an acquisition correlator using array processing. This array processing architecture can initially arrange the digitized GNSS sample data, for example, in rows in an array, where the rows are arranged in time in a baseband sample memory. A DFT operation performed on the data can produce an output that can then be processed by an inverse DFT operation without rotating, reformatting, rearranging, or transposing the data in the array prior to the inverse DFT operation. The data can be arranged so that each ALU in a set of multiple ALUs processes a row or column of the array, thereby breaking the processing into discrete segments that can be processed by each of the DFT ALUs. Each row or column can be calculated by a single DFT ALU in an atomic processing operation within one or a few processing clock cycles. In one embodiment, the single DFT ALU can perform multiple DFT operations once instructed to do so. The baseband sample memory can be implemented in a circular buffer containing an ordered array of data. In one embodiment, the processing operation may be a DFT computed in place, such that rows (or columns) of input data are retrieved from memory and processed (using the DFT), and then the output from this processing is stored back into the same memory locations as the input data (thereby overwriting the input data in those memory locations).

[0010] In one embodiment in which an array processing architecture may be used, a system for processing GNSS signals may include the following components: an RF analog-to-digital converter (ADC) for generating a digital representation of a received GNSS signal; and a baseband sample memory for storing the digital representation of the received GNSS signal as digitized GNSS sample data in N2 rows (e.g., 1024 rows in one embodiment or 512 rows in another embodiment) and N1 columns (e.g., 20 columns in one embodiment or 40 columns in another embodiment), wherein the array is stored in the baseband sample memory in row order, and the row order contains digitized GNSS sample data received during a time period (including a first time period and a second time period), such that a first row in the row order contains digitized GNSS sample data received during the first time period, and a second row following the first row in the row order contains digitized GNSS sample data received during the second time period following the first time period, wherein the baseband sample memory is coupled to the RF An ADC comprises an ADC; and a set of arithmetic logic units (ALUs) configured to perform discrete Fourier transform (DFT) operations, the set of ALUs being coupled to a baseband sample memory and configured to perform N1 DFTs simultaneously and in parallel in time, wherein each of the N1 DFTs includes N2 points in the DFT, and the outputs of the N1 DFTs are stored in a partial sample array, and wherein the set of ALUs is configured to then perform N2 DFTs, each of the N2 DFTs including N1 points from the partial sample array, the N2 DFTs providing outputs stored in a DFT result array arranged in column order. In one embodiment, the baseband sample memory is configured as a circular memory buffer for storing digitized GNSS sample data. In one embodiment, the N1 DFTs are operated on different data using the same operation and the same program control instructions for the set of ALUs. In one embodiment, the N2 DFTs are performed sequentially over time. In one embodiment, the circular sample memory buffer stores more than one frame of pseudo-random GNSS signal (which is more than one millisecond). In one embodiment, the N1 DFTs and the N2 DFTs use a time decimation method, and N1 is one of the following integer values: 5, 10, 20, or 40. In another embodiment, N2 is set such that N1×N2=20480 (or N1×N2 is greater than 20480). In one embodiment, the change from row order to column order avoids a reordering or transposition algorithm, and the change is produced by a combination of N1 DFTs followed by N2 DFTs configured to produce this change. In one embodiment, the GNSS code generator is configured to generate a GNSS code spectrum, and the group of ALUs performs a group of DFTs on the GNSS PRN code to provide code spectrum result data, which is stored in the code spectrum memory in column order.In one embodiment, the baseband sample spectrum is stored in a special / dedicated memory and recalculated every 1 ms, and the code spectrum is stored in a general variable memory and overwritten once for each channel every ms. In one embodiment, the group of ALUs can be configured to multiply the code spectrum result data by the sample output stored in the DFT result array to produce a product array. In one embodiment, the group of ALUs can be configured to perform an inverse DFT on the product array using a frequency sampling method. In one embodiment, the inverse DFT may include: (1) in a first stage, N2 DFTs with conjugate inputs, each of the N2 DFTs containing N1 points, and (2) in a second stage after the first stage, N1 DFTs, each of the N1 DFTs containing N2 points. In one embodiment, the baseband sample memory can be a dual-port memory that allows different processors or processes to access different parts of the baseband sample memory simultaneously. In one embodiment, when needed during the acquisition phase, the GNSS code generator can repeatedly generate a pseudo-random noise code for each GNSS SV in view every millisecond, and the generated pseudo-random noise code (and / or its code spectrum from the DFT) is not stored after it is used, and the generated pseudo-random noise code can be used to generate the GNSS code spectrum. In one embodiment, the GNSS code spectrum is aligned in memory in situ in both frequency and phase to match the code phase and frequency offset assumptions associated with the received GNSS signal. In one embodiment, this alignment can be performed by CORDIC hardware.

[0011] One or more embodiments of the GNSS receiver described herein may perform one of the following methods using a DFT sequence. In one embodiment, a method may include the following operations:

[0012] Receive GNSS signals;

[0013] digitizing the received GNSS signal and providing an output of GNSS sample data from an analog-to-digital converter (ADC), the output comprising at least one of: (1) GNSS sideband A sample data of the received GNSS signal and (2) GNSS sideband B sample data of the received GNSS signal;

[0014] computing at least one of: (1) a first set of DFTs of the GNSS sideband A sample data to provide a first set of results, and (2) a second set of DFTs of the GNSS sideband B sample data to provide a second set of results;

[0015] computing at least one of: (1) a third set of DFTs of GNSS sideband A primary PRN code data, the GNSS sideband A primary PRN code data being adjusted for code Doppler and carrier Doppler prior to the third set of DFTs, the GNSS sideband A primary PRN code data including at least one of the two components in GNSS sideband A, the third set of DFTs providing a third set of results, and (2) a fourth set of DFTs of GNSS sideband B primary PRN code data, the GNSS sideband B primary PRN code data being adjusted for code Doppler and carrier Doppler prior to the fourth set of DFTs, the GNSS sideband B primary PRN code data including at least one of the two components in GNSS sideband B, the fourth set of DFTs providing a fourth set of results;

[0016] computing at least one of: (1) computing a first set of correlations using the complex conjugate DFT of the product of the first set of results and the complex conjugate of the third set of results to provide a fifth set of results, and (2) computing a second set of correlations using the complex conjugate DFT of the product of the second set of results and the complex conjugate of the fourth set of results to provide a sixth set of results; and

[0017] Integrating at least one of: (1) the fifth set of results with at least one prior sum for GNSS sideband A, and (2) the sixth set of results with at least one prior sum for GNSS sideband B, wherein such integrating includes at least one of (1) storing at least one new sum for the GNSS sideband A component in a single hypothesis memory, and (2) storing at least one new sum for the GNSS sideband B component in a single hypothesis memory.

[0018] One implementation of this method can be summarized as ("Case 1"):

[0019] 1. Calculate the FFT of the sideband A samples;

[0020] 2. Calculate the FFT of the sideband B samples;

[0021] 3. Calculate the FFT of at least one sideband A-component primary code adjusted for code Doppler and carrier Doppler (e.g., a range of potential Dopplers to be searched);

[0022] 4. Calculate the FFT of at least one sideband B component primary code adjusted for code Doppler and carrier Doppler;

[0023] 5. Compute the correlation using the inverse FFT (IFFT) of the product of (a) the FFT calculated from 1 (the FFT of the sideband A samples) and (b) the FFT calculated from 3 (the FFT of the sideband A components).

[0024] 6. Compute the correlation using the IFFT of the product of (a) the FFT computed from 2 and (b) the FFT computed from 4.

[0025] This implementation can provide several advantages. For example, this implementation can have very few FFTs on the received sideband samples and can reduce or eliminate the large amount of data transfer typically required to move pre-computed GNSS sample spectra from memory (e.g., DRAM or non-volatile memory) to the frequency domain correlator array processor. By reusing the frequency domain correlation engine at a reasonable clock speed, the engine can be very efficient while requiring a low or small memory footprint. For example, the frequency domain correlation engine can calculate the master code and its spectrum in situ within the engine in the pipeline architecture described herein (e.g., in operations 3 and 4 in "Case 1" outlined above). Furthermore, applying code Doppler compensation and carrier Doppler compensation to the in-situ generated code (e.g., in operations 3 and 4 in "Case 1" outlined above) reduces the input (received) sample FFTs and also improves code Doppler accuracy.

[0026] There are many combinations and arrangements of this implementation for acquiring, for example, L5 GNSS signals. However, these combinations and arrangements may be less efficient than "Case 1" above because they require a faster processing clock and / or more memory (relative to "Case 1"), or because they have lower acquisition sensitivity or take longer to acquire a signal of a given signal strength. The use of the six (6) operations in "Case 1" can be retained but with an arrangement based on one or more of the following: (1) where and how the code and carrier compensation is performed, for example: (a) carrier Doppler compensation can be a "wipe-off" of the received GNSS samples or an up-multiply of locally generated (or pre-computed) PRN code samples; or (b) code Doppler adjustment can be applied to the received GNSS samples ("input samples") or locally generated (or pre-computed) PRN code samples by complex multiplication of the code spectrum (e.g., see Appendix 3) or by compensating the post correlation result and its integration in memory (see Appendix 1); (2) whether the code spectrum is generated locally in situ in the acquisition engine (AE) or is pre-computed and loaded into the AE based on the GNSS SVs in view; or (3) alternative hardware architectures such as parallel FFT cores or higher radix cores (rather than sequential time-decimation FFT and frequency-decimation FFT) to reduce the number of processing clocks per FFT. The following 6 arrangements are examples of possible arrangements.

[0027] Case 2 (Switch code and carrier Doppler to samples: requires more input samples FFT)

[0028] 1. FFT of sideband A with adjusted code and carrier Doppler

[0029] 2. FFT of sideband B with adjusted code and carrier Doppler

[0030] 3. FFT of at least one A component main code

[0031] 4. FFT of at least one B component main code

[0032] 5. Correlation using the IFFT of the product of 1 and 3, integrated into a single hypothesis memory

[0033] 6. Correlation using the IFFT of the product of 2 and 4, integrated into a single hypothesis memory

[0034] Case 2B (same as 2 where the code spectrum is precomputed: requires more memory and data bandwidth)

[0035] 1. FFT of sideband A with adjusted code and carrier Doppler

[0036] 2. FFT of sideband B with adjusted code and carrier Doppler

[0037] 3. Obtain the pre-calculated FFT of at least one A component main code

[0038] 4. Obtain the pre-calculated FFT of at least one B component main code

[0039] 5. Correlation of the IFFT of the product of 1 and 3, integrated into a single hypothesis memory

[0040] 6. Utilize the correlation of the IFFT of the product of 2 and 4, integrated into a single hypothesis memory

[0041] Case 3 (same as 2 with code Doppler compensation after correlation)

[0042] 1. FFT of sideband A with carrier Doppler adjusted

[0043] 2. FFT of sideband B with carrier Doppler adjusted

[0044] 3. FFT of at least one A component main code

[0045] 4. FFT of at least one B component main code

[0046] 5. Utilize correlation of the IFFT of the product of 1 and 3 adjusted for code Doppler, integrated into a single hypothesis memory

[0047] 6. Utilize correlation of the IFFT of the product of 2 and 4 adjusted for code Doppler, integrated into a single hypothesis memory

[0048] Case 3B (same as 3, but with precomputed code spectrum)

[0049] 1. FFT of sideband A with carrier Doppler adjusted

[0050] 2. FFT of sideband B with carrier Doppler adjusted

[0051] 3. Obtain the pre-calculated FFT of at least one A component main code

[0052] 4. Obtain the pre-calculated FFT of at least one B component main code

[0053] 5. Correlation using the IFFT of the product of 1 and 3 adjusted for code Doppler, integrated into a single hypothesis memory

[0054] 6. Correlation using the IFFT of the product of 2 and 4 adjusted for code Doppler, integrated into a single hypothesis memory

[0055] The following set of cases uses the method described in Appendix 1, which calculates the FFT of the input sample sideband samples every millisecond at multiple frequencies such as 0, 200, 400, 600, 800, and then the sample sideband A or B spectrum is approximated by selecting the closest sub-kHz FFT and then shifting by + / - N samples to obtain super-kHz compensation. For example, 2450 Hz uses a 400 Hz FFT and shifts this FFT by +2 samples to obtain a combined 400 Hz + 2 kHz Doppler compensation.

[0056] Case 4 (similar to the method described in Appendix 1)

[0057] 1. Select at least one FFT from a set of sideband A-sample FFTs adjusted for carrier Doppler at a frequency group covering a k-Hz range, the one FFT being shifted by N samples to produce an approximate carrier Doppler

[0058] 2. Select at least one FFT from a set of sideband B-sample FFTs adjusted for carrier Doppler at a frequency group covering a k-Hz range, the one FFT being shifted by N samples to produce an approximate carrier Doppler

[0059] 3. FFT of at least one A-component main code with adjusted code Doppler

[0060] 4. FFT of at least one B-component main code with code Doppler adjusted

[0061] 5. Correlation using the IFFT of the product of 1 and 3, integrated into a single hypothesis memory

[0062] 6. Correlation using the IFFT of the product of 2 and 4, integrated into a single hypothesis memory

[0063] Case 4A (similar to method 4, but with pre-calculated code spectrum and correlated code Doppler)

[0064] 1. Select at least one FFT from a set of sideband A-sample FFTs adjusted for carrier Doppler at a frequency group covering a k-Hz range, the one FFT being shifted by N samples to produce an approximate carrier Doppler

[0065] 2. Select at least one FFT from a set of sideband B-sample FFTs adjusted for carrier Doppler at a frequency group covering a k-Hz range, the one FFT being shifted by N samples to produce an approximate carrier Doppler

[0066] 3. Obtain the pre-calculated FFT of at least one A component main code

[0067] 4. Obtain the pre-calculated FFT of at least one B component main code

[0068] 5. Correlation using the IFFT of the product of 1 and 3 adjusted for code Doppler, integrated into a single hypothesis memory

[0069] 6. Correlation using the IFFT of the product of 2 and 4 adjusted for code Doppler, integrated into a single hypothesis memory

[0070] In some embodiments described herein, one or both of code Doppler and carrier Doppler are adjusted or compensated. As described herein, these adjustments can be performed independently and at different stages. Code Doppler adjustment is an adjustment of a locally generated code (or pre-calculated code) or received GNSS code samples to adjust for the Doppler effect on a code (such as a primary GNSS PRN code); for example, during the search or acquisition phase, a variety of possible code Doppler adjustments can be made to the locally generated code or received GNSS code samples to search for and acquire GNSS signals affected by the Doppler effect. Carrier Doppler adjustment is an adjustment to adjust for the Doppler effect on the signal's carrier frequency. Carrier Doppler is the observed offset from the transmit frequency due to relative motion between the satellite and receiver, and the offset from the nominal values of the satellite oscillator and the receiver oscillator. Code Doppler is the shift in the received code phase over time, which is coherent with carrier Doppler. At L5, there are 115 carrier cycles per chip. Therefore, code Doppler, expressed in chips per second, is carrier Doppler divided by 115. Thus, for a carrier Doppler of 4321 Hz, the received code phase will shift by 37.57 chips in one second. To receive weak signals, it is necessary to correlate the received signal with multiple replicas of the receiver's primary code frame. This requires that each incoming code phase hypothesis be shifted by the carrier Doppler hypothesis. This shift is known as code Doppler.

[0071] Another aspect of the present disclosure relates to the use of primary and / or secondary codes in E5 GNSS signals from one GNSS SV to derive code phase data or time data based on those GNSS signals, and then using that information to estimate the code phase of other GNSS signals from other GNSS SVs to capture the code phase of other GNSS signals from other GNSS SVs. In this regard, a GNSS receiver may employ processing epochs that are less than a 1 ms GNSS PRN code epoch and may be offset from the 1 ms GNSS PRN code epoch, and the GNSS receiver may use this processing to attempt to coherently integrate before acquiring the code phase of other GNSS signals; for example, a GNSS processing system in the GNSS receiver may retrieve a full 1 ms of digitized GNSS sample data from a circular memory buffer every 0.25 ms and perform a set of DFTs and inverse DFTs on the retrieved data to coherently integrate for each frequency bin, and then repeat this VFFDC process for the next processing epoch, each processing epoch being 0.25 ms or other fraction of a code epoch, which in one embodiment is 1 ms in length. This may allow the GNSS receiver to reuse the 1 ms of data from the circular buffer over multiple processing epochs to attempt to coherently integrate other GNSS signals using information obtained from previously acquiring the primary or secondary code phase of at least one GNSS signal. In this example, the satellite codes are searched to align with the approximate time bin in which they are expected to be received, so that sub-millisecond coherence cancellation losses due to phase reversals associated with the secondary code phase are reduced. In another embodiment, the receiver clock may already be sufficiently accurate (much less than 1 ms error), and the a priori position may be sufficiently known to allow all GNSS signals to be processed in this precise time acquisition mode.

[0072] Another aspect of the present disclosure relates to using only a subset (a selected component) of two or four components of a GNSS signal during coarse time acquisition to first acquire that subset (such as only one of the four components) and then acquire the remaining components. In one embodiment, this selected component is selected based on the lowest probability of signal changes due to sign or phase reversals caused by the coding scheme used in the selected component. In the case of Galileo's E5 GNSS signal, the E5BI component has the lowest probability of signal changes due to sign or phase reversals and can therefore be used as the selected component to perform coarse or fine time acquisition before attempting to acquire and / or track the remaining components in the Galileo GNSS signal. This use of only a subset of components can be done initially when starting acquisition (such as coarse time acquisition), or as a fallback mode of operation after conventional acquisition has failed, or as a method of acquiring stronger satellites more quickly because the number of correlations is reduced, allowing a portion of the GNSS acquisition engine to search a large frequency space of many SVs more quickly and with lower power than when more GNSS signal components are employed.

[0073] Another aspect of the present disclosure relates to mitigating the effects of interference from certain known strong interference sources, such as aeronautical radio navigation (ARN) signals, which are typically present around, for example, airports or military bases. ARN signals, such as those from tactical air navigation systems (DME / TACAN), are typically strong pulsed signals that are well above the noise floor, while GNSS signals are typically below the noise floor. In addition, ARN signals can cause interference to GNSS in the L5 band. In one embodiment, this interference can be mitigated by detecting a signal source above the noise floor (e.g., detecting a signal above a predetermined threshold, which can be several dB above the noise floor) and then removing the signal in the frequency domain. Interference signals can be identified using the DFT array processing described herein during the signal acquisition phase, and then the interference signals can be processed by an FIR (finite impulse response) filter before time domain correlation processing to remove the interference signals. Alternatively, frequencies with strong interference can be observed in the input data spectrum because the input sample spectrum is performed once per millisecond and at each upper and lower sideband. Another aspect of the present disclosure relates to mitigating the effects of interference from certain known interferers by narrowing the processing bandwidth of the radio receiver, focusing on one of the two sidebands E5a or E5b, depending on the location of the interferer. Once the approximate interferer frequency location is determined using DFT array processing detection or other methods, various analog and mixed signal techniques can be used to reduce the effects of the interferer before quantization. In one case, radio filtering can narrow the effective radio bandwidth from 52 MHz to 26 MHz or less. While this may incur a small performance penalty, it allows the receiver to operate with a larger interference margin. In another case, in Figure 4D、 4F During the IF bandpass filtering of the radio architecture of 4J and 5J, a configurable notch can be placed at the effective frequency position. Figure 4B 、 4D During the low-pass filtering of the architecture shown in 4F, the notch can also be placed at the effective frequency position. In another case, it is possible to modify Figure 4J The IF frequency and / or sampling frequency of the radio architecture can be improved to improve the immunity of the frequency planning to aliasing interference.

[0074] Another aspect of the present disclosure relates to a method for reducing memory usage by calculating but not storing outputs from certain DFT calculations. This method can reduce the size of the integration or hypothesis memory by eliminating the storage of selected outputs from the DFT calculation. In one embodiment, the outputs are evaluated to determine whether to save them. This can be employed when the DFT method is used to perform the correlation. In this case, the DFT produces correlation results for all code hypotheses within one millisecond. If the uncertainty of the full range of epoch positions is much less than one millisecond, only a portion around the estimated position needs to be integrated and saved.

[0075] Aspects and embodiments described herein may include a non-transitory machine-readable medium storing executable computer program instructions that, when executed by one or more data processing systems, may cause the one or more data processing systems to perform the methods described herein. The instructions may be stored in a non-volatile memory such as flash memory or a volatile dynamic random access memory or other form of memory.

[0076] The above summary does not include an exhaustive list of all embodiments in the present disclosure. All systems and methods can be practiced from all suitable combinations of the various aspects and embodiments summarized above and those disclosed in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] The patent or application file contains at least one drawing in color. Copies of this patent or patent application publication and any color drawing will be provided by the Office upon request and payment of the necessary fee.

[0078] The present disclosure is illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which like references indicate similar elements.

[0079] FIG. 1 is a block diagram illustrating an example of a data processing system including a GNSS processor and one or more application processors.

[0080] Figure 2 is a block diagram illustrating an example of an embodiment including a GNSS processing system and one or more application processors and a cache memory.

[0081] Figure 3 is a flow chart illustrating a method for sharing a cache memory between one or more application processors and a GNSS processor according to one embodiment.

[0082] Figure 4 An example of a front end of a GNSS receiver that digitizes received GNSS signals according to one embodiment is shown.

[0083] Figure 4A An example of a convention or nomenclature used to describe the radio portion of a GNSS receiver is shown.

[0084] Figure 4B An example of a conventional IQ receiver architecture that may be used in a GNSS receiver is shown.

[0085] Figure 4C Shown Figure 4B An example of frequency planning for the receiver architecture is shown.

[0086] Figure 4D An example of a GNSS receiver according to one embodiment is shown.

[0087] Figure 4E Shown Figure 4D An example of frequency planning for the receiver architecture shown in .

[0088] Figure 4F Pictured Figure 4D A variant of the GNSS receiver shown in .

[0089] Figure 4G Shown Figure 4F An example of frequency planning for the receiver architecture shown in .

[0090] Figure 4H An example of a subsampling arrangement that may be used in one or more embodiments of the invention described herein is shown.

[0091] Figure 4I Shows the available Figure 4H An example of frequency planning in a subsampling architecture is shown in the example shown in .

[0092] Figure 4J Shows that you can use Figure 4H An example of an architecture of a GNSS receiver in terms of the arrangement.

[0093] Figure 4K Shown Figure 4J An example of frequency planning for the receiver architecture shown in .

[0094] Figure 4L An example of an embodiment of a GSSS receiver configured to fold sidebands of a GNSS signal onto each other is shown.

[0095] Figure 4M Another example of an embodiment of a GSSS receiver configured to fold sidebands of a GNSS signal onto each other is shown.

[0096] Figure 4N An example of another embodiment of a GSSS receiver configured to fold sidebands of a GNSS signal onto each other is shown; Figure 4O shows the Galileo E5 signal spectrum, and Figure 4P The Galileo E5B signal spectrum is shown.

[0097] Figure 5A and 5B An example of a method using array processing using DFT according to one embodiment is shown.

[0098] Figure 6 is a block diagram illustrating a frequency domain correlator architecture using array processing according to one embodiment.

[0099] Figure 7 An example of processing components for performing array processing according to one embodiment is shown in block diagram form.

[0100] Figure 8 An example of additional processing components for performing array processing according to one embodiment is shown in block diagram form.

[0101] Figure 9A 、 9B , 9C and 9D show examples of processing components and methods for generating a PRN code spectrum for use Figure 6 、 7 and the method of the array processing architecture shown in 8.

[0102] Figure 10 Shown are examples of components that may be used in one embodiment of a GNSS receiver.

[0103] Figure 11 is a flow chart illustrating a method according to one embodiment.

[0104] Figure 12 An example of an L5 WB band-only GNSS receiver is shown in block diagram form.

[0105] Figure 13 Examples of embodiments are shown that use selected signals from a set of GNSS signal components to initially acquire a GNSS signal in certain circumstances.

[0106] Figure 14A An example of an embodiment of a front-end processing flow in a GNSS receiver is shown.

[0107] Figure 14B A timing diagram is shown for an embodiment using a series of acquired GNSS signals that are stored in a buffer and then processed to accumulate a code phase hypothesis.

[0108] Figure 14C A rough temporal capture processing timeline is shown according to one embodiment.

[0109] Figure 14D A precise time capture processing timeline is shown according to one embodiment.

[0110] Figure 14E and 14F An example of an FFT processor architecture according to one embodiment is shown.

[0111] Figure 14G is a flow chart illustrating a method that may be used with a frequency domain correlator, particularly a correlator using an array processor.

[0112] Figure 14H Another example of an FFT processor architecture according to one embodiment is shown.

[0113] Figure 14I is a flow chart illustrating a method that may be used with a frequency domain correlator, particularly a correlator using an array processor.

[0114] Figure 14J is a flow chart illustrating a method that may be used with a frequency domain correlator, particularly a correlator using an array processor.

[0115] Figure 14K is a block diagram of a system on a chip (SOC) including a GNSS receiver and one or more application processors according to one embodiment.

[0116] Figure 14L is a flow chart illustrating a method that may be used with a frequency domain correlator, particularly a correlator using an array processor, during a coarse time acquisition mode.

[0117] Figure 14M is a flow chart illustrating a method that may be used with a frequency domain correlator, particularly a correlator using an array processor, during a precise time acquisition mode.

[0118] Figure 14N An example of a hypothetical memory arrangement for non-coherent integration in coarse time mode during code phase acquisition of GNSS signals is shown.

[0119] Figure 14O An example of a hypothetical memory arrangement example for coherent integration in precise time mode (when time is known to within, for example, 0.5 ms) during code phase acquisition of a GNSS signal is shown.

[0120] Figure 14P is a flow chart illustrating a method for configuring a hypothesis memory according to one embodiment.

[0121] Figure 15A is a flow chart illustrating a method for mitigating interference, such as ARN interference, according to one embodiment.

[0122] Figure 15B is a flow chart illustrating another method for mitigating interference, such as ARN interference, according to one embodiment.

[0123] Figure 16A A process flow for acquiring GNSS signals using rotation or interpolation along with DFT is shown according to one embodiment.

[0124] Figure 16B A process flow for acquiring GNSS signals using rotation or interpolation along with DFT according to another embodiment is shown.

[0125] Figure 16C A process flow for acquiring GNSS signals using rotation or interpolation along with DFT according to another embodiment is shown.

[0126] Figure 17 An example of a method by which power consumption may be reduced by acquiring a set of GNSS signal components during an acquisition phase and then tracking using only a subset of these acquired components is shown. DETAILED DESCRIPTION

[0127] Various embodiments and aspects will be described with reference to the details discussed below, and the accompanying drawings will illustrate various embodiments. The following description and drawings are illustrative and should not be construed as limiting. Numerous specific details are described to provide a thorough understanding of the various embodiments. However, in some cases, well-known or conventional details have not been described to provide a concise discussion of the embodiments.

[0128] References in the specification to "one embodiment" or "an embodiment" mean that the specific features, structures, or characteristics described in conjunction with the embodiment may be included in at least one embodiment. The appearance of the phrase "in one embodiment" in various places in the specification does not necessarily refer to the same embodiment. The processes depicted in the following figures are performed by processing logic including hardware (e.g., circuits, dedicated logic, etc.), software, or a combination of the two. Although these processes are described below in terms of some sequential operations, it should be understood that some of the operations described may be performed in different orders. In addition, some operations may be performed in parallel rather than sequentially.

[0129] One aspect of the embodiments described herein relates to sharing cache memory between one or more application processors and a GNSS processing system. Before describing these sharing embodiments, a description of existing architectures in the prior art will be provided with reference to FIG1 . FIG1 shows a system 10 including one or more application processors 12 and a GNSS processor 20 coupled via a bus 14, which is also coupled to the system's main memory, which is dynamic random access memory (DRAM) 24. System 10 includes one or more input / output (I / O) devices 26, such as, for example, one or more touch screens, speakers, microphones, and one or more sensors such as a camera, facial detection sensor, etc. System 10 also includes a cellular phone modem and processor 16, which may include its own cache memory, which may be SRAM 16A. The cellular phone modem and processor 16 are coupled to a cellular phone RF assembly 17 to receive cellular phone signals via an antenna 18. The GNSS processor 20 is configured to receive and process GNSS signals in both the L1 and L5 frequency bands. Furthermore, the GNSS radio frequency (RF) assembly 21 is configured to receive GNSS signals in both the L1 and L5 bands via antennas 22A and 22B, and includes one or more RF mixers and RF-to-IF downconverters, as well as an RF local oscillator. These GNSS signals are processed by the GNSS processor 20, which includes its own dedicated processor memory as part of the GNSS processor 20. The GNSS processor does not use or share cache memory 12A, which is used by one or more application processors 12 using techniques known in the art to utilize cache memory. The GNSS processor receives and processes GNSS signals and provides position outputs, such as latitude and longitude outputs, to the one or more application processors 12 via bus 14. The GNSS processor receives and processes GNSS signals without utilizing cache memory 12A and requires two separate GNSS antennas 22A and 22B, as well as two separate GNSS RF paths originating at the two GNSS antennas 22A and 22B.

[0130] Figure 2 An example of a system is shown in which cache memory in the system is shared between one or more application processors and a GNSS processing system. Figure 2 The system 50 shown in FIG. 5 includes a system on a chip (SOC) 52 that includes one or more application processors 66 and a cache memory 70 and a GNSS processing system 68. In one embodiment, the SOC 52 may be a single monolithic semiconductor device embodied in a substrate of an integrated circuit that includes, for example, Figure 2 All components shown are within the perimeter of the illustrated SOC 52. The SOC 52 may include a memory controller 72 that controls access to a cache memory 70 (or other memory) coupled to both the one or more application processors 66 and the GNSS processing system 68. Thus, the memory controller 72 may arbitrate use of the cache memory 70, which in one embodiment may be implemented as SRAM memory, to allow both the GNSS processing system 68 and the one or more application processors 66 to use the cache memory. In one embodiment, the memory controller 72 may allocate a portion of the cache memory 70 for use by the GNSS processing system and allow the remaining portion of the cache memory 70 to be used by the one or more application processors 66. In one embodiment, the cache memory 70 may be used to store program code or program instructions and data to be operated on by the processing system. As will be described below, when an acquisition engine of the GNSS processing system 68 is acquiring GNSS signals, the acquisition engine may use the cache memory to store, for example, hypotheses in a hypothesis memory used during the acquisition phase, or may use the cache memory 70 to store PRN codes (and / or their code spectra from a DFT) generated for the GNSS signals. The GNSS processing system 68 may be coupled to the one or more application processors 66 via a bus 74. The one or more application processors 66 and the GNSS processing system 68 may also be coupled to a cellular telephone modem and processor 76 via the bus 74. In one embodiment, the bus 74 is a set of buses on the SOC 52. The SOC 52 also includes a bus interface 78 that allows the SOC 52 to couple to a system bus 54 external to the SOC 52. There are several other components that are external to the SOC 52, and they include the GNSS radio frequency component 63, which is located on the SOC 52. Figure 2 The example shown is configured to operate only in the L5 Wideband (WB) band to receive and process only Figure 2L5 wideband (WB) GNSS signals in the illustrated embodiment. The term or phrase L5 WB band or L5 WB signals or L5 WB GNSS is intended to include or refer to modern GNSS signals and modern GNSS systems (e.g., SV constellations and receivers) operating on a modern frequency band centered at 1191.795 MHz and having a chip rate of 10.23 MHz or significantly higher than the legacy chip rate or GPS L1 of 1.023 MHz, and these modern GNSS systems include, for example, the U.S. L5 GPS system, the European E5 Galileo system, the Chinese Beidou (Compass) B2 system, Glonass K2, and QZSS. A cellular phone modem and processor 76 is coupled to the cellular phone RF assembly 64 to receive cellular phone signals and transmit cellular phone signals. DRAM 56 is coupled to the bus 54 and can store user data and applications as well as an operating system. In addition, the system 50 can also include non-volatile memory 57, such as flash memory, in addition to the DRAM 56. The non-volatile memory 57 can store user data and applications as well as the operating system of the system 50. The system 50 can also include various input / output devices that can interface with the rest of the system through one or more I / O controllers 58. The input / output devices can include one or more sensors 62 and other input / output devices 60. For example, the sensors can include one or more of a 3-axis accelerometer, a 3-axis gyroscope, an ambient light sensor (ALS), an air pressure sensor, a magnetometer, one or more cameras, etc. In addition, the system 50 can include other radio frequency components 62, such as Bluetooth, Wi-Fi, etc. Methods for operating the system 50 will now be described with reference to Figure 3 is provided.

[0131] In operation 101 ( Figure 3), the system 50 may receive a request from an application to determine a location. This request may come from a foreground application or from a background application. For example, a map application that is in the foreground and therefore displaying a user interface of a map to a user requests a location, and this request may cause the GNSS processing system 68 to be activated. Alternatively, a background daemon process may make the request for a location. The nature of the request may determine the priority that the memory controller 72 has when determining how and when to allocate a portion of the cache memory 70 for use by the GNSS processing system 68. For example, in some embodiments, a foreground application request for a location may cause the allocation of a portion of the cache memory 70 for use by the GNSS processing system 68 to be a high priority task, causing the portion to be allocated as soon as possible. Alternatively, a background application request for a location may cause the allocation of a portion of the cache memory 70 by the memory controller 72 to be a deferred process or task, thereby giving the memory controller 72 more time to allocate a portion of the cache memory 70.

[0132] In operation 103, the GNSS processing system 68 may receive assistance data from, for example, a cellular telephone modem and processor 76. In one embodiment, a satellite almanac or other data source regarding satellites in view over a period of time may be received by the system 50 and stored for later use by the GNSS processing system 68. Based on the satellites or space vehicles (SVs) in view (e.g., from the received satellite almanac), the GNSS processing system 68 may generate, in operation 105, pseudorandom noise (PRN) codes and / or their code spectra from DFT for those GNSS SVs in view (e.g., see Figure 6 In one embodiment, the GNSS processing system 68 may generate these codes on demand during the acquisition and tracking phases for processing GNSS signals and use these codes without storing them. In another embodiment, the GNSS processing system 68 may generate these codes and / or their DFT-derived code spectra on demand during the acquisition and tracking phases for processing GNSS signals (e.g., see Figure 6 ) and use these codes and / or their code spectra from the DFT (see, for example, Figure 6The code spectrum memory 263 in the tracking phase may also store them, but these codes are no longer stored once the tracking phase is completed. In one embodiment, a code spectrum (generated from the GNSS PRN codes of the GNSS SVs in view) may be generated but not stored (for more than about 1 millisecond), and the code spectrum may be repeatedly generated over and over again for each millisecond (ms) of GNSS sample data received and stored (e.g., in a circular memory buffer); thus, in the first ms, a code Doppler (e.g., time shift) and carrier frequency Doppler adjustment (see, e.g., the DFT ALU 261) may be applied to the generated GNSS master PRN code prior to DFT (e.g., by the DFT ALU 261). Figure 6 and Figure 9D ) to generate a code spectrum, and then generate a new code spectrum in the second ms (the next millisecond after the first ms). Figure 6 A benefit of applying code Doppler and carrier frequency adjustment before the DFT ALU 261 in the GNSS processor (generated) is that the code spectrum cannot be pre-calculated or even used in the following milliseconds because the code Doppler rate of the E5 GNSS signal is high and therefore the code Doppler should be shifted every millisecond interval to maintain high correlation. In one embodiment, if memory is available to reduce computing resource usage, the code Doppler-shifted code spectrum can be stored for a short period of time. Generating these codes on demand (which continues until position data is determined) without long-term storage or without any storage can reduce the amount of memory used by the GNSS processing system 68. Similarly, sharing cache memory 70 with one or more application processors 66 can also reduce memory usage by the GNSS processing system 68. In operation 107, a portion of cache memory (such as SRAM memory) on an integrated circuit containing the GNSS processing system and one or more application processors can be allocated by, for example, the memory controller 72. This can then allow the acquisition engine in the GNSS processing system 68 to use the allocated portion, at least during the acquisition phase.

[0133] The acquisition phase typically involves determining the frequency and master code phase of the acquired PRN codes, as well as the identifier of the satellite that transmitted these acquired PRN codes. When a correlation operation indicates a match between the locally generated PRN code and the received PRN code, the PRN code is acquired. In one embodiment, in operation 109, an acquisition engine in the GNSS processing system uses the allocated portion to store hypothesis data and / or GNSS PRN codes. Then, in operation 111, the acquisition engine acquires one or more GNSS signals to allow a tracking engine in the GNSS processing system to track the acquired GNSS signals and thereby determine pseudoranges from the GNSS SV that transmitted the GNSS signals acquired by the acquisition engine. In one embodiment, in operation 113, the portion of the cache memory may be de-allocated after the tracking phase begins. For example, the memory controller 72 may de-allocate the portion containing the hypothesis data while retaining the GNSS PRN codes and / or their code spectra from the DFT (e.g., see the description of the code spectrum memory 263 below), if stored in the cache memory, for tracking. In embodiments where PRN codes and / or their code spectra from the DFT (e.g., see description of code spectrum memory 263 below) are not stored during use but are instead generated on the fly, then the deallocation of the portion of the cache memory used by the acquisition engine may be a complete deallocation, thereby freeing up the cache memory 70 for use by one or more application processors 66. In operation 115, the GNSS processing system 68 may then derive pseudoranges and may use the pseudoranges and ephemeris data of the GNSS SVs to determine position data for the system (e.g., system 50).

[0134] In one embodiment, the GNSS processing system 68 may include dedicated memory that is separate from the cache memory 70 and dedicated for use by the GNSS processing system. In one embodiment, the memory controller 72 may include a first port controller that controls reads and writes to a portion used for the acquisition engine and a second port controller that controls reads and writes to the remainder of the cache memory 70. In one embodiment, generation of GNSS PRN codes and / or their DFT-derived code spectra may be performed only for healthy GNSS SVs that are in view when position data is requested (e.g., based on information about SV health and information about SVs in view in a received satellite almanac). This selective generation of GNSS PRN codes and / or their DFT-derived code spectra without storing the codes (in memory other than registers and buffers of the pipeline processing logic) after the tracking phase or during the acquisition and tracking phases may reduce memory usage of the GNSS processing system. The pipeline processing logic may include registers and buffers that transiently store codes and code spectra during one or a few clock cycles. In one embodiment, the GNSS processing system 68 may use an array processing architecture such as the one described below. Figure 6 、 7 , 8 and 9, to provide additional reduction in memory usage by the GNSS processing system by, for example, using an in-situ DFT algorithm.

[0135] In one embodiment, an operating system (or processor firmware) may perform allocation of portions of cache memory for a GNSS processing system based on information about the data stored in the cache memory (which may be referred to as metadata). For example, this metadata may indicate whether the data stored in the cache memory was "dirty" (e.g., it had been modified while stored in the cache memory) or whether it already existed in storage such as non-volatile memory (e.g., flash memory) or even backing storage in DRAM memory prior to allocating a portion of the cache memory for use by the capture engine. For example, if the cache memory was storing computer program instructions or code that had already been stored in non-volatile memory prior to allocating a portion of the cache memory for use by the capture engine, and those computer program instructions had not been modified while it was within the cache memory, then that portion of the cache memory may be allocated to the capture engine without having to write the data in that portion out to DRAM memory or out to non-volatile memory. This may allow the operating system (or processor firmware) to quickly refresh a portion of the cache memory; so that it may be quickly allocated for use by the capture engine of the GNSS processing system. Figure 2In the illustrated example, the GNSS processing system shares memory (e.g., cache memory 70) with one or more application processors (APs); in an alternative embodiment, the GNSS processing system may share the other memory with other processing systems on the IC (e.g., one or more other processors). In this alternative embodiment, the GNSS processing system shares the other memory and does not use or share the cache memory of the one or more APs. The other memory and the GNSS processing system and the other processing system may all be on the same IC (e.g., a system-on-chip (SoC) that also includes the one or more APs and the cache memory of the one or more APs). The other processing system may be one or more modem processors or graphics processors or codecs that use the other memory separate from the cache memory used by the one or more APs, and this separate (on-chip) other memory may also be a two-port ("dual-port") memory that supports high-bandwidth data access (both read and write). As described herein, when both the GNSS processing system and the other processing system(s) seek concurrent access to the other memory, the memory controller may arbitrate access to the other memory. In one implementation of this alternative embodiment, the other memory may be processor local storage of one or more other processing systems, and these one or more other processing systems use their processor local storage exclusively except when the GNSS processing system needs to use the processor local storage.

[0136] Another aspect of the present disclosure relates to using an array processing architecture utilizing DFT to acquire and track GNSS signals from, for example, an E5GNSS SV. Figure 4 、 5A , 5B, 6, 7, 8, 9A-9D and 10 and will now be described with reference to these figures. Figure 4 An example of a portion 150 of a GNSS receiver that receives GNSS signals and stores them in a two-dimensional (2D) baseband sample array after analog-to-digital conversion is shown. The GNSS receiver may include a GNSS radio frequency (RF) front end 153 that receives the GNSS signals via an antenna 151 coupled to the GNSS RF front end 153. In one embodiment, the GNSS RF front end 153 receives only L5 WB GNSS signals.

[0137] Figure 12 1 shows an example of components and architecture that may be used in one embodiment of the GNSS radio receiver 153. Figure 12As shown, the GNSS receiver includes an RF front-end module 701, an RF and mixed-signal section 702, and a digital front-end 703, both of which can be integrated into an ASIC (which can be part of the SOC 52). The RF front-end module 701 can be separate from the ASIC containing the digital front-end 703 and possibly the RF and mixed-signal section 702. The RF front-end module 701 can be implemented in an RF integrated circuit (IC) coupled to a GNSS antenna 707, which is tuned to receive L5 WB GNSS signals. The GNSS antenna 707 is typically off-chip and therefore not on the RF IC. The GNSS antenna 707 receives the GNSS signals and provides them to a bandpass filter 709, which is configured to pass signals centered at 1192 MHz and having a 51 MHz passband. Thus, GNSS signals between approximately 1166.5 MHz and 1217.5 MHz pass through the bandpass filter 709. The output of the bandpass filter 709 is coupled to the LNA 711 to provide the bandpass filtered GNSS signal to the LNA 711. In one embodiment, the GNSS antenna 707 is tuned to receive only the L5 WB GNSS frequency signal. The RF front-end module may include a low noise amplifier (LNA) 711 that is tuned for only the L5 WB band and is therefore optimized to receive the L5 WB band and is Figure 12 In the GNSS receiver shown in FIG, , there are no other LNAs for receiving other GNSS signals (e.g., L1 GPS). The output of LNA 711 may be filtered by bandpass filter 713, and the output from filter 713 is amplified in amplifier 715 (located on the ASIC containing the RF and mixed-signal section 702), and ADC 71 then generates digitized GNSS sample data, which is then processed in one embodiment to generate two streams of digitized GNSS sample data: one for GNSS sideband A and the other for GNSS sideband B. A clock generation phase-locked loop 719 and clock dividers 723 and 725 generate clock signals used by ADC 717 and by CIC decimators 721 and 729 to generate digitized GNSS sample data for up to four GNSS signal components (e.g., E5AI, E5AQ, E5BI, and E5BQ). Downconverter 727 separates the I and Q signals, and sideband separation downconverter 731 separates the upper sideband from the lower sideband to provide GNSS sample data, which is stored in a baseband sample memory such as a Figure 6 In the baseband sample memory 253). Figure 12In one embodiment of the GNSS receiver shown, the GNSS receiver has a direct connection from an LNA (e.g., LNA 711) through one or more filters (e.g., bandpass filter 713) and / or one or more gain stages (e.g., amplifier 715) to an analog-to-digital converter (ADC 717), and this GNSS receiver does not have an RF mixer, and therefore does not have an RF mixer in the RF front-end module 701 and does not have an RF mixer in the digital front-end 703. In addition, this GNSS receiver does not have an RF reference local oscillator (e.g., no phase-locked loop), and there is no down-conversion (of frequency) in the RF signal path before the ADC (e.g., ADC 717). In conventional GNSS receivers, an RF local oscillator and one or more RF mixers are used to perform RF down-conversion in the RF signal path before the ADC.

[0138] Reference Figure 4 The output from the GNSS RF front end 153 may be provided to a radio frequency (RF) analog-to-digital converter (ADC) 155, which may generate digitized GNSS sample data from the digitized GNSS signal. In one embodiment, the output from the RF ADC 155 may be stored in a baseband sample array (such as Figure 4 1 ). In one embodiment, the baseband sample array 157 may have N2 or more rows and N1 columns to provide an N2 by N1 array (N2×N1). The number of samples in the array may be configured so that the Nyquist criterion is met to provide a sufficient number of samples. If, in one embodiment, N1=20 and N2=1024, then there are 20,480 samples over time (e.g., 1 ms or slightly more than 1 ms, such as 1.05 ms) that may meet the Nyquist criterion. The RF ADC 155 is configured to repeatedly receive analog samples from the GNSS RF front end 153 over time and convert them into digitized GNSS samples stored in the array 157. For example, the RF ADC may repeatedly convert samples of the GNSS signal and cause them to be stored in the array 157. In one embodiment, the array 157 may be implemented as a circular memory buffer that stores the digitized samples; as is known in the art, a circular memory buffer may use a write pointer to indicate the next write location in the array and a read pointer to indicate the next read location. The write pointer is used when the ADC 155 provides output to be stored in the circular buffer, and the read pointer is used when the ALU reads the next set of inputs for processing. The array 157 can provide data to a set of arithmetic logic units (ALUs) 159, which are configured to perform DFT and inverse DFT to provide acquisition of GNSS signals and (in one embodiment) tracking of GNSS signals, and Figure 6 、 7 , 8 and 9 show embodiments of the ALU 159. Before describing these ALUs 159, in reference Figure 5A and 5B , methods for manipulating the schema using this array will now be provided. Figure 5A and 5B The method shown can be used Figure 6 Array processing architecture shown.

[0139] exist Figure 5A In operation 201, digitized GNSS sample data is stored in a two-dimensional memory array, which may be a circular buffer (such as a buffer) containing slightly more than one 1 millisecond frame of GNSS signal data (such as 1.05 or 1.25 milliseconds of GNSS signal data). Figure 6 Memory 253 in the memory array. A frame of E5 GNSS PRN code data in a GNSS signal is 1.0 milliseconds long. The additional memory exceeding one millisecond can be determined based on the time required to calculate the spectrum of the input data (via DFT) before the data is overwritten. Therefore, a faster DFT means that a shorter additional time of more than one millisecond is sufficient. In one embodiment, the data in the memory array is formatted so that consecutive rows contain consecutive time samples. For example, the first row may contain samples from the time period t1 to t20, and the second row may contain samples from the time period t21 to t40. Figure 4 Array 157 shown in FIG. 1 shows an example of such an array, which, in one embodiment, may be stored in Figure 6In one embodiment, these optimizations aim to minimize the number of clock cycles required to perform the correlation process, which is implemented using frequency-domain operations: that is, the inverse DFT of the product of the DFT of the input samples multiplied by the complex conjugate of the code samples adjusted for carrier frequency produces correlations of the input samples under all possible code hypotheses under the carrier frequency hypothesis. This single step, defined herein, is referred to as very fast frequency-domain correlation (VFFDC), a form of frequency-domain correlation (FDC). Optimizing the data flow through these operations reduces the number of clock cycles required to perform the correlation. The advantage is that for a given system clock, the number of carrier frequency estimates or hypotheses that can be checked within a millisecond is increased. Furthermore, reducing clocks means that system timing requirements can be relaxed, allowing for more reliable chip designs, designs that can operate at lower voltages to reduce power consumption, or faster clocks for higher throughput. Alternatively, methods for performing FDC that require more clocks but then require a higher clock frequency can be employed. The clock required to perform FDC can be reduced by using a matrix configuration (e.g., array 157) whereby the outputs of the samples and code spectrum are ordered so that the clock required to perform the IDFT of the complex conjugate of the product is reduced. Then, in operation 203, the GNSS processing system (such as Figure 6 The GNSS processing system shown or Figure 2 The GNSS processing system 68 shown can retrieve the GNSS baseband data from the two-dimensional memory array and load the retrieved GNSS baseband data into a set of DFT ALUs. For example, the set of DFT ALUs can be a set of four ASIC hardware DFT ALUs in the capture engine, wherein each of the DFT ALUs can perform 20 parallel DFT operations in each DFT ALU in response to a single program instruction. In one embodiment, the set of DFT ALUs can be Figure 6 2. In operation 205, the GNSS processing system may generate PRN code data (or alternatively retrieve such PRN code data from memory) and / or their code spectra from the DFT for each expected GNSS signal source (such as each set of E5 or L5 or B2 GNSS SVs known to be in view). Once the PRN code data is generated, it may be time- and frequency-shifted, and may also be row-upsampled and interpolated (e.g., by adding zeros to fill the last bit in the code) to generate the PRN code data obtained by a set of DFTs (e.g., using Figure 6 The DFT ALU 261 in the DFT ALU 261 generates code data that can be stored in a code spectrum array (such as Figure 6 In one embodiment, operation 205 may be performed by a code generator 259 that generates code array data, which may then be stored in a code spectrum memory 263 as shown in FIG. Figure 6The DFT ALU 261 shown in FIG. 2 is processed to generate a code spectrum array (in column order) temporarily stored in the code spectrum memory 263.

[0140] It should be noted that the code Doppler on the E5 band signal is much faster than the code Doppler on the L1 band. This code Doppler is the carrier Doppler scaled by the ratio of the carrier period to the code chip. In L1, there are 1540 carrier periods per code chip. For example, in L5, there are 116 carrier periods per code chip. Therefore, the code chip number in L5 is 13.28 times faster, which means that the correlation in the E5 band requires faster updates to the code phase to accommodate consistent correlations over consecutive frames of the PRN code. This means that it is generally impossible to pre-calculate this effect. An alternative solution is to apply the code Doppler effect to the correlation results before adding them to the hypothesis memory. The storage address can be shifted to account for the code Doppler, but this results in some loss because the shift is quantized to the number of hypotheses, typically about 2 hypotheses per code chip. Therefore, it is preferable to apply the code Doppler to the generated code before generating the code spectrum. Another optimization is to multiply the carrier Doppler by the generated code to match the carrier information in the input samples. In this way, the DFT of the input samples only needs to be performed once per millisecond for each sideband and or centerband, and the same input spectrum can be used for all correlations within that millisecond.

[0141] In operation 207, a set of DFT ALUs (such as Figure 6 The DFT ALU 255 shown in FIG. 255 may perform multiple DFTs in parallel on the loaded GNSS baseband data using a time decimation method and store the results in a frequency domain result memory (such as a Figure 6 In the memory 257 shown. Figure 6 In the example shown, operation 207 performed by DFT ALU 255 produces an array that is stored in a memory 257 in column order, and the data in memory 257 can be retrieved to provide Figure 6 The output 258 in operation 209 may be multiplied by a code spectrum stored in a code spectrum memory such as code spectrum memory 263; Figure 6 In the example shown, multiplier 265 performs this multiplication of operation 209 and produces a product array of data. Then, in operation 211, a set of inverse DFTs can be performed on the data in the product array using a frequency decimation method, and these DFTs can use conjugate inputs to produce an inverse DFT. In one embodiment, Figure 6 The inverse DFT ALU 267 shown may perform operation 211, and the output from the inverse DFT ALU 267 may be Figure 6 The data is processed in the relevant post-processing operator 269 shown and then stored in what may be referred to as an integration memory (e.g., Figure 6In one embodiment, this integration memory can store the hypothesis data during the capture phase. In one embodiment, this integration memory can be located in a memory allocated for the Figure 6 The GNSS processing system may then perform operation 215 by determining the frequencies of the acquired PRN codes, which frequencies identify the GNSS SV that transmitted the acquired PRN codes. Once it is confirmed that GNSS signals have been acquired from a particular GNSS SV, operation 217 may be performed for each acquired GNSS SV signal by entering a tracking mode for those acquired GNSS signals. In one embodiment, the tracking mode may use conventional correlators or other techniques (such as DFT) to determine pseudoranges to the acquired and tracked GNSS SVs. This is done in Figure 5B , shown as operation 219. The GNSS processing system may then use the determined pseudoranges to derive the position of the GNSS receiver by using the pseudoranges to the tracked GNSS SVs and ephemeris data to derive the position (e.g., the latitude and longitude of the GNSS receiver), as is known in the art.

[0142] Figure 6 Shows that it can be executed Figure 5A and 5B An example of a fast frequency domain correlator architecture for the method shown in . Memory 253 may be a circular buffer memory that stores N2 by N1 digitized GNSS signal samples. In one embodiment, memory 253 may be two circular memory buffers that store 1.05 or 1.25 ms of GNSS sample data; one of these circular memory buffers may store GNSS sideband A sample data and the other may store GNSS sideband B sample data. The two different sidebands may be separated and then stored using the following method. To obtain the upper sideband (e.g., E5B or B2B), the GNSS sample data is digitally carrier shifted down (for a sampler centered at 1191.795 MHz) by, for example, 15.345 MHz (and thus will now represent information in the sample data that was originally at 1207.14 MHz), the shifted sample data is then filtered through a low pass filter to capture a data bandwidth of + / - 10.23 MHz, and the filtered sample data is then decimated from the wideband samples to a lower sampling rate for use in Figure 6To obtain the lower sideband (e.g., E5A or B2A or L5 or QZSS), the GNSS sample data is digitally carrier shifted up (for samples centered at 1191.795 MHz) by, for example, 15.345 MHz (and thus will now represent information originally at 1176.45 MHz in the sample data), and then the shifted sample data is filtered through a low pass filter (LPF) to capture a data bandwidth of + / - 10.23 MHz, and then the filtered data is decimated from the wideband samples to a lower sampling rate for use in Figure 6 The DFTALU 255 retrieves data from memory 253 and performs a set of DFTs in the DFT ALU 255; Figure 7 An example of the components within DFT ALU 255 is shown. Figure 7 In the example shown, there are two stages of DFT. The first stage uses N1 DFTs, each operating on 1024 points based on inputs including the phase factor input from array 301 and the data input from memory 253, which can be similar to Figure 4 The data shown in array 157 in . The input to this array is input 251, which can be composed of, for example Figure 4 An analog-to-digital converter such as RF ADC 155 shown in FIG. Figure 7 A set of 20 DFT operations are shown, three of which are shown as operations 303, 304, and 306. The results of these operations can be stored in a partial result sample array 308, which in turn provides an output that is used as input to the second stage (where there are N2 DFTs); these N2 DFT operations include Figure 7 One of the inputs to these N2 DFTs is a set of phase factors from array 311. Figure 7 The output of these DFT operations in the second stage shown in FIG2 is stored in FFT result array 257, and the data is stored in column order that is reversed from the row order in which the data is stored in memory 253. This reversal allows the data to be prepared for inverse DFT operations, such as those performed by inverse DFT ALU 267, without having to transpose or otherwise reformat the data.

[0143] Figure 8 An embodiment of the inverse DFT ALU 267 is shown. Figure 8In the example shown, the inverse DFT ALU may include two stages of DFT operations that receive data from the product array of multiplier 265. The first stage may include N2 DFT operations that use the data from the product array generated by multiplier 265 (with conjugate inputs) and also use phase factors from phase factor array 351 to generate outputs that may be stored in first stage sample array 361. Figure 8 Each of the N2 DFT operations in is performed on 20 data points. Figure 8 Two DFT operations 355 and 357 are shown out of a total of N2 DFT operations. Figure 8 In the example shown, the second stage of the DFT operation uses N1 DFT operations, where each operation is performed on N2 points; Figure 8 Three of these operations 363, 365, and 367 are shown, each receiving a column of data from the first stage sample array 361. These DFT operations in the second stage also receive phase factor inputs from the phase factor array 353, and these DFT operations in the second stage produce 20 outputs that can be found in Figure 8 The results of the post-processing can be stored in the integral array 373 (which can be connected to the integral array 373). Figure 6 from arrays 301 and 311 (in Figure 7 ) and arrays 351 and 353 (in Figure 8 The phase factors (in the figure) specify the required phase shift for each radix-20 / 16 / 8 DFT at each stage of the FFT. In one embodiment, these phase shifts are used to decompose the 20480-point DFT into multiple stages of radix-20 / 16 / 8 DFTs, which form the basis of the FFT implementation of the DFT. The phase factors are also known as the "rotation factors" of the FFT.

[0144] Figure 9A 、 9B , 9C and 9D show that the code spectrum memory (such as Figure 6 and 8 In one embodiment, Figure 9DThe code generator 259 and DFT ALU 261 shown in can generate PRN codes and / or their code spectra from the DFT on-demand and on-the-fly for only GNSS SVs in view as the GNSS processing system acquires and tracks those GNSS SVs, without storing (except for transient storage for a few clock cycles in registers and buffers in the processing pipeline) the PRN codes and / or their code spectra from the DFT. This can improve the memory usage of the GNSS processing system by reducing the amount of memory required to operate the GNSS processing system. In an alternative embodiment, the code generator can generate PRN codes and / or their code spectra from the DFT on-demand during the acquisition and tracking phases for only GNSS SVs in view but store those codes until one or more positions, such as one or more latitude and longitude values, are determined. Thereafter, the PRN codes and / or their code spectra from the DFT can be deleted from storage to allow other uses of the storage. In one embodiment, as Figure 9D As shown in FIG, the code spectrum generator 259 may use a polynomial type generator 402 ( Figure 9A 408, 410, and 412. The phase rotations may be based on a programmable phase split input 406. Another set of CORDIC phase rotations, including phase rotations 417, 419, and 421, may then produce an output that is then processed using the same DFT operation (in one embodiment, by Figure 6 The DFT operation (performed by the DFT ALU 261 in one embodiment) then processes the output. Figure 6 The result of the DFT ALU 261 in the code spectrum memory (such as Figure 6 In the code spectrum memory 263 shown.

[0145] One embodiment of the polynomial type generator 402 is Figure 9A This embodiment can be used to perform Figure 9B and 9CThe method shown. This generator 402 includes two calculated (pre-calculated) code advance matrices 501 and 502. If pre-calculated, the code advance matrices 501 and 502 are retrieved from a lookup table, for example. For example, for each of the four components of the Galileo E5A and E5B signals, there is a corresponding code seed and master code polynomial data; this information is well known in the art and published in the ICD of the source of the GNSS constellation. The generator 402 can generate more than 2 master PRN code bits in a single clock cycle by using the calculated code advance matrices 501 and 502; see Figure 9B Operations 955 and 957 in FIG. Figure 9A As shown, the calculated code advancing matrix 501 includes a first input for receiving a generator polynomial 503 (generator polynomial 503 may be master code polynomial data for a given GNSS constellation and a given GNSS signal component), a second input for receiving a value fed back from a register 515, and an output that serves as a first input to a multiplexer (MUX) 511. A second input 507 of the MUX 511 is a constant initial value of all 1s (14 bits, each set to a value of 1 in one embodiment); this second input 507 is used only for the initial output from register 515, and thereafter the MUX 511 selects the first input (to the MUX 511) as the output from the MUX 511, and this output is stored in register 515 (which may be a clock register) so that on the next clock cycle, the last output from the MUX 511 is fed back to the second input of the code advancing matrix 501 and is also provided as the first input to an XOR logic gate 519. The output from MUX 511 fed back to the second input (of the code advancement matrix 501) is multiplied by a constant value (derived from the generator polynomial 503) in the code advancement matrix 501 to generate the next output from the code advancement matrix 501, and the next output passes through MUX 511 and is stored in register 515; this process of feeding back the output from register 515 and performing matrix multiplication of the output and the constant value in the code advancement matrix 501 is repeated on each clock cycle (or alternatively on a group of several clock cycles) to generate an N-bit primary PRN code for a given GNSS constellation (e.g., Galileo E5) and a given GNSS signal component (e.g., E5AI) in each clock cycle. In one embodiment, N can be greater than 2, such as 10 or 14 bits. Thus, the generator 402 can quickly generate many (e.g., N) bits of primary GNSS PRN codes in one clock cycle or several clock cycles. Figure 9AIn the example shown, 14 bits are generated at the output of register 515, but only the last 10 bits are used by XOR logic gate 519 (which performs an exclusive-OR logic operation). Code advance matrix 502 is used in a similar manner to code advance matrix 501. For a given GNSS constellation and GNSS signal component, and a given seed for a GNSS SV in a given constellation, code advance matrix 501 and code advance matrix 502 (in one embodiment) are pre-computed to generate the next N bits (N-bit "advance") of the master GNSS PRN code for that GNSS signal component from that GNSS SV (at the output of exclusive-OR logic gate 519) based on the values in the matrices and the previous outputs from registers 515 and 517. The Matlab appendix includes an example of code generator 402 that can create and use these pre-computed code advance matrices, in the form of well-known Matlab code. In one embodiment, the pre-computed code advance matrix can be pre-computed (or calculated at runtime) for each clock cycle by multiplying the original matrix containing the master polynomial data N times to provide an N-bit advance in the PRN code. For example, if N=3 advancement is required, the original matrix ("A") is multiplied 3 times (A*A*A) to provide the output of the next 3 bits in the PRN code for the N=3-bit code advancement matrix. Figure 9AAs shown, the calculated code advancing matrix 502 includes a first input for receiving a generator polynomial 505 (generator polynomial 505 may be a master code polynomial data for a given GNSS constellation and a given GNSS signal component), a second input for receiving a value fed back from register 517, and an output that serves as the first input to multiplexer 513. Second input 509 of multiplexer 513 is a seed value corresponding to a GNSS SV in a given GNSS constellation. This seed value is used only for the initial outputs from multiplexer 513 and register 517. Thereafter, multiplexer 513 selects the first input (to multiplexer 513) as the output from multiplexer 513, and this output is stored in register 517 (which may be a clock register), such that on the next clock cycle, the last output from multiplexer 513 is fed back to the second input of code advancing matrix 502 and also serves as the second input provided to an XOR logic gate 519. The output from MUX 513, which is fed back to the second input (of code advance matrix 502), is multiplied (in a matrix multiplication operation) by the precomputed value in code advance matrix 502 to generate the next output from code advance matrix 502. This next output passes through MUX 513 and is stored in register 517. The outputs of registers 515 and 517 are XORed by XOR logic gate 519 on each clock cycle to provide 10 new bits (i.e., a 10-bit advanced PRN code). The 14-bit output is truncated to provide 10 new bits in the current clock cycle. Code advance tens bit 524 selects this truncation. XOR logic gate 521 then performs an XOR operation on the output from XOR logic gate 519 and the secondary code bit 523 of a given GNSS signal component from a given GNSS SV to "erase" or "remove" the secondary code from the code generated at the output of XOR logic gate 519. Left shift logic 527, upsampling logic block 529, and left shift logic 533, along with registers 526 and 531, further process the generated master PRN code to provide code samples that can be "aligned" with GNSS samples received at a particular sampling rate so that the sampling rates match and can be aligned. The shift logic can be used to shift or move to different parts of the PRN code. The output of left shift logic 533 is provided to Figure 9D The time shifter 404 in the code spectrum processing pipeline is shown.

[0146] Figure 9B and 9CA method for operating the code generator 402 is shown. In operation 951, the GNSS processing system determines the GNSS SVs in view from conventional assistance data (e.g., such as the most recently downloaded version of the GNSS satellite almanac) or from ephemeris data in the form of equations. In one embodiment, the GNSS SVs in view may be limited to L5 WB GNSS SVs, such as one or more of the Galileo E5 GNSS constellation, the U.S. L5 GNSS constellation, and the Chinese Beidou (Beidou / Compass) B2 constellation. Then, in operation 953, the GNSS processing system may determine a code seed and a code generator polynomial for each GNSS signal component from the GNSS SV in view (e.g., the E5AI and E5BI of the Galileo E5 GNSS SV) to generate a primary PRN code for the GNSS signal component. The code generator polynomial may be a set of known coefficients for the signal component. Then, in operation 955, the G1 code advance matrix is calculated (or the G1 code advance matrix is pre-calculated and retrieved from a lookup table in non-volatile memory), and in operation 957, the G2 code advance matrix is calculated (or the G2 code advance matrix is pre-calculated and retrieved from a lookup table in non-volatile memory). In one embodiment, each of the G1 and G2 code advance matrices is pre-calculated by multiplying the original matrix of the master code polynomial data N times, where N represents the number of desired code bits to be generated. For example, if the amount of code "advance" is 10 bits of master PRN code data, the original matrix is multiplied (by itself) 10 times to create a 10-bit code advance matrix. In one embodiment, the amount of code "advance" is the number of bits of master PRN code data generated in one clock cycle, so if N=10, then for each clock cycle, the code generator generates 10 bits of new master PRN code data. After the G1 and G2 code advance matrices are retrieved (if pre-calculated) or calculated, the method can continue in operation 959. In operation 959, the system uses the initialization vector (all 1s) to provide a first G1 output (thus, the first G1 output is an initialization vector of all 1s) and the system uses the code seed to provide a first G2 output (thus, the first G2 output is the code seed); in operation 961, the system performs an exclusive OR operation on the first G1 output and the first G2 output to provide a first set of N-bit PRN code data. After operation 961, the first set of N-bit PRN code data is processed in operations 969, 971, and 973 (as shown in FIG. Figure 9B and 9C As shown, when processing proceeds from operation 961 to operation 969 via 9X) and all subsequent groups of N-bit PRN codes are generated in a loop of operations 963, 965, 967, 969, 971, 973, and 975. In operation 963, (e.g., from Figure 9A The G1 output of register 515 in is fed back to the G1 code advancement matrix, and (e.g. from Figure 9AThe G2 output (e.g., from register 517) is fed back to the G2 code advance matrix. Then, in operation 965, the last G1 output (e.g., from register 515) is multiplied by the G1 code advance matrix to generate the next G1 output, and the last G2 output (e.g., from register 517) is multiplied by the G2 code advance matrix to generate the next G2 output. In operation 967, the G1 and G2 outputs are XORed (e.g., in Figure 9A 969). In operation 969, the code output from XOR logic gate 519 is XORed (e.g., in XOR logic gate 521) with the expected auxiliary code bit (e.g., auxiliary code bit 523) to erase or remove the auxiliary code from the code output. Code samples are then generated and provided to the remaining code spectrum processing pipeline in operations 971 and 973. These operations prepare the code samples so that their sampling rate can match the sampling rate of the received GNSS sample data. Operation 975 determines whether to continue generating GNSS primary PRN code data. In one embodiment, when tracking of all required GNSS signals is completed, the generation of PRN code data can be terminated, but if such tracking is required, the process continues in a loop of operations 963-975.

[0147] Figure 10 An example of a GNSS processing system that can be used to perform the methods described herein or that can be used to implement the systems described herein is shown. The GNSS processing system 450 can be implemented on its own integrated circuit (such as a navigation chip 451) or as part of a system-on-chip architecture that is part of a larger system such as a smartphone or tablet. The GNSS processing system 450 may include processing logic such as an ARM processor 466 that uses ARM program and data memory 467 to control the operation of the GNSS processing system 450. In addition, the GNSS processing system 450 may include a processor that can be similar to Figure 44. The GNSS processing system 450 may also include a clock phase-locked loop generation and gating circuit 464 to generate a clock using a phase-locked loop and for other operations in the GNSS processing system 450. The GNSS processing system 450 may include both logic modules and memory to perform the acquisition and tracking processes described herein. For example, the logic module 457 may include an acquisition engine 458, which may include a set of DFT and inverse DFT processors or ALUs to perform the DFT operations described herein. In addition, the logic module 457 may include a digital front end 460, which may provide processing both before and after the RF ADC 465 in all digital E5 GNSS front ends. The logic module 457 may also include multiple satellite signal generators, such as a satellite signal generator 459 that generates GNSS PRN codes for GNSS satellites (SVs) in view based on assistance data that may be received from a cellular data communication network, for example. The logic module 457 may also include a timing and control module 461 and a memory interface and bus control module 462 to allow the GNSS processing system to be coupled to one or more application processors. The logic module 457 may be coupled to one or more memories to store various data in various data structures, including, for example, a baseband sample memory 468, a capture engine command memory 469, an FFT program memory 470, an FFT constant memory 471, an FFT variable memory 472, an FFT result memory 473, a code spectrum generation memory 474, a coherent integration memory 475, an IFFT memory 476, an IFFT memory 477, an IFFT variable memory 478, and a non-coherent integration memory 479. These memories may be used with the logic module 457 to perform the operations described herein. It will be understood that alternative architectures may be used with Figure 10 Different processor and memory arrangements are shown.

[0148] In another embodiment, the clocks required to perform the DFT calculation are reduced by executing multiple kernel operations in parallel. For example, if the sampling rate is chosen to be 2^N, e.g., N=14, the DFT can be implemented using a radix 4 kernel with seven stages. Each step in each stage processes four samples in place. Assuming only dual-port memory with one read and write per cycle, the clocks required are 4*4096 per stage, and seven stages result in 114,688 clocks. Figure 6The VFFDC shown in [1] can implement a DFT in approximately 4096 clocks. To achieve similar performance, 32 cores can be implemented in parallel, allowing one stage to complete in 512 clocks, and seven stages to complete after 3584 clocks. However, this approach would require the ability to handle 32 input samples in parallel. Therefore, the advantage of VFFDC is that it can achieve low clock rates, reading only 10 memories in parallel. Another embodiment is to use a clock rate four times higher, and then only 8 cores would be required in parallel, reducing the parallel memory read requirement to 8 inputs / outputs per clock. The advantage of VFFDC is that it maintains both a low clock rate and a low parallel memory read / write configuration. Such optimization allows for low power consumption, as the system can operate at low clock speeds and achieve reliable timing at low voltages.

[0149] In one embodiment, VFFDC implements a processing chain with minimal memory requirements. Every millisecond, two DFTs are performed on the input samples, one for each of the upper and lower sidebands of E5. Then, for each component of each satellite signal (four for E5, two for L5, and four for future B2), there is a DFT that includes code Doppler and carrier frequency effects, eliminating the need to apply a different DFT to the input samples to remove carrier frequency assumptions. Another DFT then performs the inverse DFT of the input and the code-spectral product. Therefore, the total number of DFTs per millisecond is 2 + 2 * N channels * M components, where the first two are the original input DFTs and the second two are the IDFTs to derive the code spectrum and spectral product. For 22 channels with a maximum of four components per channel, this results in 2 + 2 * (22 * 4) = 178 DFTs per millisecond. If the code-spectral DFTs are precomputed, the input samples are necessarily unique for each frequency of each PRN. In this case, for M = 4 and N = 22, the number of DFTs is (2 * M * N) = 176. However, this requires memory to store the code spectrum. Such a system also requires a method to generate the code Doppler after each IFFT and before updating the hypothesis memory. Therefore, even if this alternative has nearly the same number of DFTs, it requires additional memory and potentially higher power consumption to move the code spectrum DFT to the AE every millisecond. For example, at 20,480 hypotheses per millisecond, it would require 22 channels * 4 components * 2 bytes for the I and Q components of the code spectrum * 20,480 hypotheses * 8 bits per byte = 28 Mbits per millisecond = a bus rate of 28 Gbits per second. Such a configuration would be nearly impossible to implement. Therefore, in-situ computing power makes the system feasible.

[0150] Another optimization to reduce system memory is to allow all four components of E5-band signals (such as Galileo E5 and the future B2) to be processed into a single hypothesis memory for long-term integration to overcome weak signals (which are caused by high system losses in the handset and / or high losses caused by foliage or the user's body attenuating the signal). The public domain interface control document for B2 only describes the lower sideband, but other technical papers indicate that the upper sideband signal structure will be available in late 2019 or later. Therefore, GPS L5, which has only one sideband, will have only two components, while E5 and B2 will have four components: two components each for the upper and lower sidebands.

[0151] The main challenge in coherently integrating the sum of each millisecond code correlation is to reduce cancellation losses due to phase reversals at 1 ms epochs. If the received signal primary code phase can be estimated to be on the order of 0.5 ms or less, it is possible to at least partially align the received signal spectrum in time with the estimated code phase, so that sub-millisecond cancellation is avoided. Figure 11 An embodiment is shown that can provide accurate temporally coherent integration.

[0152] In one embodiment, estimating the expected fractional primary (ms long) code phase of the candidate signal requires knowledge of both the precise time and the initial position. The precise time can be derived from the secondary code phase of the first received signal, or it can be derived from a fine time source, as is well known in the art. This estimate can be Figure 11 Operation 601 in.

[0153] Once the master code phase uncertainty is reduced to well below 1ms, the submillisecond cancellation problem can be solved by at least partially aligning the received 1ms signal epoch with the time at which the code from each SV is expected to be received. This means that multiple received signal spectra must be calculated every millisecond and staggered in time to match the master code spectrum and thus reduce the level of submillisecond coherent cancellation.

[0154] The search order may establish which SVs, their signal components, and Doppler bins will be searched for at each fractional phase offset. Figure 11, shown as operation 603. Because long coherent integration yields greater sensitivity, the E5Aq and E5Bq pilot signals may be used preferentially due to their 100ms-long secondary codes and lack of data bit reversals. In one embodiment, E5Ai and E5Bi may also be used when the navigation message symbols are predicted and removed, thereby eliminating or reducing their corresponding coherent cancellation losses. It should be noted that while the primary code phases of all signals are expected to be evenly distributed within milliseconds, there may be situations where the only available processing slot for a given signal is suboptimal. Regardless, it is always possible to avoid the worst-case scenario where the first 1 / 2 ms signal cancels the second 1 / 2 ms signal in the presence of secondary code bit reversals.

[0155] In one embodiment of the present invention, M 1ms signal spectra are calculated every millisecond, each offset by 1 / M ms. For example, if M=4, then every 0.25 milliseconds, a full 1 millisecond (or more) of received and digitized GNSS sample data is processed by FFT correlation (e.g. using Figure 6 ), so in this case the processing epochs are separated by 0.25ms and offset (one to the next) by 0.25ms, and the received GNSS sample data is also offset by 0.25ms. In this example, the first processing epoch at relative time 0.0ms will process the FFT correlation with respect to the 1ms of GNSS sample data generated in operation 605. The correlation is as follows Figure 11 607. The second processing epoch at relative time 0.25 ms will process the FFT correlation (operation 607) using 1 ms of GNSS sample data that ends at relative time 0.25 (operation 605) and is offset by 0.25 ms from the previous 1 ms of GNSS sample data. The third processing epoch at relative time 0.5 ms will process the FFT correlation (607) using 1 ms of GNSS sample data that ends at relative time 0.5 (operation 605) and is offset by 0.25 ms from the previous 1 ms of GNSS sample data. Thus, operations 605, 607, and 609 are repeated four times during the 1 ms time interval. In an alternative, more sensitive embodiment, the signal spectrum will be calculated to align as closely as possible with each expected satellite code phase.

[0156] In the case of coarse time mode, candidate signal codes (received GNSS sample data) and their associated spectra must be generated and aligned every millisecond and correlated with the signal spectrum using VFFDC or similar FFT-based methods.

[0157] As these resulting correlation results are generated, they must be summed in a coherence hypothesis memory specific to each SV band and frequency bin, while removing the phase reversal associated with the secondary code phase. This is shown as operation 607. This process requires computing a full 1 ms correlation, even with code phase uncertainty much less than 1 ms. However, only that portion of the full PN code that is likely to contain the correlation peak must be stored in the hypothesis memory.

[0158] At secondary code epoch boundaries, or even more frequently in some cases, the coherent hypothesis memory must be incoherently added to an incoherent hypothesis memory that mirrors the coherent hypothesis memory but contains only amplitude information and can therefore remain half the memory. This is shown as operation 611.

[0159] Figure 11 The process continues in operation 613 (by looping back to operation 605) until the correlation peak rises above the noise floor. Once the correlation peak rises above the noise floor with sufficient confidence, the search result is reported and the acquisition search for the particular SV of interest can be stopped to make way for the next SV in the search sequence for its fractional code phase. The search may also time out after a preset time interval, and a search failure can be reported.

[0160] Figure 11 An example of a method is shown for searching for satellite codes aligned with the approximate time slots in which satellite codes are expected to be received, such that sub-millisecond coherence cancellation losses due to phase reversals can be reduced. This search can be performed based on an initial information group, which in one embodiment can include at least two of the following: (1) code phases of primary or secondary code signals received from at least one GNSS SV; (2) an estimated GNSS time based on one or more time sources, the estimated GNSS time uncertainty being estimated (e.g., based on the known accuracy of the sources) or known to be within less than + / - 0.5 milliseconds of the actual GNSS time; and (3) an approximate position of the GNSS receiver. Using this initial group, a method can be performed to determine the location of the satellite code. Figure 11 In operation 601. In effect, this initial set gives the system an estimate of GNSS time, enabling acquisition using GNSS time.

[0161] Another aspect of the present disclosure relates to using only a subset (a selected component) of two or four components of a GNSS signal during coarse time acquisition to first acquire the subset (such as only one of the four components) and then acquire the remaining components. In one embodiment, this selected component is selected based on the lowest probability of signal changes due to sign or phase reversal due to the coding scheme used in the selected component. In the case of Galileo's E5 GNSS signal, the E5BI component has the lowest probability of signal changes due to sign or phase reversal (see the Appendix for a detailed description of the various probabilities for different signal components) and can therefore be used as the selected component to perform coarse or fine time acquisition before attempting to acquire and / or track the remaining components in the Galileo GNSS signal. Figure 13 An embodiment of a method using this aspect is shown, which uses only a subset of the components. The method can be Figure 13 The process begins as shown in operation 801. In operation 801, a GNSS processing system in a GNSS receiver receives a request for position information, such as from an application processing system. In operation 803, the GNSS processing system determines a need or desire to switch to a simplified acquisition mode. This need or desire may be triggered by a failure in conventional acquisition attempts to acquire a complete set of GNSS signal components from a set of GNSS SVs in view of the GNSS receiver. For example, the GNSS may be unable to acquire E5AI and E5AQ signal components from several SVs in the Galileo constellation within a predetermined time period. This failure may trigger the GNSS processing system to switch to a simplified acquisition mode, in which the GNSS processing system attempts to acquire only selected components from each of the set of SVs in view during an initial acquisition phase. In operation 805, the GNSS processing system attempts to acquire only the selected component; in one embodiment, this is the E5BI signal component, and the GNSS processing system may attempt to acquire this signal component from several GNSS SVs. In operation 807, if the GNSS processing determines that the selected component has not been acquired, the processing system may revert back to operation 805 to continue attempting to acquire the selected component. In operation 807, if the GNSS processing determines that the selected component(s) have been acquired, the GNSS processing system may proceed to operation 809 to acquire other components from the same SV; for example, the GNSS processing system may attempt to acquire other signal components such as E5BQ, E5AI, and E5AQ from the same SV in operation 809. In operation 809, the GNSS processing system may use the time and phase information obtained from the acquisition process of the selected component from each SV to facilitate acquisition of the other signal components. As the number of correlations decreases, Figure 13The method shown in can also be used as a way to acquire stronger satellites more quickly, allowing a portion of the GNSS acquisition engine to search for multiple SVs in a larger frequency space more quickly and with lower power than when more GNSS signal components are employed.

[0162] Modern GNSS signals in the L5 band are susceptible to interference from aeronautical radio navigation (ARN) signals from commonly nearby locations such as airports or military bases. Figure 15A and 15B ) to mitigate this interference.

[0163] exist Figure 15A In the illustrated embodiment, the GNSS receiver may receive both GNSS signals and ARN signals in the L5 frequency band in operation 821. Typically, the GNSS receiver may include hardware that can measure signal levels (such as signal strength levels), and these measured signal levels may be compared with a predetermined noise floor in operation 825. This predetermined noise floor may be fixed over time or dynamically adjusted over time, but in most cases, the GNSS signal from the GNSS SV will be below the noise floor. The noise floor may be set based on the known signal strength of the GNSS signal relative to the known signal strength of the ARN signal. When the GNSS receiver is close to the source of the ARN signal (for example, the receiver is close to an airport), the ARN signal will typically be above the noise floor. Therefore, operation 825 may be used to detect the presence of an ARN signal by comparing the received signal with the noise floor. In one embodiment, a predetermined threshold above the noise floor may be used so that the ARN signal must exceed the predetermined threshold (the predetermined threshold is above the noise floor) before operation 829 is used to remove the ARN signal. In one embodiment, the ARN signal may be detected during the signal acquisition phase using the DFT array processing techniques described herein; in this embodiment, when the ARN signal is detected in the frequency domain, operation 829 may be invoked. When the ARN signal is detected above the noise floor (or the ARN signal is detected in the frequency domain), in operation 829, the GNSS processing system in the GNSS receiver may remove the ARN signal prior to correlation processing of the GNSS signal. In one embodiment, the ARN signal may be removed by a finite impulse response filter; the finite impulse response filter may receive a signal containing both a GNSS signal and an ARN signal and provide a filtered output containing the GNSS signal (with a significantly reduced amount of the ARN signal in the output). In another embodiment, during an intermediate frequency (IF) bandpass filtering operation (e.g., at Figure 4D 、 4FThe configurable notch filter used in the receiver architecture shown in FIG4 or 4J can be used to filter out the ARN signal before GNSS correlation processing.

[0164] exist Figure 15B In the illustrated embodiment, mitigation of known interfering signals (such as ARN signals) may be achieved by reducing the bandwidth of the GNSS radio receiver. Figure 15B An example of a method for narrowing bandwidth to one of two sidebands in a GNSS signal is shown. In operation 835, a radio receiver may receive a GNSS signal and an ARN signal via one or more antennas. The GNSS signal may include two sidebands, such as an E5A sideband and an E5B sideband. In operation 839, the GNSS receiver may detect interference caused by an interfering signal, such as an ARN signal, in one of the two sidebands. In one embodiment, this detection may be performed by observing the input data spectrum at each of the upper and lower sidebands every millisecond as the input data spectrum is received and processed. This detection may involve detecting a difference in interference levels such that one sideband has little or no interference while the other sideband has significant interference. In response to this detection, the GNSS processing system in the GNSS receiver may configure the GNSS processing system in operation 842 to process the sideband with less interference (such as less ARN interference) and not process (e.g., without any correlation processing) the sideband with more interference. In this case, only one sideband is used to derive code phase measurements and determine position data, while the other sideband is not used to determine the position of the GNSS receiver. In one embodiment, the GNSS receiver may continue to monitor for interference and switch between using the two sidebands in response to changes in the interference; for example, a GNSS receiver experiencing greater interference in the upper sideband may initially use the lower sideband (such that GNSS signals from the lower sideband are processed and GNSS signals from the upper sideband are not processed to determine position), and then switch to use of the upper sideband when the lower sideband experiences greater interference.

[0165] Single hypothesis memory

[0166] Another aspect of the present disclosure relates to using a single hypothesis memory to accumulate or sum the amplitudes of code phase hypotheses for multiple signal components from the same GNSS SV (such as a GNSS SV in the Galileo constellation of GNSS satellites). This technique can improve sensitivity by summing the code phase hypotheses for, for example, the E5BI, E5BQ, E5AI, and E5AQ signal components from the same GNSS SV in the Galileo constellation of GNSS satellites. This accumulation can be performed non-coherently when the time uncertainty is greater than 0.5 milliseconds (ms). This accumulation can also reduce the amount of memory used by the GNSS receiver.

[0167] Galileo E5 has four components: a data component and a pilot component on each of the two sidebands. GPS L5 has only two components: a data component and a pilot component, but only one sideband. BDS B2A and B2B also have four components: a data component and a pilot component on each of the two sidebands. QZSS has two components: a data component and a pilot component, but only one sideband.

[0168] Typically, each component has its own primary and secondary codes. For multiple components, it is also assumed that the number of bits in the primary code is the same across all components and that it repeats simultaneously. It is also assumed that the secondary codes can change as each primary code is completed. The length of the secondary codes need not be the same across all components, and typically each system has a different length for each component. For modern signals, the chip rate is 10230 bits per millisecond.

[0169] Typically, the sampling clock is chosen to be close to twice the chip rate in order to minimize the worst-case loss (where the signal arrival time is midway between two adjacent samples). Faster sampling rates (i.e., greater than twice the chip rate) reduce this loss, but increase the number of correlations to be performed and also increase the size of the integration memory. Slower rates (i.e., less than twice the chip rate) increase the loss, but also reduce the number of correlations to be performed and also reduce the size of the integration memory. Generally, the average loss is considered more important than the worst-case loss.

[0170] The preferred embodiment has a sampling rate close to twice the chip rate, but also has a rate that can be expressed as the product of N1 and N2, where N2 is a large power of 2, so that the FFT can be used to reduce the calculations on the DFT. Here the sampling rate is chosen to be 20480 samples per millisecond, so that N1=20 and N2=1024. Another option is N1=5 and N2=4096, and N1=10 and N2=2048.

[0171] For two samples per chip, the worst-case loss is when the true arriving code phase is halfway between the two samples. The correlation function is + / - 1 chip, and therefore there are 0.25 chips on either side of the true code phase. In this case, the correlation yields a 75% correlation, resulting in a loss of approximately 2.5 dB. (0.75 = 1 – 0.5 / 2 = 1 – 0.25)

[0172] Another example is N1 = 1 and N2 = 16384. This arrangement uses the largest possible FFT size, but is undersampled relative to the 2 samples per chip approach described above. Here, there are 10230 / 16384 = 0.6244 chips / sample, or 1.6 samples per chip. The worst-case correlation is now 69% of the maximum: 0.69 = (1–0.624 / 2), with a worst-case loss of 3.25 dB, or only a 0.75 dB increase in loss. This configuration reduces the number of correlations by 25% and reduces the integration memory by 25%.

[0173] Modern satellite broadcasts distribute additional power across multiple components. One approach to improving sensitivity is to correlate more than one component from the same input sample data signal in parallel and then sum all the individual component amplitudes or powers at each correlation hypothesis in the signal detection test. The signal information for all components at each code phase hypothesis is compressed by summing into a single value, which is integrated for each code phase hypothesis. In each frequency bin to be searched, the number of code phase hypotheses is equal to the number of correlations per primary code phase, which is 20,480 for a 20.48 MHz sampling clock and a primary code with 10,230 chips per millisecond.

[0174] At each code phase, each primary code sequence is tested at all possible candidate phases for each component. This can be best accomplished using a DFT implemented with an N1 and N2 point FFT; see, for example, Figure 6-8 This results in 20480 amplitudes for each component.

[0175] There are two ways to combine: coherently or incoherently.

[0176] The preferred embodiment is to combine non-coherently because the time uncertainty is typically greater than 1 / 2 millisecond, making it impossible to predict the secondary code phase. In addition, the random data bit phase makes it difficult to predict the phase between the data and pilot channels, even if the secondary code phase is known.

[0177] The magnitude of the complex correlation at the same code phase hypothesis is calculated for each component and added to a single value, which is integrated into a single memory segment. Figure 14N An example of a hypothetical memory arrangement with multiple bins is shown; each of these bins can store the cumulative sum of a code phase hypothesis across several signal components. Power can also be calculated, but amplitude is preferred because fewer bits are required.

[0178] Typically, the hypothesis memory is an integrating memory. For each primary code phase hypothesis, a new sum of the magnitudes of all components from the same GNSS SV for the current millisecond is added to the previous sum in the integrating memory, and this running sum overwrites the previous sum.

[0179] Summarize,

[0180] 1) At msec(k) and each primary code phase hypothesis (j), form the correlation amplitude of the primary code (i) for each component:

[0181] a.AMP(i,j,k)=real(i,j,k) 2 +imaginary(i,j,k) 2 For i = 1, 4 and j = 1, 20480, and k = current msec, AMP(i, j, k) = real(i, j, k) 2 +imaginary(i,j,k) 2 ,

[0182] 2) For each code phase, form the sum of the amplitude (AMP) at each component

[0183] a.AMP_ALL(j,k)=sum{AMP(i,j,k)}, for i=1,4, at the kth msec. That is, AMP_ALL(j,k)=AMP(1,j,k)+AMP(2,j,k)+AMP(3,j,k)+AMP(4,j,k), where i=1 is the E5A data channel component, i=2 is the E5A pilot channel component, i=3 is the E5B data channel component, and i=4 is the E5B pilot channel component.

[0184] 3) Retrieve the previous (k-1) millisecond integration segment for the jth code phase hypothesis

[0185] aX(j,k-1)=INT_MEM(j,k-1)

[0186] 4) Add the new amplitudes from all 4 components

[0187] aX(j,k)=X(j,k-1)+AMP_ALL(j,k)

[0188] The updated current integral sum X(j, k) is stored back into the hypothesis memory of the j-th code phase hypothesis.

[0189] In this above-described method, the number of memory banks is equal to the number of code phase hypotheses, which is smaller than with a similarly sized integration memory for each component.

[0190] Signal detection then uses this single integration memory so that there is no independent signal detection on each component. This test is typically:

[0191] The maximum integration memory value is obtained from the integration memory across 20480 hypotheses and its memory index X corresponding to a specific phase is remembered, where each bin holds the current sum of the amplitudes of all primary code components at that code phase.

[0192] Estimate the noise floor mean and standard deviation from 20480-Y hypotheses, where Y is the integration memory value adjacent to the maximum at code phase X. Here Y = 7, which includes the maximum at X, as well as the 3 integration memory samples before and after it. In this way, a total of 7 removed samples are ignored, making the noise floor statistics unaffected by the peak hypothesis.

[0193] Test that the signal-to-noise ratio estimate is above a threshold to set the false alarm rate.

[0194] test:

[0195] If SNR=10*log10((X 2 –noiseFloor 2 ) / noiseVariance)>K, a predetermined threshold sets the false alarm rate to an acceptably small value, then the signal is declared to be found and the integration is stopped. Otherwise, the signal is declared not to be found and the integration continues.

[0196] It should be noted that the carrier frequency generates code Doppler based on the well-known relationship between the number of carrier cycles in one chip of the primary code sequence. For E5a at 1176.45 MHz, there are exactly 116 carrier cycles per chip. This phase also has a negative rate. Therefore, long integration requires shifting the locally generated code at a rate equal to the carrier frequency assumption divided by -116 chips per second, so that the code remains consistent with the initial code phase assumption at the start of the integration.

[0197] Coherent integration of multiple components into a single hypothesis memory is also possible when the secondary code phase is known and the data bit phase is known. This is feasible when fine time assistance is available and the data bit stream is observed and quickly communicated from a second receiver. This is only possible when data is repeated or known data is available, which is possible over communications such as the Internet.

[0198] In addition to the phase reversal from the secondary code sequence and the data sequence, signals in the same sideband have different, but known, 90-degree phase offsets between the data and pilot channels. Due to the different carrier frequencies, signals in different sidebands have different phase offsets. However, the frequency offset of each sideband from the center channel is known because the Doppler shifts have the same magnitude but different signs about the center frequency. For example, if the E5 frequency Doppler is 1000 Hz, the E5A Doppler is 992 Hz, and the E5B Doppler is 1008 Hz. The carrier phase difference rotates with opposite signs, but the amplitude is equal between the A and B sidebands. The known phase offset is applied to the complex correlation by multiplying by a complex exponential with a known phase. In this way, the real and complex components of all adjusted components can be added to a single complex correlation value. The amplitude or power is then integrated into a single hypothesis memory segment for each code phase hypothesis.

[0199] Frequency Domain Doppler Compensation

[0200] GNSS (Global Navigation Satellite System) signals typically incorporate a pseudo-randomly modulated (PRN) waveform to enable accurate time-of-arrival measurements at the receiving terminal. Typically, the PRN waveform incorporates a repeating code whose duration is referred to as the frame length. The received waveform is processed using signal processing structures such as correlators, matched filters, and the like. The present invention focuses on GNSS signal acquisition based on the use of a Fast Fourier Transform (FFT) method, which effectively implements a matched filter corresponding to the received signal. This approach is particularly attractive when the spreading ratio (SR) of the PRN waveform is large, that is, when the ratio of the signal bandwidth to the frame length is large. In many modern GNSS systems, this spreading ratio can exceed 10,000. The FFT is a very efficient algorithm for computing the discrete Fourier transform (DFT), and although we use the term "FFT" throughout, by FFT we mean any method for computing the DFT, including various FFT algorithms including the Cooley-Tukey algorithm, the prime factor algorithm, the chirp z-transform algorithm, and so on.

[0201] Acquiring a GNSS signal with a high SR is difficult because the arrival time of the signal must be tested at a large set of time instants (e.g., more than 10,000 in the example above) and, in addition, at a large set of potential frequency offsets from the nominal hypothetical carrier frequency (the latter being due to Doppler effects and local clock errors). Furthermore, the test must be performed on a set of possible satellite signals that exist. These sets of time instants, frequency offsets, and number of satellite signals are referred to as "hypotheses." As can be seen above, the acquisition of a GNSS signal requires searching over a large three-dimensional hypothesis space. The use of an FFT method is very efficient for performing the time hypothesis search because it can process each possible time hypothesis over the frame length in parallel. The FFT method performs a matched filtering operation on a set of incoming time samples by (1) performing a forward FFT on the set of incoming time samples to produce a set of "signal frequency samples," (2) multiplying the signal frequency samples by the frequency samples of the PRN reference signal (referred to as "reference frequency samples"), and (3) performing an inverse FFT on the result. The output sample set is then further accumulated with the previous output set to perform "coherence processing," or the output samples are detected (usually by magnitude or magnitude squared operations) and accumulated with the previous data set that was similarly processed. The processed data set thus accumulated is observed for the occurrence of large peaks above the background noise samples, where the location of such peaks indicates the arrival time of the incoming signal.

[0202] As indicated above, during the acquisition process, the incoming signal may have a carrier frequency offset associated with it, which must also be determined. Conventional methods for such determination involve assuming a Doppler frequency, compensating for Doppler in the time domain by multiplying the incoming sample set by a complex sinusoid having the assumed frequency to remove the Doppler component, and then performing the three steps described above. This process is performed for each of a set of assumed Doppler frequencies. A problem with this approach, in an FFT implementation, is that it requires a forward FFT and a reverse FFT for each Doppler hypothesis frequency. In many cases, a set of such hypothetical frequencies, numbering 20 or more, must be searched. These embodiments of the present invention reduce the number of such FFTs to approximately half or less of the number required in the prior art methods described above, thereby reducing the overall processing time by approximately one-half or less.

[0203] In the following discussion, we refer to frequency uncertainty as "Doppler," but frequency uncertainty can also be due to local oscillator frequency errors. To simplify the discussion, we refer to any frequency uncertainty as "Doppler," but when we do so, we are actually referring to any source of frequency uncertainty, including possible errors in the components of the GNSS transmitter. Furthermore, in the initial discussion below, for simplicity, we ignore the multiplication of the forward FFT data with the reference frequency samples (as described above). In the first example discussed below, this is done just before performing the inverse FFT operation.

[0204] In the following discussion, reference is made to Figure 16A It may be helpful. After the forward FFT (1101), considering the FFT output as a vector, if one rotates the vector by m positions (1102), then this is equivalent to a frequency shift equal to m×bin spacing, where the bin spacing is equal to the sampling rate divided by the number of samples per FFT. Here m is an integer that can be positive for positive shifts or negative for negative shifts. If the input signal is positively Doppler shifted, then to compensate, one typically rotates the vector negatively, and vice versa. This has the effect of shifting the signal to near zero frequency or some other desired frequency. The advantage of this approach is that after one forward FFT, one can test multiple Dopplers with a series of inverse FFTs, each following a frequency shift via the rotation operation. The data in the frequency domain is considered to be cyclic in the sense that the data sample after the last frequency sample is the data sample after the first frequency sample. Therefore, this is usually called a rotation, rather than a shift. The invention also applies to normal shifts where zeros are appended to the data as needed. For example, if 20 Doppler frequencies are tested in this manner, only one forward FFT and 20 inverse FFTs are required, one for each of the Dopplers being tested. In this example, only 21 FFT operations need to be performed, whereas 40 are required in the standard method. Operation 1102 is performed multiple times to provide a series of Doppler-compensated frequency vectors, one for each of the Doppler bins being tested.

[0205] In many cases, checking the Doppler uncertainty region in increments of integer bin spacing is coarse, resulting in a worst-case loss of sinc(0.5) or 3.9 dB. To reduce this loss, it is desirable to perform a rotation of 1 / 2 bin spacing on the above vector, i.e., it is desirable to test for a Doppler equal to m + 1 / 2 bin frequency offset. This can be done in one of three ways.

[0206] In the first approach, two forward FFTs are performed, one without modification and the second with a time-domain implemented frequency shift equal to half the bin spacing, i.e., a frequency offset of sampling rate / (2′no_FFT_samples). This frequency offset is accomplished in the time domain by multiplying by a complex sinusoid in the usual way (or using an equivalent algorithm, such as CORDIC rotation). Each of these forward FFTs is stored. To test for Doppler error over an integer number of bins, the first forward FFT vector is rotated by the required number of bins. To test for Doppler error incorporating half the bin spacing, a second forward FFT vector is selected and rotated by the appropriate integer number of bins. For example, if one wants to test for Doppler error over m+1 / 2 bins (m being an integer), i.e., if one wants an overall compensation shift of -m-1 / 2 bins, then the second forward FFT vector is rotated by -m-1 positions. Here we note that the second FFT data set incorporates a shift of +1 / 2 segments (by assumption), resulting in a total shift of -m-1 + 1 / 2 = -m-1 / 2. Of course, the above technique also works if the data used before the second forward FFT is the first frequency offset minus one-half segment, or indeed the offset one-half segment plus a positive integer multiple or a negative integer multiple segment. In this case, the data vector after the second forward FFT will need to be rotated by the appropriate integer amount to achieve the overall required Doppler compensation.

[0207] The first method described above is very accurate, but of course, it doubles the number of forward FFT operations. In the previous example, a total of 22 forward FFTs are required compared to 40 FFTs in the standard method, which is still a significant saving. However, another disadvantage is that twice as many forward FFT vectors need to be maintained, which can be costly in memory, especially when multiple parallel FFTs are required to achieve the overall acquisition time.

[0208] refer to Figure 16A In the above discussion, switches (1109, 1110) pass the data from the forward FFT through processing block 1102, but switches (1111, 1112) bypass block 1103 (the interpolation operation). For alternative approaches to these embodiments, the switches are placed in other positions. Note that these "switches" are not necessarily hardware elements, but can be viewed as flow chart decision paths.

[0209] A second method for implementing an offset that incorporates 1 / 2 bin spacing is to use an interpolation technique in the frequency domain on the forward FFT samples to construct intermediate samples from each original frequency sample at 1 / 2 bin spacing. The vector of intermediate samples then replaces the second forward FFT as described above. This intermediate sample vector also rotates the required number of positions to achieve 1 / 2 bin spacing plus the Doppler shift of the necessary number of integer bins. Depending on the required complexity and accuracy, many different interpolation functions can be used to determine the intermediate samples. For example, a sinc interpolator can be used, i.e., sin(2pf) / (2pf), where f is in units of bin spacing. Alternatives include polynomial interpolators, splines, etc. Generally, the most suitable interpolator can be determined empirically because it depends on the frequency response of the time samples and the maximum complexity of the interpolator. By implementing 1 / 2 bin spacing via either method, the worst-case loss due to Doppler error becomes -0.91 dB. This does not include any additional implementation errors (e.g., interpolation errors).

[0210] The above interpolation method can be used in Figure 16A , where switches 1111, 1112 allow data to pass through the interpolation vector block 103. If the frequency shift is not + / - 1 / 2 bands, switches 1109 and 1110 may additionally be used.

[0211] In yet a third method, interpolation is performed, but instead of performing it in the frequency domain, the input set of data samples is augmented or "zero-padded" with additional frequency samples of zero value appended at the beginning or end of the sample set. If the set of zero-valued samples is equal to the sample set of the original sample set, then the FFT of the resulting augmented sample set will have an FFT that now has a bin spacing of 1 / 2 relative to the FFT of the non-augmented set. Thus, a simple rotation of the FFT vector now provides a frequency translation in either the positive or negative direction in a manner similar to that discussed above. Spacings of less than 1 / 2 bin can be achieved by augmenting the original set with more zero-valued samples (e.g., adding twice as many zero-valued samples would provide 1 / 3 bin spacing, etc.). The third method has the disadvantage of requiring an FFT of twice the size or larger and twice the storage space required to perform this process. This may not be as efficient as methods 1 and 2, although it may be competitive in some cases, particularly for relatively small FFT sizes. Zero padding can be used in Figure 16A , which is considered as an optional step at the input of block 1101 performing the FFT.

[0212] The choice between the first and second methods for testing Doppler with m+1 / 2 bin spacing depends on the complexity of the interpolation and the memory requirements of the first method. In terms of computational speed, it is desirable that the interpolator method use fewer operations per frequency sample than the FFT. While it appears that the interpolation process is computationally more efficient, a closer look reveals that this is not entirely clear, especially when only a few different Doppler frequencies are to be searched. In terms of operations per data sample, the FFT operation is very efficient. A radix-2 FFT of length N requires only approximately 2log2(N) real multiplications per data sample. For example, an FFT of size 1024 requires only approximately 20 real multiplications per data sample. An interpolator of equivalent complexity would have an interpolation filter of length (number of taps) equal to 10, since two real multiplications are required per frequency sample. Since frequency data is often very noisy, it is unclear whether such a short length would be sufficient to achieve the required accuracy. Note that even using the first approach, one can still advantageously employ the rotation vector block 1102 to reduce processing time when searching over a wide range of Doppler frequencies.

[0213] In addition to m+1 / 2 bin spacing, the above method can also be generalized to offsets of m+e bin spacing, where e is any number between 0 and 1. An additional forward FFT can be calculated after the frequency conversion of the input data (corresponding to the amount of e bins) and stored for later use, where this vector is used with an appropriate number of vector position shifts. Alternatively, an interpolation method can be used to determine the intermediate samples from any pre-computed FFT data set (e.g., a set with 0 frequency offset and 1 / 2 bin offset). Again, there is a trade-off between the required additional forward FFTs and the resulting increase in storage compared to the acceptable computational complexity of the interpolation method.

[0214] It should be clear from the above discussion that the three methods discussed above can be combined in various ways, for example the third method can be combined with the second method to achieve very small bin spacing without the need for additional FFT operations.

[0215] In another aspect of these embodiments, a set of Doppler frequency tests can be performed for more than one PRN, corresponding to more than one received GNSS satellite signal, without performing additional forward FFTs. That is, in the previously discussed method, a forward FFT or several forward FFTs are performed on the data, followed by a set of inverse FFTs to test for various Doppler shifts, all corresponding to a specific satellite signal, i.e., a specific PRN. As indicated above, as part of the overall processing, the frequency samples are multiplied with the frequency samples of the PRN reference signal. This occurs after the Doppler shift operation described above. This is because the PRN frequency samples are assumed to have zero frequency offset. Using the corresponding frequency samples of these additional PRNs, a similar set of inverse FFTs can be performed for the other PRNs, and additional Doppler frequencies can again be tested without having to perform another forward FFT corresponding to these additional PRNs. In all of the above methods, the frequency-shifted data is multiplied with the reference data from 1105 in multiplication block 1104 and then processed by the inverse transform process 1106. The output from this can be accumulated in 1107, either pre-detected or detected. Finally, the accumulated data is examined for strong correlation peaks that indicate the arrival time of the GNSS signal with the specified Doppler and PN sequence. This is of course the case when the reference generator 1105 generates a Fourier transformed PRN sequence. Such a transformed sequence can be stored in memory for later use or calculated on the fly.

[0216] In yet another aspect of the present invention, instead of rotating or shifting the frequency sample vector provided by the forward FFT of the signal samples, a similar operation can be performed on the frequency samples of the PRN reference signal. That is, Doppler compensation is performed on the PRN frequency samples rather than on the signal frequency samples. This is done in Figure 16B Switches 1209, 1210, 1211, and 1212 allow for Figure 16A The discussion proceeds by way of rotation or interpolation, or both.

[0217] The problem with this approach is that the resulting product of the signal frequency samples and the Doppler-compensated PRN samples will no longer be at zero frequency, even if the assumed Doppler is exactly associated with the signal. Therefore, the inverse FFT will contain a frequency offset. To perform multiple coherent summations of these inverse FFT vectors, it may be necessary to first compensate for the frequency offset by multiplying with a complex sinusoid to convert such vectors to zero frequency. However, taking the magnitude of the inverse FFT will remove the frequency offset component. Therefore, for applications that only perform incoherent summations of these inverse FFT vectors, this approach works well. An advantage of this approach is that the Doppler-shifted PRN frequency samples can be pre-calculated, thereby eliminating any additional forward FFT of the signal data, as would be indicated by the previously mentioned approach (using Doppler-shifted signal frequency samples). Of course, such pre-calculation comes at a cost in terms of memory storage.

[0218] In the above description, we describe Doppler shift as vector rotation or cyclic rotation. For small rotations, the loss is minimal when one can replace the rotation with a shift operation, where, rather than rotating samples from the end of the vector to the beginning (or vice versa), one replaces samples near the beginning (or end) with samples of zero or other values. The above method still works in this case, with little change in GNSS acquisition performance. For example, if a frequency vector is rotated by 5 bins in the positive direction, such a rotation would move the last 5 elements of the vector to the first 5 elements of the vector, which would be the 5 most negative frequency bins. If a shift were used instead, these first 5 bins would typically be replaced with zero-valued data. In all cases, we refer to "rotation" or "cyclic rotation," which also includes such a shift operation. Typical Doppler shift due to GNSS satellite motion is typically in the range of + / - 5 kHz, and a typical PRN frame rate is 1 kHz. Therefore, the Doppler shift due to satellite motion is typically in the range of + / - 5 FFT bins. Since the FFT size corresponds to the PRN length, which is often over 1000, there are cases where frequency shifting and rotation produce similar results. We should also note that the amplitude of the band edges of the FFT data tends to be low due to filtering of the input data, so that edge effects associated with rotation or shifting are usually minimal.

[0219] One or more embodiments may combine frequency rotation / interpolation with reference signal rotation / interpolation. Figure 16A and 16B The embodiments in can be combined, such as Figure 16C As shown, switches are used to facilitate the manner and type of rotation and / or interpolation.

[0220] Of course, in all of the above methods, it may be possible to process a data block with more than one PN reference (corresponding to more than one satellite signal) without having to perform multiple forward FFT operations. After the forward FFT operation, different PN sequences and different frequency hypotheses can be used for the transformed data, and then each undergoes an inverse transform without the need for additional forward FFT operations.

[0221] All the previous cases incorporate term-by-term multiplication of the frequency data with the reference data, inverse FFT, accumulation operation and peak detection operation, such as Figure 16A Blocks 1104, 1106, 1107, and 1108, Figure 16B 1204, 1206, 1207, 1208 and Figure 16C As shown in 1304, 1308, 1309 and 1310.

[0222] For clarity of terminology, we often use general notation to refer to a collection of samples (whether signal samples or reference samples) as a vector. When we speak of multiplying vectors, the output is a vector of similar size. The multiplication is the term-wise multiplication of the two vectors, sometimes called the "Hadamard" product. We sometimes use the term "a set of function samples," which can also be considered a vector. This multiplication may also involve complex operations on frequency samples or reference samples.

[0223] Receiver Architecture Embodiments

[0224] To achieve flexible and power-efficient sideband A or sideband B processing, a number of GNSS radio architectures have been proposed, modifying the overall frequency planning, filtering, ADC clocking, and subsequent decimation planning. This configuration allows for optimal performance versus power consumption tradeoffs. These architectures utilize varying degrees of digital circuit content, as described below.

[0225] Figure 4A Figure 1 shows the convention used to describe the radio portion of a GNSS receiver. This convention relates to the following description of the radio architecture and distinguishes the RF front-end components 1401, which tend to be external to the integrated circuit and can include switches, mixers, filters, amplifiers, and local oscillator circuits, as well as the mixed signal section 1402, which provides signal sampling and quantization functions, and the analog-to-digital converter (ADC) 1403 block. Any additional subsequent processing blocks are beyond the scope of this specification. Figure 4A The range of the radio receiver is defined in .

[0226] Figure 4BThe figure shows a conventional IQ quadrature receiver architecture that requires significant analog circuitry. The signal received by the antenna passes through an RF front-end 1401, which provides low-noise amplification and filtering. The RF signal is then downconverted to baseband (zero-IF or ultra-low-IF) by a set of quadrature passive or active mixers 1404 and 1405. It is then low-pass filtered by a set of active low-pass filters (LPFs) 1406 and 1407 and quantized by a set of quadrature ADCs 1408 and 1409 at a given sampling rate Fs. A quadrature local oscillator signal, IQLO, 1426 provides an I local oscillator signal, ILO, and a Q local oscillator signal, QLO, with a 90-degree phase difference. Each of these signals drives a branch of the quadrature mixers 1405 and 1406. The IQLO frequency is derived by dividing the output frequency, fPLL 1421, of the RF phase-locked loop (RF PLL) 1420 by divider D2 1425. RF PLL 1420 synthesizes an output frequency fPLL 1421 based on a reference frequency fREF 1419 obtained from a crystal reference oscillator 1418. fREF 1419 is typically shared with other radio circuits on the board of a given device. Note that the value of D2 can be 1 or higher. In this figure, the frequency division function 1425 and the orthogonal generation function 1427 are shown as two different blocks. Depending on the actual design, they can be performed in the same block (for example, using an orthogonal binary clock divider). Figure 4B The signals ILO and QLO shown are essentially the same signal, but with a phase difference of 90 degrees. A sampling clock at frequency Fs 1423 is also derived from the RF PLL 1420 by frequency division in 1422. The clock signal 1423 is also fed to the digital front end block 1450 to help further process the digitized signal.

[0227] The frequency planning of IQ quadrature receiver is also Figure 4C Each figure is a frequency-domain representation of the signal, with the horizontal axis expressed in frequency units and the vertical axis showing the power spectral density or discrete spectral components. The first figure shows the spectrum of the desired signal at RF. The next figure shows the location of the ILO and the low-pass downconverted BB-I signal, with the low-pass filter response indicated by the dashed line. Similarly, the QLO and the downconverted low-pass Q-path signal BB-Q are also shown below.

[0228] Figure 4D The diagram shows Figure 4BThe RF front-end 1401 is modified in this architecture, where a switching mixer 1410 converts the RF signal at the output of the RF front-end 1401 to an intermediate frequency (IF) signal. The IF signal is then amplified and filtered using a continuous or discrete-time bandpass filter (e.g., N-way) 1411 before being downconverted to low-pass baseband using a set of quadrature mixers 1404 and 1405. It is then passed to a set of anti-aliasing active LPFs 1406 and 1407, which provide low-pass I and Q signals centered at a low or zero IF to quadrature ADCs 1408 and 1409, as described above. The receiver is time-synchronized via a single RF PLL 1420, and all clock and LO frequencies are derived by dividing the fPLL 1421 signal. The RF PLL 1420 synthesizes the output frequency PLL 1421 based on a reference frequency fREF 1419 derived from a crystal reference oscillator 1418. fREF 1419 is typically shared with other radio circuitry on a given device. To increase flexibility, but at the expense of complexity and area, RF-PLL 1420 can be implemented using a fractional-N divider. Divider D1 1422 provides sampling clock Fs 1423, and divider D2 1425 provides IQLO signal 1426 to quadrature-phase generator 1427. As mentioned above, quadrature generation function 1427 can also be integrated with divider 1425. Alternative quadrature-phase generation techniques include passive resistor-capacitor or inductor-capacitor circuits in the IQLO or RF paths and are well known to those skilled in the art. RF mixer 1410 is driven by local oscillator signal RFLO 1428, which is generated by divider D3 1427. Note that D3 can take a value of 1 or higher.

[0229] Figure 4D Frequency planning for the mid-range architecture works around the following relationship:

[0230] 1) Intermediate frequency: IF = RFLO – RF (for high-side injection)

[0231] IF = RF – RFLO (for low-side injection)

[0232] 2) Baseband center frequency: fcBB = IF – IQLO (minimized for very low IF, zero IF)

[0233] 3) RF local oscillator frequency: RFLO = fPLL / D3

[0234] 4) IQ local oscillator frequency: IQLO = fPLL / D2

[0235] 5) Sampling clock frequency Fs = fPLL / D1

[0236] 6) Harmonic relationship between RF and IF: IF = RF × M / L

[0237] 7) RF PLL frequency: fPLL = (N + J / K) × fREF (assumed fraction - N division)

[0238] fPLL = N × fREF (assuming integer N division)

[0239] If RF is related to IF via the M / L factor, the following relationships can be derived algebraically: RFLO = RF(1+M / L) for high-side injection, and RFLO = RF(1-M / L) for low-side injection. Furthermore, since fPLL = (N+J / K)×fREF = RFLO×D3, RFLO = (N+J / K)×D3×fREF. Furthermore, in the case of a zero-IF receiver frequency plan, IF = IQLO, and since RFLO, IQLO, and Fs are harmonically related to fPLL via integer division, the following relationship can be derived between D2 and D3: D2 = D3×(L / M+1) for high-side injection, and D2 = D3×(L / M–1) for low-side injection. Figure 4D The frequency planning of the architecture is as follows Figure 4E As an example, a high-side RFLO injection is shown.

[0240] The following table describes four frequency planning scenarios associated with a desired signal centered at 1191.795 MHz. Each scenario has different RFLO, IF, and IQLO positioning. For example, scenario A features a PLL frequency of 4×RFLO at 5952 MHz and places the IF at 296.2 MHz, or one-quarter of the desired RF center frequency. Similarly, scenario B places the fPLL at 4×RFLO and the IF at one-third of RF. Scheme C places the fPLL at 2×RFLO and the IF at one-quarter of RF, while scenario D places the fPLL at 2×RFLO and the IF at one-third of RF. For each scenario, the table also lists the D2 and D1 divider values, the sampling frequency fS, and the baseband signal center frequency fcBB. The location of fcBB indicates how close the receiver operates to a zero-IF condition. In the following scenarios, an integer-N RF PLL is used with a reference frequency fREF of 19.2 MHz. Using an integer-N PLL results in a slight offset in fcBB, which can be removed by de-rotating the final digitally down-converted baseband signal in the digital front end.

[0241] f fPLL D3 fRFLO IF / RF fIF D2 fIQLO D1 f fcBB plan MHz MHz - MHz - MHz - MHz - MHz MHz A 1191.795 5952.00 4 1488.00 1 / 4 296.205 20 297.6 42 141.7143 -1.395 B 1191.795 6355.20 4 1588.80 1 / 3 397.01 16 397.2 48 132.4 -0.195 C 1191.795 2976.00 2 1488.00 1 / 4 296.21 10 297.6 24 124 -1.395 D 1191.795 3187.20 2 1593.60 1 / 3 401.81 8 398.4 24 132.8 3.405

[0242] Figure 4F Pictured Figure 4DThis is a variation of the architecture shown in

[14] , in which the analog LPF and mixer are replaced with a quadrature sampling arrangement. The RF signal at the output of RF front-end 1401 is downconverted by mixer 1410 with the help of RFLO signal 1428, which is derived by dividing fPLL signal 1421 by divider D2 1427. RF PLL 1420 synthesizes output frequency PLL 1421 based on reference frequency fREF 1419 derived from crystal reference oscillator 418. fREF 1419 is typically shared with other radio circuits on a given device. To increase flexibility, but at the expense of complexity and area, RF-PLL 1420 can be implemented using a fractional-N divider. The IF signal obtained at the output of mixer 1410 is then amplified and filtered by bandpass filter 1411, which acts as an anti-aliasing filter. The amplified and filtered IF signal is then sampled by a quadrature ADC consisting of I ADC 1409 and Q ADC 1408. The quadrature sampling function is achieved by a 90-degree phase difference between the two sampling clocks, Fs-I and Fs-Q. This phase difference is achieved by the quadrature phase generator 1424, which is implemented as a divide-by-4 frequency divider that can provide four Fs signals with different phases. Note that by combining the frequency divider D1 with the quadrature phase generator and the divide-by-4 frequency divider 1424, the effective sampling frequency Fs is derived from the signal fPLL 1421. Therefore, Fs is derived as fPLL / [D1×4]. The two quadrature sampling clocks, Fs-I and Fs-Q, are also provided to the digital front end 1450 and are synchronized with each other using the 4×Fs clock signal 1423. Figure 4F The architecture is more suitable for digital implementation because the RF mixer can be implemented as a passive block with switches and resistors, while the BPF can be implemented as a discrete-time block (e.g., an N-way filter) with switches, resistors, and capacitors. A larger division ratio of D1×4 (e.g., 8 or 12) also provides a greater number of different phase states and, therefore, can produce better N-way filter resolution and rejection characteristics. The quadrature ADC effectively subsamples the signal at the IF.

[0243] Figure 4F Frequency planning for the mid-range architecture works around the following relationship:

[0244] Intermediate frequency: IF = RFLO – RF (for high-side injection)

[0245] IF = RF - RFLO (for low-side injection)

[0246] RF local oscillator frequency: RFLO = fPLL / D2

[0247] Quadrature sampling frequency: Fs-I = Fs-Q = fPLL / (D1×4)

[0248] Harmonic relationship between RF and IF: IF = RF × M / L

[0249] RF PLL frequency: fPLL = (N + J / K) × fREF (fractional-N divider)

[0250] fPLL = N × fREF (integer-N divider)

[0251] If RF is related to IF via an integer N, then algebraically, the following relationships can be derived: RFLO = RF(1+M / L) for high-side injection, and RFLO = RF(1-M / L) for low-side injection. Furthermore, since fPLL = (N+J / K)×fREF = RFLO×D2, RFLO = (N+J / K)×D2×fREF. Furthermore, since a true zero-IF receiver frequency plan is preferred in this case, a fractional PLL should provide the required flexibility in fPLL synthesis. Note that IF = Fs-I = Fs-Q, and since RFLO, Fs-I, and Fs-Q are harmonically related to fPLL via integer division, after some algebraic manipulation, the following relationships can be derived between D1 and D2: for high-side injection, D1 = D2(L / M+1) / 4, and D1 = D2×(L / M–1) / 4.

[0252] A schematic diagram of the frequency domain processing in the above arrangement is also shown in Figure 4G . High-side RFLO injection is used as an example because it provides greater image rejection by low-pass filtering the input signal at the RF front end. The IF signal is anti-aliased filtered and sampled with clocks Fs-I and Fs-Q to produce digital baseband signals BB-I and BB-Q. Note that the BB-I and BB-Q signals are in discrete time compared to the signals before digitization, and therefore their frequency axis is defined as radian frequency from -2pi to +2pi radians.

[0253] The table below describes four frequency planning scenarios associated with a desired signal centered at 1191.795 MHz. Each scenario has different RFLO and IQLO positioning. For example, scenario A features a PLL frequency of 4×RFLO at 5958.975 MHz and places the IF at 297.949 MHz, or 1 / 4 of the desired RF center frequency. Similarly, scenario B places the fPLL at 4×RFLO and the IF at 1 / 3 of RF. Scheme C places the fPLL at 2×RFLO and the IF at 1 / 5 of RF, while scenario D places the fPLL at 2×RFLO and the IF at 1 / 3 of RF. Note that all of the following scenarios utilize fractional-N PLLs, which ensures zero baseband frequency offset, meaning the receiver downconverts to zero IF. In cases where an integer PLL is used with a given crystal oscillator frequency, fREF, slight baseband conversion frequency offsets may be observed. As described above, these can be downconverted to zero offset from DC.

[0254] f fPLL D2 RFLO IF / RF IF D1 f plan MHz MHz - MHz - MHz - MHz A 1191.795 5958.975 4 1489.7438 1 / 4 297.949 20 297.949 B 1191.795 5720.616 4 1430.154 1 / 3 238.359 24 238.359 C 1191.795 2860.308 2 1430.154 1 / 5 238.359 12 238.359 D 1191.795 3178.12 2 1589.06 1 / 3 397.265 8 397.265

[0255] In yet another implementation, Figure 4H The sampling architecture implemented for the GNSS system described herein is shown. As previously mentioned, the RF front end 1401 typically consists of discrete RF components (low noise amplifiers and filters) and provides filtered and amplified signals to amplifier and BPF blocks 1411, which may be integrated into a SOC. The low noise amplifiers and selective filters typically require inductors, which are expensive to integrate onto a SOC and are typically located off-chip, especially if an all-digital manufacturing process is utilized. After the RF signal is adequately anti-aliased filtered by blocks 1401 and 1411, it is sampled by an RF ADC 1460. The sampled signal is down-converted / mixed by the nearest harmonic of the sampling clock and processed by the digital front end 1450, which includes complex down-conversion using complex multipliers, de-rotators, and similar blocks to ultimately produce digital complex quadrature baseband I 1451 and Q 1452 signals. Although Figure 4H The architecture seems more suitable for integration in a digital CMOS process, but it suffers from linearity and noise immunity issues. The anti-aliasing filtering is implemented by the BPF in block 1411, which can be better integrated if implemented in discrete time (i.e. with some form of sample and hold circuit in front of it). Mixed signal techniques such as N-way filters can also be used, although they operate at very high radio frequencies and at the expense of power consumption. One approach that can save power but requires a spectrally clean clock is subsampling, where a lower frequency sampling clock creates many aliasing bands, thereby downconverting a large number of signals that are aliased by the various sampling harmonics. The anti-aliasing filtering function in the amplifier and BPF 1411 is designed to ensure that unwanted aliasing components (including noise) are adequately suppressed. Figure 4I The frequency plan for the subsampling arrangement is shown. Two subsampling schemes are considered. Scheme 1 uses fundamental bandpass sampling that downconverts the RF signal to the lowest digital Nyquist band, while scheme 2 uses subsampled harmonics to bandpass sample the RF signal and convert it to the first image band, or to the lowest digital Nyquist band but with an inverted spectrum. Note again that the digitized IF signals are defined in discrete time, so their frequency axis refers to radian frequencies from -2pi to 2pi.

[0256] In yet another implementation, Figure 4J The diagram shows Figure 4H Improvements to the architecture, Figure 4H The architecture suffers from low aliasing immunity due to limited selectivity and higher power consumption due to higher quality clock requirements. Figure 4D In the manner of the architecture described in

[14] , the RF signal from the antenna passes through an external RF front-end 1401 with appropriate amplification and bandpass filtering, then enters a passive mixer 1410, which downconverts the signal to an intermediate frequency (IF) based on the RFLO signal, which is again derived by dividing the fPLL signal 1421 from the RF PLL 1420 (in divider D2). The IF signal at the output of mixer 1410 is fed into an amplification and bandpass filtering arrangement in amplifier and BPF block 1411. Amplifier and BPF block 1411 ensures that adequate low-noise anti-aliasing filtering is provided. It can also utilize discrete-time signal processing techniques, such as N-way filtering, which can be easily implemented in a fully digital IC manufacturing process. The filtered output IF signal is then subsampled by ADC 1460 operating at a rate of Fs 1423. This again simplifies the filtering implementation requirements as well as the ADC clock requirements. By filtering the IF signal, a favorable power-performance tradeoff can be achieved in the anti-aliasing filtering performance of the LNA and BPF block 1411, with lower clock rates and power consumption and better rejection characteristics. In addition, by subsampling the IF signal, the ADC 1460 can now operate at a lower sampling rate while also ensuring less aliasing and allowing for higher resolution and lower power consumption. Note that the large number of clock phases achieved by including a factor of 4 divider can lead to further performance improvements for the N-way filter integrated in the amplifier and BPF block 1411. Figure 4J The frequency planning of the architecture is as follows Figure 4KAs shown. Consider the two options again. In Option 1, sampling and downconversion employ a mechanism that subsampling is performed at the upper Nyquist band of the fundamental frequency. In Option 2, sampling and downconversion employ a mechanism that subsampling is performed at the lower image band of the subsampled harmonics. Note that the constraint that the frequency fPLL 1421 can be divided by divider D1 1422 and divider D2 1427 requires optimizing the IF placement. For hardware-efficient IF downconversion to baseband in the digital front end 1450, it is best to locate the IF at Fs / 4, 3Fs / 4, 5Fs / 4, 7Fs / 4, etc. Other locations such as Fs / 8, 7Fs / 8, 9Fs / 8, and 15Fs / 8 also work efficiently.

[0257] 52MHz wide Galileo E5 signal ( Figure 4O The spectrum shown in ) poses interference immunity and power consumption challenges to GNSS receivers operating in this frequency band. To mitigate interference and reduce power consumption, three general possibilities are identified for radio receivers:

[0258] (1) Select E5a+E5b or E5a or E5b signal processing to achieve optimal power consumption through time division (i.e., time duplexing / multiplexing) with adaptive duty cycle

[0259] (2) Select E5a+E5b or E5a or E5b through RF or mixed signal filtering (i.e., frequency multiplexing)

[0260] (3) Intentionally folding E5a onto E5b (ie, code domain multiplexing), or folding E5a onto itself, or folding E5b onto itself, by using real mixing and appropriate local oscillator frequency placement.

[0261] In addition to duty cycling the receiver based on interference suppression, using different parts of the signal spectrum selectively or by folding can also reduce power consumption on the analog / RF and digital front-ends to varying degrees and depending on the given architecture. Since the receiver can tune to either of the two sidebands, it can be operated in the following ways:

[0262] (1) The upper sideband (E5b) or the lower sideband (E5a) is selected and processed at half the rate (20×1.023MHz) compared to the full 52MHz band. For example, the E5B sideband is selected as Figure 4P shown.

[0263] (2) Either the upper sideband (E5b) or the lower sideband (E5a) is selected and processed. Additionally, the processing can be duty cycled to achieve optimal power consumption.

[0264] (3) The upper sideband (E5b) is selected and if excessive DME / TACAN interference is detected, the receiver switches to the lower (E5a) sideband. The reverse can also occur.

[0265] (4) The two sidebands are folded onto each other using a real mixing operation as described below.

[0266] (5) By folding onto itself and by using a real mixing operation as described below, the upper sideband (E5b) or the lower sideband (E5a) is selected and processed at half the rate (20×1.023 MHz) and with half the low-pass bandwidth (e.g., 12 MHz).

[0267] The selection of E5a and E5b can occur in real time or in a predetermined manner as described above. Figure 4B 、 4D The radio receiver architectures shown in FIG4F allow flexible processing by switching between double-sideband and single-sideband signals with performance and power trade-offs. Receiver configuration involves appropriately changing the RFLO and IQLO frequencies and, if applicable, modifying the filter passbands.

[0268] By using a single mixer and by placing the local oscillator frequency within the operating bandwidth of the desired signal, real mixing results in folding the bandpass desired signal onto itself. With the two sidebands E5a and E5b folded onto each other, real mixing results in a form of code domain multiplexing. To illustrate this concept, Figure 4B The radio architecture is configured as Figure 4L As shown, the Q path of the quadrature mixer, LPF and ADC is turned off. The local oscillator ILO 426 frequency is maintained at 1191.795 MHz. Referring to the analysis shown in Appendix 3, at the output of the mixer 405, the two sidebands E5a and E5b are converted to baseband and folded over each other, and in addition E5a is spectrally inverted. The low-pass bandwidth of the folded signal in the single real path remains the same as before, i.e. 26 MHz. In addition, the corner frequency of the anti-aliasing LPF 407 and the sampling rate of the ADC 409 remain the same as in the double-sideband case. Although it carries two sidebands folded over each other, the resulting signal is not completely in baseband, but is centered around a frequency offset of 15.345 MHz. In the digital front end, further processing downconverts the signal to zero frequency and despreads one or the other sideband. The processing gain is assumed to be well maintained on the inverse code. Since the mixer output noise is increased by 3 dB, this implementation assumes a reasonable SNR margin. This technique can also reduce the receiver processing load and power consumption, especially in Figure 4B 、 4D , 4F architecture, because they are reconfigured as Figure 4L 、 4M , 4N.

[0269] Real Mixing In the case of folding a given sideband (E5a or E5b) onto itself, the local oscillator is placed close to the center of that sideband (1176.450 MHz for E5a and 1207.140 MHz for E5b), while also reducing the low-pass bandwidth to much less than 26 MHz (because the effective bandwidth is now double-sided due to the folding onto the negative frequency axis). The folding results in a 3 dB SNR drop, but since each sideband is spread by a pseudo-random code with sufficient coding gain, the spread signal can still be retrieved. Depending on the frequency tracking loop bandwidth, a small frequency offset (e.g., 10 kHz or more) may need to be applied to the local oscillator signal so that the negative folded spectrum does not interfere with receiver synchronization. This technique results in significant radio power reduction, especially in Figure 4B 、 4D , 4F architecture, because they are reconfigured as Figure 4L 、 4M Furthermore, further interference immunity can be achieved by reducing the effective receiver bandwidth compared to full double-sideband operation.

[0270] One way to save power during tracking is to use single sideband, as this reduces the clock rate requirements in the digital front end and subsequent stages. In one particular implementation, during acquisition, the full double sideband signal (E5a and E5b sidebands) is acquired by operating a full complex radio receiver (e.g. Figure 4B The low-pass filter bandwidth, ADC clock, and decimation scheme are adapted to the wideband signal, as shown in the spectrum of the E5A or E5B signal. When the receiver enters tracking mode, the radio receiver follows the Figure 4L A configuration is made where 2× real 26MHz bandwidth is processed by a single mixer, resulting in a 26MHz complex signal bandwidth offset to the 15.345MHz IF, but also carrying two sidebands folded over each other. As mentioned above, although Figure 4B The architecture in is particularly well suited to this characteristic, but other architectures are also suitable. In particular, Figure 4D The radio architecture described in Figure 4M In addition, Figure 4F The radio architecture described in Figure 4N Configuration.

[0271] Figure 17An example of a method for using multiple signal components during acquisition and switching between using a subset of these acquired signal components during tracking after successfully acquiring at least one signal component from a GNSS SV is shown. This method can save power by reducing power consumption in the digital processing of received GNSS signals and potentially (depending on the implementation) in the RF portion of the GNSS receiver. It is typically the case that the acquisition phase lasts only a short period of time, while the tracking phase lasts a longer period of time; reducing power consumption during tracking can significantly improve the performance of the GNSS receiver (at least in terms of its power consumption metrics). Now referring to Figure 17 In operation 1701, the GNSS receiver may begin to acquire a GNSS signal; for example, the GNSS receiver may use one of the above-described receiver architectures (e.g., Figure 4M or 4N) using a capture array processor such as described herein (e.g., see Figure 6-8) to acquire GNSS signals. In operation 1703, the GNSS receiver may attempt to acquire multiple GNSS signal components from one or more GNSS SVs during the acquisition phase. For example, during the acquisition phase of operation 1703, the GNSS receiver may attempt to acquire four signal components from GNSS SVs in the Galileo constellation (e.g., E5AI, E5AQ, E5BI, and E5BQ signal components from a particular SV in the Galileo constellation). Typically, the GNSS receiver (at least in a "cold start" scenario) will attempt to acquire multiple signal components from a sufficient number of GNSS SVs (e.g., at least 4 or 5 SVs) in operation 1703 to allow a position to be determined. After one or more signal components have been acquired, as determined in operation 1705, the GNSS receiver may select or determine a subset of the successfully acquired signal components to be tracked in operation 1707. Thus, rather than tracking all successfully acquired signal components (which were determined to have been successfully acquired in operation 1705), the GNSS receiver selects a subset of the successfully acquired signal components and tracks only the signal components in the subset in operation 1709. For example, if the GNSS receiver has acquired all four signal components from a first SV in the Galileo constellation (e.g., E5AI, E5AQ, E5BI, and E5BQ signal components from the first SV in the Galileo constellation) and has acquired two signal components from a second SV in the Galileo constellation (e.g., E5BI and E5BQ signal components from the second SV in the Galileo constellation), the GNSS receiver may select to track only one or four signal components from the first SV and one of the two signal components from the second SV during the tracking phase. Those signal components that were not selected will not be tracked, thereby reducing power consumption in the GNSS receiver. The selection in operation 1707 may attempt to select the "best" signal component to track, and some examples of possible selection criteria or algorithms are provided below. In one embodiment, "best" may be close to optimal rather than truly optimal, as being close to optimal may still reduce power consumption while still providing acceptable tracking.

[0272] The best sideband can be selected using one or more of the following algorithms:

[0273] 1) The sideband with the least interference. DME / TACAN will typically be visible in only one sideband. The best sideband is the one without any current DME interference. Later, in different areas, interference may dominate in different sidebands.

[0274] 2) The sideband with the most transmitting satellites. Currently, the lower sideband, centered around 1176.45 MHz, has the most satellites: US L5, China B2a, Japan QZSS L5, and Europe E5a. Therefore, the upper sideband can be disabled after acquisition.

[0275] 3) The sideband with the most visible satellites at the current time and location (determined by calculating the elevation angles of all transmitting satellites). Visible satellites have positive elevation angles above the horizon, followed by non-zero obscuration angles (such as 10 degrees). At a given time, one sideband may contain more satellites than another.

[0276] 4) When the receiver has not yet determined fine time, the sideband with the fastest data rate. For example, the upper sideband of B2 has a data rate of 1 kHz and the lower sideband has a data rate of 200 Hz, and the upper sideband of E5 has a data rate of 250 Hz and the lower sideband has a data rate of 50 Hz. Faster decoding of the timestamp allows for improved accuracy by learning the fine time.

[0277] 5) The number of these "best" sidebands can be changed dynamically, for example, starting with data decoding, then transitioning to the most visible, then interference-free modulation.

[0278] 6) Sidebands containing satellites from a selected constellation that are required by a specific country based on import regulations. For example, if Russia requires the use of Russian L5 satellites and they are specifically placed in one sideband, then based on import requirements, that sideband will be best as a single tracking sideband.

[0279] Spoofing may be seen on one sideband but not on another. If the receiver is capable of processing each system independently, spoofing is identified (wherein the spoofing is identified using an independent fix of one constellation) and the best sideband of the non-spoofed constellation is identified.

[0280] To reduce power consumption, tracking can be performed on the optimal sideband rather than multiple sidebands from the same GNSS SV. This means that RF and digital processing can be turned off for the non-optimal sideband, reducing power consumption. For example, the RF mixer, filters, A2D, and digital front-end can be disabled for this other sideband. Baseband correlation can also be disabled.

[0281] After acquiring enough SVs and determining at least one secondary code, a fix allows determining the remaining secondary codes and, therefore, almost direct acquisition of the remaining satellites with a significantly narrower code search. In this case, the acquisition engine can be turned off. Tracking can be recovered from system losses by coherent tracking of the pilot channel. Therefore, this extra sideband (which is not tracked) is not critical.

[0282] Exemplary embodiments

[0283] The following text presents numbered embodiments in a claim-like format, and it is understood that these embodiments may be presented as claims in one or more future filings, such as one or more continuations or divisions. Although individual embodiments are described in detail below, it is understood that these embodiments may be combined or modified in part or in whole. At least some of these numbered embodiments were presented as claims in prior provisional applications.

[0284] Embodiment 1: A system comprising:

[0285] a set of one or more application processors (APs) configured to execute an operating system (OS) and one or more application programs, the set of one or more application processors being implemented in an integrated circuit (IC);

[0286] a set of one or more buses coupled to the set of one or more APs, the one or more buses being on the IC;

[0287] a cache memory on the IC and coupled to the set of one or more buses and to the set of one or more APs to store data for use by the OS and the one or more applications;

[0288] a bus interface coupled to the set of one or more buses, the bus interface coupling the set of one or more APs to a dynamic random access memory DRAM external to the IC;

[0289] a GNSS processing system implemented on the IC, the GNSS processing system comprising an acquisition engine AE and a tracking engine TE, the GNSS processing system being coupled to a shared memory via the one or more buses, the shared memory being one or both of: (a) the cache memory or (b) other memory on the IC;

[0290] A memory controller is coupled to the shared memory and the GNSS processing system, the memory controller being responsive to one or more instructions from the operating system to allocate a portion of the shared memory for use by the AE to allow GNSS signals to be acquired.

[0291] Embodiment 2. The system of embodiment 1, wherein the shared memory comprises SRAM (static random access memory), and the AE comprises ASIC hardware logic for performing a fast Fourier transform (FFT) operation using a time decimation method.

[0292] Embodiment 3. The system of embodiment 2, wherein the GNSS processing system includes dedicated memory separate from the shared memory and dedicated for use by the GNSS processing system, and wherein the other memory is processor local storage for a processor that is not one of the one or more APs.

[0293] Embodiment 4. The system of embodiment 1, wherein the memory controller comprises a first port controller for controlling reading and writing to the portion of the AE and a second port controller for controlling reading and writing to the remaining portion of the shared memory.

[0294] Example 5. A system as described in Example 3, wherein the AE performs acquisition of GNSS signals from (one or more) GNSS space vehicles (SVs), and the acquisition includes determining the frequency of the received GNSS signals containing pseudo-random codes to achieve tracking of the GNSS signals to generate pseudo-ranges to the GNSS SVs as a result of the tracking.

[0295] Embodiment 6. The system of embodiment 5, wherein the shared memory has a first port for use when the portion is allocated for use by the AE, and a second port for use by the processor or the one or more APs when the portion is allocated.

[0296] Embodiment 7. The system of embodiment 5, wherein the allocated portion stores one or more of: (1) pseudorandom codes of GNSS SVs or (2) hypotheses of identifiers of potentially acquired GNSS signals and hypotheses of their frequencies.

[0297] Embodiment 8. The system of embodiment 7, wherein the memory controller is to deallocate the portion after the GNSS processing system begins tracking GNSS signals that have been acquired from at least three (3) GNSS SVs.

[0298] The system described in Example 9 and Example 8 further includes:

[0299] Antenna input for receiving GNSS signals in the L5 WB band;

[0300] a low noise amplifier (LNA) coupled to the antenna input to amplify the GNSS signal;

[0301] A radio frequency analog-to-digital converter (ADC) is coupled to an output of the LNA, the radio frequency ADC and the LNA being configured to receive and process GNSS signals in the L5 WB band, and wherein the GNSS processing system is configured to process only GNSS signals in the L5 WB band.

[0302] Example 10. A system as described in Example 1, wherein the one or more APs generate a GNSS pseudo-random code for at least a GNSS SV in the field of view of the system before or during a capture phase, and the generated GNSS pseudo-random code is initially stored in the DRAM external to the IC and then copied to the shared memory during or at the beginning of the capture phase.

[0303] Example 11. A system as in Example 10, wherein the one or more APs generate the GNSS pseudo-random code in background operation only for healthy GNSS SVs that are in view or will be in view within a period of time, and wherein the OS reserves a portion of the shared memory for use by the AE in response to the one or more APs receiving a request to provide location data.

[0304] Embodiment 12: A method for operating a system, the method comprising:

[0305] receiving, from one or more application processors (APs) on an integrated circuit (IC), a request to generate position data using a GNSS processing system on the IC, the GNSS processing system comprising an acquisition engine (AE) configured to acquire a plurality of GNSS signals, each of the GNSS signals being transmitted from one of the GNSS space vehicle (SV) constellations;

[0306] identifying a portion of shared memory on the IC and allocating the portion for use by the AE in response to the request, while one or more other processors are allocated a remaining portion of the shared memory, the allocating being performed by an operating system executing on the one or more APs or by firmware executing on the IC;

[0307] Data related to the GNSS signal acquisition process is stored in the allocated portion by the AE or the one or more APs.

[0308] Embodiment 13. The method of embodiment 12, wherein the shared memory comprises SRAM (static random access memory) on the IC and the AE comprises ASIC hardware logic for performing a fast Fourier transform (FFT) operation using a time decimation method.

[0309] Example 14: The method according to Example 13, wherein the method further comprises:

[0310] After the GNSS processing system begins tracking GNSS signals acquired from at least three (3) GNSS SVs, the allocated portion is de-allocated in response to acquisition of the GNSS signals from at least three (3) GNSS SVs prior to a tracking phase.

[0311] Embodiment 15. The method of embodiment 14, wherein the GNSS processing system includes dedicated memory separate from the shared memory and dedicated for use by the GNSS processing system.

[0312] Embodiment 16. The method of embodiment 14, wherein a memory controller coupled to the shared memory comprises a first port controller for controlling access to the allocated portion for the AE and a second port controller for controlling access to the remaining portion of the shared memory.

[0313] Example 17. A method as described in Example 14, wherein the AE performs acquisition of a GNSS signal from a GNSS SV, and the acquisition includes determining the frequency of the received GNSS signal containing a pseudo-random code to achieve tracking of the GNSS signal to generate a master code phase to the GNSS SV as a result of the tracking.

[0314] Embodiment 18. The method of embodiment 17, wherein the allocated portion is used to store one or more of: (1) a pseudorandom code of a GNSS SV or (2) hypotheses of identifiers of potentially acquired GNSS signals and hypotheses of their frequencies.

[0315] Example 19. A method as described in Example 13, wherein the one or more APs generate a GNSS pseudo-random code for at least a GNSS SV in the field of view of the system before or during a capture phase, and the generated GNSS pseudo-random code is initially stored in a DRAM external to the IC and then copied to the shared memory during the capture phase or in response to a request for position.

[0316] Example 20. A method as described in Example 19, wherein the one or more APs generate the GNSS pseudo-random code in background operation only for healthy GNSS SVs that are in view or will be in view within a period of time, and wherein the system reserves the portion of the shared memory for use by the AE by determining the data stored in the non-volatile memory in the cache memory.

[0317] Embodiment 21. A non-transitory machine-readable medium storing executable program instructions, which, when executed by a data processing system, causes the data processing system to perform the method as described in any one of embodiments 12-20.

[0318] Embodiment 22: A data system, comprising:

[0319] a set of one or more application processors AP, configured to execute an operating system and one or more application programs;

[0320] a set of one or more buses coupled to the set of one or more application processors;

[0321] a dynamic random access memory (DRAM) coupled to the set of one or more application processors via the set of one or more buses;

[0322] a GNSS processing system on an integrated circuit (IC), the IC including a cache memory on the IC and coupled to the GNSS processing system, the GNSS processing system coupled to the set of one or more application processors, the GNSS processing system including an acquisition engine (AE) and a tracking engine (TE);

[0323] The group of one or more application processors is used to receive a request for position data and generate a GNSS pseudo-random code of a GNSS space vehicle (SV) for use by the AE, the generated GNSS pseudo-random code being stored in the DRAM and then copied to the cache memory for use by the AE during the acquisition phase.

[0324] Embodiment 23. The data processing system of embodiment 22, wherein the generated GNSS pseudorandom code is generated in response to the request.

[0325] Embodiment 24. The data processing system of embodiment 22, wherein the cache memory comprises SRAM (static random access memory) and the AE comprises ASIC hardware logic for performing a fast Fourier transform (FFT) operation using a time decimation method.

[0326] Embodiment 25. The data processing system of embodiment 24, wherein the one or more APs generate a GNSS pseudo-random code for at least a GNSS SV in view of the data processing system before or during an acquisition phase.

[0327] Embodiment 26. The data processing system of embodiment 25, wherein the one or more APs generate the GNSS pseudo-random code only for healthy GNSS SVs that are in view or will be in view within a period of time.

[0328] Embodiment 27: The data processing system according to embodiment 26, further comprising:

[0329] Antenna input for receiving GNSS signals in the E5 band;

[0330] a low noise amplifier (LNA) coupled to the antenna input to amplify the GNSS signal;

[0331] A radio frequency analog-to-digital converter (ADC) is coupled to an output of the LNA, the radio frequency ADC and the LNA being configured to receive and process GNSS signals in the E5 band, and wherein the data processing system is configured to process only GNSS signals in the E5 band.

[0332] Example 28. A data processing system as described in Example 27, wherein the AE performs acquisition of a GNSS signal from a GNSS SV, and the acquisition includes determining the frequency of the received GNSS signal containing a pseudo-random code to achieve tracking of the GNSS signal to generate a pseudo-range to the GNSS SV as a result of the tracking, and wherein the generated GNSS pseudo-random code includes a GNSS pseudo-random code shifted in frequency or time or both to generate a code spectrum for use by the AE in the acquisition phase.

[0333] Embodiment 29. The data processing system of embodiment 28, wherein during said acquisition of said AE, said allocated portion of said cache memory is to store hypotheses of identifiers of potentially acquired GNSS signals and hypotheses of their frequencies.

[0334] Embodiment 30: A GNSS processing system, comprising:

[0335] Antenna input for receiving GNSS signals in the E5 band;

[0336] a low noise amplifier (LNA) coupled to the antenna input to amplify the GNSS signal;

[0337] a radio frequency (RF) analog-to-digital converter (ADC) coupled to an output of the LNA, the RF ADC and the LNA being configured to receive and process GNSS signals in the E5 band;

[0338] A circular memory buffer is coupled to the output of the RF ADC to receive and store the digitized GNSS sample data, the circular memory buffer storing the digitized GNSS sample data exceeding 1 millisecond and the digitized GNSS sample data less than 2 milliseconds.

[0339] Example 31. A GNSS processing system as described in Example 30, wherein the circular memory buffer stores the digitized GNSS sample data in an array of rows and columns, and the sample data is arranged in row order, which is also arranged in time order, where 1 millisecond is the frame duration of the main code of the modernized GNSS signal, and the main code is further covered by a secondary code with a rate of 1 kHz.

[0340] Embodiment 32: The GNSS processing system according to embodiment 31, further comprising:

[0341] A GNSS processor includes an acquisition engine and a tracking engine, wherein the acquisition engine includes a set of DFT ALUs, which process the digitized GNSS sample data in the array and generate intermediate outputs without transposing the data in the array.

[0342] Embodiment 33. A GNSS processing system as described in embodiment 32, wherein a first group of DFT ALUs in the group of DFT ALUs uses a time extraction method to generate the intermediate outputs stored in the variable memory, and a second group of DFT ALUs in the group of FFT ALUs uses the intermediate outputs to generate outputs stored in the FFT result memory.

[0343] Example 34: A GNSS processing system as described in Example 33, wherein the circular memory buffer includes a first circular memory buffer for storing the A sideband in the E5 frequency band and a second circular memory buffer for storing the B sideband in the E5 frequency band.

[0344] Embodiment 35: A method for processing a GNSS signal in a GNSS receiver, the method comprising:

[0345] determining an initial information set comprising at least two of the following: (1) a code phase of a primary or secondary code signal received from at least one GNSS space vehicle (SV); (2) an estimated GNSS time based on one or more time sources, the estimated GNSS time being estimated or known to within less than + / - 0.5 milliseconds of the actual GNSS time; and (3) an approximate position of the GNSS receiver;

[0346] estimating an expected fractional primary code phase of a GNSS signal to be received based on the initial information group;

[0347] performing a first DFT-based correlation using at least a first complete primary code epoch of digitized GNSS sample data received within a time period comparable to a time period of code epochs of the GNSS signal, a first FFT-based correlation using the digitized GNSS sample data starting at a first time;

[0348] performing a second DFT correlation using at least a second complete code epoch of the received digitized GNSS sample data, the at least second complete code epoch of the digitized GNSS sample data including at least some of the received GNSS sample data in the first complete code epoch, the second DFT correlation using the digitized GNSS sample data beginning at a second time that is after the first time and offset from the first time by a period less than the code epoch;

[0349] removing the auxiliary code from the results of the first DFT correlation and the second DFT correlation to provide input for a coherent integration operation;

[0350] integrating at least one of the inputs into a coherent hypothesis memory;

[0351] The results from the coherent hypothesis memory are squared or taken in magnitude to acquire a GNSS signal from at least one GNSS SV.

[0352] Embodiment 36. The method of embodiment 35, wherein the I data and the Q data are summed within each of the first full code epoch and the second full code epoch.

[0353] Embodiment 37. The method of embodiment 35 further comprises summing the squared results in the non-coherent hypothesis memory, and wherein the summing of the squared results occurs several milliseconds after the first time.

[0354] Example 38. The method of Example 35, further comprising:

[0355] A search order is established for GNSS signals from a GNSS SV, the search order being based at least in part on the expected fractional primary code phase.

[0356] Example 39. The method of Example 35, wherein the method further comprises:

[0357] A subset of the correlation hypotheses is selected within a window that includes the expected fractional code phase for storage in a coherent hypothesis memory.

[0358] Example 40: The method of Example 35, wherein the method further comprises:

[0359] Each SV is assigned to an input sample offset group based on its expected primary code phase, among other factors.

[0360] Example 41. The method of Example 40, wherein the method further comprises:

[0361] One SV is assigned to one estimated code epoch, and another SV is assigned to another estimated code epoch, wherein each SV is assigned to a code epoch that is closer in time to the code epoch of the SV.

[0362] Embodiment 42: A method for processing a GNSS signal, the method comprising:

[0363] Receive GNSS signals;

[0364] digitizing the received GNSS signal and providing an output of GNSS sample data from an analog-to-digital converter (ADC), the output comprising at least one of: (1) GNSS sideband A sample data of the received GNSS signal and (2) GNSS sideband B sample data of the received GNSS signal;

[0365] computing at least one of: (1) a first set of DFTs of the GNSS sideband A sample data to provide a first set of results and (2) a second set of DFTs of the GNSS sideband B sample data to provide a second set of results;

[0366] computing at least one of: (1) a third set of DFTs of the GNSS sideband A primary PRN code data adjusted for code Doppler and carrier Doppler prior to the third set of DFTs, the GNSS sideband A primary PRN code data comprising at least one of the two components in GNSS sideband A, the third set of DFTs providing a third set of results, and (2) a fourth set of DFTs of the GNSS sideband B primary PRN code data adjusted for code Doppler and carrier Doppler prior to the fourth set of DFTs, the GNSS sideband B primary PRN code data comprising at least one of the two components in GNSS sideband B, the fourth set of DFTs providing a fourth set of results;

[0367] computing at least one of: (1) computing a first set of correlations using the complex conjugate DFT of the product of the first set of results and the complex conjugate of the third set of results to provide a fifth set of results, and (2) computing a second set of correlations using the complex conjugate DFT of the product of the second set of results and the complex conjugate of the fourth set of results to provide a sixth set of results;

[0368] Integrating at least one of: (1) the fifth set of results with at least one prior sum for GNSS sideband A, and (2) the sixth set of results with at least one prior sum for GNSS sideband B, wherein such integration includes at least one of (1) storing at least one new sum for the GNSS sideband A component in a single hypothesis memory, and (2) storing at least one new sum for the GNSS sideband B component in the single hypothesis memory.

[0369] Example 43: The method of Example 42, wherein the fourth set of results includes IDFT results of the two components of the GNSS sideband A, and the sixth set of results includes IDFT results of the two components of the GNSS sideband B.

[0370] Embodiment 44. The method of embodiment 43, wherein the GNSS sideband A sample data is stored in a first circular memory buffer and the GNSS sideband B sample data is stored in a second circular memory buffer.

[0371] Example 45. A method as described in Example 44, wherein the GNSS sideband A sample data is stored in a first circular memory buffer in an array format of rows and columns, and the GNSS sideband B sample data is stored in a second circular memory buffer in the said format of an array of rows and columns.

[0372] Example 46. A method as described in Example 45, wherein the GNSS sample data is processed to separate the GNSS sideband A sample data from the GNSS sideband B sample data by the following operations: (1) for the GNSS sideband A, the samples centered at the first frequency are shifted upward by the first offset frequency, and a low-pass filter is performed to capture the first bandwidth of the data, and the output of the low-pass filter is extracted to a lower sampling rate; and (2) for the GNSS sideband B, the samples centered at the first frequency are shifted downward by the first offset frequency, and a low-pass filter is performed to capture the second bandwidth of the data, and the output of the low-pass filter is extracted to a lower sampling rate.

[0373] Embodiment 47: A method as described in embodiment 45, wherein the computing operation does not require a separate operation to transpose or rearrange the sample data or the generated code spectrum data at the input of the first set of correlations and the second set of correlations.

[0374] Example 48. A method as described in Example 45, wherein the code generator generates at least one of the following: (1) GNSS sideband A primary PRN code data every millisecond when the GNSS signal is acquired and tracked, and the GNSS sideband A primary PRN code data is not stored after the Fourier transform is completed, and (2) GNSS sideband B primary PRN code data every millisecond when the GNSS signal is acquired and tracked, and the GNSS sideband B primary PRN code data is not stored after the Fourier transform is completed.

[0375] Embodiment 49. The method of embodiment 48, wherein the integration is non-coherent during at least a portion of an acquisition phase when the GNSS signal is received.

[0376] Embodiment 50: A system for processing GNSS signals, the system comprising:

[0377] a radio frequency analog-to-digital converter (ADC) to generate a digital representation of the received GNSS signal;

[0378] a baseband sample memory for storing the digital representation of the received GNSS signal as digitized GNSS sample data, the baseband sample memory being configured to store an array of the digitized GNSS sample data in N2 rows and N1 columns, the digitized GNSS sample data in the array being stored in row order in the baseband sample memory, and N2 being greater than N1, the row order containing the digitized GNSS sample data received during a time period including a first time period and a second time period, such that a first row in the row order contains digitized GNSS sample data received during the first time period, and a second row following the first row in the row order contains digitized GNSS sample data received during the second time period following the first time period, the baseband sample memory being coupled to the RF ADC;

[0379] A set of arithmetic logic units (ALUs) configured to perform discrete Fourier transform (DFT) operations, the set of ALUs being coupled to the baseband sample memory, the set of ALUs being configured to perform N1 DFTs in parallel and simultaneously in time, wherein each of the N1 DFTs includes N2 points in the DFT, and outputs of the N1 DFTs are stored in a partial result sample array, and wherein the set of ALUs is configured to then perform N2 DFTs, each of the N2 DFTs including N1 points from the partial result sample array, the N2 DFTs providing outputs stored in a DFT result data array arranged in column order.

[0380] Embodiment 51. The system of embodiment 50, wherein the baseband sample memory is configured as a circular memory buffer to store the array.

[0381] Embodiment 52: The system of embodiment 51, wherein the N1 DFTs use the same operation and the same program control instructions for the set of ALUs to operate on different data.

[0382] Embodiment 53. The system of embodiment 52, wherein the N2 DFTs are performed sequentially over time, and wherein the circular memory buffer stores more than one frame of pseudorandom GNSS codes, the more than one frame of pseudorandom GNSS codes being greater than 1 millisecond.

[0383] Embodiment 54. The system of embodiment 52, wherein the N1 DFTs and the N2 DFTs use a time decimation method, and wherein N1 is one of the following integer values: 5, 10, 20, or 40.

[0384] Embodiment 55. The system of embodiment 52, wherein a change from row order to column order resulting from a combination of the N1 DFTs and subsequent N2 DFTs avoids a reordering algorithm.

[0385] Example 56. A system as described in Example 52, wherein the GNSS code generator is configured to generate a GNSS code, and the set of ALUs performs a set of DFTs on the GNSS code to provide code spectrum result data stored in a code spectrum memory in column order, the code spectrum result data including GNSS PRN code data that is frequency and / or time offset.

[0386] Embodiment 57. The system of embodiment 56, wherein the set of ALUs is configured to multiply the code spectrum result data by the output stored in the DFT result array to generate a product array.

[0387] Embodiment 58. The system of embodiment 57, wherein the set of ALUs is configured to perform an inverse DFT on the product array using a frequency decimation method.

[0388] Example 59. A system as described in Example 58, wherein the inverse DFT includes: (1) in a first stage, N2 DFTs with conjugated inputs, each of the N2 DFTs containing N1 points, and (2) in a second stage after the first stage, N1 DFTs, each of the N1 DFTs containing N2 points.

[0389] Embodiment 60. The system of embodiment 51, wherein the baseband sample memory is a dual-port memory.

[0390] Example 61. A system as described in Example 56, wherein the GNSS code generator generates a pseudo-random code for each GNSS SV in view every millisecond when required during the acquisition phase, and the generated pseudo-random code is not stored after use, and the generated pseudo-random code is used to generate a GNSS code spectrum.

[0391] Embodiment 62. The system of embodiment 61, wherein the GNSS code spectrum is aligned in situ in memory in both frequency and phase to match a code phase hypothesis and a frequency shift hypothesis associated with the received GNSS signal.

[0392] Embodiment 63. The system of embodiment 62, wherein the alignment is performed by CORDIC hardware.

[0393] Example 64. The system of Example 50, wherein the digitized GNSS sample data is stored in column order rather than row order.

[0394] Embodiment 65: A system for processing GNSS L5 frequency band signals, the system comprising:

[0395] A radio frequency analog-to-digital converter (ADC) for generating a digital representation of the received GNSS signal;

[0396] a baseband sample memory for storing the digital representation of the received GNSS signal, the baseband sample memory being coupled to the ADC;

[0397] a GNSS processing system coupled to the baseband sample memory to process the digital representation of the received GNSS signal, the GNSS processing system being configured to process four GNSS signal components of the GNSS signal to non-coherently integrate all four GNSS signal components to generate non-coherent integration data for each of the four GNSS signal components and to store the non-coherent integration data in a single hypothesis memory to acquire the GNSS signal.

[0398] Example 66. A system as described in Example 65, wherein the single hypothetical memory is a memory of less than 2 megabytes, and wherein the four GNSS signal components include a Galileo E5AI signal component, a Galileo E5BI signal component, a Galileo E5BQ signal component, and a Galileo E5AQ signal component, or four GNSS signal components for the BeiDou B2 system, or both the Galileo E5 and BeiDou B2 signal components.

[0399] Example 67. A system as described in Example 66, wherein the GNSS processing system processes GNSS signals received from at least two GNSS constellations, and the at least two GNSS constellations include: the Galileo E5 constellation of the GNSS SV; the L5 GPS constellation of the GNSS SV, the Glonass K2 constellation of the GNSS SV, the QZSS constellation of the GNSS SV, and the BeiDou B2 constellation of the GNSS SV.

[0400] Example 68: The system of Example 65, further comprising:

[0401] The code generator is used to generate a GNSS PRN code during the acquisition and tracking of the GNSS signal, and not store the GNSS PRN code after the tracking is completed.

[0402] Embodiment 69. The system of embodiment 68, wherein the code generator generates more than two primary PRN code bits in a clock cycle during the acquisition and tracking.

[0403] Embodiment 70. A system as described in embodiment 69, wherein for a given GNSS constellation and a GNSS signal component in the GNSS constellation, the code generator generates more than two primary PRN code bits in one clock cycle by calculating using a calculated code advancement matrix derived from N multiplications of the code polynomial matrix, where N represents the number of primary PRN code bits generated in one clock cycle.

[0404] Embodiment 71. A system as described in embodiment 70, wherein the GNSS processing system shares a memory with one or more processors, and the GNSS processing system, the cache memory and the one or more application processors are all arranged on the same single integrated circuit.

[0405] Example 72. A system as described in Example 71, wherein the GNSS processing system includes an acquisition engine and a tracking engine, and the acquisition engine includes processing logic for receiving an array of GNSS sample data, wherein the array of GNSS sample data is arranged in row order or column order according to the reception time, and the acquisition engine includes processing logic for performing a DFT on the array of GNSS sample data using a time decimation algorithm to produce a frequency domain result, the frequency domain result is multiplied by the code spectrum of the GNSS PRN code of the GNSS SV in view, and then the product of the resulting frequency domain result and the code spectrum is processed by an IDFT using a frequency decimation algorithm in the processing logic to produce a hypothesis of a possible acquired GNSS signal, and the hypothesis is accumulated incoherently in the single hypothesis memory.

[0406] Example 73. A system as described in Example 72, wherein the GNSS sample data array is stored in two circular memory buffers, the two circular memory buffers including a first circular memory buffer for storing A-band GNSS sample data and a second circular memory buffer for storing B-band GNSS sample data, wherein multiple GNSS constellations can be received in at least one of the frequency bands.

[0407] Example 74. A system as described in Example 70, wherein before applying a set of DFTs using a time decimation algorithm, the GNSS master PRN code from the output of the code generator is shifted in frequency and shifted in time to generate a code spectrum, which is multiplied by the frequency domain results from a set of DFTs performed on the received GNSS signal using the time decimation algorithm.

[0408] Embodiment 75. The system of embodiment 73, wherein a GNSS master PRN code from the output of the code generator is shifted in frequency and shifted in time to generate the code spectrum.

[0409] Embodiment 76: The system of embodiment 72, wherein the order in the array is changed by the sequence of the DFT so that no transposition or rearrangement of data is required when the IDFT is performed.

[0410] Embodiment 77 The system of embodiment 76, wherein the sequence of DFTs avoids using memory or processing resources that would otherwise be used for the transposition or rearrangement.

[0411] Embodiment 78: A system for processing GNSS signals; the system comprising:

[0412] an analog-to-digital converter (ADC) to generate a digital representation of the received GNSS signal;

[0413] a baseband sample memory for storing the digital representation of the received GNSS signal, the baseband sample memory being coupled to the ADC;

[0414] a GNSS processing system coupled to the baseband sample memory to process the digital representation of the received GNSS signal, the GNSS processing system acquiring up to four GNSS signal components of the GNSS signal by non-coherently integrating the up to four GNSS signal components over a period of time in an array processing system, the array processing system being located in an acquisition engine of the GNSS processing system, the array processing system receiving GNSS sample data from the baseband memory, the GNSS sample data being formatted as a row and column array having a plurality of rows and a plurality of columns.

[0415] Embodiment 79. The system of embodiment 78, wherein the array processing system includes processing logic that performs a set of DFTs using a time decimation algorithm and then performs a set of inverse DFTs using a frequency decimation algorithm.

[0416] Embodiment 80. The system of embodiment 79, wherein the output from the array processing system provides frequencies and GNSS SV identifiers for storage in a hypothesis memory for integrating hypotheses of GNSS signals.

[0417] Example 81. A system as described in Example 78, wherein the array processing system receives GNSS sample data in a first order and generates output in a second order different from the first order, and wherein the first order is one of the row order or the column order in the row and column array, and the second order is one of the row order or the column order, and wherein the first order and the second order are based on the reception time of the GNSS sample data.

[0418] Example 82. A system as described in Example 81, wherein the GNSS sample data is stored in the row and column arrays in two circular memory buffers, the two circular memory buffers including a first circular memory buffer for storing a first GNSS signal component from the GNSS SV sample data and a second circular memory buffer for storing a second GNSS signal component from the GNSS SV sample data, the first circular memory buffer and the second circular memory buffer being coupled to the array processing system.

[0419] Embodiment 83: A system for processing GNSS signals, the system comprising:

[0420] a memory for storing a master code seed for GNSS signals of GNSS SVs from one or more GNSS constellations and storing a representation of master code polynomial data for use in generating a master PRN code for the GNSS signals;

[0421] A code generator, coupled to the memory, is configured to receive the master code seed and the master code polynomial data and generate more than two master PRN code bits in a single clock cycle using the master code seed and the master code polynomial data during acquisition and tracking of the GNSS signal.

[0422] Embodiment 84. A system as described in embodiment 83, wherein for a given GNSS constellation and GNSS signal components in the GNSS constellation, the code generator generates more than two primary PRN code bits in a single clock cycle by calculation, and the calculation uses a calculated code advancement matrix derived from N multiplications of the primary code polynomial matrix, where N represents the number of primary PRN code bits generated in one clock cycle.

[0423] Embodiment 85. The system of embodiment 84, wherein the system generates the primary PRN code bits without storing the primary PRN code bits after tracking is completed or after a DFT transform of a current primary code epoch is completed.

[0424] Embodiment 86. The system of embodiment 84, wherein the calculated code advance matrix is pre-calculated and stored in the memory before acquisition begins, and wherein N represents the amount of code advance provided by the code generator between clock cycles.

[0425] Example 87: The system of Example 84, further comprising:

[0426] a GNSS processing system coupled to the code generator, the GNSS processing system acquiring at least two of the four GNSS signal components of the GNSS signal by non-coherently integrating the at least two of the four GNSS signal components over a period of time in an array processing system, the array processing system receiving GNSS sample data from a baseband memory, the GNSS sample data formatted as a row and column array having a plurality of rows and columns.

[0427] Embodiment 88. The system of embodiment 87, wherein the generation of the GNSS PRN code by the code generator is dynamic based on GNSS SVs in view during the acquisition and tracking of GNSS signals.

[0428] Embodiment 89. The system of embodiment 88, wherein the GNSS master PRN code from the output of the code generator is shifted in frequency and time to generate a code spectrum, which is used in the DFT together with the frequency result of the DFT of the received GNSS signal.

[0429] Embodiment 90: A GNSS receiver, comprising:

[0430] a radio frequency (RF) receiver including at least a first RF filter and a low noise amplifier (LNA) tuned to only the L5 WB band to receive L5 WB GNSS signals;

[0431] An analog-to-digital converter (ADC) is coupled to the LNA to generate GNSS sample data for storage in a baseband sample memory, wherein the RF receiver is the only GNSS receiver among the GNSS receivers.

[0432] Embodiment 91. A GNSS receiver as described in embodiment 90, wherein the RF receiver does not include an amplifier for GNSS signals other than the L5 WB band, and wherein the RF receiver includes a first RF filter coupled to the GNSS antenna, the output of the first RF filter is coupled to the input of the LNA, and the output of the LNA is coupled to a second RF filter.

[0433] Example 92. A GNSS receiver as described in Example 91, wherein the input of the first amplifier is coupled to the output of the second RF filter, and the output of the first amplifier is coupled to the ADC, and wherein the LNA and the first RF filter are arranged on a first IC, and the ADC and the first amplifier are arranged on a second IC.

[0434] Embodiment 93: The GNSS receiver of embodiment 92, wherein the GNSS receiver further comprises:

[0435] A sideband separation down-converter separates GNSS sideband A sample data from GNSS sideband B sample data; and wherein the second RF filter is disposed in the first IC.

[0436] Embodiment 94: The GNSS receiver according to embodiment 93, further comprising:

[0437] a first circular memory buffer, configured to store the GNSS sideband A sample data; and

[0438] The second circular memory buffer is used to store the GNSS sideband B sample data.

[0439] Embodiment 95: A GNSS receiver as described in embodiment 94, wherein the RF receiver does not include an RF mixer.

[0440] Embodiment 96. The GNSS receiver of embodiment 95, wherein the RF receiver does not include an RF reference local oscillator, and wherein the GNSS antenna is tuned to only the L5 WB band.

[0441] Example 97. A GNSS receiver as described in Example 95, wherein the sideband separation downconverter generates GNSS sideband A sample data arranged in a first array of rows and columns, and generates GNSS sideband B samples arranged in a second array of rows and columns.

[0442] Embodiment 98. The GNSS receiver of embodiment 95, wherein the RF receiver is tuned to receive GNSS signals centered at 1191.795 MHz, and the L5 WB GNSS signal has a chip rate of 10.23 MHz.

[0443] Example 99. A GNSS receiver as in Example 97, wherein the GNSS antenna is the only GNSS antenna in the GNSS receiver, and wherein the RF receiver is tuned to receive GNSS signals centered at 1191.795 MHz, and wherein the L5 WB GNSS signal has a chip rate of 10.23 MHz.

[0444] Embodiment 100: A system for processing GNSS signals, the system comprising:

[0445] an analog-to-digital converter (ADC) for generating a digital representation of the GNSS signal received in the L5 WB GNSS band;

[0446] a baseband sample memory for storing the digital representation of the received GNSS signal, the baseband sample memory being coupled to the ADC;

[0447] A GNSS processing system is coupled to the baseband sample memory to process the digital representation of the received GNSS signal, the GNSS processing system being configured to receive and process at least one of the four GNSS signal components of the L5 WB band GNSS signal without using the L1 GNSS signal.

[0448] Embodiment 101. A system as described in embodiment 100, wherein the system includes only a single GNSS antenna tuned to the L5 WB band centered at 1191.795 MHz, and the received GNSS signal has a chip rate of 10.23 MHz or a chip rate significantly higher (e.g., more than 2 times) than the L1 GPS chip rate of 1.023 MHz.

[0449] Embodiment 102. The system of embodiment 101, wherein the baseband sample memory stores the digital representation in an array of rows and columns arranged in rows according to reception time.

[0450] Embodiment 103. The system of embodiment 101, wherein the baseband sample memory stores the digital representation in an array of rows and columns arranged in columns according to reception time.

[0451] Example 104. A system as described in Example 102, wherein the GNSS processing system processes the received GNSS signal through a sequence of DFTs, wherein the sequence of DFTs includes a first set of DFTs using a time extraction method and then a second set of DFTs using a frequency extraction method, without requiring transposition or rearrangement of data in an array containing the data.

[0452] Embodiment 105. The system of embodiment 100, wherein an initial signal is captured in a coarse time capture mode, further signals are captured in a fine time capture mode, and all signals are tracked in a tracking mode.

[0453] Embodiment 106. The system of Embodiment 105, wherein acquisition-specific hardware usage is reduced when in coherent tracking mode.

[0454] Embodiment 107. The system of embodiment 65, wherein the GNSS processing system does not receive and capture L1 GNSS signals.

[0455] Embodiment 108. The system of embodiment 78, wherein the GNSS processing system does not receive and capture L1 GNSS signals.

[0456] Embodiment 109: A GNSS receiver, comprising:

[0457] input, coupled to the antenna;

[0458] an RF front end coupled to the input;

[0459] an ADC converter coupled to the RF front end;

[0460] a GNSS processing system coupled to the ADC converter, the GNSS processing system receiving a GNSS signal from the ADC converter, wherein the GNSS processing system acquires only selected components of the GNSS signal during an initial acquisition phase, the selected components having a low signal change probability relative to signal change probabilities of other components of the GNSS signal based on a coding scheme used in the selected components.

[0461] Embodiment 110. The GNSS receiver of embodiment 109, wherein after the initial acquisition phase, the GNSS processing system acquires other components of the GNSS signal.

[0462] Embodiment 111. A GNSS receiver as described in embodiment 110, wherein the selected component is an E5BI component from an SV in the Galileo constellation of GNSS satellites, and the other components include one or more of the following: an E5BQ component, an E5AI component, and an E5AQ component from the same SV.

[0463] Embodiment 112. The GNSS receiver of embodiment 110, wherein the signal change is a sign reversal in the coding scheme in the selected component.

[0464] Embodiment 113: The GNSS receiver of embodiment 110, wherein the initial acquisition phase is one of acquisition using coarse time or acquisition using precise time.

[0465] Embodiment 114. The GNSS receiver of embodiment 110, wherein the initial acquisition phase is performed after a failure to acquire a set of the other components of the GNSS signal within a predetermined time period.

[0466] Embodiment 115: A method of operating a GNSS receiver, the method comprising:

[0467] Switching to a simplified acquisition mode in which only selected components of GNSS signals from SVs in the GNSS constellation are acquired during an initial acquisition phase;

[0468] capturing the selected component, the selected component having a low signal change probability relative to signal change probabilities of other components in the GNSS signal from the SV based on a coding scheme used in the selected component,

[0469] After capturing the selected component, the other components are captured.

[0470] Example 116. A method as described in Example 115, wherein the selected component is an E5BI component of an SV in the Galileo constellation of GNSS satellites, and the other components include one or more of the following: an E5BQ component, an E5AI component, and an E5AQ component from the same SV.

[0471] Embodiment 117. The method of embodiment 116, wherein the switching occurs in response to a failure to capture the other component within a predetermined time period.

[0472] Embodiment 118. A method for mitigating interference from an aeronautical radio navigation (ARN) signal, the method comprising:

[0473] receiving GNSS signals and ARN signals via one or more antennas;

[0474] Detecting an interference signal source having a signal strength greater than a noise floor, the signal source comprising an ARN signal;

[0475] The detected interference signal source is removed before correlation processing is performed on the GNSS signal.

[0476] Example 119. The method of Example 118, wherein a predetermined threshold above the noise floor is used in the detection of the signal source.

[0477] Example 120: The method of Example 118, wherein the detected signal source is removed in the frequency domain by a finite impulse response (RF) filter or an infinite impulse response (IIR) filter.

[0478] Example 121. A method as described in Example 118, wherein the signal source is detected by an array processor that calculates a discrete Fourier transform of the GNSS signal.

[0479] Embodiment 122. A method for mitigating interference from an aeronautical radio navigation (ARN) signal, the method comprising:

[0480] receiving a GNSS signal and an ARN signal from a GNSS SV via one or more antennas, the received GNSS signal having a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband;

[0481] detecting interference from a signal source based on the ARN signal, the interference interfering with the first sideband but not substantially interfering with the second sideband;

[0482] In response to the detected interference, the GNSS processing system is configured to process the second sideband from the GNSS SV and not process the first sideband in order to acquire or track the GNSS signal from the GNSS SV.

[0483] Embodiment 123. The method of embodiment 122, wherein the first sideband is a higher frequency sideband and the second sideband is a lower frequency sideband.

[0484] Example 124. A method as described in Example 122, wherein the interference is detected when (1) the strength of the signal source is higher than a threshold above the background noise or (2) the correlated signal-to-noise ratio of a specific sideband is lower than a given threshold.

[0485] Embodiment 125. The method of embodiment 124, wherein the GNSS processing system processes the second sideband without processing the first sideband during the duration of the detected interference and reverts to processing both after the interference decreases below the noise floor.

[0486] Embodiment 126: A GNSS receiver, comprising:

[0487] Input, used to receive GNSS signals from the antenna;

[0488] an RF front end coupled to the input to receive the GNSS signal;

[0489] an RF switch mixer coupled to the RF front end;

[0490] a discrete time filter coupled to the RF switch mixer, the discrete time filter comprising a bandpass response for selecting a desired GNSS signal and suppressing out-of-band interference and noise;

[0491] A local oscillator signal, derived from a phase-locked loop (PLL) circuit, is coupled to the RF switch mixer to provide a local reference signal.

[0492] Embodiment 127. The GNS receiver of embodiment 126, wherein the discrete-time filter is configured with a notch response for suppressing interference from aeronautical radio navigation (ARN) signals at specific locations.

[0493] Embodiment 128. The GNSS receiver of embodiment 126, wherein the GNSS receiver further comprises:

[0494] One or more direct sampling or double sampling analog-to-digital converters (ADCs) are coupled to the discrete-time filter.

[0495] Embodiment 129: A GNSS receiver as described in embodiment 128, wherein the bandwidth of the discrete-time filter can be dynamically adjusted to switch between single-sideband signal processing or double-sideband signal processing.

[0496] Example 130. A GNSS receiver as in Example 128, wherein the clock signal operably received by the RF switch mixer and the discrete time filter is capable of being adjusted to position the high sideband or the low sideband at baseband or at a low intermediate frequency (IF), or to position the center between the high sideband and the low sideband at baseband or at a low intermediate frequency (IF).

[0497] Embodiment 131. The GNSS receiver of embodiment 128, wherein a local reference signal from a PLL local oscillator is harmonically related to a sampling clock of the ADC and the discrete-time filter.

[0498] Embodiment 132: A GNSS receiver, comprising:

[0499] Input, used to receive GNSS signals from the antenna;

[0500] an RF switch mixer coupled to the input to receive a GNSS signal;

[0501] a discrete-time filter coupled to the RF switch mixer;

[0502] one or more analog-to-digital converters (ADCs) coupled to the discrete-time filter;

[0503] A phase-locked loop (PLL) circuit is coupled to the RF switch mixer to provide a local oscillator signal, the output of the PLL circuit being harmonically related to a sampling clock of the one or more ADCs and a clock signal of the discrete-time filter.

[0504] Embodiment 133. A GNSS receiver as described in embodiment 132, wherein the one or more ADCs downconvert and provide digitized GNSS signals.

[0505] Embodiment 134: A GNSS receiver as described in embodiment 132, wherein the bandwidth of the discrete-time filter can be dynamically adjusted to switch between single double-sideband signal processing or double-sideband signal processing.

[0506] Embodiment 135. A GNSS receiver as described in embodiment 132, wherein the clock signal that the discrete-time filter is operably received is capable of being adjusted to position the high sideband or the low sideband at baseband or at a low intermediate frequency (IF), or to position the center between the high sideband and the low sideband at baseband or at a low intermediate frequency (IF).

[0507] Example 136. A GNSS receiver as in Example 132, wherein the one or more ADCs include an in-phase branch portion and an orthogonal phase branch portion, and wherein the orthogonal phase branch portion can be disabled so as to fold the received modulated signal onto itself, and wherein a subsequent stage of demodulation operation restores the original signal existing before the folding.

[0508] Embodiment 137: A method of operating a GNSS receiver, the method comprising:

[0509] receiving a GNSS signal from a GNSS SV, the GNSS signal comprising a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband;

[0510] selecting a first mode or a second mode of operation based on a desired power state of the GNSS receiver;

[0511] in response to selecting the first mode and while in the first mode, processing a first GNSS signal component in a first sideband and not processing a second GNSS signal component in a second sideband to acquire or track a GNSS signal from the GNSS SV;

[0512] In response to selecting the second mode and while in the second mode, a first GNSS signal component in a first sideband is processed and a second GNSS signal component in a second sideband is processed to acquire a GNSS signal from the GNSS SV.

[0513] Embodiment 138. The method of embodiment 137, wherein in the first mode, at least a portion of the GNSS receiver operates at a reduced processing rate.

[0514] Embodiment 139. A method as described in embodiment 138, wherein the first mode reduces power consumption in the GNSS receiver, and wherein the GNSS receiver operates in the second mode when acquiring GNSS signals and is then configured to operate in the first mode when tracking GNSS signals.

[0515] Embodiment 140: A method of operating a GNSS receiver, the method comprising:

[0516] receiving a GNSS signal from a GNSS SV, the GNSS signal comprising a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband;

[0517] mixing the first GNSS signal component and the second GNSS signal component in a mixer to fold the first signal component and the second GNSS signal component over each other;

[0518] A GNSS signal is obtained from the first GNSS signal component and the second GNSS signal component after the mixing.

[0519] Embodiment 141. A method of operating a GNSS receiver, the method comprising:

[0520] acquiring a plurality of GNSS signal components from one or more GNSS SVs during an acquisition phase;

[0521] A subset of the plurality of GNSS signal components is tracked after the acquisition phase is completed.

[0522] Example 142. The method of Example 141, wherein the method further comprises:

[0523] The subset is selected based on one or more criteria or algorithms for selecting the subset, the selection occurring before the position of the GNSS receiver is determined.

[0524] Embodiment 143. The method of embodiment 142, wherein the one or more criteria or algorithms provide sufficient signal for tracking while reducing power consumption.

[0525] Embodiment 144. The method of embodiment 142, wherein the one or more standards or algorithms provide sufficient GNSS signals to determine the position of the GNSS receiver while reducing power consumption.

[0526] Embodiment 145. The method of embodiment 142, wherein the plurality of GNSS signal components from one or more GNSS SVs include upper and lower sideband signals and a lower sideband signal, and wherein the subset is limited to one of the upper sideband and the lower sideband.

[0527] Embodiment 146. A method for determining a time of arrival of a GNSS signal, wherein more than one Doppler assumption is required for the received signal, the method comprising:

[0528] Perform a forward fast Fourier transform operation on the block of signal samples to construct a frequency vector,

[0529] Perform at least one of the following to provide a first Doppler-compensated frequency vector: (A) cyclically rotating the frequency vector by a non-zero integer amount, or (B) performing an interpolation operation on the frequency vector

[0530] The first Doppler-compensated frequency vector is multiplied by a first reference function vector to form a first weighted Doppler-compensated frequency vector, and an inverse fast Fourier transform operation is performed on the first weighted Doppler-compensated frequency vector to produce a first output time vector, which is used to determine the arrival time of the GNSS signal.

[0531] Embodiment 147. The method of embodiment 146, wherein before performing the fast Fourier transform operation, the block of signal samples is first multiplied by a complex sinusoid to frequency shift the block of signal samples.

[0532] Embodiment 148. The method of embodiment 146, wherein the signal sample block is first augmented with a set of zero-valued samples before performing the fast Fourier transform operation.

[0533] The method described in Example 149 and Example 146 further includes:

[0534] performing at least one of the following to provide a second Doppler-compensated frequency vector: (A) cyclically rotating the frequency vector by a non-zero integer amount, or (B) performing an interpolation operation on the frequency vector, wherein the second Doppler-compensated frequency vector is different from the first Doppler-compensated frequency vector,

[0535] The second Doppler compensated frequency vector is multiplied by a first reference function vector to form a second weighted Doppler compensated frequency vector, and an inverse fast Fourier transform operation is performed on the second weighted Doppler compensated frequency vector to produce a second output time vector for determining the time of arrival of the GNSS signal.

[0536] The method described in Example 150 and Example 146 further includes:

[0537] multiplying the first Doppler compensated frequency vector by a second reference function vector to form a second weighted Doppler compensated frequency vector, wherein the second reference function vector is different from the first reference function vector,

[0538] and performing an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

[0539] The method described in Example 151 and Example 146 further includes:

[0540] performing at least one of the following to provide a second Doppler-compensated frequency vector: (A) cyclically rotating the frequency vector by a non-zero integer amount or (B) performing an interpolation operation on the frequency vector, wherein the second Doppler-compensated frequency vector is different from the first Doppler-compensated frequency vector,

[0541] multiplying the second Doppler compensated frequency vector by a second reference function vector to form a second weighted Doppler compensated frequency vector, wherein the second reference function vector is different from the first reference function vector,

[0542] and performing an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the time of arrival of the GNSS signal.

[0543] Embodiment 152. A method for determining a time of arrival of a GNSS signal, wherein more than one Doppler assumption is required for the received signal, the method comprising:

[0544] Perform a forward fast Fourier transform operation on the block of signal samples to construct a frequency vector,

[0545] performing at least one of the following to provide a first Doppler-compensated reference function vector: (A) cyclically rotating the first reference function vector by a non-zero integer amount or (B) performing an interpolation operation on the reference function vector,

[0546] multiplying the first Doppler compensated reference function vector by the frequency vector to form a first weighted Doppler compensated frequency vector,

[0547] and performing an inverse fast Fourier transform operation on the first weighted Doppler compensated frequency vector to generate a first output time vector for determining the time of arrival of the GNSS signal.

[0548] Embodiment 153. The method of embodiment 152, wherein before performing the fast Fourier transform operation, the block of signal samples is first multiplied by a complex sinusoid to frequency shift the block of signal samples.

[0549] Embodiment 154: The method of embodiment 152, wherein the signal sample block is first augmented with a set of zero-valued samples before performing the fast Fourier transform operation.

[0550] The method described in Example 155 and Example 152 further includes:

[0551] performing at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically rotating the first reference function vector by a non-zero integer amount, or (B) performing an interpolation operation on the reference function vector,

[0552] wherein the second Doppler-compensated reference function vector is different from the first Doppler-compensated reference function vector,

[0553] multiplying the second Doppler compensated reference function vector by the frequency vector to form a second weighted Doppler compensated frequency vector,

[0554] and performing an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the time of arrival of the GNSS signal.

[0555] The method described in Example 156 and Example 152 further includes:

[0556] performing at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically rotating a second reference function vector by a non-zero integer amount or (B) performing an interpolation operation on a second reference function vector, wherein the second reference function vector is different from the first reference function vector,

[0557] multiplying the second Doppler compensated reference function vector by the frequency vector to form a second weighted Doppler compensated frequency vector,

[0558] and performing an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

[0559] The method described in Example 157 and Example 152 further includes:

[0560] performing at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically rotating the second reference function vector by a non-zero integer amount or (B) performing an interpolation operation on the reference function vector,

[0561] wherein the second Doppler-compensated reference function vector is different from the first Doppler-compensated frequency vector, wherein the second reference function vector is different from the first reference function vector,

[0562] multiplying the second Doppler compensated reference function vector by the frequency vector to form a second weighted Doppler compensated frequency vector,

[0563] and performing an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the time of arrival of the GNSS signal.

[0564] Embodiment 158. A method for determining a time of arrival of a GNSS signal, wherein more than one Doppler assumption is required for the received signal, the method comprising:

[0565] Perform a forward fast Fourier transform operation on the block of signal samples to construct a frequency vector,

[0566] performing at least one of the following to provide a first Doppler-compensated frequency vector: (A) cyclically rotating the frequency vector by a non-zero integer amount, or (B) performing an interpolation operation on the frequency vector,

[0567] performing at least one of the following to provide a first Doppler-compensated reference function vector: (A) cyclically rotating the first reference function vector by a non-zero integer amount, or (B) performing an interpolation operation on the reference function vector,

[0568] multiplying the first Doppler compensated frequency vector by the first Doppler compensated reference function vector to form a first weighted Doppler compensated frequency vector,

[0569] and performing an inverse fast Fourier transform operation on the first weighted Doppler compensated frequency vector to generate a first output time vector for determining the time of arrival of the GNSS signal.

[0570] The method described in Example 159 and Example 158 further includes:

[0571] performing at least one of the following to provide a second Doppler-compensated frequency vector: (A) cyclically rotating the frequency vector by a non-zero integer amount, or (B) performing an interpolation operation on the frequency vector,

[0572] performing at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically rotating the second reference function vector by a non-zero integer amount, or (B) performing an interpolation operation on the second reference function vector,

[0573] multiplying the first Doppler compensated frequency vector by the first Doppler compensated reference function vector to form a second weighted Doppler compensated frequency vector, wherein the second weighted Doppler compensated frequency vector is different from the first weighted Doppler compensated frequency vector; and

[0574] An inverse fast Fourier transform operation is performed on the second weighted Doppler compensated frequency vector to produce a second output time vector for determining the time of arrival of the GNSS signal.

[0575] A machine-readable medium includes any mechanism (e.g., a computer or processing logic implemented in hardware) for storing information in a form readable by a machine. For example, machine-readable media include read-only memory ("ROM"); random access memory ("RAM") such as dynamic random access memory; magnetic disk storage media; optical storage media; flash memory devices; and the like.

[0576] Articles of manufacture can be used to store program code. Articles of manufacture storing program code can be embodied as, but not limited to, one or more memories (e.g., one or more flash memories, random access memories (static, dynamic, or other)), optical disks, CD-ROMs, DVDROMs, EPROMs, EEPROMs, magnetic or optical cards, or other types of machine-readable media suitable for storing electronic instructions. Program code can also be downloaded from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a data signal embodied in a propagation medium (e.g., via, through a communication link (e.g., a network connection)). Processing logic such as one or more hardware processing systems (e.g., microprocessors or microcontrollers, etc.) can execute program code to cause a data processing system to perform the method of one or more embodiments described herein.

[0577] In the foregoing description, specific exemplary embodiments have been described. It will be apparent that various modifications may be made to those embodiments without departing from the broader spirit and scope of the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system for processing GNSS signals, the system comprising: A radio frequency analog-to-digital converter (ADC) for generating a digital representation of the received GNSS signal; a baseband sample memory for storing the digital representation of the received GNSS signal as digitized GNSS sample data, the baseband sample memory being configured to store an array of the digitized GNSS sample data in N2 rows and N1 columns, the digitized GNSS sample data in the array being stored in row order in the baseband sample memory and N2 being greater than N1, the row order containing the digitized GNSS sample data received during a time period including a first time period and a second time period, such that a first row in the row order contains digitized GNSS sample data received during the first time period, and a second row following the first row in the row order contains digitized GNSS sample data received during the second time period following the first time period, the baseband sample memory being coupled to the RF ADC; A set of arithmetic logic units (ALUs) configured to perform discrete Fourier transform (DFT) operations, the set of ALUs being coupled to the baseband sample memory, the set of ALUs being configured to perform N1 DFTs in parallel and simultaneously in time, wherein each of the N1 DFTs includes N2 points in the DFT, and outputs of the N1 DFTs are stored in a partial result sample array, and wherein the set of ALUs is configured to then perform N2 DFTs, each of the N2 DFTs including N1 points from the partial result sample array, the N2 DFTs providing outputs stored in a DFT result array arranged in column order.

2. The system of claim 1, wherein: The baseband sample memory is configured as a circular memory buffer storing the array.

3. The system of claim 2, wherein: The N1 DFTs use the same operation and the same program control instructions for the set of ALUs to operate on different data.

4. The system of claim 3, wherein: The N2 DFTs are performed successively over time, and wherein the circular memory buffer stores more than one frame of pseudo-random GNSS codes, the more than one frame of pseudo-random GNSS codes being greater than 1 millisecond.

5. The system of claim 3, wherein: The N1 DFTs and the N2 DFTs use a time decimation method, and wherein N1 is one of the following integer values: 5 or 10 or 20 or 40.

6. The system of claim 3, wherein: The change from row order to column order, which results from the combination of the N1 DFTs and the subsequent N2 DFTs, avoids a reordering algorithm.

7. The system of claim 3, wherein: The GNSS code generator is configured to generate a GNSS code, and the set of ALUs performs a set of DFTs on the GNSS code to provide code spectrum result data stored in a code spectrum memory in column order, the code spectrum result data including GNSS PRN code data that is frequency and / or time offset.

8. The system of claim 7, wherein: The set of ALUs is configured to multiply the code spectrum result data by the output stored in the DFT result array to generate a product array.

9. The system of claim 8, wherein: The set of ALUs is configured to perform an inverse DFT on the product array using a frequency decimation method.

10. The system of claim 9, wherein: The inverse DFT includes: (1) in a first stage, N2 DFTs with conjugated inputs, each of the N2 DFTs containing N1 points, and (2) in a second stage after the first stage, N1 DFTs, each of the N1 DFTs containing N2 points.

11. The system of claim 2, wherein: The baseband sample memory is a dual-port memory.

12. The system of claim 7, wherein: The GNSS code generator generates a pseudorandom code for each GNSS SV in view every millisecond when needed during the acquisition phase, and does not store the generated pseudorandom code after use, and the generated pseudorandom code is used to generate the GNSS code spectrum.

13. The system of claim 12, wherein: The GNSS code spectrum is aligned in situ in memory in both frequency and phase to match a code phase hypothesis and a frequency shift hypothesis associated with the received GNSS signal.

14. The system of claim 13, wherein: The alignment is performed by the CORDIC hardware.

15. The system of claim 1, wherein: The digitized GNSS sample data is stored in column order rather than row order.

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