Memory mapping apparatus and method

Abstract

Disclosed devices and methods include a sequential mapping table located within a flash memory array of a flash memory device. Selected examples include firmware in the flash memory device for loading the sequential mapping table into a cache upon power-up and performing read and write operations using the sequential mapping table. Selected examples include firmware in the flash memory device for storing an updated sequential mapping table in the flash memory array when the flash memory device is powered off.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to mapping logical locations to physical locations in memory; and more specifically to reduced-size data structures for this mapping. Background Technology

[0002] A memory device is a semiconductor circuit that provides electronic storage for data to a host system (e.g., a computer or other electronic device). Memory devices can be volatile or non-volatile. Volatile memory requires power to maintain its data and includes devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM). Non-volatile memory can retain stored data when not powered and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistive variable memory such as phase-change random access memory (PCRAM), resistive random access memory (RRAM), or magnetoresistive random access memory (MRAM).

[0003] A host system typically includes a host processor, a primary amount of main memory (e.g., typically volatile memory, such as DRAM) to support the host processor, and one or more storage systems (e.g., typically non-volatile memory, such as flash memory) that provide additional storage for data retention in addition to or independently of the main memory.

[0004] Memory is typically described and organized using virtual logical blocks and physical blocks. Physical blocks are described by their actual physical locations within one or more semiconductor dies. Logical blocks are conceptual and can be used in a software environment. In such memory organization, a mapping table can be used to track the association between virtual and physical blocks. As memory devices increase in size and complexity, there is a growing demand for devices and methods to improve the efficiency of memory mapping tables.

[0005] Memory is typically described and organized using virtual logical blocks that are associated with physical blocks. Physical blocks are described by their actual physical locations within one or more memory arrays, such as one or more semiconductor memory dies. Logical blocks are conceptual and can be used in a software environment. In such memory organization, data structures such as memory mapping tables can be used to track the association between virtual and physical blocks. As memory devices increase in size and complexity, there is a growing demand for devices and methods to improve the efficiency of memory mapping tables. Attached Figure Description

[0006] In diagrams that are not necessarily drawn to scale, similar numbers can describe similar components in different views. Similar numbers with different letter subscripts can represent different examples of similar components. The diagrams generally illustrate the various embodiments discussed in this document by way of example rather than limitation.

[0007] Figure 1 This describes an instance host system that includes host devices and storage systems.

[0008] Figure 2 A block diagram illustrating a memory device according to some example embodiments.

[0009] Figure 3 This describes a sequential mapping table based on some example implementations.

[0010] Figure 4 This describes an instance method flowchart based on some example implementations.

[0011] Figures 5A to 5F This describes a series of instance sequential mapping table operations based on some example implementations.

[0012] Figure 6 This describes an instance sequence mapping table based on some example implementations.

[0013] Figure 7 This section illustrates an example block diagram of an information processing system based on some exemplary embodiments. Detailed Implementation

[0014] The following description and figures fully illustrate specific embodiments to enable those skilled in the art to practice thereon. Other embodiments may be incorporated with structural, logical, electrical, technological, and other changes. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. The embodiments set forth in the claims cover all available equivalents of the claims.

[0015] Many storage devices (e.g., flash memory) use data structures (e.g., translation tables) to map logical elements (e.g., pages or blocks) to their physical equivalents (such translation tables are called "L2P tables"). These L2P tables are typically stored within the storage device, and during operation, the table, or portions thereof, are typically loaded into the controller's internal memory. If the table size is larger than the controller's internal memory (e.g., random access memory (RAM), such as dynamic RAM (DRAM) or static RAM (SRAM)), then a portion of the table is loaded into internal memory, and the remainder is stored in other storage devices, such as primary storage (in some instances, NAND flash memory). If a translation request (e.g., a logical-to-physical (L2P) mapping) is not in internal memory, the controller replaces the internal memory portion of the table with the appropriate portion from the other storage device. This process can increase latency when performing operations such as reading from or writing to the storage device.

[0016] This problem is exacerbated in devices containing limited RAM available for storing a portion of the L2P table (which would typically be a further limitation on the amount of L2P table that can be stored). Embodiments as described herein involve the generation and use of reduced-size representations of all or a portion of the L2P table. In the examples described below, when multiple sequential logical addresses correspond to multiple sequential physical addresses, the correspondence can be indicated by the initial logical address of the sequence, the initial physical address of the sequence, and the number of sequentially corresponding logical and physical addresses.

[0017] For example, a sequence of physical addresses (e.g., physical block addresses, "PBAs") corresponding to a group of sequential logical addresses (e.g., logical block addresses, "LBAs") can be represented by: the PBA of the initial block of the sequence of PBAs; the LBA of the initial block of the group of sequential LBAs associated with the group of sequential LBAs; and an indicator of the number of sequential PBAs associated with the group of sequential LBAs. For the purposes of this description, in selected examples of the discussion below, such representations may be presented in a table, referred to herein as a "sequential mapping table". In many instances, the sequential mapping table will also contain representations of non-sequential logical and physical addresses.

[0018] A memory device comprises individual memory dies, which may, for example, include a memory region comprising one or more memory cell arrays implementing one or more selected memory technologies. This memory die typically includes supporting circuitry for operating the memory array. Other instances, sometimes commonly referred to as “managed memory devices,” comprise combinations of one or more memory dies associated with controller functionality configured to control the operation of the one or more memory dies. This controller functionality simplifies interoperability with external devices, such as “hosts,” as discussed later herein. In such managed memory devices, the controller functionality may be implemented on one or more dies also incorporated into the memory array or on separate dies. In other instances, one or more memory devices may be combined with controller functionality to form a solid-state drive (SSD) storage volume.

[0019] Embodiments of this disclosure are described in examples of managed memory devices (referred to as “managed NAND” devices) that implement NAND flash memory cells. However, these examples do not limit the scope of this disclosure, which may be implemented in other forms of memory devices and / or with other forms of storage technologies.

[0020] Each flash memory cell in a NOR or NAND architecture semiconductor memory array can be individually or collectively programmed into one or more programming states. For example, a single-level cell (SLC) can represent one of two programming states (e.g., 1 or 0), which represents one data bit. Flash memory cells can also represent more than two programming states, which allows for the fabrication of higher-density memory without increasing the number of memory cells, because each cell can represent more than one binary digit (e.g., more than one bit). Such cells may be referred to as multi-state memory cells, multi-digit cells, or multi-level cells (MLCs). In some instances, MLC can refer to a memory cell that can store two data bits per cell (e.g., one of four programming states), a three-level cell (TLC) can refer to a memory cell that can store three data bits per cell (e.g., one of eight programming states), and a four-level cell (QLC) can store four data bits per cell. In its broader context, MLC is used herein to refer to any memory cell that can store more than one data bit per cell (i.e., that can represent more than two programming states).

[0021] The managed memory device can be configured and operated according to recognized industry standards. For example, the managed NAND device can be (as a non-limiting instance) Universal Flash Storage (UFS). TM ) device, or embedded MMC device (eMMC) TMFor example, in the above scenarios, a UFS device can be configured according to a Joint Electronic Devices Engineering Committee (JEDEC) standard (e.g., JEDEC standard JESD223D entitled "JEDEC UFS Flash Storage 3.0") and / or a later or subsequent version of this standard. Similarly, an identified eMMC device can be configured according to a JEDEC standard JESD84-A51 entitled "JEDEC eMMC standard 5.1" and / or a later or subsequent version of this standard.

[0022] SSDs are particularly well-suited for use as primary storage devices in computers and offer advantages over traditional hard drives with moving parts in areas such as performance, size, weight, robustness, operating temperature range, and power consumption. For example, SSDs can have reduced search times, latency, or other delays associated with disk drives (e.g., electromechanical latency). SSDs use non-volatile memory cells, such as flash memory cells, to eliminate the need for an internal battery supply, allowing for more versatile and compact drives. Managed memory devices (such as managed NAND devices) can be used as primary or secondary storage in various forms of electronic devices and are commonly found in mobile devices.

[0023] SSDs and managed memory devices may include several memory devices (comprising several dies or logical units (e.g., logical unit numbers or LUNs)) and may include one or more processors or other controllers that perform the logical functions required to operate the memory devices or interface with external systems. Such SSDs and managed memory devices may include one or more flash memory dies on which several memory arrays and peripheral circuitry are included. Flash memory arrays may include blocks of memory cells organized into several physical pages. In some instances, SSDs may also include DRAM or SRAM (or other forms of memory dies or other memory structures). Similarly, managed NAND devices may include one or more arrays of volatile and / or non-volatile memory, separate from or within a controller and independent of the NAND memory array. SSDs and managed NAND devices may receive commands from the host associated with memory operations (e.g., read or write operations to transfer data (e.g., user data and associated integrity data, such as error data and address data) between the memory devices and the host, or erase operations to erase data from the memory devices).

[0024] Figure 1The illustrated example system (e.g., host system) 100 includes a host device 105 and a storage system 110 configured to communicate via a communication interface (I / F) 115 (e.g., a bidirectional parallel or serial communication interface). The host device 105 may include a host processor 106 (e.g., a host central processing unit (CPU) or other processor or processing device) or other host circuitry (e.g., a memory management unit (MMU), interface circuitry, evaluation circuitry 107, etc.). In some instances, the host device 105 may include main memory 108 (e.g., DRAM, etc.) and optionally static memory 109 to support the operation of the host processor 106.

[0025] Storage system 110 may include a universal flash storage (UFS) device, embedded MMC (eMMC) TM The storage system 110 may contain one or more other memory devices. For example, if the storage system 110 includes a UFS device, then the communication interface 115 may include a serial bidirectional interface, such as that defined in the JEDEC UFS standard indicated above. In another instance, if the storage system 110 includes an eMMC device, then the communication interface 115 may include several parallel bidirectional data lines (e.g., DAT[7:0]) and one or more command lines, such as those defined in the JEDEC eMMC standard indicated above. In other instances, the storage system 110 may include one or more other memory devices, or the communication interface 115 may include one or more other interfaces, depending on the host device 105 and the storage system 110.

[0026] The storage system 110 may include a memory controller 111 and non-volatile memory 112. In an example, the non-volatile memory may include several memory devices (e.g., dies or LUNs), such as one or more flash memory devices, each containing peripheral circuitry thereon and controlled by the memory controller 111.

[0027] Flash memory devices typically comprise one or more groups of single-transistor floating-gate memory cells. Two common types of flash memory array architectures are NAND and NOR architectures. The floating-gate memory cells of a memory array are typically arranged in a matrix. The gate of each memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drains of each memory cell in a column of the array are coupled together in series (source to drain) between the source line and the bit line.

[0028] In a semiconductor memory array of NOR, NAND, 3D crossover, ferroelectric RAM (FeRAM), MRAM, or one or more other architectures, each memory cell can be individually or collectively programmed into one or more programming states. A single-level cell (SLC) can represent one data bit per cell in one of two programming states (e.g., 1 or 0). A multi-level cell (MLC) can represent one data bit per cell in several programming states (e.g., 2...). n In MLC (where n is the number of data bits), each cell represents two or more data bits. In some instances, MLC may refer to a memory cell that can store two data bits in one of four programming states. A three-level cell (TLC) can represent three data bits per cell in one of eight programming states. A four-level cell (QLC) can represent four data bits per cell in one of sixteen programming states. Unless clearly indicated by explicit language or context, MLC is used in its broader context herein to refer to a memory cell that can store more than one data bit per cell (i.e., that can represent more than two programming states).

[0029] Storage system 110 may include a multimedia card (MMC) solid-state storage device (e.g., a Micro Secure Digital (SD) card). The MMC device includes several parallel interfaces (e.g., an 8-bit parallel interface) with host device 105 and is typically a removable and detachable component from the host device. In contrast, embedded MMC (eMMC) devices are attached to a circuit board and considered as components of the host device, offering read speeds comparable to Serial ATA (SATA)-based SSD devices. With increasing demands for mobile device performance, such as for fully enabling virtual or augmented reality devices and utilizing ever-increasing network speeds, storage systems have transitioned from parallel communication interfaces to serial communication interfaces. UFS devices (including controllers and firmware) communicate with the host device using a Low Voltage Differential Signaling (LVDS) serial interface with a dedicated read / write path, further enhancing read / write speeds between the host device and the storage system.

[0030] In three-dimensional (3D) architecture semiconductor memory device technology, vertically floating gate or charge-trapping memory structures can be stacked, thereby increasing the number of layers, physical pages, and therefore memory cell density in the memory device.

[0031] Data is typically stored arbitrarily in small units on storage systems. Even when accessed as individual units, data can be received in small, random single-file reads of 4 to 16 kilobytes (e.g., 60% to 80% of operations are less than 16 kilobytes). It is difficult for users, and even kernel applications, to instruct data to be stored as a sequential, cohesive unit. File systems are typically designed to optimize space usage rather than sequentially retrieving space.

[0032] The memory controller 111 may receive instructions from the host device 105 and may communicate with the non-volatile memory 112, for example, to transfer (e.g., write or erase) data to (e.g., write or erase) one or more memory cells of the non-volatile memory array 112 or to transfer (e.g., read) data from one or more memory cells of the non-volatile memory array 112. The memory controller 111 may in particular include circuitry or firmware, such as components or integrated circuits. For example, the memory controller 111 may include one or more memory control units, circuitry, or components configured to control access across the memory array and provide a translation layer between the host device 105 and the storage system 100.

[0033] The non-volatile memory array 112 (e.g., a 3D NAND architecture semiconductor memory array) may include a number of memory cells arranged in, for example, devices, planes, blocks, and / or physical pages. As an example, a TLC memory device may include 18,592 bytes (B) of data per page, 1536 pages per block, 548 blocks per plane, and 4 planes per device. As another example, an MLC memory device with two bits per cell may include 18,592 bytes (B) of data per page, 1024 pages per block, 548 blocks per plane, and 4 planes per device, but its write time is half that of the corresponding TLC memory device, and its program / erase (P / E) cycles are twice that of the corresponding TLC memory device. Other examples may include other numbers or arrangements.

[0034] In operation, data is typically written to or read from storage system 110 in pages and erased in blocks. However, as needed, one or more memory operations (e.g., read, write, erase, etc.) can be performed on larger or smaller groups of memory cells. For example, partial updates to tagged data from offloaded cells can be collected during data migration or garbage collection to ensure efficient rewriting. The data transfer size of a memory device is typically referred to as a page, while the data transfer size of a host device is typically referred to as a sector. Although a page of data may contain several bytes of user data (e.g., a data payload containing several data sectors) and its corresponding metadata, the page size typically refers only to the number of bytes used to store the user data. As an example, a data page with a page size of 4KB may contain 4KB of user data (e.g., eight sectors of a sector size of 512B) and several bytes of metadata corresponding to the user data (e.g., 32B, 54B, 224B, etc.), such as integrity data (e.g., error detection or correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data.

[0035] Different types of memory cells or memory arrays can provide different page sizes, or require different amounts of associated metadata. For example, different memory device types can have different bit error rates, which can lead to different amounts of metadata needed to ensure the integrity of data pages (e.g., a memory device with a higher bit error rate may require more bytes of error correction code data compared to a memory device with a lower bit error rate). As an example, MLC NAND flash devices have a higher bit error rate than their corresponding SLC NAND flash devices. Therefore, MLC devices may require more bytes of metadata for erroneous data compared to their corresponding SLC devices.

[0036] Figure 2 A block diagram showing a memory device 200, which is from... Figure 1 An example implementation of the storage system 110 is shown. A controller 211 is coupled to a flash memory array 212 via interconnect 214. In the illustrated example, both the controller 211 and the flash memory array 212 are coupled to a common substrate 202. The substrate 202 can be configured to connect to a motherboard or other intermediate substrates in the computing device. Connections may include sockets, such as through-hole memory sockets, or solder bump connections, etc.

[0037] One example of flash memory array 212 includes a NAND flash memory array. Flash memory array 212 may include multiple dies to provide increased memory storage capacity. In one example, multiple dies are stacked to reduce the amount of physical space required for the dies, but the invention is not limited thereto. Other examples include dies mounted side-by-side on a substrate. In selected examples, multiple die stacks may be located side-by-side on the substrate as part of flash memory array 212. Other logic configurations besides NAND, such as NOR or other logical organization of memory cells, may also be used.

[0038] Controller 211 is configured (e.g., hardware and / or software implementation) to perform the memory mapping method described herein, including references below. Figures 4 to 6 The exemplary method described herein. For example, controller 211 stores instructions for performing the memory mapping method described herein. In this example, the instructions are contained in firmware 213. In one example, firmware 213 is configured to interact with sequential mapping table 216, as described in this disclosure. Figure 2 In this example, the sequential mapping table 216 is stored in the flash memory storage array 212.

[0039] In one instance, firmware 213 is configured to access sequential mapping table 216. In one instance, firmware 213 is configured to write to sequential mapping table 216. In one instance, firmware 213 is configured to create sequential mapping table 216. In one instance, firmware 213 is configured to edit and / or modify sequential mapping table 216. In one instance, firmware 213 is also configured to interact with individual mapping tables 218. The interaction functionality between firmware 213 and individual mapping tables 218 is similar to that of the sequential mapping tables described above, and includes access, writing, creation, editing, and modification.

[0040] In one instance, buffer 222 is included in controller 211. In another instance, firmware 213 contains instructions executable by the processor of controller 211 to utilize buffer 222 during operation to track memory operations (e.g., write and erase operations that modify the mapping table). At specified times, the contents of buffer 222 can be written to sequential mapping table 216 to store the latest mapping information. A more detailed example of utilizing the buffer will be described below.

[0041] In one instance, cache 224 is contained within controller 211. In one instance, firmware 213 contains instructions executable by the processor of controller 211 to load sequential mapping table 216 into cache 224 upon startup of memory device 200. In one instance, cache 224 is a faster form of memory, such as static random access memory (SRAM). In one instance, when memory device 200 is powered off, sequential mapping table 216 is written from cache 224 back into memory storage array 212.

[0042] Figure 3 Displays such as those available for operation, for example Figure 2 The memory device 200 includes an individual mapping table 310 and a sequential mapping table 300. In the individual mapping table 310, a first column 312 records logical block addresses (LBAs), and a second column 314 records corresponding physical addresses (PPAs). In the individual mapping table 310, there is a one-to-one correspondence between individual blocks stored in an LBA and individual blocks stored in a PPA. Individual descriptors 316 map this one-to-one relationship. Each individual descriptor contains one LBA and one PPA.

[0043] In the example shown, sequential write operations are represented by group 318 of a single descriptor. In one instance, the sequential (i.e., contiguous) blocks of data written are stored in a sequential mapping table, not as a list of individual LBAs and PPAs, but with a starting address and length.

[0044] The sequential mapping table 300 displays a first column 302 containing the starting position of the logical block used for sequential writing, a second column 304 containing the starting position of the corresponding physical block, and a length column 306 recording how many blocks the sequential write operation is.

[0045] As from Figure 3 As can be seen, the long group 318 from individual mapping tables 310 is significantly reduced in size to a single sequential descriptor 301. In most memory operations, large amounts of data are written sequentially. By using a sequential mapping table as described, the size of the sequential mapping table will be significantly smaller than that of individual mapping tables, even though the sequential mapping table contains all the information necessary to find the desired data block.

[0046] In some systems, Dynamic Random Access Memory (DRAM) resides within a flash memory device. Access to DRAM is faster than access to a flash memory array. Therefore, a mapping table, such as an individual mapping table 310, is loaded into local DRAM memory to provide faster access to data stored in the flash memory array. However, DRAM memory increases the cost of such systems. Therefore, in other systems, local DRAM memory is removed to save manufacturing costs, and a small portion of the mapping table (e.g., individual mapping table 310) is loaded into a small cache within the memory controller, such as from... Figure 2 The cache 224. In some instances, the size of cache 224 is finite. For example, the size of cache 224 may allow less than all (e.g., a selected small portion) of an individual mapping table 310 to be loaded into cache 224 during operation. Due to the finite size of the cache, the selected small portion of the mapping table in the cache may not be the part necessary for a given read request. In this case, the controller may request a different portion of the mapping table loaded from the flash memory array, and then the read request can be completed. This operation of swapping the cache and reloading a portion of the mapping table can take a long time.

[0047] As described above, instances of sequential mapping tables (such as sequential mapping table 300) can store a large portion or the entire sequential mapping table in the cache memory of the memory controller. Compared to individual mapping table 310, Figure 3 The description illustrates the significant reduction in the size of the sequential mapping table 300. In this way, local DRAM memory can be eliminated to save costs, and the relatively long operations of frequently swapping portions of the mapping table in the cache can be reduced or eliminated. In some instances, the storage system 110 and / or the memory device 200 do not contain DRAM.

[0048] In one instance, a large amount of data is stored in the flash memory array as sequential writes. Therefore, the large number of maps can be stored as a sequential map table, as described in the example above. In some instances, some remaining writes are still individual writes. In one instance, in addition to the sequential map table, an individual map table is included to account for remaining non-sequential writes. In instances with both sequential and individual map tables, the cache size required to maintain a given number of map tables is reduced because the size of the sequential map table, as described above, is reduced.

[0049] Figure 4 Demonstrates the operation of a memory device based on an example. Figure 4 The method can be performed, for example, by a memory device described above (e.g., system 110 or memory device 200), and in some instances can be implemented to create and use a sequential mapping table represented at 216 in memory device 200, wherein in some instances, it can be substantially as shown in Figure 3 The sequence map is in the form of 300 indications. In operation 402, a sequence map (e.g., sequence map 216) is stored in the flash memory (e.g., flash memory array 212) of the memory device (e.g., system 110 or device 200). The sequence map is stored to contain the logical block start positions. In operation 404, the sequence map is stored to contain the physical block start positions. In operation 406, the sequence map is stored to contain the sequence block write lengths. In operation 408, the sequence map is loaded into the controller cache (e.g., cache 224) when the memory device is started.

[0050] In one instance, the sequential mapping table is initially generated (e.g., during the manufacture of the memory device) as all zeros stored in the mapping field. During operation, the firmware in the memory controller contains instructions executable by the controller's processor to create entries in the sequential mapping table during sequential writes performed during system operation. In one instance, upon power-up, the sequential mapping table is loaded from the flash memory array into a cache located within the memory controller. For example, most or all of the sequential mapping table is loaded into the cache. The cache then enables fast access to locations within the flash memory array because all or most of the sequential mapping table fits into the cache.

[0051] During operation, new writes may be performed by the memory controller. If the new write is a sequential write, the memory controller may check to see how long the sequential write is. In one instance, the memory controller will then check the sequential map to see how long the new write is compared to other sequential writes in the sequential map. In one instance, the new write is added to the sequential map only if the new write is greater than or equal to the shortest existing entry in the sequential map. When the memory device is powered off, the sequential map (e.g., with recently added / updated entries) is saved from the cache to the flash memory array (e.g., flash memory array 212). When the memory device is subsequently powered on, the most recently stored sequential map is loaded from the flash memory array into the cache.

[0052] In one instance of a read operation, the memory controller first checks the sequential mapping table to see if the requested data falls within one of the entries in the sequential mapping table. If it is determined that the requested data is included in one of the entries in the sequential mapping table, the data is retrieved based on the mapping entry. In one instance, if it is determined that the requested data is not included in one of the entries in the sequential mapping table, then the individual mapping table can be searched. If additional entries from the individual mapping table are needed, the memory controller can retrieve a portion of the individual mapping table from the flash memory array, and the data read operation is completed once the location within the flash memory array is determined. Although some individual mapping table searches may still be required, because many data writes are sequential, using a sequential mapping table as described above can significantly reduce the time required to retrieve most of the requested data.

[0053] Although this scenario is uncommon, in one instance, if an unexpected power loss occurs during operation, the memory controller can reset the sequence map to all zeros. This prevents corruption of the sequence map because, in the event of an unexpected power loss, the memory controller would not have been able to store an updated sequence map in the flash memory array before the power failure.

[0054] Figures 5A to 5F This explains the instance operations of the sequential mapping table described above. Figure 5A In the process, the temporary mapping descriptor (TMD) 502 is initialized to all zeros at startup. A write operation is performed, and then 0x100LBA is recorded in TMD 502, with the corresponding PPA being 0x200.

[0055] exist Figure 5B In the process, another LBA of 0x101 is written sequentially, and PPA0x201 is written accordingly. TMD is updated from length "1" to length "2".

[0056] exist Figure 5CIn this process, another write is performed on LBA 0x90 and PPA0x202. Because this write is not sequential, it is not written to the Temporary Mapped Descriptor (TMD). Figure 5C In the middle, instance sequence mapping table 504 is initialized to all zeros, and comes from Figure 5A and 5B The TMD is written to the mapping descriptor 503 in the sequential mapping table 504. Figures 5C to 5F The sequential mapping table 504 is shown with only four mapping descriptors (MDs) for illustrative purposes. In practice, a larger sequential mapping table 504 could be used. Figure 5C In this process, because the sequential mapping table 504 is initialized to zero, TMD data is entered into the first MD slot MD0.

[0057] Figure 5D Display the sequential mapping table 504 in different states, which is filled with all four instance mapping descriptors 503. Figure 5D In the example, if from Figure 5B If a TMD is written to sequential mapping table 504, then table 504 is first checked to see if there is any overlap between the TMD to be written and the existing MD 503. Figure 5D Since there is no overlap, the TMD entries 0x100, 0x200, and 2 are written to the MD3. Previous MD3 entries 0x90, 0x60, and 1 are overwritten because their length is "1", and the new TMD has a length of "2". In this way, only the highest volume entries are stored in the sequential mapping table 504, and lower volume entries are overwritten. The mapping for lower volume entries can be stored in a regular table and accessed without using the sequential mapping table 504.

[0058] Figure 5E The example sequence map 504 is shown, where the suggested TMDs 0x100, 0x200, 2 are shorter than all four MDs 503 in the sequence map 504. In one instance, to maximize the efficiency of the sequence map 504, entries of TMDs 0x100, 0x200, 2 will not be added to the sequence map 504 because it is already full of longer sequence entries.

[0059] Figure 5F The example sequence mapping table 504 is shown, where the proposed TMDs 0x100, 0x200, and 2 overlap with the existing MD3s 0xF0, 0x60, and 20. In this case, the TMD is overwritten on the MD3.

[0060] Figure 6 Display instance sequence mapping table 604. Figure 6In this example, the read request looks up the LBA of 0x35 in the sequential mapping table 604. Based on MD1, it is determined that the LBA of 0x35 in the range of LBA (0x30, 0x3a) corresponds to MD1. In this example, the corresponding PPA of 0x25 is determined from the sequential mapping table 604 based on MD1.

[0061] Figure 7 The description may include a block diagram of instance machine 700, representing the memory device or system described in the examples above. Machine 700 may include a memory device containing firmware containing instructions for creating a sequential mapping table and / or interacting with the sequential mapping table when executed by the controller's processor, as described above relative to... Figure 3 and Figure 5A See description F. Machine 700 can execute the method described above using a sequential mapping table.

[0062] In alternative embodiments, machine 700 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 700 may operate as a server machine, a client machine, or both in a server-client network environment. In an example, machine 700 may act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 700 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, IoT device, automotive system, or any machine capable of executing instructions (sequentially or otherwise) specifying actions to be taken by said machine. Furthermore, while only a single machine is described, the term "machine" should also be considered to include any collection of machines that individually or collectively execute a set (or more) of instructions to perform one or more of the methods discussed herein, such as cloud computing, Software as a Service (SaaS), or other computer cluster configurations.

[0063] As described herein, an instance may comprise, or be operable through, logic, components, devices, packages, or mechanisms. A circuit system is a collection (e.g., set) of circuits implemented in a tangible entity containing hardware (e.g., simple circuits, gates, logic, etc.). The membership of a circuit system can be flexible over time and due to the variability of the underlying hardware. A circuit system contains members that can perform specific tasks individually or in combination during operation. In an instance, the hardware of a circuit system may be invariably designed to perform specific operations (e.g., hardwired). In an instance, the hardware of a circuit system may contain variably connected physical components (e.g., execution units, transistors, simple circuits, etc.) containing physically modified (e.g., magnetically, electrically, or movably placed particles of invariant mass, etc.) computer-readable media to encode instructions for specific operations. For example, when connecting physical components, the underlying electrical properties of the hardware composition may change from an insulator to a conductor, and vice versa. Instructions enable participating hardware (e.g., execution units or loading mechanisms) to create components of a circuit system within the hardware via variable connections to perform specific tasks during operation. Therefore, while the device is operating, it is communicatively coupled to other components of the circuit system via computer-readable media. In an example, any of the physical components may be used in more than one part of more than one circuit system. For instance, under operation, an execution unit may be used at one point in time in a first circuit of a first circuit system and may be reused at different times by a second circuit in the first circuit system or a third circuit in the second circuit system.

[0064] The machine (e.g., computer system, host system, etc.) 700 may include a processing device 702 (e.g., a hardware processor, central processing unit (CPU), graphics processing unit (GPU), hardware processor core or any combination thereof), a main memory 704 (e.g., read-only memory (ROM), dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM)) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., static random access memory (SRAM), etc.) and a storage system 718, some or all of which may communicate with each other via a communication interface (e.g., bus) 730.

[0065] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 702 may be configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communicating via network 720.

[0066] Storage system 718 may include machine-readable storage media (also known as computer-readable media) on which one or more sets of instructions 726 or software embodying any or more of the methods or functions described herein are stored. During execution of instructions 726 by computer system 700, instructions 726 may also reside wholly or at least partially in main memory 704 or processing device 702, which also constitute machine-readable storage media.

[0067] The term "machine-readable storage medium" should be understood to include a single or multiple media storing one or more sets of instructions, or any media capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be understood to include (but is not limited to) solid-state memory, optical media, and magnetic media. In examples, mass-capacity machine-readable media includes machine-readable media with multiple particles having invariant (e.g., rest) mass. Therefore, mass-capacity machine-readable media is not a transiently propagating signal. Specific examples of mass-capacity machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0068] Machine 700 may further include a display unit, an alphanumeric input device (e.g., a keyboard), and a user interface (UI) navigation device (e.g., a mouse). In an example, one or more of the display unit, input device, or UI navigation device may be a touchscreen display. The machine may include a signal generating device (e.g., a speaker) or one or more sensors, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or one or more other sensors. Machine 700 may include an output controller, such as serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.)) connection, to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0069] Instructions 726 (e.g., software, programs, operating system (OS), etc.) or other data stored on storage system 718 can be accessed by main memory 704 for use by processing device 702. Main memory 704 (e.g., DRAM) is typically fast but volatile, and is therefore a different type of storage device from storage system 718 (e.g., SSD), which is suitable for long-term storage, including storage under "off" conditions. Instructions 726 or data used by user or machine 700 are typically loaded into main memory 704 for use by processing device 702. When main memory 704 is full, virtual space from storage system 718 can be allocated to supplement main memory 704; however, since storage system 718 devices are typically slower than main memory 704, and write speeds are typically at least twice as slow as read speeds, using virtual memory can significantly degrade the user experience (compared to main memory 704, e.g., DRAM) due to storage system latency. Furthermore, using storage system 718 for virtual memory can significantly reduce the available lifespan of storage system 718.

[0070] Instruction 724 may further utilize any of several transport protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.) to transmit or receive data via the network interface device 708 using a transport medium through the communication network 720. Example communication networks may include Local Area Networks (LANs), Wide Area Networks (WANs), Packet Data Networks (e.g., the Internet), Mobile Phone Networks (e.g., Cellular Networks), Ordinary Old-Style Telephone (POTS) Networks, and Wireless Data Networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards, referred to as…). The IEEE 802.16 series of standards are called This includes standards such as IEEE 802.15.4 series and peer-to-peer (P2P) networks. In an example, network interface device 708 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to network 720. In an example, network interface device 708 may include multiple antennas for wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" is intended to include any intangible medium capable of storing, encoding, or carrying instructions executed by machine 700, and includes digital or analog communication signals or other intangible media to facilitate communication of this software.

[0071] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The drawings illustrate specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements other than those shown or described. However, the inventors also contemplate examples in which only the elements shown or described are provided. Furthermore, the inventors contemplate examples using any combination or arrangement of the elements (or aspects thereof) shown or described with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0072] All publications, patents, and patent documents referenced in this document are incorporated herein by reference in their entirety as if individually incorporated by reference. In the event of any inconsistency between this document and any such document so incorporated by reference, the usage in the incorporated reference shall be considered supplementary to the usage in this document; in the case of irreconcilable inconsistencies, the usage in this document shall prevail.

[0073] In this document, the term "a / an," as is common in patent documents, is used independently of any other example or use of "at least one" or "one or more" to include one or more. In this document, the term "or" is used to refer to a non-exclusive "or," such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "comprising" and "in which" are used as concise English equivalents to the corresponding terms "including" and "wherein." Furthermore, in the appended claims, the terms "comprising" and "including" are open-ended, meaning that a system, apparatus, article, or process comprising elements other than those listed after this term in a claim is still considered within the scope of the claim. Additionally, in the appended claims, the terms "first," "second," and "third," etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0074] In various instances, the components, controllers, processors, units, engines, or tables described herein may include, in particular, physical circuitry systems or firmware stored on a physical device. As used herein, "processor" means any type of computing circuitry, such as, but not limited to, a microprocessor, microcontroller, graphics processor, digital signal processor (DSP), or any other type of processor or processing circuitry, including processor groups or multi-core devices.

[0075] As used herein, operating a memory cell includes reading from a memory cell, writing to a memory cell, or erasing a memory cell. The operation of placing a memory cell in a desired state is referred to herein as “programming” and may include both writing to and erasing from a memory cell (e.g., a memory cell can be programmed to an erase state).

[0076] It will be understood that when a component is referred to as "on another component," "connected to another component," or "coupled to another component," it may be directly on, connected to, or coupled to the other component, or there may be an intermediary component. In contrast, when a component is referred to as "directly on another component," "directly connected to another component," or "directly coupled to another component," there is no intermediary component or layer. If two components are shown in a diagram as being connected by a line, then the two components may be coupled or directly coupled, unless otherwise indicated.

[0077] The methods described herein may be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions operable to configure an electronic device to perform the methods described in the examples above. Implementations of such methods may include program code, such as microprogram code, assembly language code, higher-level language code, or the like. This code may contain computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, the code may be tangibly stored, for example, during execution or at other times, on one or more volatile or non-volatile tangible computer-readable media. Examples of such tangible computer-readable media may include (but are not limited to) hard disks, removable disks, removable optical disks (e.g., optical discs and digital video disks), magnetic tapes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), and the like.

[0078] To better illustrate the methods and apparatus disclosed herein, a non-limiting list of embodiments is provided herein:

[0079] Example 1 is a memory device. The memory device includes at least one flash memory array. The memory device includes a sequential mapping table stored within the flash memory array, wherein the sequential mapping table includes sequential write entries, wherein the number of sequential write entries is greater than one, and the sequential mapping table includes data fields for logical block start position, physical block start position, and sequential block write length.

[0080] In Example 2, the objects of Example 1 are optionally configured to further include individual mapping tables.

[0081] In Example 3, the object of any of Examples 1 to 2 is optionally configured such that the flash memory array includes a NAND memory array.

[0082] In Example 4, the object of any of Examples 1 to 3 is optionally configured to further include a controller within the memory device, the controller including firmware to update the sequence mapping table from the host device when the host device is powered off.

[0083] In Example 5, the object of any of Examples 1 to 4 is optionally configured to further include a controller within the memory device, the controller including firmware for resetting the sequential mapping table to all zeros in the event of an unexpected power loss.

[0084] Example 6 is a system. The system includes a host device comprising a processor, and a flash memory device coupled to the host device. The flash memory device includes at least one flash memory array and a sequence mapping table stored within the flash memory array, wherein the sequence mapping table contains sequence write entries, wherein the number of sequence write entries is greater than one, and the sequence mapping table contains data fields for logical block start position, physical block start position, and sequence block write length. The system includes firmware for loading data from the sequence mapping table into a controller configured to interface between the flash memory device and the processor.

[0085] In Example 7, the object of Example 6 is optionally configured to further include individual mapping tables located within the flash memory array.

[0086] In Example 8, the object of any of Examples 6 to 7 is optionally configured such that the control includes firmware to search for data by checking whether the desired data is within the range of sequential entries in the sequential mapping table, and the firmware is further configured to search the individual mapping table if the desired data is not within the range of sequential entries in the sequential mapping table.

[0087] In Example 9, the object of any of Examples 6 to 8 is optionally configured such that the control includes firmware for updating the sequence mapping table during operation.

[0088] In Example 10, the object of any of Examples 6 to 9 is optionally configured such that the controller includes firmware to add an entry to the sequential mapping table only when a new entry is written that is sequentially longer than the shortest entry in the sequential mapping table.

[0089] In Example 11, the object of any of Examples 6 to 10 is optionally configured such that the controller includes firmware for storing an updated sequential mapping table to the flash memory storage array in the event of a power failure.

[0090] In Example 12, the object of any of Examples 6 to 11 is optionally configured such that the control includes firmware for storing all zeros into the sequential mapping table in the event of unexpected power loss.

[0091] Example 13 is a method. The method includes storing a sequential mapping table in the flash memory of a memory device, including storing the start position of a logical block, storing the start position of a physical block, storing the sequential block write length, and loading the sequential mapping table into a controller cache when the memory device is started.

[0092] In Example 14, the object of Example 13 is optionally configured such that the sequential mapping table is constructed and updated in a buffer within the controller and stored in the flash memory when the memory device is powered off.

[0093] In Example 15, the objects of any of Examples 13 to 14 are optionally configured to further include the sequential mapping table being initialized to all zeros during manufacturing.

[0094] In Example 16, the object of any of Examples 13 to 15 is optionally configured to further include initializing the sequential mapping table to all zeros in the event of unexpected power loss.

[0095] In Example 17, the object of any of Examples 13 to 16 is optionally configured to further include only the entry added to the sequential mapping table if it is newly written sequentially longer than the shortest entry in the sequential mapping table.

[0096] In Example 18, the object of any of Examples 13 to 17 is optionally configured to further include searching for data by checking whether the desired data is within the range of sequential entries in the sequential mapping table, and searching individual mapping tables if the desired data is not within the range of sequential entries in the sequential mapping table.

[0097] The foregoing description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with each other. Other embodiments may be used by those skilled in the art upon review of the foregoing description. An abstract is provided to conform to 37C.FR §1.72(b) to allow the reader to quickly determine the nature of the technical disclosure. The description is submitted under the understanding that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the detailed description above, various features may be grouped together to simplify this disclosure. This should not be construed as expecting any unclaimed disclosed feature to be essential to any claim. Rather, the subject matter of the invention may lie in fewer than all the features of a particular disclosed embodiment. Therefore, the appended claims are hereby incorporated into the detailed description, wherein each claim is itself an individual embodiment, and such embodiments are contemplated to be combined or arranged in various ways with each other. The scope of the invention should be determined with reference to the appended claims together with the full scope of the equivalents granted by such claims.

Claims

1. A memory device comprising: At least one memory storage array, comprising physical blocks of memory cells; A controller that operates in response to instructions stored in the memory device, wherein the instructions, when executed by the controller, cause the controller to perform operations including: In response to a first read request for the memory device, a sequential mapping table stored in the memory device is read. The sequential mapping table contains a plurality of sequential write entries that associate logical block addresses (LBAs) with physical block addresses (PBAs) of blocks in the memory array. The sequential mapping table includes: The sequential block write length indicator identifies the number of sequential PBAs corresponding to the first group of sequential LBAs; and The initial PBA of the sequential PBA; and If a new entry is written that is sequentially longer than the shortest entry in the sequential mapping table, only that entry is added to the sequential mapping table.

2. The memory device of claim 1, wherein the operation further comprises: By referring to the sequential mapping table, multiple PBAs containing multiple memory units are identified in response to the first read request; and In response to the first read request, access the plurality of PBAs and read the electrical properties of the memory cells.

3. The memory device of claim 2, wherein the memory cells within the physical block of the memory cell are arranged in the form of pages, and wherein reading the electrical properties of the memory cell in response to the first read request includes reading a plurality of pages arranged in the form of corresponding physical blocks.

4. The memory device of claim 1, wherein the operation further comprises: Read at least a portion of the logical-to-physical (L2P) table stored in the memory array; and Generate the sequential mapping table representing at least a portion of the L2P table.

5. The memory device of claim 1, wherein the operation further comprises: Identify sequential writes to physical block addresses performed in the memory device; and The descriptor that generates the sequential mapping table is executed in the memory device on write.

6. The memory device of claim 5, wherein the operation further comprises: The sequential mapping table is stored in the memory storage array; and Write the sequential mapping table into the cache memory of the memory device; The reading of the sequential mapping table includes reading the sequential mapping table from the cache memory.

7. The memory device of claim 6, wherein the cache memory includes volatile memory.

8. The memory device of claim 7, wherein the cache memory comprises SRAM.

9. The memory device of claim 1, wherein the sequential mapping table includes data fields for: LBA associated with the storage array; The PBA of the storage array; and The sequential block writes a length indicator.

10. The memory device of claim 1, further comprising a separate mapping table.

11. The memory device of claim 1, wherein the at least one memory storage array comprises a NAND storage array.

12. The memory device of claim 1, further comprising a controller within the memory device, the controller including firmware for updating the sequential mapping table from the host device when the host device is powered off.

13. The memory device of claim 1, further comprising a controller within the memory device, the controller including firmware for resetting the sequential mapping table to all zeros in the event of an unexpected power loss.

14. A system comprising: A host device, which includes a processor; Flash memory device coupled to the host device, wherein the flash memory device comprises: At least one flash memory array; A sequential mapping table, stored within the flash memory array, wherein the sequential mapping table contains sequential write entries, wherein the number of sequential write entries is greater than one, and the sequential mapping table contains data fields for the following: Logical block start position; Physical block starting position; Sequential block write length; and Firmware for loading data from the sequential mapping table into a controller, wherein the controller is configured to interface between the flash memory device and the processor, and wherein the firmware is configured to add an entry to the sequential mapping table only when a new entry is written that is sequentially longer than the shortest entry in the sequential mapping table.

15. The system of claim 14, further comprising individual mapping tables located within the flash memory storage array.

16. The system of claim 15, wherein the controller includes firmware for searching for data by checking whether the desired data is within the range of sequential entries in the sequential mapping table; and The firmware is further configured to search the individual mapping table if the desired data is not within the range of sequential entries in the sequential mapping table.

17. The system of claim 14, wherein the controller includes firmware for updating the sequence mapping table during operation.

18. The system of claim 14, wherein the controller includes firmware for storing an updated sequential mapping table to the flash memory storage array in the event of a power failure.

19. The system of claim 14, wherein the controller includes firmware for storing all zeros into the sequential mapping table in the event of unexpected power loss.

20. A method comprising: The sequential mapping table is stored in the flash memory of the memory device, which contains: The starting position of the storage logical block; Store the starting position of the physical block; Store the sequential block write length; and When the memory device is started, the sequential mapping table is loaded into the controller cache; and If a new entry is written that is sequentially longer than the shortest entry in the sequential mapping table, only that entry is added to the sequential mapping table.

21. The method of claim 20, wherein the sequential mapping table is constructed and updated in a buffer within the controller and stored in the flash memory when the memory device is powered off.

22. The method of claim 20, further comprising initializing the sequential mapping table to all zeros during manufacturing.

23. The method of claim 20, further comprising initializing the sequential mapping table to all zeros in the event of an unexpected power loss.

24. The method of claim 20, further comprising searching for data by checking whether the desired data falls within the range of sequential entries in the sequential mapping table; and If the desired data is not within the range of sequential entries in the sequential mapping table, search the individual mapping table.

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