On-chip cache and integrated chip

Abstract

The application discloses an on-chip cache and an integrated chip, which are used for solving the problems of low page storage space utilization and waste of on-chip cache storage space in the prior art. The on-chip cache comprises a storage unit, which is used for storing a first page. The first page comprises a first part of data units and a second part of data units. First tag information corresponding to the first part of data units has a first priority, and second tag information corresponding to the second part of data units has a second priority. The second priority is lower than the first priority.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technology field, and particularly relates to an on-chip cache and an integrated chip. BACKGROUND

[0002] With the development of manufacturing process and technology, the on-chip cache capacity of a processor is getting larger and larger, and the implementation media of the on-chip cache is getting more and more diversified. For example, the cache implemented by a static random-access memory (SRAM) and an enhanced dynamic random access memory (eDRAM) can reach 128 MB or even more, and the 3D packaged SRAM can further increase the storage density of the ordinary SRAM to achieve a larger storage capacity and access bandwidth. The 2.5D or 3D packaged DRAM (i.e., on-chip memory) as the on-chip cache capacity can reach 16 GB and is expected to be further improved. The larger the cache capacity is, the greater the influence of the management efficiency on the processor performance is. In the embodiments of the present application, the on-chip memory and the on-chip cache both refer to the 2.5D or 3D packaged DRAM.

[0003] Specifically, the access bandwidth problem of the memory system has become one of the main reasons hindering the improvement of the processor performance. The on-chip large-capacity cache is a new technology proposed by the industry to solve the access bandwidth problem of the memory system. The on-chip large-capacity cache can package the memory die on the chip through the through silicon via (TSV) technology, thereby achieving the effect of improving the access bandwidth of the memory system. Taking the 2.5D or 3D packaged DRAM as an example, there are data showing that the bandwidth of the on-chip memory can reach 4-8 times of that of the double data rate DRAM (DDR DRAM).

[0004] Generally, the on-chip cache can have three working modes: a cache mode, a flat mode and a hybrid mode. When working in the cache mode, the on-chip cache can be used as the cache of the off-chip memory; when working in the flat mode, the on-chip cache is used as the ordinary memory; and when working in the hybrid mode, part of the on-chip cache is used as the cache of the off-chip memory and part of the on-chip cache is used as the ordinary memory. The present application improves the scenario that the on-chip cache is used as the cache of the off-chip memory.

[0005] When on-chip caching is used as a cache for off-chip DRAM, the concept of footprint cache is proposed. Its design idea is to allocate cache at the page level, but only store footprint-sized data on demand in the on-chip cache, while other unaccessed data is not cached to save bandwidth for accessing off-chip memory. For example... Figure 1 The image shown is a schematic diagram of a page stored in the on-chip cache. Figure 1 In the image, each small square represents a footprint (e.g., a block). Gray-filled footprints store data, while white-filled footprints are blank and do not store data. That is, gray-filled footprints can store frequently accessed data on a page, while data corresponding to the white-filled portions of the page is accessed less frequently and therefore not stored in the on-chip cache.

[0006] use Figure 1 The proposed solution, while improving memory system access efficiency and reducing unnecessary memory bandwidth waste, suffers from low page storage space utilization, resulting in wasted on-chip cache storage space. Summary of the Invention

[0007] This application provides an on-chip cache and integrated chip to solve the problems of low page storage space utilization and wasted on-chip cache storage space in the prior art.

[0008] In a first aspect, embodiments of this application provide an on-chip cache, including: a storage unit for storing a first page, the first page including a first part of data units and a second part of data units, the first tag information corresponding to the first part of data units having a first priority, and the second tag information corresponding to the second part of data units having a second priority, the second priority being lower than the first priority.

[0009] The data units stored in the first page can be divided into two parts, and each part of the data units corresponds to a tag information. In the off-chip memory, one tag information corresponds to one page in the off-chip memory, that is, in the on-chip cache provided in the first aspect, each part of the data units is used to store the data units of one page in the off-chip memory, and the on-chip cache provided in the first aspect can store the data units originally stored in two pages in the off-chip memory into the first page. In the prior art, the data units stored in one page in the on-chip cache all come from the same page in the off-chip memory, that is, the data units stored in the on-chip cache all correspond to one tag information, and in the first page of the on-chip cache provided in the first aspect, the data units corresponding to two tag information are stored. That is, the on-chip cache provided in the first aspect can compress the data originally stored in two pages into one page, thereby saving the storage space of the on-chip cache.

[0010] In a possible design, the storage unit is further configured to store index information of the first page, and the index information of the first page includes index information of the first part of data units and index information of the second part of data units.

[0011] According to the above scheme, the data units stored in the first page can be indexed according to the index information of the first page.

[0012] Specifically, the index information of the first part of data units can include first tag information and first valid bit information, and the index information of the second part of data units can include second tag information and second valid bit information.

[0013] According to the above scheme, the priority of the first part of data units and the valid data units in the first page can be determined through the index information of the first part of data units, and the priority of the second part of data units and the valid data units in the first page can be determined through the index information of the second part of data units.

[0014] In a possible design, the on-chip cache can further include a storage controller configured to set the priority of the second tag information as a first priority, and set the priority of the first tag information or the third tag information with the first priority as a second priority.

[0015] According to the above scheme, the priorities of the first part of data units and the second part of data units can be swapped.

[0016] In a possible design, the first page further includes a third part of data units, and fourth tag information corresponding to the third part of data units has a third priority, and the third priority is lower than the second priority.

[0017] According to the scheme, the on-chip cache can store a plurality of partial storage units, and each partial storage unit has different priority.

[0018] In a second aspect, an integrated chip is provided, which includes: an on-chip cache configured to store a first page, the first page including a first partial data unit and a second partial data unit, the first partial data unit corresponding to first tag information having a first priority, and the second partial data unit corresponding to second tag information having a second priority, the second priority being lower than the first priority.

[0019] According to the integrated chip provided in the second aspect, the first partial data unit corresponding to the first tag information and the second partial data unit corresponding to the second tag information can be stored in the first page. Compared with the prior art of storing only one data unit corresponding to one tag information in one page, the data originally stored in a plurality of pages in the on-chip cache can be compressed and stored in one page, thereby saving the storage space of the on-chip cache.

[0020] In a possible design, the on-chip cache is further configured to store index information of the first page, the index information of the first page including index information of the first partial data unit and index information of the second partial data unit.

[0021] According to the above scheme, the data unit stored in the first page can be indexed according to the index information of the first page.

[0022] Specifically, the index information of the first partial data unit includes the first tag information and first valid bit information, and the index information of the second partial data unit includes the second tag information and second valid bit information.

[0023] According to the above scheme, the priority of the first partial data unit and the valid data unit in the first page can be determined according to the index information of the first partial data unit, and the priority of the second partial data unit and the valid data unit in the first page can be determined according to the index information of the second partial data unit.

[0024] In a possible design, the integrated chip provided in the second aspect further includes: a processor configured to send a first access instruction, the first access instruction being used to request access to a first data unit, the first data unit corresponding to the first tag information; and the on-chip cache is further configured to: determine, according to the first valid bit information, that the first data unit is stored in the on-chip cache; and send the first data unit to the processor.

[0025] According to the above scheme, when the processor requests to access the data unit corresponding to the first tag information, if the data unit is stored in the on-chip cache, the data unit is directly returned to the processor, instead of being obtained from the off-chip memory, thereby improving the data access efficiency.

[0026] In a possible design, the processor is further configured to: send a second access instruction, the second access instruction being used to request access to a second data unit, the second data unit corresponding to the second tag information; and the on-chip cache is further configured to: determine, according to the second valid bit information, that the second data unit is stored in the on-chip cache; and send the second data unit to the processor.

[0027] By using the above scheme, when the processor requests to access the data unit corresponding to the second tag information, if the data unit is stored in the on-chip cache, the data unit is directly returned to the processor, and it is not necessary to obtain the data unit from the off-chip memory, thereby improving data access efficiency.

[0028] In a possible design, the on-chip cache is further configured to: determine, according to the number of times of access of the second data unit in a unit time, whether to set the priority of the second tag information as the first priority and set the priority of the first tag information or the third tag information with the first priority as the second priority.

[0029] By using the above scheme, the priority of the second tag information and the first tag information can be replaced.

[0030] In a possible design, the processor is further configured to: send a third access instruction, the third access instruction being used to request access to a third data unit, the third data unit corresponding to the second tag information; and the on-chip cache is further configured to: determine, according to the second valid bit information, that the third data unit is not stored in the on-chip cache; the processor is further configured to: read the third data unit from the off-chip memory; and the on-chip cache is further configured to: store the third data unit.

[0031] By using the above scheme, when the processor requests to access the data unit corresponding to the second tag information, if the data unit is not stored in the on-chip cache, the corresponding data unit is read from the off-chip memory, and the on-chip cache stores the data unit.

[0032] Specifically, when the on-chip cache stores the third data unit, the on-chip cache is specifically configured to: store the third data unit in the first page or the second page.

[0033] The second page and the first page are data units on a same way in the Data Array.

[0034] Further, the on-chip cache is further configured to: set the valid bit corresponding to the third data unit in the second valid bit information as valid; set the priority of the second tag information as the first priority, and set the priority of the first tag information or the fourth tag information with the first priority as the second priority.

[0035] The second tag information can be regarded as a victim of the first tag information. When the data unit corresponding to the second tag information is not stored in the on-chip cache, and the corresponding storage location of the data unit is occupied by the first tag information, the second tag information with the second priority needs to be upgraded to the first priority when the corresponding data is read into the on-chip cache. At this time, a tag information with the first priority in the Tag Array must be downgraded to the second priority. The downgraded tag information can be the first tag information or the fourth tag information.

[0036] In addition, the integrated chip provided in the second aspect can further include a tag buffer configured to store the first tag information and the second tag information.

[0037] With the above scheme, when the processor issues an access instruction, the corresponding information can be first searched in the tag buffer to determine whether the data accessed by the processor is stored in the on-chip cache, thereby improving the data access efficiency.

[0038] In a possible design, the first page further includes a third part of data units, and fourth tag information corresponding to the third part of data units has a third priority, which is lower than the second priority.

[0039] With the above scheme, the on-chip cache can store a plurality of part storage units, and each part storage unit has a different priority. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 A schematic diagram of a page of on-chip cache storage provided by the prior art;

[0041] Figure 2 A structural schematic diagram of a first integrated chip provided by an embodiment of the present application;

[0042] Figure 3 A schematic diagram of a page in an on-chip cache provided by an embodiment of the present application;

[0043] Figure 4 A schematic diagram of a tag array and a data array provided by an embodiment of the present application;

[0044] Figure 5 A structural schematic diagram of a second integrated chip provided by an embodiment of the present application;

[0045] Figure 6 A structural schematic diagram of an on-chip cache provided by an embodiment of the present application;

[0046] Figure 7 A structural schematic diagram of a third integrated chip provided by an embodiment of the present application;

[0047] Figure 8 A flowchart illustrating the first priority replacement process provided in this application embodiment;

[0048] Figure 9 A flowchart illustrating the second priority replacement process provided in this application embodiment;

[0049] Figure 10 This application provides a schematic diagram of a data access process as an embodiment of the present application.

[0050] Figure 11 This is a flowchart illustrating the third priority replacement process provided in the embodiments of this application. Detailed Implementation

[0051] The application scenarios of the embodiments of this application will be introduced below.

[0052] The embodiments of this application can be applied to Figure 2 The integrated chip shown includes a processor, a memory controller (MC), and an on-chip cache. Furthermore, the integrated chip is connected to off-chip memory. The processor initiates data access requests and performs data processing; the memory controller controls data interaction between the processor and the on-chip cache, and between the processor and off-chip memory; the off-chip memory stores a large amount of data, and the on-chip cache can be considered as an on-chip cache of the off-chip memory.

[0053] In this embodiment, the on-chip cache is used as a cache for off-chip memory. That is, the on-chip cache stores a portion of the data in off-chip memory. When the processor issues an access instruction, if the data accessed by the processor is stored in the on-chip cache, the data is returned directly from the on-chip cache; if the data accessed by the processor is not stored in the on-chip cache, the data needs to be retrieved from off-chip memory, and the retrieved data is stored in the on-chip cache to ensure a hit in the next access.

[0054] In on-chip caching, cache space is allocated at the page level. A page can be divided into multiple data units. In this embodiment, the on-chip cache can store data units in the page that have been accessed by the processor before, so that the processor can access them again later. That is to say, the on-chip cache may not cache all the data units in the page.

[0055] Specifically, a data unit stored in a page of on-chip cache can be divided into multiple parts, each part corresponding to a tag. Each part stores data units from a page in off-chip memory. In other words, on-chip cache can store data units that were originally stored across multiple pages in off-chip memory into a single page of on-chip cache. Taking the division of data units stored in a single page of on-chip cache into two parts as an example, a schematic diagram of a single page in on-chip cache can be shown below. Figure 3 As shown. In Figure 3 In this embodiment, one page of the on-chip cache stores data units corresponding to the first tag information (Tag1) and the second tag information (Tag2). The data unit corresponding to Tag1 is stored in one page in off-chip memory, and the data unit corresponding to Tag2 is stored in another page in off-chip memory. In the prior art, all data units stored in one page of the on-chip cache come from the same page in off-chip memory, that is, all data units stored in the on-chip cache correspond to one tag. However, in this embodiment, one page of the on-chip cache stores data units corresponding to multiple tags. In other words, in this embodiment, data that was originally stored in multiple pages in off-chip memory can be compressed and stored into one page of the on-chip cache, thereby saving storage space of the on-chip cache.

[0056] In the on-chip cache, in addition to storing pages, page index information is also stored. Specifically, page index information can be stored in a tag array, and pages can be stored in a data array. There is a one-to-one correspondence between the page index information in the tag array and the page in the data array. As the names suggest, the tag array and data array are stored in array form. Taking the tag array as an example, each tag array can be an m*n array, and each element in the array is the page index information. Specifically, the row vectors in the m*n array can be called Sets, and the column vectors in the m*n array can be called Ways. Furthermore, in this embodiment, if each row vector includes N elements, this storage structure can be called an N-way set-associative. For example, on-chip cache can use a four-way set-associative storage structure, where each row vector contains four elements. In the tag array, one of the four elements in each row vector represents the index information of a page. In the data array, one of the four elements in each row vector represents a page.

[0057] A concrete example of a tag array and a data array can be seen as follows:Figure 4 As shown in FIG. 6, the elements in the Tag Array are in one-to-one correspondence with the elements in the Data Array, and the elements in the Tag Array are used to indicate the index information of the corresponding page in the Data Array. Figure 4 As shown in FIG. 6, the elements in the Tag Array are in one-to-one correspondence with the elements in the Data Array, and the elements in the Tag Array are used to indicate the index information of the corresponding page in the Data Array. Figure 4 In the example of FIG. 6, the on-chip cache adopts a four-way set-associative architecture. In actual applications, the on-chip cache can also adopt an eight-way set-associative architecture or other architectures, which are not limited in the embodiments of the present application.

[0058] The index information of the page stored in the Tag Array will be introduced below. As described above, in the embodiments of the present application, the data units in a plurality of pages of the off-chip memory are stored in one page of the on-chip cache, that is, the data units stored in one page of the on-chip cache can be divided into a plurality of parts. Each part of the data units corresponds to a group of index information, and the plurality of groups of index information constitute the index information of one page of the on-chip cache. For example, the data units stored in the on-chip cache are divided into two parts A and B, and the index information of the page includes two groups of index information, one group of index information is used to index the part A, and the other group of index information is used to index the part B. Specifically, each group of index information can include the aforementioned tag information (Tag). In addition to the tag information (Tag), the following information can also be included: overall valid bit information (Valid), which is used to indicate whether the entire Tag is valid, if the Tag is invalid, all the data units corresponding to the Tag are inaccessible; least recently used (LRU) information, which is used to indicate the least recently used data unit; dirty bit (Dirty Bits) information, which is used to indicate whether the data stored in the data unit in the on-chip cache is dirty data, if some bits of the Dirty Bits are set to 0, it indicates that the corresponding data unit is clean data, and when replacement occurs, it can be invalidated directly without writing back to the off-chip memory; otherwise, if some bits of the Dirty Bits are set to 1, when replacement occurs, the corresponding dirty data needs to be written back to the off-chip memory; valid bit (Valid Bits) information, which is used to indicate the valid data unit in the page, that is, the valid data unit in the page stores data, and the invalid data unit does not store data, for example, in the example of FIG. 6, the valid bit information (Valid) of the tag information (Tag) in the Tag Array is used to indicate the valid data unit in the corresponding page in the Data Array. Figure 3In the example, the Valid Bits information corresponding to the blank cell is invalid, i.e., no data is stored in the cell. By searching the Valid Bits information, it can be determined whether the data unit accessed by the processor is stored in the on-chip cache. For example, the processor initiates an access instruction to access a data unit corresponding to Tag 1, and searches the Tag Array in the on-chip cache to find the index information corresponding to Tag 1 (Tag 1 hit). Then, it can be further determined whether the Valid Bits information corresponding to the data unit accessed by the processor is valid. If the Valid Bits information is valid, it indicates that the data unit is stored in the on-chip cache. If the Valid Bits information is invalid, it indicates that the data unit is not stored in the on-chip cache and needs to be accessed from the off-chip memory. Of course, when determining whether the data unit is stored in the on-chip cache and whether it can be accessed, the overall Valid Bits information (Valid) and the Dirty Bits information and other information are also considered. This example is only used to introduce the use of the Valid Bits information, and other information will not be described herein.

[0059] It should be noted that the Valid Bits information corresponding to each group of index information cannot be valid at the same time. This is because, in the embodiment of the present application, the data units in the plurality of pages in the off-chip memory are stored in one page of the on-chip cache, and the storage space size of one page of the off-chip memory is the same as that of one page of the on-chip cache. Therefore, for the storage location in one page of the on-chip cache used to store a data unit, if the storage location is used to store the data unit corresponding to Tag 1 (in the index information corresponding to Tag 1, the Valid Bits corresponding to the storage location is valid), the storage location cannot be used to store the data unit corresponding to Tag 2 (in the index information corresponding to Tag 2, the Valid Bits corresponding to the storage location is invalid). Taking one page shown in FIG. 8 as an example, the storage location in the first column of the second row is used to store the data unit corresponding to Tag 1, and the storage location cannot be used to store the data unit corresponding to Tag 2 at the same time. Figure 3 Taking one page shown in FIG. 8 as an example, the storage location in the first column of the second row is used to store the data unit corresponding to Tag 1, and the storage location cannot be used to store the data unit corresponding to Tag 2 at the same time. In terms of the Valid Bits, the fifth bit in the Valid Bits corresponding to Tag 1 is valid, and the fifth bit in the Valid Bits corresponding to Tag 2 is invalid.

[0060] In addition, each group of index information can further include Reference Bits information, which is used to record the history information of which data units are accessed. When the data unit corresponding to the Tag is no longer stored in the on-chip cache and needs to be written back to the off-chip memory, the Reference Bits information also needs to be written back to the off-chip memory. In this way, when the data unit corresponding to the Tag is stored in the on-chip cache again, the data unit can be prefetched through the Reference Bits information.

[0061] As mentioned above, since a plurality of Tag corresponding data units are stored in one page in the embodiment of the present application, for each Tag in the corresponding page, there is a set of index information including Tag, Valid, LRU, Dirty Bits, ValidBits and Reference Bits. Figure 4 Taking an example of a page including two Tag corresponding data units in the integrated chip, the index information of the page includes two sets. Specifically, among the two Tags, the Tag with higher priority is called Prime Tag, and the Tag with lower priority is called Sub Tag. The index information of the page includes the index information corresponding to the Prime Tag and the index information corresponding to the Sub Tag.

[0062] In addition, in the example of the integrated chip shown in Figure 4 As mentioned above, for the storage location of one page of the on-chip cache used for storing one data unit, the storage location can only store the data unit corresponding to one Tag, and when judging which Tag corresponding data unit is stored in the storage location, the priority of storage is involved. For example, if a certain data unit corresponding to the Sub Tag wants to be stored in the on-chip cache, and at this time the storage location of the data unit is occupied by the data unit corresponding to the Prime Tag, then the data unit corresponding to the Sub Tag cannot be stored in the on-chip cache; for example, if a certain data unit corresponding to the Prime Tag wants to be stored in the on-chip cache, and at this time the storage location of the data unit is occupied by the data unit corresponding to the Sub Tag, then the data unit corresponding to the Prime Tag can occupy the storage location and kick out the data unit corresponding to the Sub Tag from the on-chip cache.

[0063] In addition, in the example of the integrated chip shown in Figure 2 In the integrated chip shown in the figure, the memory controller can further include a Tag Buffer (TB) for caching part of the data in the Tag Array stored in the on-chip cache to the TB (in order to save the storage space of the memory controller, only part of the data of the Tag Array is stored to the TB, and the whole data of the Tag Array is not stored to the TB), so as to improve the access speed of the page index information. Specifically, the specific content of the Tag Array stored in the TB can refer to the related description of the Tag Array stored in the on-chip cache as mentioned above, which will not be described here.

[0064] In the case that part of the data in the Tag Array is stored in the TB, after the processor issues an access instruction, the processor can first determine whether the accessed data is stored in the on-chip cache by searching the TB. If it is determined that the accessed data is stored in the on-chip cache by searching the TB, the Tag Array in the on-chip cache does not need to be searched again, and the data can be directly accessed from the Data Array in the on-chip cache, thereby improving the access speed of the index information of the page. If it is determined that the accessed data is not stored in the on-chip cache by searching the TB, there are two cases, the first case is that the accessed data is not actually stored in the on-chip cache, and the second case is that part of the Tag Array in the on-chip cache is stored in the TB, and the index information corresponding to the accessed data is not stored in the TB, and the Tag Array in the on-chip cache needs to be searched again to determine which of the two cases the access belongs to.

[0065] It is worth noting that the data stored in the TB can be newer than the data stored in the on-chip cache, and therefore when the data in the TB is updated, the updated data needs to be written back to the on-chip cache. In addition, in order to ensure that the data in the TB is correct, when the index information of the page in the on-chip cache or the off-chip memory changes, the data in the TB must be updated synchronously.

[0066] Similar to the Tag Array stored in the on-chip cache, the Tag Array stored in the TB is also stored in the form of an array, for example, it can be an m*n array, and each element in the array is the index information of a page. Specifically, a row vector in the m*n array can be referred to as a Set, and a column vector in the m*n array can be referred to as a Way. In addition, if each row vector includes N elements, the storage structure of the TB can be referred to as N-way set associative. Exemplarily, the TB can adopt a storage structure of four-way set associative, that is, each row vector includes four elements.

[0067] Exemplarily, the data stored in the TB and the on-chip cache in the integrated chip provided by the embodiments of the present application can be as shown in Figure 5 Exemplarily, the data stored in the TB and the on-chip cache in the integrated chip provided by the embodiments of the present application can be as shown in Figure 5 In the example, the on-chip cache and the off-chip memory share one memory controller, and in actual applications, the on-chip cache and the off-chip memory can also be controlled by two controllers, which is not limited by the present application.

[0068] In addition, in the example, the TB and the on-chip cache share one memory controller, and in actual applications, the TB and the on-chip cache can also be controlled by two controllers, which is not limited by the present application. Figure 5In the storage array of the TB, the meaning of the Tag information (Tag) is the same as that of the Prime Tag or Sub Tag in the Tag Array of the on-chip cache, and the value (Value) represents a set of information such as Valid, LRU, Valid Bits, Dirty Bits, and Reference Bits in the Tag Array of the on-chip cache. It should be noted that in the example of Figure 5 , in order to simplify the management of the TB, the status of the Prime Tag and the Sub Tag is equal from the perspective of the TB, and therefore each entry (Tag+Value) in the TB is directed to a Prime Tag or a Sub Tag, rather than recording a pair of Prime Tag and Sub Tag as in the on-chip cache. Therefore, one element in the Tag Array of the on-chip cache corresponds to two sets of Tag+Value stored in the TB, and each set of Tag+Value can be regarded as an element in the storage array of the TB. It can be seen that in the example of Figure 5 , the TB adopts a storage structure connected by four-way groups, that is, each row vector includes four elements.

[0069] In the example of Figure 5 , four page index information are included in a single cache set, each page index information occupies a storage space of 64B, and is used to store the index information of a 4KB page. The on-chip cache also adopts a storage structure connected by four-way groups. In addition, historical data information is inserted after the page index information, which is used to record the related information (including the tag information Tag, the count value of the access frequency count, and the historical footprint of the access) of the page kicked out of the on-chip cache, so that the next time the page is stored into the on-chip cache, the related information of the page can be directly obtained.

[0070] Specifically, Figure 5 , the information included in the page index information is basically the same as that in the example of Figure 4 , and the difference is that Figure 5 , the example further includes a role flipping bit. As mentioned above, the multiple Tags corresponding to a page have a priority order, and the data unit corresponding to the Tag with a higher priority can be preferentially stored in the on-chip cache. In the specific example, the priority of the Prime Tag is higher than that of the Sub Tag, but in some cases (for example, the access frequency of the data corresponding to the Sub Tag is higher), the priority needs to be replaced. At this time, in order to avoid the overhead caused by data migration, the role flipping bit can be used for indication. For example, when the role flipping bit is 0 (i.e. in the default case), it indicates that the priority of the Prime Tag is higher; when the role flipping bit is 1, it indicates that the priority of the Sub Tag is higher.

[0071] It should be noted that, in the examples of the embodiments of the present application, the on-chip cache is integrated on-chip (i.e., the on-chip cache is located inside the integrated chip). In actual applications, an off-chip cache can also be provided outside the integrated chip, the off-chip cache has the same storage structure design as the on-chip cache provided by the embodiments of the present application and implements the same function as the on-chip cache provided by the embodiments of the present application, and the off-chip cache should also be considered to fall within the protection scope of the embodiments of the present application.

[0072] In addition, in the integrated chip, the MC can serve as a controller of the on-chip cache and the off-chip memory, and realize data interaction between the processor and the on-chip cache and the off-chip memory. In actual applications, the on-chip cache can also be separately configured with a storage controller for controlling data access in the on-chip cache. For example, the storage controller in the on-chip cache can count the accessed state of the data unit corresponding to the Tag, and can determine whether the aforementioned priority replacement (SubTag promotion to PrimeTag, which can also be referred to as SubTag upgrade) is needed.

[0073] To solve the problem of waste of large-capacity cache storage space proposed in the background art, the embodiments of the present application provide an on-chip cache and an integrated chip, which are intended to optimize the storage efficiency of the above large-capacity cache system and further improve the cache management efficiency. In the embodiments of the present application, the on-chip cache of 2.5D or 3D packaging is taken as an example for introduction, and in addition, the embodiments of the present application are also applicable to on-chip caches made of other media (such as SRAM, 3D-SRAM, eDRAM mentioned in the background art).

[0074] Next, the embodiments of the present application will be described in detail in conjunction with the drawings.

[0075] The embodiments of the present application provide an on-chip cache, as shown in Figure 6 The on-chip cache 600 includes a storage unit 601, which is used to store a first page, the first page including a first part of data units and a second part of data units, the first part of data units corresponding to first tag information having a first priority, and the second part of data units corresponding to second tag information having a second priority, the second priority being lower than the first priority.

[0076] It can be seen that the data units stored in the first page can be divided into two parts, and each part of the data units corresponds to a tag information (Tag). In the off-chip memory, one Tag corresponds to one page in the off-chip memory, that is, in the on-chip cache 600, each part of the data units is used to store the data units of one page in the off-chip memory, and the on-chip cache 600 can store the data units originally stored in two pages in the off-chip memory into the first page. In the prior art, the data units stored in one page in the on-chip cache all come from the same page in the off-chip memory, that is, the data units stored in the on-chip cache all correspond to one Tag, and in the embodiment of the present application, the data units corresponding to multiple Tags are stored in one page (that is, the first page) of the on-chip cache 600. That is, by using the on-chip cache 600 shown in Figure 6 , the data originally stored in two pages can be compressed and stored in one page, thereby saving the storage space of the on-chip cache.

[0077] For example, a possible structure of the first page can be as shown in Figure 3 , where Tag1 can be regarded as the first tag information, and Tag2 can be regarded as the second tag information.

[0078] Here, the first priority and the second priority are simply described. It can be understood that in the off-chip memory, the data corresponding to Tag1 can occupy the storage space of one entire page, and the data corresponding to Tag2 can also occupy the storage space of one entire page. However, since the storage space of the on-chip cache is limited, the on-chip cache can only store part of the data in the off-chip memory (for example, frequently accessed data or once accessed data), and then the data units corresponding to Tag1 can only be partially stored in the first page, and the data units corresponding to Tag2 are also the same. This will cause a problem. For a storage location (for example Figure 3 , the first row and the first column), if the data unit corresponding to Tag1 stored in the location in the off-chip memory and the data unit corresponding to Tag2 stored in the location in the off-chip memory both want to be stored in the first page of the on-chip cache, at this time, a priority order must be determined to determine whether the data unit corresponding to Tag1 is stored in the location or the data unit corresponding to Tag2 is stored in the location. In the embodiment of the present application, the priority of the first tag information (Tag1) is higher than the priority of the second tag information (Tag2), and then when the above situation occurs, the data unit corresponding to Tag1 is preferentially stored in the on-chip cache.

[0079] In addition, the storage unit 601 is also used to store the index information of the first page. Specifically, the index information of the first page includes the index information of the first part of the data units and the index information of the second part of the data units. For example, in the first page, the index information of the first part of the data units can be stored in the first row and the first column, and the index information of the second part of the data units can be stored in the second row and the first column.Figure 4 In the example, the first half of the page's index information, PrimeTag+Valid+LRU+Valid Bits+Dirty Bit+Reference Bits, can be regarded as the index information of the first part of the data unit, and the second half, SubTag+Valid+LRU+Valid Bits+Dirty Bits+Reference Bits, can be regarded as the index information of the second part of the data unit.

[0080] Specifically, the index information of the first part of the data unit may include first tag information (e.g., PrimeTag) and first valid bit information (e.g., Valid Bits), and the index information of the second part of the data unit may include second tag information (e.g., SubTag) and second valid bit information (e.g., Valid Bits).

[0081] The first and second valid bit information will be described in detail below. Taking the first valid bit information as an example, it can be used to indicate valid data units in the first page. Figure 4 For example, in Figure 4 In the example, the first page includes 4*16 data units. Therefore, the first valid bit information can be represented by 64 bits of data. If the corresponding position stores the first part of the data unit, the corresponding bit field in the first valid bit information is set to valid (e.g., set to 1). For example, if the first position in the 64 positions of the first page stores the data unit corresponding to Tag1, then the first bit in the 64 bits of the first valid bit information is set to valid. The meaning of the second valid bit information is similar to that of the first valid bit information, and will not be repeated here.

[0082] In addition, the on-chip cache 600 may also include a storage controller 602, which is used to set the priority of the second tag information to the first priority, and set the priority of the first tag information or the third tag information with the first priority to the second priority.

[0083] As mentioned earlier, to select and manage the storage of the first page, the first priority of the first data unit is higher than the second priority of the second data unit. However, in some cases (e.g., the second data unit is accessed more frequently or has a higher number of accesses), priority needs to be changed. In this case, the priority of the second tag information needs to be set to the first priority, and the priority of the first tag information or the third tag information with the first priority needs to be set to the second priority. In this way, the priority of the second tag information is higher than the priority of the first tag information, and the data unit corresponding to the second tag information can be stored in the on-chip cache preferentially.

[0084] Specifically, when the priority replacement is performed, the index information of the first part of data units and the index information of the second part of data units can be replaced by one role flipping bit, as shown in the example of Figure 5 Alternatively, the storage positions of the index information of the first part of data units and the index information of the second part of data units can be exchanged in a traditional manner.

[0085] It should be noted that in the description of the embodiments of the present application, the first page stores two parts of data units (the first part of data units and the second part of data units) as an example, and in actual application, more than two parts of data units corresponding to tag information can also be stored in the on-chip cache, as long as the priority of each part of data units is reasonably limited. For example, the first page can further include a third part of data units, and the fourth tag information corresponding to the third part of data units has a third priority, which is lower than the second priority.

[0086] The on-chip cache shown in Figure 6 The first part of data units corresponding to the first tag information and the second part of data units corresponding to the second tag information can be stored in the first page. Compared with the prior art scheme of storing only data units corresponding to one tag information in one page, the on-chip cache 600 shown in Figure 6 The data originally stored in multiple pages can be compressed and stored in one page, thereby saving the storage space of the on-chip cache.

[0087] Based on the same inventive concept, the embodiments of the present application also provide an integrated chip. Referring to Figure 7 The integrated chip 700 includes an on-chip cache 701. The on-chip cache 701 is used to store a first page, and the first page includes a first part of data units and a second part of data units. The first tag information corresponding to the first part of data units has a first priority, and the second tag information corresponding to the second part of data units has a second priority, which is lower than the first priority.

[0088] Specifically, the integrated chip 700 can be a system on chip (SoC).

[0089] In addition, the on-chip cache 701 is further used to store index information of the first page, and the index information of the first page includes index information of the first part of data units and index information of the second part of data units. The index information of the first part of data units includes the first tag information and the first valid bit information, and the index information of the second part of data units includes the second tag information and the second valid bit information.

[0090] Similarly, the first page further includes a third part of data units, and the fifth tag information corresponding to the third part of data units has a third priority, which is lower than the second priority.

[0091] The above description of the on-chip cache 701 can refer to the description of the on-chip cache 600 shown in Figure 6 FIG. 6, which will not be repeated here.

[0092] The integrated chip 700 can further include a processor 702 configured to send a first access instruction, the first access instruction being used to request access to a first data unit, the first data unit corresponding to first tag information; and the on-chip cache 701 is further configured to determine, according to the first valid bit information, that the first data unit is stored in the on-chip cache 701, and send the first data unit to the processor 702.

[0093] That is, when the processor 702 requests to access the data unit corresponding to the first tag information, if the data unit is stored in the on-chip cache 701, the data unit is directly returned to the processor 702 without being obtained from the off-chip memory, thereby improving the data access efficiency.

[0094] In a possible design, the processor 702 is further configured to send a second access instruction, the second access instruction being used to request access to a second data unit, the second data unit corresponding to second tag information; and the on-chip cache 701 is further configured to determine, according to the second valid bit information, that the second data unit is stored in the on-chip cache 701, and send the second data unit to the processor 702.

[0095] That is, when the processor 702 requests to access the data unit corresponding to the second tag information, if the data unit is stored in the on-chip cache 701, the data unit is directly returned to the processor 702 without being obtained from the off-chip memory, thereby improving the data access efficiency.

[0096] Further, if the processor 702 accesses the data unit corresponding to the second tag information, the on-chip cache 701 is further configured to determine, according to the number of times the data unit corresponding to the second tag information is accessed within a unit time, whether to set the priority of the second tag information as a first priority and set the priority of the first tag information or a third tag information having the first priority as a second priority.

[0097] As described above, in some cases, the priorities of the second tag information and the first tag information can be replaced. Then, after determining that the processor 702 accesses the data unit corresponding to the second tag information, the on-chip cache 701 can determine whether to perform the above priority replacement according to the number of times the data unit corresponding to the second tag information is accessed within a unit time.

[0098] For example, if the access count of the second tag information exceeds 20% of the minimum value of the access count of the tag information of the first priority in the same set (for example, four pages are connected in a 4-way set), the priority replacement process described above is performed. When the replacement is performed, the tag information of the first priority in the same set is selected to be replaced.

[0099] In another possible design, the processor 702 is further configured to send a third access instruction, where the third access instruction is used to request access to a third data unit, and the third data unit corresponds to second tag information; the on-chip cache 701 is further configured to: determine, according to the second valid bit information, that the third data unit is not stored in the on-chip cache 701; the processor 702 is further configured to read the third data unit from the off-chip memory and store the third data unit; and the on-chip cache 701 is further configured to store the third data unit.

[0100] That is, when the processor 702 requests to access the data unit corresponding to the second tag information, if the data unit is not stored in the on-chip cache 701, the corresponding data unit is read from the off-chip memory, and the on-chip cache 701 stores the data unit.

[0101] Specifically, when storing the third data unit, the on-chip cache 701 can store the third data unit in the first page or the second page. The second page and the first page are data units on the same way in the Data Array.

[0102] Further, the on-chip cache 701 is further configured to: set the valid bit corresponding to the third data unit in the second valid bit information as valid; set the priority of the second tag information as the first priority, and set the priority of the first tag information or the fourth tag information with the first priority as the second priority.

[0103] In the embodiment of the present application, the second tag information can be regarded as the victim role of the first tag information. When the data unit corresponding to the second tag information is not stored in the on-chip cache 701, and the corresponding storage position of the data unit is occupied by the first tag information, the second tag information with the second priority needs to be upgraded to the first priority when the corresponding data is read to the on-chip cache 701. At this time, it is necessary to downgrade a tag information with the first priority in the Tag Array to the second priority. The downgraded tag information can be the first tag information or the fourth tag information.

[0104] It can be seen that in the management of the first page, the problem of priority replacement is often involved. Whether the priority replacement is determined according to the number of accesses in a unit of time or the priority replacement is performed due to the miss of the access of the second tag information in the on-chip cache 701, for the second tag information (SubTag), it can be called a SubTag promote process.

[0105] In the SubTag promote, the priority replacement can be in the same way (for example, the priority replacement of the first tag information and the second tag information), or the priority replacement can be in different ways (for example, the priority replacement of the first tag information and the third tag information, or the priority replacement of the first tag information and the fourth tag information).

[0106] In the SubTag promote, the PrimeTag in the same set and the same way is preferred to be selected. If the PrimeTag in other ways in the same set is selected, additional access memory operations are introduced, but the advantage is that the replaced PrimeTag is the least recently used. On the contrary, if only the PrimeTag in the same set and the same way is selected, the replaced PrimeTag can not be the least recently used.

[0107] In addition, if the priority replacement is in different ways, the tag information with the first priority to be replaced and the tag information with the second priority to be kicked out of the on-chip cache can be in the same way or in different ways.

[0108] In the SubTag promote, in addition to the replacement of the priority, the operation of the valid bit information is also involved. The following two specific examples are used to introduce the SubTag promote process.

[0109] I. The tag information with the first priority to be replaced and the tag information with the second priority to be kicked out of the on-chip cache are in the same way.

[0110] A specific example of the SubTag promote in the same way can be as follows: Figure 8The processor accesses the data unit corresponding to the fifth valid bit in the second valid bit information. The data unit is not stored in the on-chip cache, so it is read from the off-chip DRAM. It should be noted that when data is taken from the off-chip DRAM, the data units corresponding to the other valid bit information in the second tag information need to be taken together (that is, data prefetching is performed according to the historical access information). After the corresponding data is retrieved, the fifth valid bit in the second valid bit information needs to be set as valid, and the priority of the second tag information needs to be upgraded to the first priority. To this end, the tag information with the first priority (hereinafter referred to as Tag1) is selected for replacement. The valid bit information corresponding to Tag1 is 10010010, and the valid bit information corresponding to the tag information with the second priority (hereinafter referred to as Tag2) in the same way is 01100001. After the priority of the second tag information is upgraded to the first priority, the data corresponding to Tag2 is kicked out of the on-chip cache and stored to the off-chip DRAM; Tag1 is downgraded to the second priority. Since the data corresponding to the first valid bit and the fourth valid bit conflicts with the upgraded second tag information, the corresponding data unit in Tag1 is stored to the off-chip DRAM because the priority of Tag1 is lower. The valid bit information after the SubTag promote is completed is as shown in Figure 8 .

[0111] As can be seen in the example of Figure 8 , the replaced Tag2 and the kicked-out Tag1 in the on-chip cache are in the same way.

[0112] II. The replaced tag information with the first priority and the kicked-out tag information with the second priority in the on-chip cache are in different ways.

[0113] A specific example of SubTag promote in different ways can be as shown in Figure 9 . The processor accesses the data unit corresponding to the fifth valid bit in the second valid bit information. The data unit is not stored in the on-chip cache, so it is read from the off-chip DRAM. It should be noted that when data is taken from the off-chip DRAM, the data units corresponding to the other valid bit information in the second tag information need to be taken together. After the corresponding data is retrieved, the fifth valid bit in the second valid bit information needs to be set as valid, and the priority of the second tag information needs to be upgraded to the first priority. To this end, the tag information with the first priority Tag1 (assuming it is in Way1, that is, in column vector 1) is selected for replacement. At this time, a tag information with the second priority needs to be selected to be kicked out of the on-chip cache (assuming it is in Way3, that is, in column vector 3).

[0114] In Figure 9In the example, after the fifth valid bit in the second valid bit information is valid, Tag1 with the first priority in Way1 is selected to be replaced, and the information corresponding to Tag1 can be stored in other locations in the on-chip cache, and the part of the information corresponding to Tag2 that is not in conflict with the updated second valid bit information can be retained, and the conflicting part is stored to the off-chip DRAM.

[0115] In order to continue to store Tag1 in the on-chip cache, Tag4 with the second priority in Way3 is found to be replaced, and thus the information corresponding to Tag4 can be stored to the off-chip DRAM. Then, Tag1 is compared with Tag3 with the first priority in Way3, and the part not in conflict with Tag3 can be retained in the on-chip cache, and the conflicting part is stored to the off-chip DRAM.

[0116] In addition, in the embodiment of the present application, the integrated chip 700 can further include a tag cache 703 for storing the first tag information and the second tag information. The tag cache 703 can be located in the MC.

[0117] That is, the index information of the page stored in the on-chip cache can also be stored in the tag cache 703. In addition to storing the tag information, valid bit information, dirty bit information and the like can also be stored. In this way, when the processor issues an access instruction, the corresponding information can be first searched in the tag cache 703 to determine whether the data accessed by the processor is stored in the on-chip cache, thereby improving the data access efficiency.

[0118] It should be noted that the data in the tag cache 703 can be newer than the data in the on-chip cache 701, and thus when the data in the tag cache 703 is updated, the updated data needs to be written back to the on-chip cache 701. In addition, when the page index information in the on-chip cache 701 or the off-chip memory changes, the data in the tag cache 703 must be updated synchronously.

[0119] As can be seen, in the integrated chip 700, the judgment of the storage location of the accessed data can occur in the tag cache (TB), the on-chip cache (DC, i.e. DRAM cache) and the off-chip DRAM. In a specific example, the data access process of the processor can be as shown in Figure 10

[0120] ​When the memory access request misses in the last level cache (LLC), the request is sent to the TB in the memory controller. If a TB hit occurs, the corresponding valid bits in the TB are checked to determine if the valid bit is 1 (valid bit = 1 means valid, valid bit = 0 means invalid). If the valid bit is 1, it means that the data is in the DC, and the DC is accessed. In the DC, it is determined whether the accessed address hits the first tag information (PrimeTag) or the second tag information (SubTag). If the PrimeTag hits (TB hit, DC PrimeTag hit, valid), it is determined that the data is in the DC, and the DC is directly accessed to obtain the data. The PrimeTag is updated. If the SubTag hits (TB hit, DC SubTag hit, valid), it is determined that the data is in the DC, and the DC is directly accessed to obtain the data. The SubTag is updated, and it is determined whether the second tag information needs to be promoted (SubTag promote).

[0121] If the TB is accessed and the Tag hits (valid bit = 0), it means that the Tag corresponds to a page in the DC, but the footprint (i.e., data) does not exist in the DC (DC Tag hit, data miss, i.e., false miss). After the DC is queried, it is determined whether the PrimeTag or the SubTag is accessed. If the PrimeTag is accessed (TB hit, PrimeTag, not valid), because the PrimeTag has a high priority, the data can be directly returned from the off-chip DRAM, and the corresponding valid bits in the DC and the TB are updated to 1. At this time, the valid bits corresponding to the SubTag in the same group in the DC and the TB are cleared to 0. If the SubTag is accessed (TB hit, DC SubTag hit, not valid), the data is accessed from the off-chip DRAM, and it is determined whether the SubTag is promoted.

[0122] If a miss occurs in accessing the TB, at this time it is not determined whether the data is in the DC, because the TB miss only means that the Tag Array in the DC is not in the TB at this time. Continue to access the DC to confirm whether a real hit (i.e. Tag hit, and valid bit = 1, in this application, the real hit can also be referred to as full hit) occurs, if a real hit occurs, continue to distinguish whether it is a PrimeTag or a SubTag, if a PrimeTag hit (TB miss, DC PrimeTag hit, valid) occurs, return the data from the DC, and write the corresponding Tag and valid bits back to the TB, if a SubTag hit (TB miss, DC subTag Hit, valid) occurs, return the data from the DC, and write the corresponding Tag and valid bits back to the TB.

[0123] If a miss occurs in accessing the TB, and a Tag hit of the DC occurs but valid = 0 (i.e. invalid), a DConly Tag hit (only Tag hit) occurs. At this time, it is necessary to continue to judge whether a PrimeTag hit occurs, if a DC primeTag hit (TB miss, DC PrimeTag hit, not valid) occurs, access the off-chip DRAM to obtain data, and update the valid bits in the DC and the Tag and valid bits in the TB. If a DC SubTag hit (TB miss, DC SubTag hit, not valid) occurs, access the off-chip DRAM to obtain data, and decide whether to perform SubTag promote.

[0124] If a miss occurs in accessing the TB, and the DC is also a real miss (TB miss, DC real miss), the original PrimeTag replacement standard is reached, and a PrimeTag replacement occurs.

[0125] Specifically, the process of the second tag information promotion (SubTag promote) can be as follows Figure 11The shown. First, according to the access flow and set conditions to determine whether to proceed SubTag promote. If not, only update the second label information (SubTag) access count can be. If SubTag promote, determine whether the replaced first label information (PrimeTag) and SubTag in the same column vector (way), if in the same way, then directly Prime Tag and SubTag role flip can be, while the Prime Tag and SubTag conflict with the corresponding data valid bit write back off-chip; if the replaced Prime Tag and SubTag not in the same way, then can be in accordance with the foregoing Figure 8 and Figure 9 SubTag promote method shown, here will not be described.

[0126] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. An on-chip cache, characterized by The method comprises the following steps: A storage unit is used to store a first page, the first page comprising a first part data unit and a second part data unit, the first part data unit corresponding to first tag information having a first priority, and the second part data unit corresponding to second tag information having a second priority, the second priority being lower than the first priority. The first tag information and the second tag information correspond to a page in off-chip memory respectively.

2. The on-chip cache of claim 1, wherein, The storage unit is further used to: Store index information of the first page, the index information of the first page comprising index information of the first part data unit and index information of the second part data unit.

3. The on-chip cache of claim 2, wherein, The index information of the first part data unit comprises the first tag information and first valid bit information, and the index information of the second part data unit comprises the second tag information and second valid bit information.

4. The in-die cache of any one of claims 1-3, wherein, The method further comprises the following steps: A storage controller is used to set the priority of the second tag information to the first priority, and set the priority of the first tag information or third tag information having the first priority to the second priority.

5. The in-die cache of any one of claims 1-4, wherein, The first page further comprises a third part data unit, the third part data unit corresponding to fourth tag information having a third priority, the third priority being lower than the second priority.

6. An integrated chip, characterized by The method comprises the following steps: An on-chip cache is used to store a first page, the first page comprising a first part data unit and a second part data unit, the first part data unit corresponding to first tag information having a first priority, and the second part data unit corresponding to second tag information having a second priority, the second priority being lower than the first priority. The first tag information and the second tag information correspond to a page in off-chip memory respectively.

7. The integrated chip of claim 6, wherein, The on-chip cache is further used to: Store index information of the first page, the index information of the first page comprising index information of the first part data unit and index information of the second part data unit.

8. The integrated chip of claim 7, wherein, The index information of the first part data unit comprises the first tag information and first valid bit information, and the index information of the second part data unit comprises the second tag information and second valid bit information.

9. The integrated chip of claim 8, wherein, The method further comprises the following steps: A processor is used to send a first access instruction, the first access instruction being used to request access to a first data unit, the first data unit corresponding to the first tag information. The on-chip cache is further used to: Determine, according to the first valid bit information, that the first data unit is stored in the on-chip cache; Send the first data unit to the processor.

10. The integrated chip of claim 9, wherein, The processor is further used to: Send a second access instruction, the second access instruction being used to request access to a second data unit, the second data unit corresponding to the second tag information. The on-chip cache is further used to: Determine, according to the second valid bit information, that the second data unit is stored in the on-chip cache; Send the second data unit to the processor.

11. The integrated chip of claim 10, wherein, The on-chip cache is further used to: The processor is further configured to:

12. The integrated chip of any of claims 9 to 11, wherein, determine whether to set a priority of the second tag information as the first priority and set a priority of the first tag information or third tag information with the first priority as the second priority according to a number of times of access of the second data unit in a unit time. The processor is further configured to: send a third access instruction, the third access instruction being used to request to access a third data unit, the third data unit corresponding to the second tag information. The on-chip cache is further configured to: determine that the third data unit is not stored in the on-chip cache according to the second valid bit information; The processor is further configured to: read the third data unit from off-chip memory; The on-chip cache is further configured to:

13. The integrated chip of claim 12, wherein, store the third data unit. When the on-chip cache stores the third data unit, the on-chip cache is specifically configured to:

14. The integrated chip of claim 12 or 13, wherein, store the third data unit in the first page or the second page. The on-chip cache is further configured to: set a valid bit corresponding to the third data unit in the second valid bit information as valid; 15. The integrated chip of any of claims 6 to 14, wherein, set the priority of the second tag information as the first priority and set a priority of the first tag information or fourth tag information with the first priority as the second priority. Further comprising:

16. The integrated chip of any of claims 6 to 15, wherein, a tag cache configured to store the first tag information and the second tag information. The first page further comprises a third part of data units, fifth tag information corresponding to the third part of data units having a third priority, the third priority being lower than the second priority.

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